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195 lines
5.1 KiB
ReStructuredText
195 lines
5.1 KiB
ReStructuredText
.. SPDX-License-Identifier: CC-BY-SA-4.0
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Lattice Mico32 Specific Information
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***********************************
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This chaper discusses the Lattice Mico32 architecture dependencies in this port
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of RTEMS. The Lattice Mico32 is a 32-bit Harvard, RISC architecture "soft"
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microprocessor, available for free with an open IP core licensing
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agreement. Although mainly targeted for Lattice FPGA devices the microprocessor
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can be implemented on other vendors' FPGAs, too.
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**Architecture Documents**
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For information on the Lattice Mico32 architecture, refer to the following
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documents available from Lattice Semiconductor http://www.latticesemi.com/.
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- *"LatticeMico32 Processor Reference Manual"*
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http://www.latticesemi.com/dynamic/view_document.cfm?document_id=20890
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CPU Model Dependent Features
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============================
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The Lattice Mico32 architecture allows for different configurations of the
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processor. This port is based on the assumption that the following options are
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implemented:
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- hardware multiplier
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- hardware divider
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- hardware barrel shifter
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- sign extension instructions
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- instruction cache
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- data cache
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- debug
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Register Architecture
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=====================
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This section gives a brief introduction to the register architecture of the
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Lattice Mico32 processor.
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The Lattice Mico32 is a RISC archictecture processor with a 32-register file of
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32-bit registers.
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Register Name
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Function
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r0
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holds value zero
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r1-r25
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general purpose
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r26/gp
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general pupose / global pointer
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r27/fp
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general pupose / frame pointer
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r28/sp
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stack pointer
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r29/ra
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return address
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r30/ea
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exception address
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r31/ba
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breakpoint address
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Note that on processor startup all register values are undefined including r0,
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thus r0 has to be initialized to zero.
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Calling Conventions
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===================
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Calling Mechanism
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-----------------
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A call instruction places the return address to register r29 and a return from
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subroutine (ret) is actually a branch to r29/ra.
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Register Usage
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--------------
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A subroutine may freely use registers r1 to r10 which are *not* preserved
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across subroutine invocations.
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Parameter Passing
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-----------------
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When calling a C function the first eight arguments are stored in registers r1
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to r8. Registers r1 and r2 hold the return value.
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Memory Model
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============
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The Lattice Mico32 processor supports a flat memory model with a 4 Gbyte
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address space with 32-bit addresses.
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The following data types are supported:
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================== ==== ======================
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Type Bits C Compiler Type
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================== ==== ======================
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unsigned byte 8 unsigned char
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signed byte 8 char
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unsigned half-word 16 unsigned short
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signed half-word 16 short
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unsigned word 32 unsigned int / unsigned long
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signed word 32 int / long
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================== ==== ======================
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Data accesses need to be aligned, with unaligned accesses result are undefined.
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Interrupt Processing
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====================
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The Lattice Mico32 has 32 interrupt lines which are however served by only one
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exception vector. When an interrupt occurs following happens:
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- address of next instruction placed in r30/ea
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- IE field of IE CSR saved to EIE field and IE field cleared preventing further
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exceptions from occuring.
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- branch to interrupt exception address EBA CSR + 0xC0
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The interrupt exception handler determines from the state of the interrupt
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pending registers (IP CSR) and interrupt enable register (IE CSR) which
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interrupt to serve and jumps to the interrupt routine pointed to by the
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corresponding interrupt vector.
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For now there is no dedicated interrupt stack so every task in the system MUST
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have enough stack space to accommodate the worst case stack usage of that
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particular task and the interrupt service routines COMBINED.
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Nested interrupts are not supported.
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Default Fatal Error Processing
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==============================
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Upon detection of a fatal error by either the application or RTEMS during
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initialization the ``rtems_fatal_error_occurred`` directive supplied by the
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Fatal Error Manager is invoked. The Fatal Error Manager will invoke the
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user-supplied fatal error handlers. If no user-supplied handlers are
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configured or all of them return without taking action to shutdown the
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processor or reset, a default fatal error handler is invoked.
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Most of the action performed as part of processing the fatal error are
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described in detail in the Fatal Error Manager chapter in the User's Guide.
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However, the if no user provided extension or BSP specific fatal error handler
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takes action, the final default action is to invoke a CPU architecture specific
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function. Typically this function disables interrupts and halts the processor.
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In each of the architecture specific chapters, this describes the precise
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operations of the default CPU specific fatal error handler.
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Symmetric Multiprocessing
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=========================
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SMP is not supported.
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Thread-Local Storage
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====================
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Thread-local storage is not implemented.
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Board Support Packages
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======================
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There are no Lattice Micro32 specific notes on BSPs.
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System Reset
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------------
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An RTEMS based application is initiated or re-initiated when the processor is
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reset.
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