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3.8 KiB
ReStructuredText
151 lines
3.8 KiB
ReStructuredText
SuperH Specific Information
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###########################
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This chapter discusses the SuperH architecture dependencies
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in this port of RTEMS. The SuperH family has a wide variety
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of implementations by a wide range of vendors. Consequently,
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there are many, many CPU models within it.
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**Architecture Documents**
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For information on the SuperH architecture,
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refer to the following documents available from VENDOR
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(:file:`http//www.XXX.com/`):
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- *SuperH Family Reference, VENDOR, PART NUMBER*.
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CPU Model Dependent Features
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============================
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This chapter presents the set of features which vary
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across SuperH implementations and are of importance to RTEMS.
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The set of CPU model feature macros are defined in the file``cpukit/score/cpu/sh/sh.h`` based upon the particular CPU
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model specified on the compilation command line.
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Another Optional Feature
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------------------------
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The macro XXX
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Calling Conventions
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===================
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Calling Mechanism
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-----------------
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All RTEMS directives are invoked using a ``XXX``
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instruction and return to the user application via the``XXX`` instruction.
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Register Usage
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--------------
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The SH1 has 16 general registers (r0..r15).
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- r0..r3 used as general volatile registers
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- r4..r7 used to pass up to 4 arguments to functions, arguments
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above 4 are
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passed via the stack)
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- r8..13 caller saved registers (i.e. push them to the stack if you
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need them inside of a function)
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- r14 frame pointer
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- r15 stack pointer
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Parameter Passing
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-----------------
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XXX
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Memory Model
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============
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Flat Memory Model
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-----------------
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The SuperH family supports a flat 32-bit address
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space with addresses ranging from 0x00000000 to 0xFFFFFFFF (4
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gigabytes). Each address is represented by a 32-bit value and
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is byte addressable. The address may be used to reference a
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single byte, word (2-bytes), or long word (4 bytes). Memory
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accesses within this address space are performed in big endian
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fashion by the processors in this family.
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Some of the SuperH family members support virtual memory and
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segmentation. RTEMS does not support virtual memory or
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segmentation on any of the SuperH family members. It is the
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responsibility of the BSP to initialize the mapping for
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a flat memory model.
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Interrupt Processing
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====================
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Although RTEMS hides many of the processor dependent
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details of interrupt processing, it is important to understand
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how the RTEMS interrupt manager is mapped onto the processor’s
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unique architecture. Discussed in this chapter are the MIPS’s
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interrupt response and control mechanisms as they pertain to
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RTEMS.
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Vectoring of an Interrupt Handler
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---------------------------------
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Upon receipt of an interrupt the XXX family
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members with separate interrupt stacks automatically perform the
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following actions:
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- TBD
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A nested interrupt is processed similarly by these
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CPU models with the exception that only a single ISF is placed
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on the interrupt stack and the current stack need not be
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switched.
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Interrupt Levels
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----------------
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TBD
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Default Fatal Error Processing
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==============================
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The default fatal error handler for this architecture disables processor
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interrupts, places the error code in *XXX*, and executes a ``XXX``
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instruction to simulate a halt processor instruction.
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Symmetric Multiprocessing
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=========================
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SMP is not supported.
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Thread-Local Storage
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====================
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Thread-local storage is not implemented.
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Board Support Packages
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======================
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System Reset
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------------
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An RTEMS based application is initiated or
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re-initiated when the processor is reset. When the
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processor is reset, it performs the following actions:
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- TBD
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Processor Initialization
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------------------------
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TBD
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.. COMMENT: COPYRIGHT (c) 1988-2002.
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.. COMMENT: On-Line Applications Research Corporation (OAR).
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.. COMMENT: All rights reserved.
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