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97 lines
2.1 KiB
ReStructuredText
97 lines
2.1 KiB
ReStructuredText
.. SPDX-License-Identifier: CC-BY-SA-4.0
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.. Copyright (C) 2014 Hesham Almatary
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.. Copyright (C) 1989, 2007 On-Line Applications Research Corporation (OAR)
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OpenRISC 1000 Specific Information
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**********************************
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This chapter discusses the`OpenRISC 1000 architecture
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http://opencores.org/or1k/Main_Page dependencies in this port of RTEMS. There
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are many implementations for OpenRISC like or1200 and mor1kx. Currently RTEMS
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supports basic features that all implementations should have.
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**Architecture Documents**
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For information on the OpenRISC 1000 architecture refer to the`OpenRISC 1000
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architecture manual http://openrisc.github.io/or1k.html.
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Calling Conventions
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===================
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Please refer to the`Function Calling Sequence
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http://openrisc.github.io/or1k.html#__RefHeading__504887_595890882.
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Floating Point Unit
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-------------------
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A floating point unit is currently not supported.
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Memory Model
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============
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A flat 32-bit memory model is supported.
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Interrupt Processing
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====================
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OpenRISC 1000 architecture has 13 exception types:
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- Reset
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- Bus Error
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- Data Page Fault
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- Instruction Page Fault
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- Tick Timer
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- Alignment
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- Illegal Instruction
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- External Interrupt
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- D-TLB Miss
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- I-TLB Miss
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- Range
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- System Call
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- Floating Point
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- Trap
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Interrupt Levels
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----------------
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There are only two levels: interrupts enabled and interrupts disabled.
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Interrupt Stack
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---------------
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The OpenRISC RTEMS port uses a dedicated software interrupt stack. The stack
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for interrupts is allocated during interrupt driver initialization. When an
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interrupt is entered, the _ISR_Handler routine is responsible for switching
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from the interrupted task stack to RTEMS software interrupt stack.
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Default Fatal Error Processing
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==============================
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The default fatal error handler for this architecture performs the following
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actions:
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- disables operating system supported interrupts (IRQ),
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- places the error code in ``r0``, and
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- executes an infinite loop to simulate a halt processor instruction.
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Symmetric Multiprocessing
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=========================
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SMP is not supported.
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