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65 lines
1.9 KiB
ReStructuredText
.. SPDX-License-Identifier: CC-BY-SA-4.0
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.. Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
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Xilinx MicroBlaze Specific Information
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**************************************
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This chapter discusses the dependencies of the *MicroBlaze architecture*
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(https://en.wikipedia.org/wiki/MicroBlaze).
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**Architecture Documents**
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For information on the MicroBlaze architecture, refer to
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*UG984 MicroBlaze Processor Reference Guide*
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(https://www.xilinx.com/support/documentation/sw_manuals/xilinx2021_2/ug984-vivado-microblaze-ref.pdf).
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CPU Model Dependent Features
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============================
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There are no CPU model dependent features in this port.
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Calling Conventions
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===================
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Please refer to "Chapter 4: MicroBlaze Application Binary Interface" of
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*UG984 MicroBlaze Processor Reference Guide*
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(https://www.xilinx.com/support/documentation/sw_manuals/xilinx2021_2/ug984-vivado-microblaze-ref.pdf).
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Interrupt Processing
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====================
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Hardware exceptions, interrupts, and user exceptions are all supported. When a
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hardware exception or user exception occurs, a fatal error will be generated.
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When an interrupt occurs, the interrupt source is determined by reading the
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AXI Interrupt Controller's Interrupt Status Register and masking it with the
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Interrupt Enable Register.
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Interrupt Levels
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----------------
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There are exactly two interrupt levels on MicroBlaze with respect to RTEMS.
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Level zero corresponds to interrupts disabled. Level one corresponds to
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interrupts enabled. This is the inverse of how most other architectures handle
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interrupt enable status.
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Interrupt Stack
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---------------
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The memory region for the interrupt stack is defined by the BSP.
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Default Fatal Error Processing
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==============================
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The default fatal error is BSP-specific.
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Symmetric Multiprocessing
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=========================
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SMP is not supported.
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Thread-Local Storage
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====================
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Thread-local storage is supported.
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