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ReStructuredText
138 lines
4.6 KiB
ReStructuredText
.. SPDX-License-Identifier: CC-BY-SA-4.0
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.. Copyright (C) 1988, 2020 On-Line Applications Research Corporation (OAR)
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AArch64 Specific Information
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************************
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This chapter discusses the dependencies of the
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*ARM AArch64 architecture*
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(https://en.wikipedia.org/wiki/ARM_architecture#AArch64_features) in this port
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of RTEMS. The ARMv8-A versions are supported by RTEMS. Processors with a MMU
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use a static configuration which is set up during system start. SMP is not
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supported.
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**Architecture Documents**
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For information on the ARM AArch64 architecture refer to the *ARM Infocenter*
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(http://infocenter.arm.com/).
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CPU Model Dependent Features
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============================
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This section presents the set of features which vary across ARM AArch64
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implementations and are of importance to RTEMS. The set of CPU model feature
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macros are defined in the file :file:`cpukit/score/cpu/aarch64/rtems/score/aarch64.h`
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based upon the particular CPU model flags specified on the compilation command
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line.
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CPU Model Name
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--------------
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The macro ``CPU_MODEL_NAME`` is a string which designates the architectural
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level of this CPU model. See in :file:`cpukit/score/cpu/aarch64/rtems/score/aarch64.h`
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for the values.
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Floating Point Unit and SIMD
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----------------------------
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The Advanced SIMD (NEON) and Floating-point instruction set extension is
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supported and expected to be present since all ARMv8-A CPUs are expected to
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support it as per the *ARMv8-A Programmer's Guide Chapter 7 introduction*
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(https://developer.arm.com/docs/den0024/a/aarch64-floating-point-and-neon). As
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such, ``CPU_HARDWARE_FP`` will always be set to ``TRUE``.
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Multilibs
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=========
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The following multilib variants are available:
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#. ``ILP32``: AArch64 instruction set and registers using 32bit long int and pointers
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#. ``LP64``: AArch64 instruction set and registers using 64bit long int and pointers
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Use for example the following GCC options:
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.. code-block:: shell
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-mcpu=cortex-a53 -mabi=ilp32
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to build an application or BSP for the ARMv8-A architecture and tune the code
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for a Cortex-A53 processor. It is important to select the correct ABI.
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Calling Conventions
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===================
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Please refer to the *Procedure Call Standard for the ARM 64-bit Architecture*
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(https://github.com/ARM-software/abi-aa/releases/download/2019Q4/aapcs64.pdf).
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Memory Model
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============
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A flat 64-bit or 32-bit memory model is supported depending on the selected multilib
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variant. All AArch64 CPU variants support a built-in MMU for which basic initialization
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for a flat memory model is handled.
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Interrupt Processing
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====================
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The Reset Vector is determined using RVBAR and is Read-Only. RVBAR is set using
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configuration signals only sampled at reset. The ARMv8 architecture has four
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exception types:
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- Synchronous Exception
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- Interrupt (IRQ)
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- Fast Interrupt (FIQ)
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- System Error Exception
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Of these types only the synchronous and IRQ exceptions have explicit operating
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system support. It is intentional that the FIQ is not supported by the operating
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system. Without operating system support for the FIQ it is not necessary to
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disable them during critical sections of the system.
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Interrupt Levels
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----------------
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There are exactly two interrupt levels on ARMv8 with respect to RTEMS. Level
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zero corresponds to interrupts enabled. Level one corresponds to interrupts
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disabled.
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Interrupt Stack
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---------------
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The board support package must initialize the interrupt stack. The memory for
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the stacks is usually reserved in the linker script. The interrupt stack pointer
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is stored in the EL0 stack pointer and is accessed by switching to SP0 mode
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at the beginning of interrupt calls and back to SPx mode after completion of
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interrupt calls using the `spsel` instruction.
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Default Fatal Error Processing
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==============================
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The default fatal error handler for this architecture performs the following
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actions:
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- disables operating system supported interrupts (IRQ),
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- places the error code in ``x0``, and
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- executes an infinite loop to simulate a halt processor instruction.
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Symmetric Multiprocessing
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=========================
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SMP is not currently supported on ARMv8-A.
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Thread-Local Storage
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====================
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Thread-local storage (TLS) is supported. AArch64 uses unmodified TLS variant I
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which is not explcitly stated, but can be inferred from the behavior of GCC and
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*Addenda to, and Errata in, the ABI for the Arm® Architecture*
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(https://developer.arm.com/documentation/ihi0045/g). This alters expectations
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for the size of the TLS Thread Control Block (TCB) such that, under the LP64
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multilib variant, the TCB is 16 bytes in size instead of 8 bytes.
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