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102 lines
3.8 KiB
ReStructuredText
102 lines
3.8 KiB
ReStructuredText
.. SPDX-License-Identifier: CC-BY-SA-4.0
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.. Copyright (C) 2016 Pavel Pisa
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.. Copyright (C) 2014, 2021 embedded brains GmbH & Co. KG
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.. Copyright (C) 2000, 2008 On-Line Applications Research Corporation (OAR)
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.. This file is part of the RTEMS quality process and was automatically
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.. generated. If you find something that needs to be fixed or
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.. worded better please post a report or patch to an RTEMS mailing list
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.. or raise a bug report:
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..
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.. https://www.rtems.org/bugs.html
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..
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.. For information on updating and regenerating please refer to the How-To
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.. section in the Software Requirements Engineering chapter of the
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.. RTEMS Software Engineering manual. The manual is provided as a part of
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.. a release. For development sources please refer to the online
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.. documentation at:
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..
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.. https://docs.rtems.org
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.. Generated from spec:/rtems/cache/if/group
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.. _CacheManagerIntroduction:
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Introduction
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============
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.. The following list was generated from:
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.. spec:/rtems/cache/if/flush-multiple-data-lines
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.. spec:/rtems/cache/if/invalidate-multiple-data-lines
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.. spec:/rtems/cache/if/invalidate-multiple-instruction-lines
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.. spec:/rtems/cache/if/instruction-sync-after-code-change
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.. spec:/rtems/cache/if/get-maximal-line-size
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.. spec:/rtems/cache/if/get-data-line-size
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.. spec:/rtems/cache/if/get-instruction-line-size
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.. spec:/rtems/cache/if/get-data-size
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.. spec:/rtems/cache/if/get-instruction-size
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.. spec:/rtems/cache/if/flush-entire-data
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.. spec:/rtems/cache/if/invalidate-entire-data
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.. spec:/rtems/cache/if/invalidate-entire-instruction
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.. spec:/rtems/cache/if/enable-data
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.. spec:/rtems/cache/if/disable-data
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.. spec:/rtems/cache/if/enable-instruction
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.. spec:/rtems/cache/if/disable-instruction
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.. spec:/rtems/cache/if/aligned-malloc
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The Cache Manager provides functions to perform maintenance operations for data
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and instruction caches.
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The actual actions of the Cache Manager operations depend on the hardware and
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the implementation provided by the CPU architecture port or a board support
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package. Cache implementations tend to be highly hardware dependent. The
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directives provided by the Cache Manager are:
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* :ref:`InterfaceRtemsCacheFlushMultipleDataLines` - Flushes the data cache
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lines covering the memory area.
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* :ref:`InterfaceRtemsCacheInvalidateMultipleDataLines` - Invalidates the data
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cache lines covering the memory area.
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* :ref:`InterfaceRtemsCacheInvalidateMultipleInstructionLines` - Invalidates
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the instruction cache lines covering the memory area.
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* :ref:`InterfaceRtemsCacheInstructionSyncAfterCodeChange` - Ensures necessary
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synchronization required after code changes.
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* :ref:`InterfaceRtemsCacheGetMaximalLineSize` - Gets the maximal cache line
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size in bytes of all caches (data, instruction, or unified).
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* :ref:`InterfaceRtemsCacheGetDataLineSize` - Gets the data cache line size in
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bytes.
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* :ref:`InterfaceRtemsCacheGetInstructionLineSize` - Gets the instruction cache
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line size in bytes.
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* :ref:`InterfaceRtemsCacheGetDataCacheSize` - Gets the data cache size in
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bytes for the cache level.
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* :ref:`InterfaceRtemsCacheGetInstructionCacheSize` - Gets the instruction
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cache size in bytes for the cache level.
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* :ref:`InterfaceRtemsCacheFlushEntireData` - Flushes the entire data cache.
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* :ref:`InterfaceRtemsCacheInvalidateEntireData` - Invalidates the entire data
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cache.
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* :ref:`InterfaceRtemsCacheInvalidateEntireInstruction` - Invalidates the
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entire instruction cache.
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* :ref:`InterfaceRtemsCacheEnableData` - Enables the data cache.
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* :ref:`InterfaceRtemsCacheDisableData` - Disables the data cache.
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* :ref:`InterfaceRtemsCacheEnableInstruction` - Enables the instruction cache.
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* :ref:`InterfaceRtemsCacheDisableInstruction` - Disables the instruction
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cache.
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* :ref:`InterfaceRtemsCacheAlignedMalloc` - Allocates memory from the C Program
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Heap which begins at a cache line boundary.
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