mirror of
https://git.rtems.org/rtems-libbsd/
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rtwn: Import from FreeBSD.
This commit is contained in:
Christian Mauderer
360
freebsd/sys/dev/rtwn/rtl8821a/r21a_init.c
Normal file
360
freebsd/sys/dev/rtwn/rtl8821a/r21a_init.c
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@@ -0,0 +1,360 @@
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#include <machine/rtems-bsd-kernel-space.h>
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/*-
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* Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <rtems/bsd/local/opt_wlan.h>
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#include <rtems/bsd/sys/param.h>
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#include <rtems/bsd/sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/mbuf.h>
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#include <sys/kernel.h>
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#include <sys/socket.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <sys/queue.h>
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#include <sys/taskqueue.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/linker.h>
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#include <net/if.h>
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#include <net/ethernet.h>
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#include <net/if_media.h>
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#include <net80211/ieee80211_var.h>
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#include <net80211/ieee80211_radiotap.h>
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#include <dev/rtwn/if_rtwnreg.h>
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#include <dev/rtwn/if_rtwnvar.h>
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#include <dev/rtwn/if_rtwn_debug.h>
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#include <dev/rtwn/rtl8812a/r12a_var.h>
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#include <dev/rtwn/rtl8821a/r21a.h>
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#include <dev/rtwn/rtl8821a/r21a_priv.h>
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#include <dev/rtwn/rtl8821a/r21a_reg.h>
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int
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r21a_power_on(struct rtwn_softc *sc)
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{
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#define RTWN_CHK(res) do { \
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if (res != 0) \
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return (EIO); \
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} while(0)
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int ntries;
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/* Clear suspend and power down bits.*/
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RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
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R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_APDM_HPDN, 0, 1));
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/* Disable GPIO9 as EXT WAKEUP. */
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RTWN_CHK(rtwn_setbits_1(sc, R92C_GPIO_INTM + 2, 0x01, 0));
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/* Enable WL suspend. */
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RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
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R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE, 0, 1));
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/* Enable LDOA12 MACRO block for all interfaces. */
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RTWN_CHK(rtwn_setbits_1(sc, R92C_LDOA15_CTRL, 0, R92C_LDOA15_CTRL_EN));
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/* Disable BT_GPS_SEL pins. */
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RTWN_CHK(rtwn_setbits_1(sc, 0x067, 0x10, 0));
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/* 1 ms delay. */
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rtwn_delay(sc, 1000);
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/* Release analog Ips to digital isolation. */
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RTWN_CHK(rtwn_setbits_1(sc, R92C_SYS_ISO_CTRL,
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R92C_SYS_ISO_CTRL_IP2MAC, 0));
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/* Disable SW LPS and WL suspend. */
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RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
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R92C_APS_FSMCO_APFM_RSM |
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R92C_APS_FSMCO_AFSM_HSUS |
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R92C_APS_FSMCO_AFSM_PCIE, 0, 1));
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/* Wait for power ready bit. */
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for (ntries = 0; ntries < 5000; ntries++) {
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if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
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break;
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rtwn_delay(sc, 10);
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}
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if (ntries == 5000) {
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device_printf(sc->sc_dev,
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"timeout waiting for chip power up\n");
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return (ETIMEDOUT);
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}
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/* Release WLON reset. */
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RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
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R92C_APS_FSMCO_RDY_MACON, 2));
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/* Disable HWPDN. */
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RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
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R92C_APS_FSMCO_APDM_HPDN, 0, 1));
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/* Disable WL suspend. */
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RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
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R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE, 0, 1));
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RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
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R92C_APS_FSMCO_APFM_ONMAC, 1));
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for (ntries = 0; ntries < 5000; ntries++) {
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if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
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R92C_APS_FSMCO_APFM_ONMAC))
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break;
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rtwn_delay(sc, 10);
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}
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if (ntries == 5000)
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return (ETIMEDOUT);
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/* Switch DPDT_SEL_P output from WL BB. */
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RTWN_CHK(rtwn_setbits_1(sc, R92C_LEDCFG3, 0, 0x01));
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/* switch for PAPE_G/PAPE_A from WL BB; switch LNAON from WL BB. */
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RTWN_CHK(rtwn_setbits_1(sc, 0x067, 0, 0x30));
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RTWN_CHK(rtwn_setbits_1(sc, 0x025, 0x40, 0));
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/* Enable falling edge triggering interrupt. */
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RTWN_CHK(rtwn_setbits_1(sc, R92C_GPIO_INTM + 1, 0, 0x02));
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/* Enable GPIO9 interrupt mode. */
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RTWN_CHK(rtwn_setbits_1(sc, 0x063, 0, 0x02));
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/* Enable GPIO9 input mode. */
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RTWN_CHK(rtwn_setbits_1(sc, 0x062, 0x02, 0));
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/* Enable HSISR GPIO interrupt. */
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RTWN_CHK(rtwn_setbits_1(sc, R92C_HSIMR, 0, 0x01));
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/* Enable HSISR GPIO9 interrupt. */
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RTWN_CHK(rtwn_setbits_1(sc, R92C_HSIMR + 2, 0, 0x02));
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/* XTAL trim. */
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RTWN_CHK(rtwn_setbits_1(sc, R92C_APE_PLL_CTRL_EXT + 2, 0xFF, 0x82));
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RTWN_CHK(rtwn_setbits_1(sc, R92C_AFE_MISC, 0, 0x40));
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/* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
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RTWN_CHK(rtwn_write_2(sc, R92C_CR, 0x0000));
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RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0,
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R92C_CR_HCI_TXDMA_EN | R92C_CR_TXDMA_EN |
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R92C_CR_HCI_RXDMA_EN | R92C_CR_RXDMA_EN |
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R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN |
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((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) |
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R92C_CR_CALTMR_EN));
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if (rtwn_read_4(sc, R92C_SYS_CFG) & R92C_SYS_CFG_TRP_BT_EN)
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RTWN_CHK(rtwn_setbits_1(sc, 0x07C, 0, 0x40));
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return (0);
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#undef RTWN_CHK
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}
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void
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r21a_power_off(struct rtwn_softc *sc)
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{
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struct r12a_softc *rs = sc->sc_priv;
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int error, ntries;
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/* Stop Rx. */
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error = rtwn_write_1(sc, R92C_CR, 0);
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if (error == ENXIO) /* hardware gone */
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return;
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/* Move card to Low Power state. */
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/* Block all Tx queues. */
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rtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL);
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for (ntries = 0; ntries < 10; ntries++) {
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/* Should be zero if no packet is transmitting. */
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if (rtwn_read_4(sc, R88E_SCH_TXCMD) == 0)
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break;
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rtwn_delay(sc, 5000);
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}
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if (ntries == 10) {
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device_printf(sc->sc_dev, "%s: failed to block Tx queues\n",
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__func__);
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return;
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}
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/* CCK and OFDM are disabled, and clock are gated. */
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rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BBRSTB, 0);
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rtwn_delay(sc, 1);
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/* Reset whole BB. */
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rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BB_GLB_RST, 0);
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/* Reset MAC TRX. */
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rtwn_write_1(sc, R92C_CR,
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R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN);
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/* check if removed later. (?) */
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rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSEC, 0, 1);
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/* Respond TxOK to scheduler */
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rtwn_setbits_1(sc, R92C_DUAL_TSF_RST, 0, R92C_DUAL_TSF_RST_TXOK);
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/* If firmware in ram code, do reset. */
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#ifndef RTWN_WITHOUT_UCODE
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if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL)
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r21a_fw_reset(sc, RTWN_FW_RESET_SHUTDOWN);
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#endif
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/* Reset MCU. */
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rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_CPUEN,
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0, 1);
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rtwn_write_1(sc, R92C_MCUFWDL, 0);
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/* Move card to Disabled state. */
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/* Turn off RF. */
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rtwn_write_1(sc, R92C_RF_CTRL, 0);
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rtwn_setbits_1(sc, R92C_LEDCFG3, 0x01, 0);
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/* Enable rising edge triggering interrupt. */
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rtwn_setbits_1(sc, R92C_GPIO_INTM + 1, 0x02, 0);
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/* Release WLON reset. */
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rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
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R92C_APS_FSMCO_RDY_MACON, 2);
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/* Turn off MAC by HW state machine */
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rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_APFM_OFF,
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1);
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for (ntries = 0; ntries < 10; ntries++) {
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/* Wait until it will be disabled. */
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if ((rtwn_read_2(sc, R92C_APS_FSMCO) &
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R92C_APS_FSMCO_APFM_OFF) == 0)
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break;
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rtwn_delay(sc, 5000);
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}
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if (ntries == 10) {
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device_printf(sc->sc_dev, "%s: could not turn off MAC\n",
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__func__);
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return;
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}
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/* Analog Ips to digital isolation. */
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rtwn_setbits_1(sc, R92C_SYS_ISO_CTRL, 0, R92C_SYS_ISO_CTRL_IP2MAC);
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/* Disable LDOA12 MACRO block. */
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rtwn_setbits_1(sc, R92C_LDOA15_CTRL, R92C_LDOA15_CTRL_EN, 0);
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/* Enable WL suspend. */
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rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_AFSM_PCIE,
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R92C_APS_FSMCO_AFSM_HSUS, 1);
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/* Enable GPIO9 as EXT WAKEUP. */
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rtwn_setbits_1(sc, R92C_GPIO_INTM + 2, 0, 0x01);
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rs->rs_flags &= ~(R12A_IQK_RUNNING | R12A_RADAR_ENABLED);
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}
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int
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r21a_check_condition(struct rtwn_softc *sc, const uint8_t cond[])
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{
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struct r12a_softc *rs = sc->sc_priv;
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uint8_t mask;
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int i;
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RTWN_DPRINTF(sc, RTWN_DEBUG_RESET,
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"%s: condition byte 0: %02X; ext 5ghz pa/lna %d/%d\n",
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__func__, cond[0], rs->ext_pa_5g, rs->ext_lna_5g);
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if (cond[0] == 0)
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return (1);
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mask = 0;
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if (rs->ext_pa_5g)
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mask |= R21A_COND_EXT_PA_5G;
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if (rs->ext_lna_5g)
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mask |= R21A_COND_EXT_LNA_5G;
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if (rs->bt_coex)
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mask |= R21A_COND_BT;
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if (!rs->ext_pa_2g && !rs->ext_lna_2g &&
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!rs->ext_pa_5g && !rs->ext_lna_5g && !rs->bt_coex)
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mask = R21A_COND_BOARD_DEF;
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if (mask == 0)
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return (0);
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for (i = 0; i < RTWN_MAX_CONDITIONS && cond[i] != 0; i++)
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if (cond[i] == mask)
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return (1);
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return (0);
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}
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void
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r21a_crystalcap_write(struct rtwn_softc *sc)
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{
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struct r12a_softc *rs = sc->sc_priv;
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uint32_t reg;
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uint8_t val;
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val = rs->crystalcap & 0x3f;
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reg = rtwn_bb_read(sc, R92C_MAC_PHY_CTRL);
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reg = RW(reg, R21A_MAC_PHY_CRYSTALCAP, val | (val << 6));
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rtwn_bb_write(sc, R92C_MAC_PHY_CTRL, reg);
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}
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int
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r21a_init_bcnq1_boundary(struct rtwn_softc *sc)
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{
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#define RTWN_CHK(res) do { \
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if (res != 0) \
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return (EIO); \
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} while(0)
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RTWN_CHK(rtwn_write_1(sc, R88E_TXPKTBUF_BCNQ1_BDNY,
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R21A_BCNQ0_BOUNDARY));
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RTWN_CHK(rtwn_write_1(sc, R21A_DWBCN1_CTRL + 1,
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R21A_BCNQ0_BOUNDARY));
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RTWN_CHK(rtwn_setbits_1_shift(sc, R21A_DWBCN1_CTRL, 0,
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R21A_DWBCN1_CTRL_SEL_EN, 2));
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return (0);
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#undef RTWN_CHK
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}
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void
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r21a_init_ampdu_fwhw(struct rtwn_softc *sc)
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{
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rtwn_write_1(sc, R92C_FWHW_TXQ_CTRL,
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R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW);
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rtwn_write_4(sc, R92C_FAST_EDCA_CTRL, 0x03087777);
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}
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