Add support for Xilinx Versal APAC

2025-10-16 12:32:13 +08:00 · 2021-10-20 14:15:28 +11:00
parent 87a5b45564
commit 25a883272a
5 changed files with 347 additions and 0 deletions
--- a/libbsd.py
+++ b/libbsd.py
@@ -1478,6 +1478,7 @@ class dev_net(builder.Module):
        self.addRTEMSKernelSourceFiles(
            [
                'sys/dev/mii/ksz8091rnb_50MHz.c',
+                'sys/arm64/xilinx/versal_slcr.c',
                'sys/arm64/xilinx/zynqmp_slcr.c',
            ],
            mm.generator['source']()