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Add support for Xilinx Versal APAC

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This commit is contained in:
Chris Johns
2021-10-20 14:15:28 +11:00
parent 87a5b45564
commit 25a883272a
5 changed files with 347 additions and 0 deletions
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28
rtemsbsd/include/machine/rtems-bsd-nexus-bus.h
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@@ -139,6 +139,26 @@ extern "C" {
&zynqmp_slcr_res[0])
#endif /* RTEMS_BSD_DRIVER_XILINX_ZYNQMP_SLCR */
/*
* Xilinx Versal System Level Control Registers (SLCR).
*/
#if !defined(RTEMS_BSD_DRIVER_XILINX_VERSAL_SLCR)
/*
* Hard IP part of the Versal so a fixed address.
*/
#define RTEMS_BSD_DRIVER_XILINX_VERSAL_SLCR \
static const rtems_bsd_device_resource versal_slcr_res[] = { \
{ \
.type = RTEMS_BSD_RES_MEMORY, \
.start_request = 0, \
.start_actual = 0xf0000000 \
} \
}; \
RTEMS_BSD_DEFINE_NEXUS_DEVICE(versal_slcr, 0, \
RTEMS_ARRAY_SIZE(versal_slcr_res), \
&versal_slcr_res[0])
#endif /* RTEMS_BSD_DRIVER_XILINX_VERSAL_SLCR */
/*
* Xilinx ZynqMP Arasan SDIO Driver.
*/
@@ -489,6 +509,14 @@ extern "C" {
#define RTEMS_BSD_DRIVER_XILINX_ZYNQMP_CGEM3(_irq) \
RTEMS_BSD_DRIVER_XILINX_ZYNQ_CGEM(3, 0xff0e0000, _irq)
#endif /* RTEMS_BSD_DRIVER_XILINX_ZYNQMP_CGEM3 */
#if !defined(RTEMS_BSD_DRIVER_XILINX_VERSAL_CGEM0)
#define RTEMS_BSD_DRIVER_XILINX_VERSAL_CGEM0(_irq) \
RTEMS_BSD_DRIVER_XILINX_ZYNQ_CGEM(0, 0xff0c0000, _irq)
#endif /* RTEMS_BSD_DRIVER_XILINX_VERSAL_CGEM0 */
#if !defined(RTEMS_BSD_DRIVER_XILINX_VERSAL_CGEM1)
#define RTEMS_BSD_DRIVER_XILINX_VERSAL_CGEM1(_irq) \
RTEMS_BSD_DRIVER_XILINX_ZYNQ_CGEM(1, 0xff0d0000, _irq)
#endif /* RTEMS_BSD_DRIVER_XILINX_VERSAL_CGEM1 */
/*
* Designware/Synopsys Ethernet MAC Controller.