mirror of
https://git.rtems.org/rtems-libbsd/
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Add support for Xilinx Versal APAC
This commit is contained in:
Chris Johns
parent
87a5b45564
commit
25a883272a
@ -1478,6 +1478,7 @@ class dev_net(builder.Module):
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self.addRTEMSKernelSourceFiles(
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self.addRTEMSKernelSourceFiles(
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[
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[
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'sys/dev/mii/ksz8091rnb_50MHz.c',
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'sys/dev/mii/ksz8091rnb_50MHz.c',
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'sys/arm64/xilinx/versal_slcr.c',
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'sys/arm64/xilinx/zynqmp_slcr.c',
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'sys/arm64/xilinx/zynqmp_slcr.c',
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],
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],
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mm.generator['source']()
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mm.generator['source']()
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@ -126,6 +126,15 @@ RTEMS_BSD_DRIVER_XILINX_ZYNQMP_SDHCI0;
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RTEMS_BSD_DRIVER_XILINX_ZYNQMP_SDHCI1;
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RTEMS_BSD_DRIVER_XILINX_ZYNQMP_SDHCI1;
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RTEMS_BSD_DRIVER_MMC;
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RTEMS_BSD_DRIVER_MMC;
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#elif defined(LIBBSP_AARCH64_XILINX_VERSAL_BSP_H)
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#include <bsp/irq.h>
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RTEMS_BSD_DRIVER_XILINX_VERSAL_SLCR;
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RTEMS_BSD_DRIVER_XILINX_VERSAL_CGEM0(VERSAL_IRQ_ETHERNET_0);
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RTEMS_BSD_DRIVER_XILINX_VERSAL_CGEM1(VERSAL_IRQ_ETHERNET_1);
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RTEMS_BSD_DRIVER_UKPHY;
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#elif defined(LIBBSP_ARM_ATSAM_BSP_H)
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#elif defined(LIBBSP_ARM_ATSAM_BSP_H)
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RTEMS_BSD_DRIVER_USB;
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RTEMS_BSD_DRIVER_USB;
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@ -139,6 +139,26 @@ extern "C" {
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&zynqmp_slcr_res[0])
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&zynqmp_slcr_res[0])
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#endif /* RTEMS_BSD_DRIVER_XILINX_ZYNQMP_SLCR */
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#endif /* RTEMS_BSD_DRIVER_XILINX_ZYNQMP_SLCR */
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/*
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* Xilinx Versal System Level Control Registers (SLCR).
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*/
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#if !defined(RTEMS_BSD_DRIVER_XILINX_VERSAL_SLCR)
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/*
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* Hard IP part of the Versal so a fixed address.
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*/
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#define RTEMS_BSD_DRIVER_XILINX_VERSAL_SLCR \
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static const rtems_bsd_device_resource versal_slcr_res[] = { \
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{ \
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.type = RTEMS_BSD_RES_MEMORY, \
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.start_request = 0, \
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.start_actual = 0xf0000000 \
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} \
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}; \
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RTEMS_BSD_DEFINE_NEXUS_DEVICE(versal_slcr, 0, \
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RTEMS_ARRAY_SIZE(versal_slcr_res), \
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&versal_slcr_res[0])
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#endif /* RTEMS_BSD_DRIVER_XILINX_VERSAL_SLCR */
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/*
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/*
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* Xilinx ZynqMP Arasan SDIO Driver.
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* Xilinx ZynqMP Arasan SDIO Driver.
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*/
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*/
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@ -489,6 +509,14 @@ extern "C" {
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#define RTEMS_BSD_DRIVER_XILINX_ZYNQMP_CGEM3(_irq) \
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#define RTEMS_BSD_DRIVER_XILINX_ZYNQMP_CGEM3(_irq) \
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RTEMS_BSD_DRIVER_XILINX_ZYNQ_CGEM(3, 0xff0e0000, _irq)
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RTEMS_BSD_DRIVER_XILINX_ZYNQ_CGEM(3, 0xff0e0000, _irq)
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#endif /* RTEMS_BSD_DRIVER_XILINX_ZYNQMP_CGEM3 */
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#endif /* RTEMS_BSD_DRIVER_XILINX_ZYNQMP_CGEM3 */
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#if !defined(RTEMS_BSD_DRIVER_XILINX_VERSAL_CGEM0)
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#define RTEMS_BSD_DRIVER_XILINX_VERSAL_CGEM0(_irq) \
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RTEMS_BSD_DRIVER_XILINX_ZYNQ_CGEM(0, 0xff0c0000, _irq)
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#endif /* RTEMS_BSD_DRIVER_XILINX_VERSAL_CGEM0 */
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#if !defined(RTEMS_BSD_DRIVER_XILINX_VERSAL_CGEM1)
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#define RTEMS_BSD_DRIVER_XILINX_VERSAL_CGEM1(_irq) \
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RTEMS_BSD_DRIVER_XILINX_ZYNQ_CGEM(1, 0xff0d0000, _irq)
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#endif /* RTEMS_BSD_DRIVER_XILINX_VERSAL_CGEM1 */
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/*
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/*
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* Designware/Synopsys Ethernet MAC Controller.
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* Designware/Synopsys Ethernet MAC Controller.
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223
rtemsbsd/sys/arm64/xilinx/versal_slcr.c
Normal file
223
rtemsbsd/sys/arm64/xilinx/versal_slcr.c
Normal file
@ -0,0 +1,223 @@
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#include <machine/rtems-bsd-kernel-space.h>
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2021 Chris Johns <chrisj@rtems.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Versal ACAP SLCR driver. Provides hook for CGEM clocks.
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*
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* Reference:
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* https://www.xilinx.com/html_docs/registers/am012/mod___crl.html
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <bsp.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <rtems/bsd/sys/resource.h>
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#include <sys/sysctl.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <machine/stdarg.h>
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#include <arm64/xilinx/versal_slcr.h>
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struct versal_slcr_softc {
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device_t dev;
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struct mtx sc_mtx;
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struct resource *mem_res;
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};
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static struct versal_slcr_softc *versal_slcr_softc_p;
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#define RD4(sc, off) (bus_read_4((sc)->mem_res, (off)))
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#define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val)))
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SYSCTL_NODE(_hw, OID_AUTO, versal, CTLFLAG_RD, 0, "Xilinx Versal ACAP SLCR");
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#if defined(LIBBSP_AARCH64_XILINX_VERSAL_BSP_H)
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/* Override cgem_set_refclk() in gigabit ethernet driver
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* (sys/dev/cadence/if_cgem.c). This function is called to
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* request a change in the gem's reference clock speed.
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*/
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int
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cgem_set_ref_clk(int unit, int frequency)
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{
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struct versal_slcr_softc *sc = versal_slcr_softc_p;
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int div, last_error = 0;
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uint64_t clk_ctrl, pll_ctrl;
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uint32_t clk_ctrl_val, pll_ctrl_val, pll_freq, pll_reset, pll_bypass;
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if (!sc)
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return (-1);
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switch (unit) {
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case 0:
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clk_ctrl = VERSAL_SLCR_GEM0_CLK_CTRL;
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break;
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case 1:
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clk_ctrl = VERSAL_SLCR_GEM1_CLK_CTRL;
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break;
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default:
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return (-1);
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}
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clk_ctrl_val = RD4(sc, clk_ctrl);
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switch (clk_ctrl_val & VERSAL_SLCR_GEM_CLK_CTRL_SRCSEL_MASK) {
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case VERSAL_SLCR_GEM_CLK_CTRL_SRCSEL_P_PLL:
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pll_ctrl = VERSAL_SLCR_P_PLL_CTRL;
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break;
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case VERSAL_SLCR_GEM_CLK_CTRL_SRCSEL_R_PLL:
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pll_ctrl = VERSAL_SLCR_R_PLL_CTRL;
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break;
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case VERSAL_SLCR_GEM_CLK_CTRL_SRCSEL_N_PLL:
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pll_ctrl = VERSAL_SLCR_N_PLL_CTRL;
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break;
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default:
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return (-1);
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}
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/* Get PLL frequency */
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pll_ctrl_val = RD4(sc, pll_ctrl);
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pll_reset = (pll_ctrl_val & VERSAL_SLCR_PLL_CTRL_RESET) != 0;
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pll_bypass = (pll_ctrl_val & VERSAL_SLCR_PLL_CTRL_BYPASS) != 0;
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if (pll_reset && !pll_bypass) {
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return 0;
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}
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pll_freq = VERSAL_DEFAULT_PS_CLK_FREQUENCY;
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if (!pll_bypass) {
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pll_freq *= (pll_ctrl_val & VERSAL_SLCR_PLL_CTRL_FBDIV_MASK) >> VERSAL_SLCR_PLL_CTRL_FBDIV_SHIFT;
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}
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/* Apply divider */
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pll_freq >>= (pll_ctrl_val & VERSAL_SLCR_PLL_CTRL_DIV_MASK) >> VERSAL_SLCR_PLL_CTRL_DIV_SHIFT;
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/* Find suitable divisor. Linear search, not the fastest method but hey.
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*/
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for (div = 1; div <= VERSAL_SLCR_GEM_CLK_CTRL_DIVISOR_MAX; div++) {
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int div_freq = pll_freq / div;
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int error = abs(frequency - div_freq);
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if (error >= last_error && last_error != 0) {
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div--;
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break;
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}
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last_error = error;
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}
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if (div > VERSAL_SLCR_GEM_CLK_CTRL_DIVISOR_MAX)
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return (-1);
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/* Modify GEM reference clock. */
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clk_ctrl_val &= ~VERSAL_SLCR_GEM_CLK_CTRL_DIVISOR_MASK;
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clk_ctrl_val |= div << VERSAL_SLCR_GEM_CLK_CTRL_DIVISOR_SHIFT;
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WR4(sc, clk_ctrl, clk_ctrl_val);
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return (0);
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}
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#endif
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static int
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versal_slcr_probe(device_t dev)
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{
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device_set_desc(dev, "Versal ACAP SLCR block");
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return (0);
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}
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static int
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versal_slcr_attach(device_t dev)
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{
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struct versal_slcr_softc *sc = device_get_softc(dev);
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int rid;
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/* Allow only one attach. */
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if (versal_slcr_softc_p != NULL)
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return (ENXIO);
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sc->dev = dev;
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/* Get memory resource. */
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rid = 0;
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sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (sc->mem_res == NULL) {
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device_printf(dev, "could not allocate memory resources.\n");
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return (ENOMEM);
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}
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/* For use with CGEM clock setting */
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versal_slcr_softc_p = sc;
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return (0);
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}
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static int
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versal_slcr_detach(device_t dev)
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{
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struct versal_slcr_softc *sc = device_get_softc(dev);
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bus_generic_detach(dev);
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/* Release memory resource. */
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if (sc->mem_res != NULL)
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bus_release_resource(dev, SYS_RES_MEMORY,
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rman_get_rid(sc->mem_res), sc->mem_res);
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versal_slcr_softc_p = NULL;
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return (0);
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}
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static device_method_t versal_slcr_methods[] = {
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/* device_if */
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DEVMETHOD(device_probe, versal_slcr_probe),
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DEVMETHOD(device_attach, versal_slcr_attach),
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DEVMETHOD(device_detach, versal_slcr_detach),
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DEVMETHOD_END
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};
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static driver_t versal_slcr_driver = {
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"versal_slcr",
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versal_slcr_methods,
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sizeof(struct versal_slcr_softc),
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};
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static devclass_t versal_slcr_devclass;
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DRIVER_MODULE(versal_slcr, nexus, versal_slcr_driver, versal_slcr_devclass, 0, 0);
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MODULE_VERSION(versal_slcr, 1);
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86
rtemsbsd/sys/arm64/xilinx/versal_slcr.h
Normal file
86
rtemsbsd/sys/arm64/xilinx/versal_slcr.h
Normal file
@ -0,0 +1,86 @@
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2021 Chris Johns <chrisj@rtems.org>
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|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||||
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||||
|
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||||
|
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||||
|
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||||
|
* SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
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|
* Defines for Xilinx Versal ACAP SLCR registers.
|
||||||
|
*
|
||||||
|
* Reference:
|
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|
* https://www.xilinx.com/html_docs/registers/am012/mod___crl.html
|
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|
*/
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|
#ifndef _VERSAL_SLCR_H_
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#define _VERSAL_SLCR_H_
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#define VERSAL_SLCR_CRF_OFFSET 0x01260000
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#define VERSAL_SLCR_CRL_OFFSET 0x0f5e0000
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/*
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* PLL controls
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|
*
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* P = PPLL = PMCPLL = PMCPLL_CTRL : PMC PLL Clock
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* N = NPLL = NOCPLL = NOCPLL_CTRL : NOC PLL Clock
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* R = RPLL = RPLL_CTRL : Low Power Domain clock
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*/
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#define VERSAL_SLCR_P_PLL_CTRL (VERSAL_SLCR_CRF_OFFSET + 0x40)
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#define VERSAL_SLCR_N_PLL_CTRL (VERSAL_SLCR_CRF_OFFSET + 0x50)
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#define VERSAL_SLCR_R_PLL_CTRL (VERSAL_SLCR_CRL_OFFSET + 0x40)
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#define VERSAL_SLCR_PLL_CTRL_RESET (1<<0)
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#define VERSAL_SLCR_PLL_CTRL_BYPASS (1<<3)
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#define VERSAL_SLCR_PLL_CTRL_FBDIV_SHIFT 8
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#define VERSAL_SLCR_PLL_CTRL_FBDIV_MAX 0xff
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#define VERSAL_SLCR_PLL_CTRL_FBDIV_MASK (VERSAL_SLCR_PLL_CTRL_FBDIV_MAX<<8)
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#define VERSAL_SLCR_PLL_CTRL_DIV_SHIFT (16)
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#define VERSAL_SLCR_PLL_CTRL_DIV_MASK (0x3<<16)
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#define VERSAL_SLCR_PLL_CTRL_PRE_SRC_SHIFT 20
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#define VERSAL_SLCR_PLL_CTRL_PRE_SRC_MASK (0x7<<20)
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#define VERSAL_SLCR_PLL_CTRL_POST_SRC_SHIFT 24
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#define VERSAL_SLCR_PLL_CTRL_POST_SRC_MASK (0x7<<24)
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#define VERSAL_SLCR_PLL_CTRL_SRC_REF_CLK 0x0
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#define VERSAL_SLCR_PLL_CTRL_SRC_REF_CLK_MASK 0x2
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#define VERSAL_SLCR_PLL_CTRL_SRC_PL_PMC_ALT_REF_CLK_MASK 0x3
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/* Clock controls. */
|
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#define VERSAL_SLCR_GEM0_CLK_CTRL (VERSAL_SLCR_CRL_OFFSET + 0x118)
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#define VERSAL_SLCR_GEM1_CLK_CTRL (VERSAL_SLCR_CRL_OFFSET + 0x11c)
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#define VERSAL_SLCR_GEM_CLK_CTRL_CLKACT_RX (1<<27)
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#define VERSAL_SLCR_GEM_CLK_CTRL_CLKACT_TX (1<<26)
|
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#define VERSAL_SLCR_GEM_CLK_CTRL_CLKACT (1<<25)
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#define VERSAL_SLCR_GEM_CLK_CTRL_DIVISOR_MAX 0x3ff
|
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|
#define VERSAL_SLCR_GEM_CLK_CTRL_DIVISOR_MASK (VERSAL_SLCR_GEM_CLK_CTRL_DIVISOR_MAX<<8)
|
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|
#define VERSAL_SLCR_GEM_CLK_CTRL_DIVISOR_SHIFT 8
|
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|
#define VERSAL_SLCR_GEM_CLK_CTRL_SRCSEL_MASK (7<<0)
|
||||||
|
#define VERSAL_SLCR_GEM_CLK_CTRL_SRCSEL_P_PLL (0<<0)
|
||||||
|
#define VERSAL_SLCR_GEM_CLK_CTRL_SRCSEL_R_PLL (1<<0)
|
||||||
|
#define VERSAL_SLCR_GEM_CLK_CTRL_SRCSEL_N_PLL (3<<0)
|
||||||
|
|
||||||
|
#define VERSAL_DEFAULT_PS_CLK_FREQUENCY 33333333
|
||||||
|
|
||||||
|
#ifdef _KERNEL
|
||||||
|
extern int cgem_set_ref_clk(int unit, int frequency);
|
||||||
|
#endif
|
||||||
|
#endif /* _VERSAL_SLCR_H_ */
|
||||||
Loading…
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Reference in New Issue
Block a user