mirror of
https://git.rtems.org/rtems-libbsd/
synced 2025-10-14 07:15:58 +08:00
Added RealTek nic.
This commit is contained in:
Jennifer Averett
@@ -1 +1,750 @@
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/* EMPTY */
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/*-
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* Copyright (c) 1997, Stefan Esser <se@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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/*
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* PCIM_xxx: mask to locate subfield in register
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* PCIR_xxx: config register offset
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* PCIC_xxx: device class
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* PCIS_xxx: device subclass
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* PCIP_xxx: device programming interface
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* PCIV_xxx: PCI vendor ID (only required to fixup ancient devices)
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* PCID_xxx: device ID
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* PCIY_xxx: capability identification number
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* PCIZ_xxx: extended capability identification number
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*/
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/* some PCI bus constants */
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#define PCI_DOMAINMAX 65535 /* highest supported domain number */
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#define PCI_BUSMAX 255 /* highest supported bus number */
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#define PCI_SLOTMAX 31 /* highest supported slot number */
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#define PCI_FUNCMAX 7 /* highest supported function number */
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#define PCI_REGMAX 255 /* highest supported config register addr. */
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#define PCIE_REGMAX 4095 /* highest supported config register addr. */
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#define PCI_MAXHDRTYPE 2
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/* PCI config header registers for all devices */
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#define PCIR_DEVVENDOR 0x00
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#define PCIR_VENDOR 0x00
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#define PCIR_DEVICE 0x02
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#define PCIR_COMMAND 0x04
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#define PCIM_CMD_PORTEN 0x0001
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#define PCIM_CMD_MEMEN 0x0002
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#define PCIM_CMD_BUSMASTEREN 0x0004
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#define PCIM_CMD_SPECIALEN 0x0008
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#define PCIM_CMD_MWRICEN 0x0010
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#define PCIM_CMD_PERRESPEN 0x0040
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#define PCIM_CMD_SERRESPEN 0x0100
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#define PCIM_CMD_BACKTOBACK 0x0200
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#define PCIM_CMD_INTxDIS 0x0400
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#define PCIR_STATUS 0x06
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#define PCIM_STATUS_CAPPRESENT 0x0010
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#define PCIM_STATUS_66CAPABLE 0x0020
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#define PCIM_STATUS_BACKTOBACK 0x0080
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#define PCIM_STATUS_MDPERR 0x0100
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#define PCIM_STATUS_PERRREPORT PCIM_STATUS_MDPERR
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#define PCIM_STATUS_SEL_FAST 0x0000
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#define PCIM_STATUS_SEL_MEDIMUM 0x0200
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#define PCIM_STATUS_SEL_SLOW 0x0400
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#define PCIM_STATUS_SEL_MASK 0x0600
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#define PCIM_STATUS_STABORT 0x0800
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#define PCIM_STATUS_RTABORT 0x1000
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#define PCIM_STATUS_RMABORT 0x2000
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#define PCIM_STATUS_SERR 0x4000
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#define PCIM_STATUS_PERR 0x8000
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#define PCIR_REVID 0x08
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#define PCIR_PROGIF 0x09
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#define PCIR_SUBCLASS 0x0a
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#define PCIR_CLASS 0x0b
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#define PCIR_CACHELNSZ 0x0c
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#define PCIR_LATTIMER 0x0d
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#define PCIR_HDRTYPE 0x0e
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#define PCIM_HDRTYPE 0x7f
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#define PCIM_HDRTYPE_NORMAL 0x00
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#define PCIM_HDRTYPE_BRIDGE 0x01
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#define PCIM_HDRTYPE_CARDBUS 0x02
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#define PCIM_MFDEV 0x80
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#define PCIR_BIST 0x0f
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/* Capability Register Offsets */
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#define PCICAP_ID 0x0
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#define PCICAP_NEXTPTR 0x1
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/* Capability Identification Numbers */
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#define PCIY_PMG 0x01 /* PCI Power Management */
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#define PCIY_AGP 0x02 /* AGP */
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#define PCIY_VPD 0x03 /* Vital Product Data */
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#define PCIY_SLOTID 0x04 /* Slot Identification */
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#define PCIY_MSI 0x05 /* Message Signaled Interrupts */
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#define PCIY_CHSWP 0x06 /* CompactPCI Hot Swap */
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#define PCIY_PCIX 0x07 /* PCI-X */
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#define PCIY_HT 0x08 /* HyperTransport */
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#define PCIY_VENDOR 0x09 /* Vendor Unique */
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#define PCIY_DEBUG 0x0a /* Debug port */
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#define PCIY_CRES 0x0b /* CompactPCI central resource control */
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#define PCIY_HOTPLUG 0x0c /* PCI Hot-Plug */
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#define PCIY_SUBVENDOR 0x0d /* PCI-PCI bridge subvendor ID */
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#define PCIY_AGP8X 0x0e /* AGP 8x */
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#define PCIY_SECDEV 0x0f /* Secure Device */
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#define PCIY_EXPRESS 0x10 /* PCI Express */
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#define PCIY_MSIX 0x11 /* MSI-X */
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#define PCIY_SATA 0x12 /* SATA */
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#define PCIY_PCIAF 0x13 /* PCI Advanced Features */
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/* Extended Capability Register Fields */
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#define PCIR_EXTCAP 0x100
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#define PCIM_EXTCAP_ID 0x0000ffff
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#define PCIM_EXTCAP_VER 0x000f0000
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#define PCIM_EXTCAP_NEXTPTR 0xfff00000
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#define PCI_EXTCAP_ID(ecap) ((ecap) & PCIM_EXTCAP_ID)
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#define PCI_EXTCAP_VER(ecap) (((ecap) & PCIM_EXTCAP_VER) >> 16)
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#define PCI_EXTCAP_NEXTPTR(ecap) (((ecap) & PCIM_EXTCAP_NEXTPTR) >> 20)
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/* Extended Capability Identification Numbers */
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#define PCIZ_AER 0x0001 /* Advanced Error Reporting */
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#define PCIZ_VC 0x0002 /* Virtual Channel */
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#define PCIZ_SERNUM 0x0003 /* Device Serial Number */
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#define PCIZ_PWRBDGT 0x0004 /* Power Budgeting */
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#define PCIZ_VENDOR 0x000b /* Vendor Unique */
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#define PCIZ_ACS 0x000d /* Access Control Services */
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#define PCIZ_ARI 0x000e /* Alternative Routing-ID Interpretation */
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#define PCIZ_ATS 0x000f /* Address Translation Services */
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#define PCIZ_SRIOV 0x0010 /* Single Root IO Virtualization */
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/* config registers for header type 0 devices */
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#define PCIR_BARS 0x10
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#define PCIR_BAR(x) (PCIR_BARS + (x) * 4)
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#define PCIR_MAX_BAR_0 5
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#define PCI_RID2BAR(rid) (((rid) - PCIR_BARS) / 4)
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#define PCI_BAR_IO(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE)
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#define PCI_BAR_MEM(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_MEM_SPACE)
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#define PCIM_BAR_SPACE 0x00000001
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#define PCIM_BAR_MEM_SPACE 0
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#define PCIM_BAR_IO_SPACE 1
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#define PCIM_BAR_MEM_TYPE 0x00000006
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#define PCIM_BAR_MEM_32 0
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#define PCIM_BAR_MEM_1MB 2 /* Locate below 1MB in PCI <= 2.1 */
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#define PCIM_BAR_MEM_64 4
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#define PCIM_BAR_MEM_PREFETCH 0x00000008
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#define PCIM_BAR_MEM_BASE 0xfffffffffffffff0ULL
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#define PCIM_BAR_IO_RESERVED 0x00000002
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#define PCIM_BAR_IO_BASE 0xfffffffc
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#define PCIR_CIS 0x28
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#define PCIM_CIS_ASI_MASK 0x00000007
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#define PCIM_CIS_ASI_CONFIG 0
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#define PCIM_CIS_ASI_BAR0 1
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#define PCIM_CIS_ASI_BAR1 2
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#define PCIM_CIS_ASI_BAR2 3
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#define PCIM_CIS_ASI_BAR3 4
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#define PCIM_CIS_ASI_BAR4 5
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#define PCIM_CIS_ASI_BAR5 6
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#define PCIM_CIS_ASI_ROM 7
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#define PCIM_CIS_ADDR_MASK 0x0ffffff8
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#define PCIM_CIS_ROM_MASK 0xf0000000
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#define PCIM_CIS_CONFIG_MASK 0xff
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#define PCIR_SUBVEND_0 0x2c
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#define PCIR_SUBDEV_0 0x2e
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#define PCIR_BIOS 0x30
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#define PCIM_BIOS_ENABLE 0x01
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#define PCIM_BIOS_ADDR_MASK 0xfffff800
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#define PCIR_CAP_PTR 0x34
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#define PCIR_INTLINE 0x3c
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#define PCIR_INTPIN 0x3d
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#define PCIR_MINGNT 0x3e
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#define PCIR_MAXLAT 0x3f
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/* config registers for header type 1 (PCI-to-PCI bridge) devices */
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#define PCIR_MAX_BAR_1 1
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#define PCIR_SECSTAT_1 0x1e
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#define PCIR_PRIBUS_1 0x18
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#define PCIR_SECBUS_1 0x19
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#define PCIR_SUBBUS_1 0x1a
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#define PCIR_SECLAT_1 0x1b
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#define PCIR_IOBASEL_1 0x1c
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#define PCIR_IOLIMITL_1 0x1d
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#define PCIR_IOBASEH_1 0x30
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#define PCIR_IOLIMITH_1 0x32
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#define PCIM_BRIO_16 0x0
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#define PCIM_BRIO_32 0x1
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#define PCIM_BRIO_MASK 0xf
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#define PCIR_MEMBASE_1 0x20
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#define PCIR_MEMLIMIT_1 0x22
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#define PCIR_PMBASEL_1 0x24
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#define PCIR_PMLIMITL_1 0x26
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#define PCIR_PMBASEH_1 0x28
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#define PCIR_PMLIMITH_1 0x2c
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#define PCIM_BRPM_32 0x0
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#define PCIM_BRPM_64 0x1
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#define PCIM_BRPM_MASK 0xf
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#define PCIR_BRIDGECTL_1 0x3e
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/* config registers for header type 2 (CardBus) devices */
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#define PCIR_MAX_BAR_2 0
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#define PCIR_CAP_PTR_2 0x14
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#define PCIR_SECSTAT_2 0x16
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#define PCIR_PRIBUS_2 0x18
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#define PCIR_SECBUS_2 0x19
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#define PCIR_SUBBUS_2 0x1a
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#define PCIR_SECLAT_2 0x1b
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#define PCIR_MEMBASE0_2 0x1c
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#define PCIR_MEMLIMIT0_2 0x20
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#define PCIR_MEMBASE1_2 0x24
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#define PCIR_MEMLIMIT1_2 0x28
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#define PCIR_IOBASE0_2 0x2c
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#define PCIR_IOLIMIT0_2 0x30
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#define PCIR_IOBASE1_2 0x34
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#define PCIR_IOLIMIT1_2 0x38
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#define PCIR_BRIDGECTL_2 0x3e
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#define PCIR_SUBVEND_2 0x40
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#define PCIR_SUBDEV_2 0x42
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#define PCIR_PCCARDIF_2 0x44
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/* PCI device class, subclass and programming interface definitions */
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#define PCIC_OLD 0x00
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#define PCIS_OLD_NONVGA 0x00
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#define PCIS_OLD_VGA 0x01
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#define PCIC_STORAGE 0x01
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#define PCIS_STORAGE_SCSI 0x00
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#define PCIS_STORAGE_IDE 0x01
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#define PCIP_STORAGE_IDE_MODEPRIM 0x01
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#define PCIP_STORAGE_IDE_PROGINDPRIM 0x02
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#define PCIP_STORAGE_IDE_MODESEC 0x04
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#define PCIP_STORAGE_IDE_PROGINDSEC 0x08
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#define PCIP_STORAGE_IDE_MASTERDEV 0x80
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#define PCIS_STORAGE_FLOPPY 0x02
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#define PCIS_STORAGE_IPI 0x03
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#define PCIS_STORAGE_RAID 0x04
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#define PCIS_STORAGE_ATA_ADMA 0x05
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#define PCIS_STORAGE_SATA 0x06
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#define PCIP_STORAGE_SATA_AHCI_1_0 0x01
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#define PCIS_STORAGE_SAS 0x07
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#define PCIS_STORAGE_OTHER 0x80
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#define PCIC_NETWORK 0x02
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#define PCIS_NETWORK_ETHERNET 0x00
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#define PCIS_NETWORK_TOKENRING 0x01
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#define PCIS_NETWORK_FDDI 0x02
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#define PCIS_NETWORK_ATM 0x03
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#define PCIS_NETWORK_ISDN 0x04
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#define PCIS_NETWORK_WORLDFIP 0x05
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#define PCIS_NETWORK_PICMG 0x06
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#define PCIS_NETWORK_OTHER 0x80
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#define PCIC_DISPLAY 0x03
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#define PCIS_DISPLAY_VGA 0x00
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#define PCIS_DISPLAY_XGA 0x01
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#define PCIS_DISPLAY_3D 0x02
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#define PCIS_DISPLAY_OTHER 0x80
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#define PCIC_MULTIMEDIA 0x04
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#define PCIS_MULTIMEDIA_VIDEO 0x00
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#define PCIS_MULTIMEDIA_AUDIO 0x01
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#define PCIS_MULTIMEDIA_TELE 0x02
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#define PCIS_MULTIMEDIA_HDA 0x03
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#define PCIS_MULTIMEDIA_OTHER 0x80
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#define PCIC_MEMORY 0x05
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#define PCIS_MEMORY_RAM 0x00
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#define PCIS_MEMORY_FLASH 0x01
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#define PCIS_MEMORY_OTHER 0x80
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#define PCIC_BRIDGE 0x06
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#define PCIS_BRIDGE_HOST 0x00
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#define PCIS_BRIDGE_ISA 0x01
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#define PCIS_BRIDGE_EISA 0x02
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#define PCIS_BRIDGE_MCA 0x03
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#define PCIS_BRIDGE_PCI 0x04
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#define PCIP_BRIDGE_PCI_SUBTRACTIVE 0x01
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#define PCIS_BRIDGE_PCMCIA 0x05
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#define PCIS_BRIDGE_NUBUS 0x06
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#define PCIS_BRIDGE_CARDBUS 0x07
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#define PCIS_BRIDGE_RACEWAY 0x08
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#define PCIS_BRIDGE_PCI_TRANSPARENT 0x09
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#define PCIS_BRIDGE_INFINIBAND 0x0a
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#define PCIS_BRIDGE_OTHER 0x80
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#define PCIC_SIMPLECOMM 0x07
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#define PCIS_SIMPLECOMM_UART 0x00
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#define PCIP_SIMPLECOMM_UART_8250 0x00
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#define PCIP_SIMPLECOMM_UART_16450A 0x01
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#define PCIP_SIMPLECOMM_UART_16550A 0x02
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#define PCIP_SIMPLECOMM_UART_16650A 0x03
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#define PCIP_SIMPLECOMM_UART_16750A 0x04
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#define PCIP_SIMPLECOMM_UART_16850A 0x05
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#define PCIP_SIMPLECOMM_UART_16950A 0x06
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#define PCIS_SIMPLECOMM_PAR 0x01
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#define PCIS_SIMPLECOMM_MULSER 0x02
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#define PCIS_SIMPLECOMM_MODEM 0x03
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#define PCIS_SIMPLECOMM_GPIB 0x04
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#define PCIS_SIMPLECOMM_SMART_CARD 0x05
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#define PCIS_SIMPLECOMM_OTHER 0x80
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#define PCIC_BASEPERIPH 0x08
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#define PCIS_BASEPERIPH_PIC 0x00
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#define PCIP_BASEPERIPH_PIC_8259A 0x00
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#define PCIP_BASEPERIPH_PIC_ISA 0x01
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#define PCIP_BASEPERIPH_PIC_EISA 0x02
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#define PCIP_BASEPERIPH_PIC_IO_APIC 0x10
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#define PCIP_BASEPERIPH_PIC_IOX_APIC 0x20
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#define PCIS_BASEPERIPH_DMA 0x01
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#define PCIS_BASEPERIPH_TIMER 0x02
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#define PCIS_BASEPERIPH_RTC 0x03
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#define PCIS_BASEPERIPH_PCIHOT 0x04
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#define PCIS_BASEPERIPH_SDHC 0x05
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#define PCIS_BASEPERIPH_OTHER 0x80
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|
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#define PCIC_INPUTDEV 0x09
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#define PCIS_INPUTDEV_KEYBOARD 0x00
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#define PCIS_INPUTDEV_DIGITIZER 0x01
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#define PCIS_INPUTDEV_MOUSE 0x02
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#define PCIS_INPUTDEV_SCANNER 0x03
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#define PCIS_INPUTDEV_GAMEPORT 0x04
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#define PCIS_INPUTDEV_OTHER 0x80
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|
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#define PCIC_DOCKING 0x0a
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#define PCIS_DOCKING_GENERIC 0x00
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||||
#define PCIS_DOCKING_OTHER 0x80
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||||
|
||||
#define PCIC_PROCESSOR 0x0b
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#define PCIS_PROCESSOR_386 0x00
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||||
#define PCIS_PROCESSOR_486 0x01
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#define PCIS_PROCESSOR_PENTIUM 0x02
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#define PCIS_PROCESSOR_ALPHA 0x10
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||||
#define PCIS_PROCESSOR_POWERPC 0x20
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#define PCIS_PROCESSOR_MIPS 0x30
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#define PCIS_PROCESSOR_COPROC 0x40
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|
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#define PCIC_SERIALBUS 0x0c
|
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#define PCIS_SERIALBUS_FW 0x00
|
||||
#define PCIS_SERIALBUS_ACCESS 0x01
|
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#define PCIS_SERIALBUS_SSA 0x02
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#define PCIS_SERIALBUS_USB 0x03
|
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#define PCIP_SERIALBUS_USB_UHCI 0x00
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||||
#define PCIP_SERIALBUS_USB_OHCI 0x10
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#define PCIP_SERIALBUS_USB_EHCI 0x20
|
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#define PCIP_SERIALBUS_USB_DEVICE 0xfe
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#define PCIS_SERIALBUS_FC 0x04
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#define PCIS_SERIALBUS_SMBUS 0x05
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#define PCIS_SERIALBUS_INFINIBAND 0x06
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#define PCIS_SERIALBUS_IPMI 0x07
|
||||
#define PCIP_SERIALBUS_IPMI_SMIC 0x00
|
||||
#define PCIP_SERIALBUS_IPMI_KCS 0x01
|
||||
#define PCIP_SERIALBUS_IPMI_BT 0x02
|
||||
#define PCIS_SERIALBUS_SERCOS 0x08
|
||||
#define PCIS_SERIALBUS_CANBUS 0x09
|
||||
|
||||
#define PCIC_WIRELESS 0x0d
|
||||
#define PCIS_WIRELESS_IRDA 0x00
|
||||
#define PCIS_WIRELESS_IR 0x01
|
||||
#define PCIS_WIRELESS_RF 0x10
|
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#define PCIS_WIRELESS_BLUETOOTH 0x11
|
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#define PCIS_WIRELESS_BROADBAND 0x12
|
||||
#define PCIS_WIRELESS_80211A 0x20
|
||||
#define PCIS_WIRELESS_80211B 0x21
|
||||
#define PCIS_WIRELESS_OTHER 0x80
|
||||
|
||||
#define PCIC_INTELLIIO 0x0e
|
||||
#define PCIS_INTELLIIO_I2O 0x00
|
||||
|
||||
#define PCIC_SATCOM 0x0f
|
||||
#define PCIS_SATCOM_TV 0x01
|
||||
#define PCIS_SATCOM_AUDIO 0x02
|
||||
#define PCIS_SATCOM_VOICE 0x03
|
||||
#define PCIS_SATCOM_DATA 0x04
|
||||
|
||||
#define PCIC_CRYPTO 0x10
|
||||
#define PCIS_CRYPTO_NETCOMP 0x00
|
||||
#define PCIS_CRYPTO_ENTERTAIN 0x10
|
||||
#define PCIS_CRYPTO_OTHER 0x80
|
||||
|
||||
#define PCIC_DASP 0x11
|
||||
#define PCIS_DASP_DPIO 0x00
|
||||
#define PCIS_DASP_PERFCNTRS 0x01
|
||||
#define PCIS_DASP_COMM_SYNC 0x10
|
||||
#define PCIS_DASP_MGMT_CARD 0x20
|
||||
#define PCIS_DASP_OTHER 0x80
|
||||
|
||||
#define PCIC_OTHER 0xff
|
||||
|
||||
/* Bridge Control Values. */
|
||||
#define PCIB_BCR_PERR_ENABLE 0x0001
|
||||
#define PCIB_BCR_SERR_ENABLE 0x0002
|
||||
#define PCIB_BCR_ISA_ENABLE 0x0004
|
||||
#define PCIB_BCR_VGA_ENABLE 0x0008
|
||||
#define PCIB_BCR_MASTER_ABORT_MODE 0x0020
|
||||
#define PCIB_BCR_SECBUS_RESET 0x0040
|
||||
#define PCIB_BCR_SECBUS_BACKTOBACK 0x0080
|
||||
#define PCIB_BCR_PRI_DISCARD_TIMEOUT 0x0100
|
||||
#define PCIB_BCR_SEC_DISCARD_TIMEOUT 0x0200
|
||||
#define PCIB_BCR_DISCARD_TIMER_STATUS 0x0400
|
||||
#define PCIB_BCR_DISCARD_TIMER_SERREN 0x0800
|
||||
|
||||
/* PCI power manangement */
|
||||
#define PCIR_POWER_CAP 0x2
|
||||
#define PCIM_PCAP_SPEC 0x0007
|
||||
#define PCIM_PCAP_PMEREQCLK 0x0008
|
||||
#define PCIM_PCAP_PMEREQPWR 0x0010
|
||||
#define PCIM_PCAP_DEVSPECINIT 0x0020
|
||||
#define PCIM_PCAP_DYNCLOCK 0x0040
|
||||
#define PCIM_PCAP_SECCLOCK 0x00c0
|
||||
#define PCIM_PCAP_CLOCKMASK 0x00c0
|
||||
#define PCIM_PCAP_REQFULLCLOCK 0x0100
|
||||
#define PCIM_PCAP_D1SUPP 0x0200
|
||||
#define PCIM_PCAP_D2SUPP 0x0400
|
||||
#define PCIM_PCAP_D0PME 0x0800
|
||||
#define PCIM_PCAP_D1PME 0x1000
|
||||
#define PCIM_PCAP_D2PME 0x2000
|
||||
#define PCIM_PCAP_D3PME_HOT 0x4000
|
||||
#define PCIM_PCAP_D3PME_COLD 0x8000
|
||||
|
||||
#define PCIR_POWER_STATUS 0x4
|
||||
#define PCIM_PSTAT_D0 0x0000
|
||||
#define PCIM_PSTAT_D1 0x0001
|
||||
#define PCIM_PSTAT_D2 0x0002
|
||||
#define PCIM_PSTAT_D3 0x0003
|
||||
#define PCIM_PSTAT_DMASK 0x0003
|
||||
#define PCIM_PSTAT_REPENABLE 0x0010
|
||||
#define PCIM_PSTAT_PMEENABLE 0x0100
|
||||
#define PCIM_PSTAT_D0POWER 0x0000
|
||||
#define PCIM_PSTAT_D1POWER 0x0200
|
||||
#define PCIM_PSTAT_D2POWER 0x0400
|
||||
#define PCIM_PSTAT_D3POWER 0x0600
|
||||
#define PCIM_PSTAT_D0HEAT 0x0800
|
||||
#define PCIM_PSTAT_D1HEAT 0x1000
|
||||
#define PCIM_PSTAT_D2HEAT 0x1200
|
||||
#define PCIM_PSTAT_D3HEAT 0x1400
|
||||
#define PCIM_PSTAT_DATAUNKN 0x0000
|
||||
#define PCIM_PSTAT_DATADIV10 0x2000
|
||||
#define PCIM_PSTAT_DATADIV100 0x4000
|
||||
#define PCIM_PSTAT_DATADIV1000 0x6000
|
||||
#define PCIM_PSTAT_DATADIVMASK 0x6000
|
||||
#define PCIM_PSTAT_PME 0x8000
|
||||
|
||||
#define PCIR_POWER_PMCSR 0x6
|
||||
#define PCIM_PMCSR_DCLOCK 0x10
|
||||
#define PCIM_PMCSR_B2SUPP 0x20
|
||||
#define PCIM_BMCSR_B3SUPP 0x40
|
||||
#define PCIM_BMCSR_BPCE 0x80
|
||||
|
||||
#define PCIR_POWER_DATA 0x7
|
||||
|
||||
/* VPD capability registers */
|
||||
#define PCIR_VPD_ADDR 0x2
|
||||
#define PCIR_VPD_DATA 0x4
|
||||
|
||||
/* PCI Message Signalled Interrupts (MSI) */
|
||||
#define PCIR_MSI_CTRL 0x2
|
||||
#define PCIM_MSICTRL_VECTOR 0x0100
|
||||
#define PCIM_MSICTRL_64BIT 0x0080
|
||||
#define PCIM_MSICTRL_MME_MASK 0x0070
|
||||
#define PCIM_MSICTRL_MME_1 0x0000
|
||||
#define PCIM_MSICTRL_MME_2 0x0010
|
||||
#define PCIM_MSICTRL_MME_4 0x0020
|
||||
#define PCIM_MSICTRL_MME_8 0x0030
|
||||
#define PCIM_MSICTRL_MME_16 0x0040
|
||||
#define PCIM_MSICTRL_MME_32 0x0050
|
||||
#define PCIM_MSICTRL_MMC_MASK 0x000E
|
||||
#define PCIM_MSICTRL_MMC_1 0x0000
|
||||
#define PCIM_MSICTRL_MMC_2 0x0002
|
||||
#define PCIM_MSICTRL_MMC_4 0x0004
|
||||
#define PCIM_MSICTRL_MMC_8 0x0006
|
||||
#define PCIM_MSICTRL_MMC_16 0x0008
|
||||
#define PCIM_MSICTRL_MMC_32 0x000A
|
||||
#define PCIM_MSICTRL_MSI_ENABLE 0x0001
|
||||
#define PCIR_MSI_ADDR 0x4
|
||||
#define PCIR_MSI_ADDR_HIGH 0x8
|
||||
#define PCIR_MSI_DATA 0x8
|
||||
#define PCIR_MSI_DATA_64BIT 0xc
|
||||
#define PCIR_MSI_MASK 0x10
|
||||
#define PCIR_MSI_PENDING 0x14
|
||||
|
||||
/* PCI-X definitions */
|
||||
|
||||
/* For header type 0 devices */
|
||||
#define PCIXR_COMMAND 0x2
|
||||
#define PCIXM_COMMAND_DPERR_E 0x0001 /* Data Parity Error Recovery */
|
||||
#define PCIXM_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */
|
||||
#define PCIXM_COMMAND_MAX_READ 0x000c /* Maximum Burst Read Count */
|
||||
#define PCIXM_COMMAND_MAX_READ_512 0x0000
|
||||
#define PCIXM_COMMAND_MAX_READ_1024 0x0004
|
||||
#define PCIXM_COMMAND_MAX_READ_2048 0x0008
|
||||
#define PCIXM_COMMAND_MAX_READ_4096 0x000c
|
||||
#define PCIXM_COMMAND_MAX_SPLITS 0x0070 /* Maximum Split Transactions */
|
||||
#define PCIXM_COMMAND_MAX_SPLITS_1 0x0000
|
||||
#define PCIXM_COMMAND_MAX_SPLITS_2 0x0010
|
||||
#define PCIXM_COMMAND_MAX_SPLITS_3 0x0020
|
||||
#define PCIXM_COMMAND_MAX_SPLITS_4 0x0030
|
||||
#define PCIXM_COMMAND_MAX_SPLITS_8 0x0040
|
||||
#define PCIXM_COMMAND_MAX_SPLITS_12 0x0050
|
||||
#define PCIXM_COMMAND_MAX_SPLITS_16 0x0060
|
||||
#define PCIXM_COMMAND_MAX_SPLITS_32 0x0070
|
||||
#define PCIXM_COMMAND_VERSION 0x3000
|
||||
#define PCIXR_STATUS 0x4
|
||||
#define PCIXM_STATUS_DEVFN 0x000000FF
|
||||
#define PCIXM_STATUS_BUS 0x0000FF00
|
||||
#define PCIXM_STATUS_64BIT 0x00010000
|
||||
#define PCIXM_STATUS_133CAP 0x00020000
|
||||
#define PCIXM_STATUS_SC_DISCARDED 0x00040000
|
||||
#define PCIXM_STATUS_UNEXP_SC 0x00080000
|
||||
#define PCIXM_STATUS_COMPLEX_DEV 0x00100000
|
||||
#define PCIXM_STATUS_MAX_READ 0x00600000
|
||||
#define PCIXM_STATUS_MAX_READ_512 0x00000000
|
||||
#define PCIXM_STATUS_MAX_READ_1024 0x00200000
|
||||
#define PCIXM_STATUS_MAX_READ_2048 0x00400000
|
||||
#define PCIXM_STATUS_MAX_READ_4096 0x00600000
|
||||
#define PCIXM_STATUS_MAX_SPLITS 0x03800000
|
||||
#define PCIXM_STATUS_MAX_SPLITS_1 0x00000000
|
||||
#define PCIXM_STATUS_MAX_SPLITS_2 0x00800000
|
||||
#define PCIXM_STATUS_MAX_SPLITS_3 0x01000000
|
||||
#define PCIXM_STATUS_MAX_SPLITS_4 0x01800000
|
||||
#define PCIXM_STATUS_MAX_SPLITS_8 0x02000000
|
||||
#define PCIXM_STATUS_MAX_SPLITS_12 0x02800000
|
||||
#define PCIXM_STATUS_MAX_SPLITS_16 0x03000000
|
||||
#define PCIXM_STATUS_MAX_SPLITS_32 0x03800000
|
||||
#define PCIXM_STATUS_MAX_CUM_READ 0x1C000000
|
||||
#define PCIXM_STATUS_RCVD_SC_ERR 0x20000000
|
||||
#define PCIXM_STATUS_266CAP 0x40000000
|
||||
#define PCIXM_STATUS_533CAP 0x80000000
|
||||
|
||||
/* For header type 1 devices (PCI-X bridges) */
|
||||
#define PCIXR_SEC_STATUS 0x2
|
||||
#define PCIXM_SEC_STATUS_64BIT 0x0001
|
||||
#define PCIXM_SEC_STATUS_133CAP 0x0002
|
||||
#define PCIXM_SEC_STATUS_SC_DISC 0x0004
|
||||
#define PCIXM_SEC_STATUS_UNEXP_SC 0x0008
|
||||
#define PCIXM_SEC_STATUS_SC_OVERRUN 0x0010
|
||||
#define PCIXM_SEC_STATUS_SR_DELAYED 0x0020
|
||||
#define PCIXM_SEC_STATUS_BUS_MODE 0x03c0
|
||||
#define PCIXM_SEC_STATUS_VERSION 0x3000
|
||||
#define PCIXM_SEC_STATUS_266CAP 0x4000
|
||||
#define PCIXM_SEC_STATUS_533CAP 0x8000
|
||||
#define PCIXR_BRIDGE_STATUS 0x4
|
||||
#define PCIXM_BRIDGE_STATUS_DEVFN 0x000000FF
|
||||
#define PCIXM_BRIDGE_STATUS_BUS 0x0000FF00
|
||||
#define PCIXM_BRIDGE_STATUS_64BIT 0x00010000
|
||||
#define PCIXM_BRIDGE_STATUS_133CAP 0x00020000
|
||||
#define PCIXM_BRIDGE_STATUS_SC_DISCARDED 0x00040000
|
||||
#define PCIXM_BRIDGE_STATUS_UNEXP_SC 0x00080000
|
||||
#define PCIXM_BRIDGE_STATUS_SC_OVERRUN 0x00100000
|
||||
#define PCIXM_BRIDGE_STATUS_SR_DELAYED 0x00200000
|
||||
#define PCIXM_BRIDGE_STATUS_DEVID_MSGCAP 0x20000000
|
||||
#define PCIXM_BRIDGE_STATUS_266CAP 0x40000000
|
||||
#define PCIXM_BRIDGE_STATUS_533CAP 0x80000000
|
||||
|
||||
/* HT (HyperTransport) Capability definitions */
|
||||
#define PCIR_HT_COMMAND 0x2
|
||||
#define PCIM_HTCMD_CAP_MASK 0xf800 /* Capability type. */
|
||||
#define PCIM_HTCAP_SLAVE 0x0000 /* 000xx */
|
||||
#define PCIM_HTCAP_HOST 0x2000 /* 001xx */
|
||||
#define PCIM_HTCAP_SWITCH 0x4000 /* 01000 */
|
||||
#define PCIM_HTCAP_INTERRUPT 0x8000 /* 10000 */
|
||||
#define PCIM_HTCAP_REVISION_ID 0x8800 /* 10001 */
|
||||
#define PCIM_HTCAP_UNITID_CLUMPING 0x9000 /* 10010 */
|
||||
#define PCIM_HTCAP_EXT_CONFIG_SPACE 0x9800 /* 10011 */
|
||||
#define PCIM_HTCAP_ADDRESS_MAPPING 0xa000 /* 10100 */
|
||||
#define PCIM_HTCAP_MSI_MAPPING 0xa800 /* 10101 */
|
||||
#define PCIM_HTCAP_DIRECT_ROUTE 0xb000 /* 10110 */
|
||||
#define PCIM_HTCAP_VCSET 0xb800 /* 10111 */
|
||||
#define PCIM_HTCAP_RETRY_MODE 0xc000 /* 11000 */
|
||||
#define PCIM_HTCAP_X86_ENCODING 0xc800 /* 11001 */
|
||||
|
||||
/* HT MSI Mapping Capability definitions. */
|
||||
#define PCIM_HTCMD_MSI_ENABLE 0x0001
|
||||
#define PCIM_HTCMD_MSI_FIXED 0x0002
|
||||
#define PCIR_HTMSI_ADDRESS_LO 0x4
|
||||
#define PCIR_HTMSI_ADDRESS_HI 0x8
|
||||
|
||||
/* PCI Vendor capability definitions */
|
||||
#define PCIR_VENDOR_LENGTH 0x2
|
||||
#define PCIR_VENDOR_DATA 0x3
|
||||
|
||||
/* PCI EHCI Debug Port definitions */
|
||||
#define PCIR_DEBUG_PORT 0x2
|
||||
#define PCIM_DEBUG_PORT_OFFSET 0x1FFF
|
||||
#define PCIM_DEBUG_PORT_BAR 0xe000
|
||||
|
||||
/* PCI-PCI Bridge Subvendor definitions */
|
||||
#define PCIR_SUBVENDCAP_ID 0x4
|
||||
|
||||
/* PCI Express definitions */
|
||||
#define PCIR_EXPRESS_FLAGS 0x2
|
||||
#define PCIM_EXP_FLAGS_VERSION 0x000F
|
||||
#define PCIM_EXP_FLAGS_TYPE 0x00F0
|
||||
#define PCIM_EXP_TYPE_ENDPOINT 0x0000
|
||||
#define PCIM_EXP_TYPE_LEGACY_ENDPOINT 0x0010
|
||||
#define PCIM_EXP_TYPE_ROOT_PORT 0x0040
|
||||
#define PCIM_EXP_TYPE_UPSTREAM_PORT 0x0050
|
||||
#define PCIM_EXP_TYPE_DOWNSTREAM_PORT 0x0060
|
||||
#define PCIM_EXP_TYPE_PCI_BRIDGE 0x0070
|
||||
#define PCIM_EXP_TYPE_PCIE_BRIDGE 0x0080
|
||||
#define PCIM_EXP_TYPE_ROOT_INT_EP 0x0090
|
||||
#define PCIM_EXP_TYPE_ROOT_EC 0x00a0
|
||||
#define PCIM_EXP_FLAGS_SLOT 0x0100
|
||||
#define PCIM_EXP_FLAGS_IRQ 0x3e00
|
||||
#define PCIR_EXPRESS_DEVICE_CAP 0x4
|
||||
#define PCIM_EXP_CAP_MAX_PAYLOAD 0x0007
|
||||
#define PCIR_EXPRESS_DEVICE_CTL 0x8
|
||||
#define PCIM_EXP_CTL_NFER_ENABLE 0x0002
|
||||
#define PCIM_EXP_CTL_FER_ENABLE 0x0004
|
||||
#define PCIM_EXP_CTL_URR_ENABLE 0x0008
|
||||
#define PCIM_EXP_CTL_RELAXED_ORD_ENABLE 0x0010
|
||||
#define PCIM_EXP_CTL_MAX_PAYLOAD 0x00e0
|
||||
#define PCIM_EXP_CTL_NOSNOOP_ENABLE 0x0800
|
||||
#define PCIM_EXP_CTL_MAX_READ_REQUEST 0x7000
|
||||
#define PCIR_EXPRESS_DEVICE_STA 0xa
|
||||
#define PCIM_EXP_STA_CORRECTABLE_ERROR 0x0001
|
||||
#define PCIM_EXP_STA_NON_FATAL_ERROR 0x0002
|
||||
#define PCIM_EXP_STA_FATAL_ERROR 0x0004
|
||||
#define PCIM_EXP_STA_UNSUPPORTED_REQ 0x0008
|
||||
#define PCIM_EXP_STA_AUX_POWER 0x0010
|
||||
#define PCIM_EXP_STA_TRANSACTION_PND 0x0020
|
||||
#define PCIR_EXPRESS_LINK_CAP 0xc
|
||||
#define PCIM_LINK_CAP_MAX_SPEED 0x0000000f
|
||||
#define PCIM_LINK_CAP_MAX_WIDTH 0x000003f0
|
||||
#define PCIM_LINK_CAP_ASPM 0x00000c00
|
||||
#define PCIM_LINK_CAP_L0S_EXIT 0x00007000
|
||||
#define PCIM_LINK_CAP_L1_EXIT 0x00038000
|
||||
#define PCIM_LINK_CAP_PORT 0xff000000
|
||||
#define PCIR_EXPRESS_LINK_CTL 0x10
|
||||
#define PCIR_EXPRESS_LINK_STA 0x12
|
||||
#define PCIM_LINK_STA_SPEED 0x000f
|
||||
#define PCIM_LINK_STA_WIDTH 0x03f0
|
||||
#define PCIM_LINK_STA_TRAINING_ERROR 0x0400
|
||||
#define PCIM_LINK_STA_TRAINING 0x0800
|
||||
#define PCIM_LINK_STA_SLOT_CLOCK 0x1000
|
||||
#define PCIR_EXPRESS_SLOT_CAP 0x14
|
||||
#define PCIR_EXPRESS_SLOT_CTL 0x18
|
||||
#define PCIR_EXPRESS_SLOT_STA 0x1a
|
||||
#define PCIR_EXPRESS_ROOT_CTL 0x1c
|
||||
#define PCIR_EXPRESS_ROOT_STA 0x20
|
||||
|
||||
/* MSI-X definitions */
|
||||
#define PCIR_MSIX_CTRL 0x2
|
||||
#define PCIM_MSIXCTRL_MSIX_ENABLE 0x8000
|
||||
#define PCIM_MSIXCTRL_FUNCTION_MASK 0x4000
|
||||
#define PCIM_MSIXCTRL_TABLE_SIZE 0x07FF
|
||||
#define PCIR_MSIX_TABLE 0x4
|
||||
#define PCIR_MSIX_PBA 0x8
|
||||
#define PCIM_MSIX_BIR_MASK 0x7
|
||||
#define PCIM_MSIX_BIR_BAR_10 0
|
||||
#define PCIM_MSIX_BIR_BAR_14 1
|
||||
#define PCIM_MSIX_BIR_BAR_18 2
|
||||
#define PCIM_MSIX_BIR_BAR_1C 3
|
||||
#define PCIM_MSIX_BIR_BAR_20 4
|
||||
#define PCIM_MSIX_BIR_BAR_24 5
|
||||
#define PCIM_MSIX_VCTRL_MASK 0x1
|
||||
|
||||
/* PCI Advanced Features definitions */
|
||||
#define PCIR_PCIAF_CAP 0x3
|
||||
#define PCIM_PCIAFCAP_TP 0x01
|
||||
#define PCIM_PCIAFCAP_FLR 0x02
|
||||
#define PCIR_PCIAF_CTRL 0x4
|
||||
#define PCIR_PCIAFCTRL_FLR 0x01
|
||||
#define PCIR_PCIAF_STATUS 0x5
|
||||
#define PCIR_PCIAFSTATUS_TP 0x01
|
||||
|
||||
/* Advanced Error Reporting */
|
||||
#define PCIR_AER_UC_STATUS 0x04
|
||||
#define PCIM_AER_UC_TRAINING_ERROR 0x00000001
|
||||
#define PCIM_AER_UC_DL_PROTOCOL_ERROR 0x00000010
|
||||
#define PCIM_AER_UC_POISONED_TLP 0x00001000
|
||||
#define PCIM_AER_UC_FC_PROTOCOL_ERROR 0x00002000
|
||||
#define PCIM_AER_UC_COMPLETION_TIMEOUT 0x00004000
|
||||
#define PCIM_AER_UC_COMPLETER_ABORT 0x00008000
|
||||
#define PCIM_AER_UC_UNEXPECTED_COMPLETION 0x00010000
|
||||
#define PCIM_AER_UC_RECEIVER_OVERFLOW 0x00020000
|
||||
#define PCIM_AER_UC_MALFORMED_TLP 0x00040000
|
||||
#define PCIM_AER_UC_ECRC_ERROR 0x00080000
|
||||
#define PCIM_AER_UC_UNSUPPORTED_REQUEST 0x00100000
|
||||
#define PCIM_AER_UC_ACS_VIOLATION 0x00200000
|
||||
#define PCIR_AER_UC_MASK 0x08 /* Shares bits with UC_STATUS */
|
||||
#define PCIR_AER_UC_SEVERITY 0x0c /* Shares bits with UC_STATUS */
|
||||
#define PCIR_AER_COR_STATUS 0x10
|
||||
#define PCIM_AER_COR_RECEIVER_ERROR 0x00000001
|
||||
#define PCIM_AER_COR_BAD_TLP 0x00000040
|
||||
#define PCIM_AER_COR_BAD_DLLP 0x00000080
|
||||
#define PCIM_AER_COR_REPLAY_ROLLOVER 0x00000100
|
||||
#define PCIM_AER_COR_REPLAY_TIMEOUT 0x00001000
|
||||
#define PCIR_AER_COR_MASK 0x14 /* Shares bits with COR_STATUS */
|
||||
#define PCIR_AER_CAP_CONTROL 0x18
|
||||
#define PCIM_AER_FIRST_ERROR_PTR 0x0000001f
|
||||
#define PCIM_AER_ECRC_GEN_CAPABLE 0x00000020
|
||||
#define PCIM_AER_ECRC_GEN_ENABLE 0x00000040
|
||||
#define PCIM_AER_ECRC_CHECK_CAPABLE 0x00000080
|
||||
#define PCIM_AER_ECRC_CHECK_ENABLE 0x00000100
|
||||
#define PCIR_AER_HEADER_LOG 0x1c
|
||||
#define PCIR_AER_ROOTERR_CMD 0x2c /* Only for root complex ports */
|
||||
#define PCIM_AER_ROOTERR_COR_ENABLE 0x00000001
|
||||
#define PCIM_AER_ROOTERR_NF_ENABLE 0x00000002
|
||||
#define PCIM_AER_ROOTERR_F_ENABLE 0x00000004
|
||||
#define PCIR_AER_ROOTERR_STATUS 0x30 /* Only for root complex ports */
|
||||
#define PCIM_AER_ROOTERR_COR_ERR 0x00000001
|
||||
#define PCIM_AER_ROOTERR_MULTI_COR_ERR 0x00000002
|
||||
#define PCIM_AER_ROOTERR_UC_ERR 0x00000004
|
||||
#define PCIM_AER_ROOTERR_MULTI_UC_ERR 0x00000008
|
||||
#define PCIM_AER_ROOTERR_FIRST_UC_FATAL 0x00000010
|
||||
#define PCIM_AER_ROOTERR_NF_ERR 0x00000020
|
||||
#define PCIM_AER_ROOTERR_F_ERR 0x00000040
|
||||
#define PCIM_AER_ROOTERR_INT_MESSAGE 0xf8000000
|
||||
#define PCIR_AER_COR_SOURCE_ID 0x34 /* Only for root complex ports */
|
||||
#define PCIR_AER_ERR_SOURCE_ID 0x36 /* Only for root complex ports */
|
||||
|
||||
/* Virtual Channel definitions */
|
||||
#define PCIR_VC_CAP1 0x04
|
||||
#define PCIM_VC_CAP1_EXT_COUNT 0x00000007
|
||||
#define PCIM_VC_CAP1_LOWPRI_EXT_COUNT 0x00000070
|
||||
#define PCIR_VC_CAP2 0x08
|
||||
#define PCIR_VC_CONTROL 0x0C
|
||||
#define PCIR_VC_STATUS 0x0E
|
||||
#define PCIR_VC_RESOURCE_CAP(n) (0x10 + (n) * 0x0C)
|
||||
#define PCIR_VC_RESOURCE_CTL(n) (0x14 + (n) * 0x0C)
|
||||
#define PCIR_VC_RESOURCE_STA(n) (0x18 + (n) * 0x0C)
|
||||
|
||||
/* Serial Number definitions */
|
||||
#define PCIR_SERIAL_LOW 0x04
|
||||
#define PCIR_SERIAL_HIGH 0x08
|
||||
|
||||
@@ -1 +1,473 @@
|
||||
/* EMPTY */
|
||||
/*-
|
||||
* Copyright (c) 1997, Stefan Esser <se@freebsd.org>
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice unmodified, this list of conditions, and the following
|
||||
* disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _PCIVAR_HH_
|
||||
#define _PCIVAR_HH_
|
||||
|
||||
#include <freebsd/sys/queue.h>
|
||||
|
||||
/* some PCI bus constants */
|
||||
#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */
|
||||
#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */
|
||||
#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */
|
||||
|
||||
typedef uint64_t pci_addr_t;
|
||||
|
||||
/* Interesting values for PCI power management */
|
||||
struct pcicfg_pp {
|
||||
uint16_t pp_cap; /* PCI power management capabilities */
|
||||
uint8_t pp_status; /* config space address of PCI power status reg */
|
||||
uint8_t pp_pmcsr; /* config space address of PMCSR reg */
|
||||
uint8_t pp_data; /* config space address of PCI power data reg */
|
||||
};
|
||||
|
||||
struct vpd_readonly {
|
||||
char keyword[2];
|
||||
char *value;
|
||||
};
|
||||
|
||||
struct vpd_write {
|
||||
char keyword[2];
|
||||
char *value;
|
||||
int start;
|
||||
int len;
|
||||
};
|
||||
|
||||
struct pcicfg_vpd {
|
||||
uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */
|
||||
char vpd_cached;
|
||||
char *vpd_ident; /* string identifier */
|
||||
int vpd_rocnt;
|
||||
struct vpd_readonly *vpd_ros;
|
||||
int vpd_wcnt;
|
||||
struct vpd_write *vpd_w;
|
||||
};
|
||||
|
||||
/* Interesting values for PCI MSI */
|
||||
struct pcicfg_msi {
|
||||
uint16_t msi_ctrl; /* Message Control */
|
||||
uint8_t msi_location; /* Offset of MSI capability registers. */
|
||||
uint8_t msi_msgnum; /* Number of messages */
|
||||
int msi_alloc; /* Number of allocated messages. */
|
||||
uint64_t msi_addr; /* Contents of address register. */
|
||||
uint16_t msi_data; /* Contents of data register. */
|
||||
u_int msi_handlers;
|
||||
};
|
||||
|
||||
/* Interesting values for PCI MSI-X */
|
||||
struct msix_vector {
|
||||
uint64_t mv_address; /* Contents of address register. */
|
||||
uint32_t mv_data; /* Contents of data register. */
|
||||
int mv_irq;
|
||||
};
|
||||
|
||||
struct msix_table_entry {
|
||||
u_int mte_vector; /* 1-based index into msix_vectors array. */
|
||||
u_int mte_handlers;
|
||||
};
|
||||
|
||||
struct pcicfg_msix {
|
||||
uint16_t msix_ctrl; /* Message Control */
|
||||
uint16_t msix_msgnum; /* Number of messages */
|
||||
uint8_t msix_location; /* Offset of MSI-X capability registers. */
|
||||
uint8_t msix_table_bar; /* BAR containing vector table. */
|
||||
uint8_t msix_pba_bar; /* BAR containing PBA. */
|
||||
uint32_t msix_table_offset;
|
||||
uint32_t msix_pba_offset;
|
||||
int msix_alloc; /* Number of allocated vectors. */
|
||||
int msix_table_len; /* Length of virtual table. */
|
||||
struct msix_table_entry *msix_table; /* Virtual table. */
|
||||
struct msix_vector *msix_vectors; /* Array of allocated vectors. */
|
||||
struct resource *msix_table_res; /* Resource containing vector table. */
|
||||
struct resource *msix_pba_res; /* Resource containing PBA. */
|
||||
};
|
||||
|
||||
/* Interesting values for HyperTransport */
|
||||
struct pcicfg_ht {
|
||||
uint8_t ht_msimap; /* Offset of MSI mapping cap registers. */
|
||||
uint16_t ht_msictrl; /* MSI mapping control */
|
||||
uint64_t ht_msiaddr; /* MSI mapping base address */
|
||||
};
|
||||
|
||||
/* config header information common to all header types */
|
||||
typedef struct pcicfg {
|
||||
struct device *dev; /* device which owns this */
|
||||
|
||||
uint32_t bar[PCI_MAXMAPS_0]; /* BARs */
|
||||
uint32_t bios; /* BIOS mapping */
|
||||
|
||||
uint16_t subvendor; /* card vendor ID */
|
||||
uint16_t subdevice; /* card device ID, assigned by card vendor */
|
||||
uint16_t vendor; /* chip vendor ID */
|
||||
uint16_t device; /* chip device ID, assigned by chip vendor */
|
||||
|
||||
uint16_t cmdreg; /* disable/enable chip and PCI options */
|
||||
uint16_t statreg; /* supported PCI features and error state */
|
||||
|
||||
uint8_t baseclass; /* chip PCI class */
|
||||
uint8_t subclass; /* chip PCI subclass */
|
||||
uint8_t progif; /* chip PCI programming interface */
|
||||
uint8_t revid; /* chip revision ID */
|
||||
|
||||
uint8_t hdrtype; /* chip config header type */
|
||||
uint8_t cachelnsz; /* cache line size in 4byte units */
|
||||
uint8_t intpin; /* PCI interrupt pin */
|
||||
uint8_t intline; /* interrupt line (IRQ for PC arch) */
|
||||
|
||||
uint8_t mingnt; /* min. useful bus grant time in 250ns units */
|
||||
uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */
|
||||
uint8_t lattimer; /* latency timer in units of 30ns bus cycles */
|
||||
|
||||
uint8_t mfdev; /* multi-function device (from hdrtype reg) */
|
||||
uint8_t nummaps; /* actual number of PCI maps used */
|
||||
|
||||
uint32_t domain; /* PCI domain */
|
||||
uint8_t bus; /* config space bus address */
|
||||
uint8_t slot; /* config space slot address */
|
||||
uint8_t func; /* config space function number */
|
||||
|
||||
struct pcicfg_pp pp; /* Power management */
|
||||
struct pcicfg_vpd vpd; /* Vital product data */
|
||||
struct pcicfg_msi msi; /* PCI MSI */
|
||||
struct pcicfg_msix msix; /* PCI MSI-X */
|
||||
struct pcicfg_ht ht; /* HyperTransport */
|
||||
} pcicfgregs;
|
||||
|
||||
/* additional type 1 device config header information (PCI to PCI bridge) */
|
||||
|
||||
#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff)
|
||||
#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff)
|
||||
#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff)
|
||||
#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff)
|
||||
|
||||
typedef struct {
|
||||
pci_addr_t pmembase; /* base address of prefetchable memory */
|
||||
pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
|
||||
uint32_t membase; /* base address of memory window */
|
||||
uint32_t memlimit; /* topmost address of memory window */
|
||||
uint32_t iobase; /* base address of port window */
|
||||
uint32_t iolimit; /* topmost address of port window */
|
||||
uint16_t secstat; /* secondary bus status register */
|
||||
uint16_t bridgectl; /* bridge control register */
|
||||
uint8_t seclat; /* CardBus latency timer */
|
||||
} pcih1cfgregs;
|
||||
|
||||
/* additional type 2 device config header information (CardBus bridge) */
|
||||
|
||||
typedef struct {
|
||||
uint32_t membase0; /* base address of memory window */
|
||||
uint32_t memlimit0; /* topmost address of memory window */
|
||||
uint32_t membase1; /* base address of memory window */
|
||||
uint32_t memlimit1; /* topmost address of memory window */
|
||||
uint32_t iobase0; /* base address of port window */
|
||||
uint32_t iolimit0; /* topmost address of port window */
|
||||
uint32_t iobase1; /* base address of port window */
|
||||
uint32_t iolimit1; /* topmost address of port window */
|
||||
uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */
|
||||
uint16_t secstat; /* secondary bus status register */
|
||||
uint16_t bridgectl; /* bridge control register */
|
||||
uint8_t seclat; /* CardBus latency timer */
|
||||
} pcih2cfgregs;
|
||||
|
||||
extern uint32_t pci_numdevs;
|
||||
|
||||
/* Only if the prerequisites are present */
|
||||
#if defined(_SYS_BUS_HH_) && defined(_SYS_PCIIO_HH_)
|
||||
struct pci_devinfo {
|
||||
STAILQ_ENTRY(pci_devinfo) pci_links;
|
||||
struct resource_list resources;
|
||||
pcicfgregs cfg;
|
||||
struct pci_conf conf;
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef _SYS_BUS_HH_
|
||||
|
||||
#include <freebsd/local/pci_if.h>
|
||||
|
||||
enum pci_device_ivars {
|
||||
PCI_IVAR_SUBVENDOR,
|
||||
PCI_IVAR_SUBDEVICE,
|
||||
PCI_IVAR_VENDOR,
|
||||
PCI_IVAR_DEVICE,
|
||||
PCI_IVAR_DEVID,
|
||||
PCI_IVAR_CLASS,
|
||||
PCI_IVAR_SUBCLASS,
|
||||
PCI_IVAR_PROGIF,
|
||||
PCI_IVAR_REVID,
|
||||
PCI_IVAR_INTPIN,
|
||||
PCI_IVAR_IRQ,
|
||||
PCI_IVAR_DOMAIN,
|
||||
PCI_IVAR_BUS,
|
||||
PCI_IVAR_SLOT,
|
||||
PCI_IVAR_FUNCTION,
|
||||
PCI_IVAR_ETHADDR,
|
||||
PCI_IVAR_CMDREG,
|
||||
PCI_IVAR_CACHELNSZ,
|
||||
PCI_IVAR_MINGNT,
|
||||
PCI_IVAR_MAXLAT,
|
||||
PCI_IVAR_LATTIMER
|
||||
};
|
||||
|
||||
/*
|
||||
* Simplified accessors for pci devices
|
||||
*/
|
||||
#define PCI_ACCESSOR(var, ivar, type) \
|
||||
__BUS_ACCESSOR(pci, var, PCI, ivar, type)
|
||||
|
||||
PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t)
|
||||
PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t)
|
||||
PCI_ACCESSOR(vendor, VENDOR, uint16_t)
|
||||
PCI_ACCESSOR(device, DEVICE, uint16_t)
|
||||
PCI_ACCESSOR(devid, DEVID, uint32_t)
|
||||
PCI_ACCESSOR(class, CLASS, uint8_t)
|
||||
PCI_ACCESSOR(subclass, SUBCLASS, uint8_t)
|
||||
PCI_ACCESSOR(progif, PROGIF, uint8_t)
|
||||
PCI_ACCESSOR(revid, REVID, uint8_t)
|
||||
PCI_ACCESSOR(intpin, INTPIN, uint8_t)
|
||||
PCI_ACCESSOR(irq, IRQ, uint8_t)
|
||||
PCI_ACCESSOR(domain, DOMAIN, uint32_t)
|
||||
PCI_ACCESSOR(bus, BUS, uint8_t)
|
||||
PCI_ACCESSOR(slot, SLOT, uint8_t)
|
||||
PCI_ACCESSOR(function, FUNCTION, uint8_t)
|
||||
PCI_ACCESSOR(ether, ETHADDR, uint8_t *)
|
||||
PCI_ACCESSOR(cmdreg, CMDREG, uint8_t)
|
||||
PCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t)
|
||||
PCI_ACCESSOR(mingnt, MINGNT, uint8_t)
|
||||
PCI_ACCESSOR(maxlat, MAXLAT, uint8_t)
|
||||
PCI_ACCESSOR(lattimer, LATTIMER, uint8_t)
|
||||
|
||||
#undef PCI_ACCESSOR
|
||||
|
||||
/*
|
||||
* Operations on configuration space.
|
||||
*/
|
||||
static __inline uint32_t
|
||||
pci_read_config(device_t dev, int reg, int width)
|
||||
{
|
||||
return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width);
|
||||
}
|
||||
|
||||
static __inline void
|
||||
pci_write_config(device_t dev, int reg, uint32_t val, int width)
|
||||
{
|
||||
PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width);
|
||||
}
|
||||
|
||||
/*
|
||||
* Ivars for pci bridges.
|
||||
*/
|
||||
|
||||
/*typedef enum pci_device_ivars pcib_device_ivars;*/
|
||||
enum pcib_device_ivars {
|
||||
PCIB_IVAR_DOMAIN,
|
||||
PCIB_IVAR_BUS
|
||||
};
|
||||
|
||||
#define PCIB_ACCESSOR(var, ivar, type) \
|
||||
__BUS_ACCESSOR(pcib, var, PCIB, ivar, type)
|
||||
|
||||
PCIB_ACCESSOR(domain, DOMAIN, uint32_t)
|
||||
PCIB_ACCESSOR(bus, BUS, uint32_t)
|
||||
|
||||
#undef PCIB_ACCESSOR
|
||||
|
||||
/*
|
||||
* PCI interrupt validation. Invalid interrupt values such as 0 or 128
|
||||
* on i386 or other platforms should be mapped out in the MD pcireadconf
|
||||
* code and not here, since the only MI invalid IRQ is 255.
|
||||
*/
|
||||
#define PCI_INVALID_IRQ 255
|
||||
#define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ)
|
||||
|
||||
/*
|
||||
* Convenience functions.
|
||||
*
|
||||
* These should be used in preference to manually manipulating
|
||||
* configuration space.
|
||||
*/
|
||||
static __inline int
|
||||
pci_enable_busmaster(device_t dev)
|
||||
{
|
||||
return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev));
|
||||
}
|
||||
|
||||
static __inline int
|
||||
pci_disable_busmaster(device_t dev)
|
||||
{
|
||||
return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev));
|
||||
}
|
||||
|
||||
static __inline int
|
||||
pci_enable_io(device_t dev, int space)
|
||||
{
|
||||
return(PCI_ENABLE_IO(device_get_parent(dev), dev, space));
|
||||
}
|
||||
|
||||
static __inline int
|
||||
pci_disable_io(device_t dev, int space)
|
||||
{
|
||||
return(PCI_DISABLE_IO(device_get_parent(dev), dev, space));
|
||||
}
|
||||
|
||||
static __inline int
|
||||
pci_get_vpd_ident(device_t dev, const char **identptr)
|
||||
{
|
||||
return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr));
|
||||
}
|
||||
|
||||
static __inline int
|
||||
pci_get_vpd_readonly(device_t dev, const char *kw, const char **identptr)
|
||||
{
|
||||
return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, identptr));
|
||||
}
|
||||
|
||||
/*
|
||||
* Check if the address range falls within the VGA defined address range(s)
|
||||
*/
|
||||
static __inline int
|
||||
pci_is_vga_ioport_range(u_long start, u_long end)
|
||||
{
|
||||
|
||||
return (((start >= 0x3b0 && end <= 0x3bb) ||
|
||||
(start >= 0x3c0 && end <= 0x3df)) ? 1 : 0);
|
||||
}
|
||||
|
||||
static __inline int
|
||||
pci_is_vga_memory_range(u_long start, u_long end)
|
||||
{
|
||||
|
||||
return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0);
|
||||
}
|
||||
|
||||
/*
|
||||
* PCI power states are as defined by ACPI:
|
||||
*
|
||||
* D0 State in which device is on and running. It is receiving full
|
||||
* power from the system and delivering full functionality to the user.
|
||||
* D1 Class-specific low-power state in which device context may or may not
|
||||
* be lost. Buses in D1 cannot do anything to the bus that would force
|
||||
* devices on that bus to lose context.
|
||||
* D2 Class-specific low-power state in which device context may or may
|
||||
* not be lost. Attains greater power savings than D1. Buses in D2
|
||||
* can cause devices on that bus to lose some context. Devices in D2
|
||||
* must be prepared for the bus to be in D2 or higher.
|
||||
* D3 State in which the device is off and not running. Device context is
|
||||
* lost. Power can be removed from the device.
|
||||
*/
|
||||
#define PCI_POWERSTATE_D0 0
|
||||
#define PCI_POWERSTATE_D1 1
|
||||
#define PCI_POWERSTATE_D2 2
|
||||
#define PCI_POWERSTATE_D3 3
|
||||
#define PCI_POWERSTATE_UNKNOWN -1
|
||||
|
||||
static __inline int
|
||||
pci_set_powerstate(device_t dev, int state)
|
||||
{
|
||||
return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state);
|
||||
}
|
||||
|
||||
static __inline int
|
||||
pci_get_powerstate(device_t dev)
|
||||
{
|
||||
return PCI_GET_POWERSTATE(device_get_parent(dev), dev);
|
||||
}
|
||||
|
||||
static __inline int
|
||||
pci_find_extcap(device_t dev, int capability, int *capreg)
|
||||
{
|
||||
return PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg);
|
||||
}
|
||||
|
||||
static __inline int
|
||||
pci_alloc_msi(device_t dev, int *count)
|
||||
{
|
||||
return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count));
|
||||
}
|
||||
|
||||
static __inline int
|
||||
pci_alloc_msix(device_t dev, int *count)
|
||||
{
|
||||
return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count));
|
||||
}
|
||||
|
||||
static __inline int
|
||||
pci_remap_msix(device_t dev, int count, const u_int *vectors)
|
||||
{
|
||||
return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors));
|
||||
}
|
||||
|
||||
static __inline int
|
||||
pci_release_msi(device_t dev)
|
||||
{
|
||||
return (PCI_RELEASE_MSI(device_get_parent(dev), dev));
|
||||
}
|
||||
|
||||
static __inline int
|
||||
pci_msi_count(device_t dev)
|
||||
{
|
||||
return (PCI_MSI_COUNT(device_get_parent(dev), dev));
|
||||
}
|
||||
|
||||
static __inline int
|
||||
pci_msix_count(device_t dev)
|
||||
{
|
||||
return (PCI_MSIX_COUNT(device_get_parent(dev), dev));
|
||||
}
|
||||
|
||||
device_t pci_find_bsf(uint8_t, uint8_t, uint8_t);
|
||||
device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t);
|
||||
device_t pci_find_device(uint16_t, uint16_t);
|
||||
|
||||
/* Can be used by drivers to manage the MSI-X table. */
|
||||
int pci_pending_msix(device_t dev, u_int index);
|
||||
|
||||
int pci_msi_device_blacklisted(device_t dev);
|
||||
|
||||
void pci_ht_map_msi(device_t dev, uint64_t addr);
|
||||
|
||||
int pci_get_max_read_req(device_t dev);
|
||||
int pci_set_max_read_req(device_t dev, int size);
|
||||
|
||||
#endif /* _SYS_BUS_HH_ */
|
||||
|
||||
/*
|
||||
* cdev switch for control device, initialised in generic PCI code
|
||||
*/
|
||||
extern struct cdevsw pcicdev;
|
||||
|
||||
/*
|
||||
* List of all PCI devices, generation count for the list.
|
||||
*/
|
||||
STAILQ_HEAD(devlist, pci_devinfo);
|
||||
|
||||
extern struct devlist pci_devq;
|
||||
extern uint32_t pci_generation;
|
||||
|
||||
#endif /* _PCIVAR_HH_ */
|
||||
|
||||
3344
freebsd/dev/re/if_re.c
Normal file
3344
freebsd/dev/re/if_re.c
Normal file
File diff suppressed because it is too large
Load Diff
10
freebsd/machine/resource.h
Normal file
10
freebsd/machine/resource.h
Normal file
@@ -0,0 +1,10 @@
|
||||
#ifndef _MACHINE_RESOURCE_H_
|
||||
#define _MACHINE_RESOURCE_H_ 1
|
||||
|
||||
#define SYS_RES_IRQ 1 /* interrupt lines */
|
||||
#define SYS_RES_DRQ 2 /* isa dma lines */
|
||||
#define SYS_RES_MEMORY 3 /* i/o memory */
|
||||
#define SYS_RES_IOPORT 4 /* i/o ports */
|
||||
#define SYS_RES_GPIO 5 /* general purpose i/o */
|
||||
|
||||
#endif /* !_MACHINE_RESOURCE_H_ */
|
||||
1115
freebsd/pci/if_rlreg.h
Normal file
1115
freebsd/pci/if_rlreg.h
Normal file
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user