diff --git a/Makefile b/Makefile index 56cfbd5f..d2ab410d 100644 --- a/Makefile +++ b/Makefile @@ -267,6 +267,7 @@ C_FILES = \ freebsd/dev/mii/mii.c \ freebsd/dev/mii/mii_physubr.c \ freebsd/dev/mii/icsphy.c \ + freebsd/dev/mii/brgphy.c \ freebsd/local/usb_if.c \ freebsd/local/bus_if.c \ freebsd/local/device_if.c \ @@ -328,7 +329,14 @@ C_FILES = \ freebsd/dev/e1000/e1000_ich8lan.c \ freebsd/dev/e1000/e1000_mbx.c \ freebsd/dev/e1000/e1000_phy.c \ - freebsd/dev/e1000/if_igb.c + freebsd/dev/e1000/if_igb.c \ + freebsd/dev/dc/dcphy.c \ + freebsd/dev/dc/if_dc.c \ + freebsd/dev/dc/pnphy.c \ + freebsd/dev/smc/if_smc.c \ + freebsd/dev/bce/if_bce.c \ + freebsd/dev/bfe/if_bfe.c \ + freebsd/dev/bge/if_bge.c # RTEMS Project Owned Files C_FILES += \ rtemsbsd/dev/usb/controller/ohci_lpc3250.c \ diff --git a/freebsd-to-rtems.py b/freebsd-to-rtems.py index bf18a1fb..9c43e4c5 100755 --- a/freebsd-to-rtems.py +++ b/freebsd-to-rtems.py @@ -1083,6 +1083,7 @@ devNet.addHeaderFiles( [ 'dev/mii/mii.h', 'dev/mii/miivar.h', + 'dev/mii/brgphyreg.h', 'dev/mii/icsphyreg.h', 'net/bpf.h', 'net/ethernet.h', @@ -1100,6 +1101,7 @@ devNet.addSourceFiles( 'dev/mii/mii.c', 'dev/mii/mii_physubr.c', 'dev/mii/icsphy.c', + 'dev/mii/brgphy.c', ] ) @@ -1190,6 +1192,69 @@ devNic_e1000.addSourceFiles( ] ) +# DEC Tulip aka Intel 21143 +devNic_dc = Module('dev_nic_dc') +devNic_dc.addHeaderFiles( + [ + 'dev/dc/if_dcreg.h', + ] +) +devNic_dc.addSourceFiles( + [ + 'dev/dc/dcphy.c', + 'dev/dc/if_dc.c', + 'dev/dc/pnphy.c', + ] +) + +# SMC9111x +devNic_smc = Module('dev_nic_smc') +devNic_smc.addHeaderFiles( + [ + 'dev/smc/if_smcreg.h', + 'dev/smc/if_smcvar.h', + ] +) +devNic_smc.addSourceFiles( + [ + 'dev/smc/if_smc.c', + ] +) + +# Crystal Semiconductor CS8900 +devNic_cs = Module('dev_nic_cs') +devNic_cs.addHeaderFiles( + [ + 'dev/cs/if_csreg.h', + 'dev/cs/if_csvar.h', + ] +) +devNic_cs.addSourceFiles( + [ + 'dev/cs/if_cs.c', + 'dev/cs/if_cs_isa.c', + 'dev/cs/if_cs_pccard.c', + ] +) + +# Broadcomm BCE, BFE, BGE - MII is intertwined +devNic_broadcomm = Module('dev_nic_broadcomm') +devNic_broadcomm.addHeaderFiles( + [ + 'dev/bce/if_bcefw.h', + 'dev/bce/if_bcereg.h', + 'dev/bfe/if_bfereg.h', + 'dev/bge/if_bgereg.h', + ] +) +devNic_broadcomm.addSourceFiles( + [ + 'dev/bce/if_bce.c', + 'dev/bfe/if_bfe.c', + 'dev/bge/if_bge.c', + ] +) + netDeps = Module('netDeps') netDeps.addHeaderFiles( [ @@ -1883,6 +1948,7 @@ mm.addEmptyFiles( 'machine/sf_buf.h', 'machine/smp.h', #'machine/vmparam.h', + 'local/opt_bce.h', 'local/opt_ntp.h', 'local/pci_if.h', 'security/audit/audit.h', @@ -1958,6 +2024,11 @@ mm.addModule(devNic) mm.addModule(devNic_re) mm.addModule(devNic_fxp) mm.addModule(devNic_e1000) +mm.addModule(devNic_dc) +mm.addModule(devNic_smc) +mm.addModule(devNic_broadcomm) +# TBD Requires ISA and PCCard Support to be pulled in. +# mm.addModule(devNic_cs) # Now add CPU Architecture Dependent Modules mm.addModule(armDependent) diff --git a/freebsd/dev/bce/if_bce.c b/freebsd/dev/bce/if_bce.c new file mode 100644 index 00000000..646e6cbf --- /dev/null +++ b/freebsd/dev/bce/if_bce.c @@ -0,0 +1,10847 @@ +#include + +/*- + * Copyright (c) 2006-2010 Broadcom Corporation + * David Christensen . All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Broadcom Corporation nor the name of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written consent. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +/* + * The following controllers are supported by this driver: + * BCM5706C A2, A3 + * BCM5706S A2, A3 + * BCM5708C B1, B2 + * BCM5708S B1, B2 + * BCM5709C A1, C0 + * BCM5709S A1, C0 + * BCM5716C C0 + * BCM5716S C0 + * + * The following controllers are not supported by this driver: + * BCM5706C A0, A1 (pre-production) + * BCM5706S A0, A1 (pre-production) + * BCM5708C A0, B0 (pre-production) + * BCM5708S A0, B0 (pre-production) + * BCM5709C A0 B0, B1, B2 (pre-production) + * BCM5709S A0, B0, B1, B2 (pre-production) + */ + +#include + +#include +#include + +/****************************************************************************/ +/* BCE Debug Options */ +/****************************************************************************/ +#ifdef BCE_DEBUG + u32 bce_debug = BCE_WARN; + + /* 0 = Never */ + /* 1 = 1 in 2,147,483,648 */ + /* 256 = 1 in 8,388,608 */ + /* 2048 = 1 in 1,048,576 */ + /* 65536 = 1 in 32,768 */ + /* 1048576 = 1 in 2,048 */ + /* 268435456 = 1 in 8 */ + /* 536870912 = 1 in 4 */ + /* 1073741824 = 1 in 2 */ + + /* Controls how often the l2_fhdr frame error check will fail. */ + int l2fhdr_error_sim_control = 0; + + /* Controls how often the unexpected attention check will fail. */ + int unexpected_attention_sim_control = 0; + + /* Controls how often to simulate an mbuf allocation failure. */ + int mbuf_alloc_failed_sim_control = 0; + + /* Controls how often to simulate a DMA mapping failure. */ + int dma_map_addr_failed_sim_control = 0; + + /* Controls how often to simulate a bootcode failure. */ + int bootcode_running_failure_sim_control = 0; +#endif + +/****************************************************************************/ +/* BCE Build Time Options */ +/****************************************************************************/ +/* #define BCE_NVRAM_WRITE_SUPPORT 1 */ + + +/****************************************************************************/ +/* PCI Device ID Table */ +/* */ +/* Used by bce_probe() to identify the devices supported by this driver. */ +/****************************************************************************/ +#define BCE_DEVDESC_MAX 64 + +static struct bce_type bce_devs[] = { + /* BCM5706C Controllers and OEM boards. */ + { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101, + "HP NC370T Multifunction Gigabit Server Adapter" }, + { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106, + "HP NC370i Multifunction Gigabit Server Adapter" }, + { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3070, + "HP NC380T PCIe DP Multifunc Gig Server Adapter" }, + { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x1709, + "HP NC371i Multifunction Gigabit Server Adapter" }, + { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID, + "Broadcom NetXtreme II BCM5706 1000Base-T" }, + + /* BCM5706S controllers and OEM boards. */ + { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102, + "HP NC370F Multifunction Gigabit Server Adapter" }, + { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID, + "Broadcom NetXtreme II BCM5706 1000Base-SX" }, + + /* BCM5708C controllers and OEM boards. */ + { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7037, + "HP NC373T PCIe Multifunction Gig Server Adapter" }, + { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7038, + "HP NC373i Multifunction Gigabit Server Adapter" }, + { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7045, + "HP NC374m PCIe Multifunction Adapter" }, + { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID, + "Broadcom NetXtreme II BCM5708 1000Base-T" }, + + /* BCM5708S controllers and OEM boards. */ + { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x1706, + "HP NC373m Multifunction Gigabit Server Adapter" }, + { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703b, + "HP NC373i Multifunction Gigabit Server Adapter" }, + { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703d, + "HP NC373F PCIe Multifunc Giga Server Adapter" }, + { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID, + "Broadcom NetXtreme II BCM5708 1000Base-SX" }, + + /* BCM5709C controllers and OEM boards. */ + { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7055, + "HP NC382i DP Multifunction Gigabit Server Adapter" }, + { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7059, + "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" }, + { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID, + "Broadcom NetXtreme II BCM5709 1000Base-T" }, + + /* BCM5709S controllers and OEM boards. */ + { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x171d, + "HP NC382m DP 1GbE Multifunction BL-c Adapter" }, + { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x7056, + "HP NC382i DP Multifunction Gigabit Server Adapter" }, + { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID, + "Broadcom NetXtreme II BCM5709 1000Base-SX" }, + + /* BCM5716 controllers and OEM boards. */ + { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID, + "Broadcom NetXtreme II BCM5716 1000Base-T" }, + + { 0, 0, 0, 0, NULL } +}; + + +/****************************************************************************/ +/* Supported Flash NVRAM device data. */ +/****************************************************************************/ +static struct flash_spec flash_table[] = +{ +#define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE) +#define NONBUFFERED_FLAGS (BCE_NV_WREN) + + /* Slow EEPROM */ + {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, + BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, + SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, + "EEPROM - slow"}, + /* Expansion entry 0001 */ + {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, + NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, 0, + "Entry 0001"}, + /* Saifun SA25F010 (non-buffered flash) */ + /* strap, cfg1, & write1 need updates */ + {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, + NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, + "Non-buffered flash (128kB)"}, + /* Saifun SA25F020 (non-buffered flash) */ + /* strap, cfg1, & write1 need updates */ + {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, + NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, + "Non-buffered flash (256kB)"}, + /* Expansion entry 0100 */ + {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, + NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, 0, + "Entry 0100"}, + /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ + {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, + NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, + ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, + "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, + /* Entry 0110: ST M45PE20 (non-buffered flash)*/ + {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, + NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, + ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, + "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, + /* Saifun SA25F005 (non-buffered flash) */ + /* strap, cfg1, & write1 need updates */ + {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, + NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, + "Non-buffered flash (64kB)"}, + /* Fast EEPROM */ + {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, + BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, + SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, + "EEPROM - fast"}, + /* Expansion entry 1001 */ + {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, + NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, 0, + "Entry 1001"}, + /* Expansion entry 1010 */ + {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, + NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, 0, + "Entry 1010"}, + /* ATMEL AT45DB011B (buffered flash) */ + {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, + BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, + BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, + "Buffered flash (128kB)"}, + /* Expansion entry 1100 */ + {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, + NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, 0, + "Entry 1100"}, + /* Expansion entry 1101 */ + {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, + NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, 0, + "Entry 1101"}, + /* Ateml Expansion entry 1110 */ + {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, + BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, + BUFFERED_FLASH_BYTE_ADDR_MASK, 0, + "Entry 1110 (Atmel)"}, + /* ATMEL AT45DB021B (buffered flash) */ + {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, + BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, + BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, + "Buffered flash (256kB)"}, +}; + +/* + * The BCM5709 controllers transparently handle the + * differences between Atmel 264 byte pages and all + * flash devices which use 256 byte pages, so no + * logical-to-physical mapping is required in the + * driver. + */ +static struct flash_spec flash_5709 = { + .flags = BCE_NV_BUFFERED, + .page_bits = BCM5709_FLASH_PAGE_BITS, + .page_size = BCM5709_FLASH_PAGE_SIZE, + .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, + .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, + .name = "5709/5716 buffered flash (256kB)", +}; + + +/****************************************************************************/ +/* FreeBSD device entry points. */ +/****************************************************************************/ +static int bce_probe (device_t); +static int bce_attach (device_t); +static int bce_detach (device_t); +static int bce_shutdown (device_t); + + +/****************************************************************************/ +/* BCE Debug Data Structure Dump Routines */ +/****************************************************************************/ +#ifdef BCE_DEBUG +static u32 bce_reg_rd (struct bce_softc *, u32); +static void bce_reg_wr (struct bce_softc *, u32, u32); +static void bce_reg_wr16 (struct bce_softc *, u32, u16); +static u32 bce_ctx_rd (struct bce_softc *, u32, u32); +static void bce_dump_enet (struct bce_softc *, struct mbuf *); +static void bce_dump_mbuf (struct bce_softc *, struct mbuf *); +static void bce_dump_tx_mbuf_chain (struct bce_softc *, u16, int); +static void bce_dump_rx_mbuf_chain (struct bce_softc *, u16, int); +#ifdef BCE_JUMBO_HDRSPLIT +static void bce_dump_pg_mbuf_chain (struct bce_softc *, u16, int); +#endif +static void bce_dump_txbd (struct bce_softc *, + int, struct tx_bd *); +static void bce_dump_rxbd (struct bce_softc *, + int, struct rx_bd *); +#ifdef BCE_JUMBO_HDRSPLIT +static void bce_dump_pgbd (struct bce_softc *, + int, struct rx_bd *); +#endif +static void bce_dump_l2fhdr (struct bce_softc *, + int, struct l2_fhdr *); +static void bce_dump_ctx (struct bce_softc *, u16); +static void bce_dump_ftqs (struct bce_softc *); +static void bce_dump_tx_chain (struct bce_softc *, u16, int); +static void bce_dump_rx_bd_chain (struct bce_softc *, u16, int); +#ifdef BCE_JUMBO_HDRSPLIT +static void bce_dump_pg_chain (struct bce_softc *, u16, int); +#endif +static void bce_dump_status_block (struct bce_softc *); +static void bce_dump_stats_block (struct bce_softc *); +static void bce_dump_driver_state (struct bce_softc *); +static void bce_dump_hw_state (struct bce_softc *); +static void bce_dump_mq_regs (struct bce_softc *); +static void bce_dump_bc_state (struct bce_softc *); +static void bce_dump_txp_state (struct bce_softc *, int); +static void bce_dump_rxp_state (struct bce_softc *, int); +static void bce_dump_tpat_state (struct bce_softc *, int); +static void bce_dump_cp_state (struct bce_softc *, int); +static void bce_dump_com_state (struct bce_softc *, int); +static void bce_dump_rv2p_state (struct bce_softc *); +static void bce_breakpoint (struct bce_softc *); +#endif + + +/****************************************************************************/ +/* BCE Register/Memory Access Routines */ +/****************************************************************************/ +static u32 bce_reg_rd_ind (struct bce_softc *, u32); +static void bce_reg_wr_ind (struct bce_softc *, u32, u32); +static void bce_shmem_wr (struct bce_softc *, u32, u32); +static u32 bce_shmem_rd (struct bce_softc *, u32); +static void bce_ctx_wr (struct bce_softc *, u32, u32, u32); +static int bce_miibus_read_reg (device_t, int, int); +static int bce_miibus_write_reg (device_t, int, int, int); +static void bce_miibus_statchg (device_t); + + +/****************************************************************************/ +/* BCE NVRAM Access Routines */ +/****************************************************************************/ +static int bce_acquire_nvram_lock (struct bce_softc *); +static int bce_release_nvram_lock (struct bce_softc *); +static void bce_enable_nvram_access (struct bce_softc *); +static void bce_disable_nvram_access (struct bce_softc *); +static int bce_nvram_read_dword (struct bce_softc *, u32, u8 *, u32); +static int bce_init_nvram (struct bce_softc *); +static int bce_nvram_read (struct bce_softc *, u32, u8 *, int); +static int bce_nvram_test (struct bce_softc *); +#ifdef BCE_NVRAM_WRITE_SUPPORT +static int bce_enable_nvram_write (struct bce_softc *); +static void bce_disable_nvram_write (struct bce_softc *); +static int bce_nvram_erase_page (struct bce_softc *, u32); +static int bce_nvram_write_dword (struct bce_softc *, u32, u8 *, u32); +static int bce_nvram_write (struct bce_softc *, u32, u8 *, int); +#endif + +/****************************************************************************/ +/* */ +/****************************************************************************/ +static void bce_get_media (struct bce_softc *); +static void bce_init_media (struct bce_softc *); +static void bce_dma_map_addr (void *, + bus_dma_segment_t *, int, int); +static int bce_dma_alloc (device_t); +static void bce_dma_free (struct bce_softc *); +static void bce_release_resources (struct bce_softc *); + +/****************************************************************************/ +/* BCE Firmware Synchronization and Load */ +/****************************************************************************/ +static int bce_fw_sync (struct bce_softc *, u32); +static void bce_load_rv2p_fw (struct bce_softc *, u32 *, u32, u32); +static void bce_load_cpu_fw (struct bce_softc *, + struct cpu_reg *, struct fw_info *); +static void bce_start_cpu (struct bce_softc *, struct cpu_reg *); +static void bce_halt_cpu (struct bce_softc *, struct cpu_reg *); +static void bce_start_rxp_cpu (struct bce_softc *); +static void bce_init_rxp_cpu (struct bce_softc *); +static void bce_init_txp_cpu (struct bce_softc *); +static void bce_init_tpat_cpu (struct bce_softc *); +static void bce_init_cp_cpu (struct bce_softc *); +static void bce_init_com_cpu (struct bce_softc *); +static void bce_init_cpus (struct bce_softc *); + +static void bce_print_adapter_info (struct bce_softc *); +static void bce_probe_pci_caps (device_t, struct bce_softc *); +static void bce_stop (struct bce_softc *); +static int bce_reset (struct bce_softc *, u32); +static int bce_chipinit (struct bce_softc *); +static int bce_blockinit (struct bce_softc *); + +static int bce_init_tx_chain (struct bce_softc *); +static void bce_free_tx_chain (struct bce_softc *); + +static int bce_get_rx_buf (struct bce_softc *, + struct mbuf *, u16 *, u16 *, u32 *); +static int bce_init_rx_chain (struct bce_softc *); +static void bce_fill_rx_chain (struct bce_softc *); +static void bce_free_rx_chain (struct bce_softc *); + +#ifdef BCE_JUMBO_HDRSPLIT +static int bce_get_pg_buf (struct bce_softc *, + struct mbuf *, u16 *, u16 *); +static int bce_init_pg_chain (struct bce_softc *); +static void bce_fill_pg_chain (struct bce_softc *); +static void bce_free_pg_chain (struct bce_softc *); +#endif + +static struct mbuf *bce_tso_setup (struct bce_softc *, + struct mbuf **, u16 *); +static int bce_tx_encap (struct bce_softc *, struct mbuf **); +static void bce_start_locked (struct ifnet *); +static void bce_start (struct ifnet *); +static int bce_ioctl (struct ifnet *, u_long, caddr_t); +static void bce_watchdog (struct bce_softc *); +static int bce_ifmedia_upd (struct ifnet *); +static int bce_ifmedia_upd_locked (struct ifnet *); +static void bce_ifmedia_sts (struct ifnet *, struct ifmediareq *); +static void bce_init_locked (struct bce_softc *); +static void bce_init (void *); +static void bce_mgmt_init_locked (struct bce_softc *sc); + +static int bce_init_ctx (struct bce_softc *); +static void bce_get_mac_addr (struct bce_softc *); +static void bce_set_mac_addr (struct bce_softc *); +static void bce_phy_intr (struct bce_softc *); +static inline u16 bce_get_hw_rx_cons (struct bce_softc *); +static void bce_rx_intr (struct bce_softc *); +static void bce_tx_intr (struct bce_softc *); +static void bce_disable_intr (struct bce_softc *); +static void bce_enable_intr (struct bce_softc *, int); + +static void bce_intr (void *); +static void bce_set_rx_mode (struct bce_softc *); +static void bce_stats_update (struct bce_softc *); +static void bce_tick (void *); +static void bce_pulse (void *); +static void bce_add_sysctls (struct bce_softc *); + + +/****************************************************************************/ +/* FreeBSD device dispatch table. */ +/****************************************************************************/ +static device_method_t bce_methods[] = { + /* Device interface (device_if.h) */ + DEVMETHOD(device_probe, bce_probe), + DEVMETHOD(device_attach, bce_attach), + DEVMETHOD(device_detach, bce_detach), + DEVMETHOD(device_shutdown, bce_shutdown), +/* Supported by device interface but not used here. */ +/* DEVMETHOD(device_identify, bce_identify), */ +/* DEVMETHOD(device_suspend, bce_suspend), */ +/* DEVMETHOD(device_resume, bce_resume), */ +/* DEVMETHOD(device_quiesce, bce_quiesce), */ + + /* Bus interface (bus_if.h) */ + DEVMETHOD(bus_print_child, bus_generic_print_child), + DEVMETHOD(bus_driver_added, bus_generic_driver_added), + + /* MII interface (miibus_if.h) */ + DEVMETHOD(miibus_readreg, bce_miibus_read_reg), + DEVMETHOD(miibus_writereg, bce_miibus_write_reg), + DEVMETHOD(miibus_statchg, bce_miibus_statchg), +/* Supported by MII interface but not used here. */ +/* DEVMETHOD(miibus_linkchg, bce_miibus_linkchg), */ +/* DEVMETHOD(miibus_mediainit, bce_miibus_mediainit), */ + + { 0, 0 } +}; + +static driver_t bce_driver = { + "bce", + bce_methods, + sizeof(struct bce_softc) +}; + +static devclass_t bce_devclass; + +MODULE_DEPEND(bce, pci, 1, 1, 1); +MODULE_DEPEND(bce, ether, 1, 1, 1); +MODULE_DEPEND(bce, miibus, 1, 1, 1); + +DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, 0, 0); +DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, 0, 0); + + +/****************************************************************************/ +/* Tunable device values */ +/****************************************************************************/ +SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD, 0, "bce driver parameters"); + +/* Allowable values are TRUE or FALSE */ +static int bce_tso_enable = TRUE; +TUNABLE_INT("hw.bce.tso_enable", &bce_tso_enable); +SYSCTL_UINT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0, +"TSO Enable/Disable"); + +/* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */ +/* ToDo: Add MSI-X support. */ +static int bce_msi_enable = 1; +TUNABLE_INT("hw.bce.msi_enable", &bce_msi_enable); +SYSCTL_UINT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0, +"MSI-X|MSI|INTx selector"); + +/* ToDo: Add tunable to enable/disable strict MTU handling. */ +/* Currently allows "loose" RX MTU checking (i.e. sets the */ +/* H/W RX MTU to the size of the largest receive buffer, or */ +/* 2048 bytes). This will cause a UNH failure but is more */ +/* desireable from a functional perspective. */ + + +/****************************************************************************/ +/* Device probe function. */ +/* */ +/* Compares the device to the driver's list of supported devices and */ +/* reports back to the OS whether this is the right driver for the device. */ +/* */ +/* Returns: */ +/* BUS_PROBE_DEFAULT on success, positive value on failure. */ +/****************************************************************************/ +static int +bce_probe(device_t dev) +{ + struct bce_type *t; + struct bce_softc *sc; + char *descbuf; + u16 vid = 0, did = 0, svid = 0, sdid = 0; + + t = bce_devs; + + sc = device_get_softc(dev); + bzero(sc, sizeof(struct bce_softc)); + sc->bce_unit = device_get_unit(dev); + sc->bce_dev = dev; + + /* Get the data for the device to be probed. */ + vid = pci_get_vendor(dev); + did = pci_get_device(dev); + svid = pci_get_subvendor(dev); + sdid = pci_get_subdevice(dev); + + DBPRINT(sc, BCE_EXTREME_LOAD, + "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, " + "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid); + + /* Look through the list of known devices for a match. */ + while(t->bce_name != NULL) { + + if ((vid == t->bce_vid) && (did == t->bce_did) && + ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) && + ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) { + + descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT); + + if (descbuf == NULL) + return(ENOMEM); + + /* Print out the device identity. */ + snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)", + t->bce_name, (((pci_read_config(dev, + PCIR_REVID, 4) & 0xf0) >> 4) + 'A'), + (pci_read_config(dev, PCIR_REVID, 4) & 0xf)); + + device_set_desc_copy(dev, descbuf); + free(descbuf, M_TEMP); + return(BUS_PROBE_DEFAULT); + } + t++; + } + + return(ENXIO); +} + + +/****************************************************************************/ +/* PCI Capabilities Probe Function. */ +/* */ +/* Walks the PCI capabiites list for the device to find what features are */ +/* supported. */ +/* */ +/* Returns: */ +/* None. */ +/****************************************************************************/ +static void +bce_print_adapter_info(struct bce_softc *sc) +{ + int i = 0; + + DBENTER(BCE_VERBOSE_LOAD); + + if (bootverbose) { + BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid); + printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> + 12) + 'A', ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4)); + + + /* Bus info. */ + if (sc->bce_flags & BCE_PCIE_FLAG) { + printf("Bus (PCIe x%d, ", sc->link_width); + switch (sc->link_speed) { + case 1: printf("2.5Gbps); "); break; + case 2: printf("5Gbps); "); break; + default: printf("Unknown link speed); "); + } + } else { + printf("Bus (PCI%s, %s, %dMHz); ", + ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""), + ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? + "32-bit" : "64-bit"), sc->bus_speed_mhz); + } + + /* Firmware version and device features. */ + printf("B/C (%s); Flags (", sc->bce_bc_ver); + + #ifdef BCE_JUMBO_HDRSPLIT + printf("SPLT"); + i++; + #endif + + if (sc->bce_flags & BCE_USING_MSI_FLAG) { + if (i > 0) printf("|"); + printf("MSI"); i++; + } + + if (sc->bce_flags & BCE_USING_MSIX_FLAG) { + if (i > 0) printf("|"); + printf("MSI-X"); i++; + } + + if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) { + if (i > 0) printf("|"); + printf("2.5G"); i++; + } + + if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { + if (i > 0) printf("|"); + printf("MFW); MFW (%s)\n", sc->bce_mfw_ver); + } else { + printf(")\n"); + } + } + + DBEXIT(BCE_VERBOSE_LOAD); +} + + +/****************************************************************************/ +/* PCI Capabilities Probe Function. */ +/* */ +/* Walks the PCI capabiites list for the device to find what features are */ +/* supported. */ +/* */ +/* Returns: */ +/* None. */ +/****************************************************************************/ +static void +bce_probe_pci_caps(device_t dev, struct bce_softc *sc) +{ + u32 reg; + + DBENTER(BCE_VERBOSE_LOAD); + + /* Check if PCI-X capability is enabled. */ + if (pci_find_extcap(dev, PCIY_PCIX, ®) == 0) { + if (reg != 0) + sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG; + } + + /* Check if PCIe capability is enabled. */ + if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { + if (reg != 0) { + u16 link_status = pci_read_config(dev, reg + 0x12, 2); + DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = " + "0x%08X\n", link_status); + sc->link_speed = link_status & 0xf; + sc->link_width = (link_status >> 4) & 0x3f; + sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG; + sc->bce_flags |= BCE_PCIE_FLAG; + } + } + + /* Check if MSI capability is enabled. */ + if (pci_find_extcap(dev, PCIY_MSI, ®) == 0) { + if (reg != 0) + sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG; + } + + /* Check if MSI-X capability is enabled. */ + if (pci_find_extcap(dev, PCIY_MSIX, ®) == 0) { + if (reg != 0) + sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG; + } + + DBEXIT(BCE_VERBOSE_LOAD); +} + + +/****************************************************************************/ +/* Device attach function. */ +/* */ +/* Allocates device resources, performs secondary chip identification, */ +/* resets and initializes the hardware, and initializes driver instance */ +/* variables. */ +/* */ +/* Returns: */ +/* 0 on success, positive value on failure. */ +/****************************************************************************/ +static int +bce_attach(device_t dev) +{ + struct bce_softc *sc; + struct ifnet *ifp; + u32 val; + int error, rid, rc = 0; + + sc = device_get_softc(dev); + sc->bce_dev = dev; + + DBENTER(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); + + sc->bce_unit = device_get_unit(dev); + + /* Set initial device and PHY flags */ + sc->bce_flags = 0; + sc->bce_phy_flags = 0; + + pci_enable_busmaster(dev); + + /* Allocate PCI memory resources. */ + rid = PCIR_BAR(0); + sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, + &rid, RF_ACTIVE); + + if (sc->bce_res_mem == NULL) { + BCE_PRINTF("%s(%d): PCI memory allocation failed\n", + __FILE__, __LINE__); + rc = ENXIO; + goto bce_attach_fail; + } + + /* Get various resource handles. */ + sc->bce_btag = rman_get_bustag(sc->bce_res_mem); + sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem); + sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem); + + bce_probe_pci_caps(dev, sc); + + rid = 1; +#if 0 + /* Try allocating MSI-X interrupts. */ + if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) && + (bce_msi_enable >= 2) && + ((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY, + &rid, RF_ACTIVE)) != NULL)) { + + msi_needed = sc->bce_msi_count = 1; + + if (((error = pci_alloc_msix(dev, &sc->bce_msi_count)) != 0) || + (sc->bce_msi_count != msi_needed)) { + BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d," + "Received = %d, error = %d\n", __FILE__, __LINE__, + msi_needed, sc->bce_msi_count, error); + sc->bce_msi_count = 0; + pci_release_msi(dev); + bus_release_resource(dev, SYS_RES_MEMORY, rid, + sc->bce_res_irq); + sc->bce_res_irq = NULL; + } else { + DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n", + __FUNCTION__); + sc->bce_flags |= BCE_USING_MSIX_FLAG; + sc->bce_intr = bce_intr; + } + } +#endif + + /* Try allocating a MSI interrupt. */ + if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) && + (bce_msi_enable >= 1) && (sc->bce_msi_count == 0)) { + sc->bce_msi_count = 1; + if ((error = pci_alloc_msi(dev, &sc->bce_msi_count)) != 0) { + BCE_PRINTF("%s(%d): MSI allocation failed! " + "error = %d\n", __FILE__, __LINE__, error); + sc->bce_msi_count = 0; + pci_release_msi(dev); + } else { + DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI " + "interrupt.\n", __FUNCTION__); + sc->bce_flags |= BCE_USING_MSI_FLAG; + if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || + (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) + sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG; + sc->bce_irq_rid = 1; + sc->bce_intr = bce_intr; + } + } + + /* Try allocating a legacy interrupt. */ + if (sc->bce_msi_count == 0) { + DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n", + __FUNCTION__); + rid = 0; + sc->bce_intr = bce_intr; + } + + sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, + &rid, RF_SHAREABLE | RF_ACTIVE); + + sc->bce_irq_rid = rid; + + /* Report any IRQ allocation errors. */ + if (sc->bce_res_irq == NULL) { + BCE_PRINTF("%s(%d): PCI map interrupt failed!\n", + __FILE__, __LINE__); + rc = ENXIO; + goto bce_attach_fail; + } + + /* Initialize mutex for the current device instance. */ + BCE_LOCK_INIT(sc, device_get_nameunit(dev)); + + /* + * Configure byte swap and enable indirect register access. + * Rely on CPU to do target byte swapping on big endian systems. + * Access to registers outside of PCI configurtion space are not + * valid until this is done. + */ + pci_write_config(dev, BCE_PCICFG_MISC_CONFIG, + BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | + BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4); + + /* Save ASIC revsion info. */ + sc->bce_chipid = REG_RD(sc, BCE_MISC_ID); + + /* Weed out any non-production controller revisions. */ + switch(BCE_CHIP_ID(sc)) { + case BCE_CHIP_ID_5706_A0: + case BCE_CHIP_ID_5706_A1: + case BCE_CHIP_ID_5708_A0: + case BCE_CHIP_ID_5708_B0: + case BCE_CHIP_ID_5709_A0: + case BCE_CHIP_ID_5709_B0: + case BCE_CHIP_ID_5709_B1: + case BCE_CHIP_ID_5709_B2: + BCE_PRINTF("%s(%d): Unsupported controller " + "revision (%c%d)!\n", __FILE__, __LINE__, + (((pci_read_config(dev, PCIR_REVID, 4) & + 0xf0) >> 4) + 'A'), (pci_read_config(dev, + PCIR_REVID, 4) & 0xf)); + rc = ENODEV; + goto bce_attach_fail; + } + + /* + * The embedded PCIe to PCI-X bridge (EPB) + * in the 5708 cannot address memory above + * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043). + */ + if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708) + sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR; + else + sc->max_bus_addr = BUS_SPACE_MAXADDR; + + /* + * Find the base address for shared memory access. + * Newer versions of bootcode use a signature and offset + * while older versions use a fixed address. + */ + val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE); + if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG) + /* Multi-port devices use different offsets in shared memory. */ + sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 + + (pci_get_function(sc->bce_dev) << 2)); + else + sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE; + + DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n", + __FUNCTION__, sc->bce_shmem_base); + + /* Fetch the bootcode revision. */ + val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV); + for (int i = 0, j = 0; i < 3; i++) { + u8 num; + + num = (u8) (val >> (24 - (i * 8))); + for (int k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) { + if (num >= k || !skip0 || k == 1) { + sc->bce_bc_ver[j++] = (num / k) + '0'; + skip0 = 0; + } + } + + if (i != 2) + sc->bce_bc_ver[j++] = '.'; + } + + /* Check if any management firwmare is enabled. */ + val = bce_shmem_rd(sc, BCE_PORT_FEATURE); + if (val & BCE_PORT_FEATURE_ASF_ENABLED) { + sc->bce_flags |= BCE_MFW_ENABLE_FLAG; + + /* Allow time for firmware to enter the running state. */ + for (int i = 0; i < 30; i++) { + val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); + if (val & BCE_CONDITION_MFW_RUN_MASK) + break; + DELAY(10000); + } + + /* Check if management firmware is running. */ + val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); + val &= BCE_CONDITION_MFW_RUN_MASK; + if ((val != BCE_CONDITION_MFW_RUN_UNKNOWN) && + (val != BCE_CONDITION_MFW_RUN_NONE)) { + u32 addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR); + int i = 0; + + /* Read the management firmware version string. */ + for (int j = 0; j < 3; j++) { + val = bce_reg_rd_ind(sc, addr + j * 4); + val = bswap32(val); + memcpy(&sc->bce_mfw_ver[i], &val, 4); + i += 4; + } + } else { + /* May cause firmware synchronization timeouts. */ + BCE_PRINTF("%s(%d): Management firmware enabled " + "but not running!\n", __FILE__, __LINE__); + strcpy(sc->bce_mfw_ver, "NOT RUNNING!"); + + /* ToDo: Any action the driver should take? */ + } + } + + /* Get PCI bus information (speed and type). */ + val = REG_RD(sc, BCE_PCICFG_MISC_STATUS); + if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) { + u32 clkreg; + + sc->bce_flags |= BCE_PCIX_FLAG; + + clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS); + + clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; + switch (clkreg) { + case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: + sc->bus_speed_mhz = 133; + break; + + case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: + sc->bus_speed_mhz = 100; + break; + + case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: + case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: + sc->bus_speed_mhz = 66; + break; + + case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: + case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: + sc->bus_speed_mhz = 50; + break; + + case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: + case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: + case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: + sc->bus_speed_mhz = 33; + break; + } + } else { + if (val & BCE_PCICFG_MISC_STATUS_M66EN) + sc->bus_speed_mhz = 66; + else + sc->bus_speed_mhz = 33; + } + + if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET) + sc->bce_flags |= BCE_PCI_32BIT_FLAG; + + /* Reset controller and announce to bootcode that driver is present. */ + if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { + BCE_PRINTF("%s(%d): Controller reset failed!\n", + __FILE__, __LINE__); + rc = ENXIO; + goto bce_attach_fail; + } + + /* Initialize the controller. */ + if (bce_chipinit(sc)) { + BCE_PRINTF("%s(%d): Controller initialization failed!\n", + __FILE__, __LINE__); + rc = ENXIO; + goto bce_attach_fail; + } + + /* Perform NVRAM test. */ + if (bce_nvram_test(sc)) { + BCE_PRINTF("%s(%d): NVRAM test failed!\n", + __FILE__, __LINE__); + rc = ENXIO; + goto bce_attach_fail; + } + + /* Fetch the permanent Ethernet MAC address. */ + bce_get_mac_addr(sc); + + /* + * Trip points control how many BDs + * should be ready before generating an + * interrupt while ticks control how long + * a BD can sit in the chain before + * generating an interrupt. Set the default + * values for the RX and TX chains. + */ + +#ifdef BCE_DEBUG + /* Force more frequent interrupts. */ + sc->bce_tx_quick_cons_trip_int = 1; + sc->bce_tx_quick_cons_trip = 1; + sc->bce_tx_ticks_int = 0; + sc->bce_tx_ticks = 0; + + sc->bce_rx_quick_cons_trip_int = 1; + sc->bce_rx_quick_cons_trip = 1; + sc->bce_rx_ticks_int = 0; + sc->bce_rx_ticks = 0; +#else + /* Improve throughput at the expense of increased latency. */ + sc->bce_tx_quick_cons_trip_int = 20; + sc->bce_tx_quick_cons_trip = 20; + sc->bce_tx_ticks_int = 80; + sc->bce_tx_ticks = 80; + + sc->bce_rx_quick_cons_trip_int = 6; + sc->bce_rx_quick_cons_trip = 6; + sc->bce_rx_ticks_int = 18; + sc->bce_rx_ticks = 18; +#endif + + /* Not used for L2. */ + sc->bce_comp_prod_trip_int = 0; + sc->bce_comp_prod_trip = 0; + sc->bce_com_ticks_int = 0; + sc->bce_com_ticks = 0; + sc->bce_cmd_ticks_int = 0; + sc->bce_cmd_ticks = 0; + + /* Update statistics once every second. */ + sc->bce_stats_ticks = 1000000 & 0xffff00; + + /* Find the media type for the adapter. */ + bce_get_media(sc); + + /* Store data needed by PHY driver for backplane applications */ + sc->bce_shared_hw_cfg = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); + sc->bce_port_hw_cfg = bce_shmem_rd(sc, BCE_PORT_HW_CFG_CONFIG); + + /* Allocate DMA memory resources. */ + if (bce_dma_alloc(dev)) { + BCE_PRINTF("%s(%d): DMA resource allocation failed!\n", + __FILE__, __LINE__); + rc = ENXIO; + goto bce_attach_fail; + } + + /* Allocate an ifnet structure. */ + ifp = sc->bce_ifp = if_alloc(IFT_ETHER); + if (ifp == NULL) { + BCE_PRINTF("%s(%d): Interface allocation failed!\n", + __FILE__, __LINE__); + rc = ENXIO; + goto bce_attach_fail; + } + + /* Initialize the ifnet interface. */ + ifp->if_softc = sc; + if_initname(ifp, device_get_name(dev), device_get_unit(dev)); + ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; + ifp->if_ioctl = bce_ioctl; + ifp->if_start = bce_start; + ifp->if_init = bce_init; + ifp->if_mtu = ETHERMTU; + + if (bce_tso_enable) { + ifp->if_hwassist = BCE_IF_HWASSIST | CSUM_TSO; + ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4 | + IFCAP_VLAN_HWTSO; + } else { + ifp->if_hwassist = BCE_IF_HWASSIST; + ifp->if_capabilities = BCE_IF_CAPABILITIES; + } + + ifp->if_capenable = ifp->if_capabilities; + + /* + * Assume standard mbuf sizes for buffer allocation. + * This may change later if the MTU size is set to + * something other than 1500. + */ +#ifdef BCE_JUMBO_HDRSPLIT + sc->rx_bd_mbuf_alloc_size = MHLEN; + /* Make sure offset is 16 byte aligned for hardware. */ + sc->rx_bd_mbuf_align_pad = + roundup2((MSIZE - MHLEN), 16) - (MSIZE - MHLEN); + sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size - + sc->rx_bd_mbuf_align_pad; + sc->pg_bd_mbuf_alloc_size = MCLBYTES; +#else + sc->rx_bd_mbuf_alloc_size = MCLBYTES; + sc->rx_bd_mbuf_align_pad = + roundup2(MCLBYTES, 16) - MCLBYTES; + sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size - + sc->rx_bd_mbuf_align_pad; +#endif + + ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD; + IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); + IFQ_SET_READY(&ifp->if_snd); + + if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) + ifp->if_baudrate = IF_Mbps(2500ULL); + else + ifp->if_baudrate = IF_Mbps(1000); + + /* Handle any special PHY initialization for SerDes PHYs. */ + bce_init_media(sc); + + /* MII child bus by attaching the PHY. */ + rc = mii_attach(dev, &sc->bce_miibus, ifp, bce_ifmedia_upd, + bce_ifmedia_sts, BMSR_DEFCAPMASK, sc->bce_phy_addr, + MII_OFFSET_ANY, MIIF_DOPAUSE | MIIF_FORCEPAUSE); + if (rc != 0) { + BCE_PRINTF("%s(%d): attaching PHYs failed\n", __FILE__, + __LINE__); + goto bce_attach_fail; + } + + /* Attach to the Ethernet interface list. */ + ether_ifattach(ifp, sc->eaddr); + +#if __FreeBSD_version < 500000 + callout_init(&sc->bce_tick_callout); + callout_init(&sc->bce_pulse_callout); +#else + callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0); + callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0); +#endif + + /* Hookup IRQ last. */ + rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE, + NULL, bce_intr, sc, &sc->bce_intrhand); + + if (rc) { + BCE_PRINTF("%s(%d): Failed to setup IRQ!\n", + __FILE__, __LINE__); + bce_detach(dev); + goto bce_attach_exit; + } + + /* + * At this point we've acquired all the resources + * we need to run so there's no turning back, we're + * cleared for launch. + */ + + /* Print some important debugging info. */ + DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc)); + + /* Add the supported sysctls to the kernel. */ + bce_add_sysctls(sc); + + BCE_LOCK(sc); + + /* + * The chip reset earlier notified the bootcode that + * a driver is present. We now need to start our pulse + * routine so that the bootcode is reminded that we're + * still running. + */ + bce_pulse(sc); + + bce_mgmt_init_locked(sc); + BCE_UNLOCK(sc); + + /* Finally, print some useful adapter info */ + bce_print_adapter_info(sc); + DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n", + __FUNCTION__, sc); + + goto bce_attach_exit; + +bce_attach_fail: + bce_release_resources(sc); + +bce_attach_exit: + + DBEXIT(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); + + return(rc); +} + + +/****************************************************************************/ +/* Device detach function. */ +/* */ +/* Stops the controller, resets the controller, and releases resources. */ +/* */ +/* Returns: */ +/* 0 on success, positive value on failure. */ +/****************************************************************************/ +static int +bce_detach(device_t dev) +{ + struct bce_softc *sc = device_get_softc(dev); + struct ifnet *ifp; + u32 msg; + + DBENTER(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); + + ifp = sc->bce_ifp; + + /* Stop and reset the controller. */ + BCE_LOCK(sc); + + /* Stop the pulse so the bootcode can go to driver absent state. */ + callout_stop(&sc->bce_pulse_callout); + + bce_stop(sc); + if (sc->bce_flags & BCE_NO_WOL_FLAG) + msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; + else + msg = BCE_DRV_MSG_CODE_UNLOAD; + bce_reset(sc, msg); + + BCE_UNLOCK(sc); + + ether_ifdetach(ifp); + + /* If we have a child device on the MII bus remove it too. */ + bus_generic_detach(dev); + device_delete_child(dev, sc->bce_miibus); + + /* Release all remaining resources. */ + bce_release_resources(sc); + + DBEXIT(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); + + return(0); +} + + +/****************************************************************************/ +/* Device shutdown function. */ +/* */ +/* Stops and resets the controller. */ +/* */ +/* Returns: */ +/* 0 on success, positive value on failure. */ +/****************************************************************************/ +static int +bce_shutdown(device_t dev) +{ + struct bce_softc *sc = device_get_softc(dev); + u32 msg; + + DBENTER(BCE_VERBOSE); + + BCE_LOCK(sc); + bce_stop(sc); + if (sc->bce_flags & BCE_NO_WOL_FLAG) + msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; + else + msg = BCE_DRV_MSG_CODE_UNLOAD; + bce_reset(sc, msg); + BCE_UNLOCK(sc); + + DBEXIT(BCE_VERBOSE); + + return (0); +} + + +#ifdef BCE_DEBUG +/****************************************************************************/ +/* Register read. */ +/* */ +/* Returns: */ +/* The value of the register. */ +/****************************************************************************/ +static u32 +bce_reg_rd(struct bce_softc *sc, u32 offset) +{ + u32 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, offset); + DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", + __FUNCTION__, offset, val); + return val; +} + + +/****************************************************************************/ +/* Register write (16 bit). */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val) +{ + DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n", + __FUNCTION__, offset, val); + bus_space_write_2(sc->bce_btag, sc->bce_bhandle, offset, val); +} + + +/****************************************************************************/ +/* Register write. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val) +{ + DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", + __FUNCTION__, offset, val); + bus_space_write_4(sc->bce_btag, sc->bce_bhandle, offset, val); +} +#endif + +/****************************************************************************/ +/* Indirect register read. */ +/* */ +/* Reads NetXtreme II registers using an index/data register pair in PCI */ +/* configuration space. Using this mechanism avoids issues with posted */ +/* reads but is much slower than memory-mapped I/O. */ +/* */ +/* Returns: */ +/* The value of the register. */ +/****************************************************************************/ +static u32 +bce_reg_rd_ind(struct bce_softc *sc, u32 offset) +{ + device_t dev; + dev = sc->bce_dev; + + pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); +#ifdef BCE_DEBUG + { + u32 val; + val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); + DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", + __FUNCTION__, offset, val); + return val; + } +#else + return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); +#endif +} + + +/****************************************************************************/ +/* Indirect register write. */ +/* */ +/* Writes NetXtreme II registers using an index/data register pair in PCI */ +/* configuration space. Using this mechanism avoids issues with posted */ +/* writes but is muchh slower than memory-mapped I/O. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val) +{ + device_t dev; + dev = sc->bce_dev; + + DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", + __FUNCTION__, offset, val); + + pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); + pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4); +} + + +/****************************************************************************/ +/* Shared memory write. */ +/* */ +/* Writes NetXtreme II shared memory region. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_shmem_wr(struct bce_softc *sc, u32 offset, u32 val) +{ + DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Writing 0x%08X to " + "0x%08X\n", __FUNCTION__, val, offset); + + bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val); +} + + +/****************************************************************************/ +/* Shared memory read. */ +/* */ +/* Reads NetXtreme II shared memory region. */ +/* */ +/* Returns: */ +/* The 32 bit value read. */ +/****************************************************************************/ +static u32 +bce_shmem_rd(struct bce_softc *sc, u32 offset) +{ + u32 val = bce_reg_rd_ind(sc, sc->bce_shmem_base + offset); + + DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Reading 0x%08X from " + "0x%08X\n", __FUNCTION__, val, offset); + + return val; +} + + +#ifdef BCE_DEBUG +/****************************************************************************/ +/* Context memory read. */ +/* */ +/* The NetXtreme II controller uses context memory to track connection */ +/* information for L2 and higher network protocols. */ +/* */ +/* Returns: */ +/* The requested 32 bit value of context memory. */ +/****************************************************************************/ +static u32 +bce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset) +{ + u32 idx, offset, retry_cnt = 5, val; + + DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || + cid_addr & CTX_MASK), BCE_PRINTF("%s(): Invalid CID " + "address: 0x%08X.\n", __FUNCTION__, cid_addr)); + + offset = ctx_offset + cid_addr; + + if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || + (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { + + REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ)); + + for (idx = 0; idx < retry_cnt; idx++) { + val = REG_RD(sc, BCE_CTX_CTX_CTRL); + if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0) + break; + DELAY(5); + } + + if (val & BCE_CTX_CTX_CTRL_READ_REQ) + BCE_PRINTF("%s(%d); Unable to read CTX memory: " + "cid_addr = 0x%08X, offset = 0x%08X!\n", + __FILE__, __LINE__, cid_addr, ctx_offset); + + val = REG_RD(sc, BCE_CTX_CTX_DATA); + } else { + REG_WR(sc, BCE_CTX_DATA_ADR, offset); + val = REG_RD(sc, BCE_CTX_DATA); + } + + DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " + "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val); + + return(val); +} +#endif + + +/****************************************************************************/ +/* Context memory write. */ +/* */ +/* The NetXtreme II controller uses context memory to track connection */ +/* information for L2 and higher network protocols. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset, u32 ctx_val) +{ + u32 idx, offset = ctx_offset + cid_addr; + u32 val, retry_cnt = 5; + + DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " + "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val); + + DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK), + BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n", + __FUNCTION__, cid_addr)); + + if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || + (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { + + REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val); + REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ)); + + for (idx = 0; idx < retry_cnt; idx++) { + val = REG_RD(sc, BCE_CTX_CTX_CTRL); + if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0) + break; + DELAY(5); + } + + if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) + BCE_PRINTF("%s(%d); Unable to write CTX memory: " + "cid_addr = 0x%08X, offset = 0x%08X!\n", + __FILE__, __LINE__, cid_addr, ctx_offset); + + } else { + REG_WR(sc, BCE_CTX_DATA_ADR, offset); + REG_WR(sc, BCE_CTX_DATA, ctx_val); + } +} + + +/****************************************************************************/ +/* PHY register read. */ +/* */ +/* Implements register reads on the MII bus. */ +/* */ +/* Returns: */ +/* The value of the register. */ +/****************************************************************************/ +static int +bce_miibus_read_reg(device_t dev, int phy, int reg) +{ + struct bce_softc *sc; + u32 val; + int i; + + sc = device_get_softc(dev); + + /* Make sure we are accessing the correct PHY address. */ + if (phy != sc->bce_phy_addr) { + DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d " + "for PHY read!\n", phy); + return(0); + } + + /* + * The 5709S PHY is an IEEE Clause 45 PHY + * with special mappings to work with IEEE + * Clause 22 register accesses. + */ + if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { + if (reg >= MII_BMCR && reg <= MII_ANLPRNP) + reg += 0x10; + } + + if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { + val = REG_RD(sc, BCE_EMAC_MDIO_MODE); + val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; + + REG_WR(sc, BCE_EMAC_MDIO_MODE, val); + REG_RD(sc, BCE_EMAC_MDIO_MODE); + + DELAY(40); + } + + + val = BCE_MIPHY(phy) | BCE_MIREG(reg) | + BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT | + BCE_EMAC_MDIO_COMM_START_BUSY; + REG_WR(sc, BCE_EMAC_MDIO_COMM, val); + + for (i = 0; i < BCE_PHY_TIMEOUT; i++) { + DELAY(10); + + val = REG_RD(sc, BCE_EMAC_MDIO_COMM); + if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) { + DELAY(5); + + val = REG_RD(sc, BCE_EMAC_MDIO_COMM); + val &= BCE_EMAC_MDIO_COMM_DATA; + + break; + } + } + + if (val & BCE_EMAC_MDIO_COMM_START_BUSY) { + BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, " + "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); + val = 0x0; + } else { + val = REG_RD(sc, BCE_EMAC_MDIO_COMM); + } + + + if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { + val = REG_RD(sc, BCE_EMAC_MDIO_MODE); + val |= BCE_EMAC_MDIO_MODE_AUTO_POLL; + + REG_WR(sc, BCE_EMAC_MDIO_MODE, val); + REG_RD(sc, BCE_EMAC_MDIO_MODE); + + DELAY(40); + } + + DB_PRINT_PHY_REG(reg, val); + return (val & 0xffff); + +} + + +/****************************************************************************/ +/* PHY register write. */ +/* */ +/* Implements register writes on the MII bus. */ +/* */ +/* Returns: */ +/* The value of the register. */ +/****************************************************************************/ +static int +bce_miibus_write_reg(device_t dev, int phy, int reg, int val) +{ + struct bce_softc *sc; + u32 val1; + int i; + + sc = device_get_softc(dev); + + /* Make sure we are accessing the correct PHY address. */ + if (phy != sc->bce_phy_addr) { + DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d " + "for PHY write!\n", phy); + return(0); + } + + DB_PRINT_PHY_REG(reg, val); + + /* + * The 5709S PHY is an IEEE Clause 45 PHY + * with special mappings to work with IEEE + * Clause 22 register accesses. + */ + if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { + if (reg >= MII_BMCR && reg <= MII_ANLPRNP) + reg += 0x10; + } + + if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { + val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); + val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; + + REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); + REG_RD(sc, BCE_EMAC_MDIO_MODE); + + DELAY(40); + } + + val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val | + BCE_EMAC_MDIO_COMM_COMMAND_WRITE | + BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT; + REG_WR(sc, BCE_EMAC_MDIO_COMM, val1); + + for (i = 0; i < BCE_PHY_TIMEOUT; i++) { + DELAY(10); + + val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM); + if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) { + DELAY(5); + break; + } + } + + if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY) + BCE_PRINTF("%s(%d): PHY write timeout!\n", + __FILE__, __LINE__); + + if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { + val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); + val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL; + + REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); + REG_RD(sc, BCE_EMAC_MDIO_MODE); + + DELAY(40); + } + + return 0; +} + + +/****************************************************************************/ +/* MII bus status change. */ +/* */ +/* Called by the MII bus driver when the PHY establishes link to set the */ +/* MAC interface registers. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_miibus_statchg(device_t dev) +{ + struct bce_softc *sc; + struct mii_data *mii; + int val; + + sc = device_get_softc(dev); + + DBENTER(BCE_VERBOSE_PHY); + + mii = device_get_softc(sc->bce_miibus); + + val = REG_RD(sc, BCE_EMAC_MODE); + val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX | + BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK | + BCE_EMAC_MODE_25G); + + /* Set MII or GMII interface based on the PHY speed. */ + switch (IFM_SUBTYPE(mii->mii_media_active)) { + case IFM_10_T: + if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { + DBPRINT(sc, BCE_INFO_PHY, + "Enabling 10Mb interface.\n"); + val |= BCE_EMAC_MODE_PORT_MII_10; + break; + } + /* fall-through */ + case IFM_100_TX: + DBPRINT(sc, BCE_INFO_PHY, "Enabling MII interface.\n"); + val |= BCE_EMAC_MODE_PORT_MII; + break; + case IFM_2500_SX: + DBPRINT(sc, BCE_INFO_PHY, "Enabling 2.5G MAC mode.\n"); + val |= BCE_EMAC_MODE_25G; + /* fall-through */ + case IFM_1000_T: + case IFM_1000_SX: + DBPRINT(sc, BCE_INFO_PHY, "Enabling GMII interface.\n"); + val |= BCE_EMAC_MODE_PORT_GMII; + break; + default: + DBPRINT(sc, BCE_INFO_PHY, "Unknown link speed, enabling " + "default GMII interface.\n"); + val |= BCE_EMAC_MODE_PORT_GMII; + } + + /* Set half or full duplex based on PHY settings. */ + if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { + DBPRINT(sc, BCE_INFO_PHY, + "Setting Half-Duplex interface.\n"); + val |= BCE_EMAC_MODE_HALF_DUPLEX; + } else + DBPRINT(sc, BCE_INFO_PHY, + "Setting Full-Duplex interface.\n"); + + REG_WR(sc, BCE_EMAC_MODE, val); + + if ((mii->mii_media_active & IFM_ETH_RXPAUSE) != 0) { + DBPRINT(sc, BCE_INFO_PHY, + "%s(): Enabling RX flow control.\n", __FUNCTION__); + BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); + } else { + DBPRINT(sc, BCE_INFO_PHY, + "%s(): Disabling RX flow control.\n", __FUNCTION__); + BCE_CLRBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); + } + + if ((mii->mii_media_active & IFM_ETH_TXPAUSE) != 0) { + DBPRINT(sc, BCE_INFO_PHY, + "%s(): Enabling TX flow control.\n", __FUNCTION__); + BCE_SETBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); + sc->bce_flags |= BCE_USING_TX_FLOW_CONTROL; + } else { + DBPRINT(sc, BCE_INFO_PHY, + "%s(): Disabling TX flow control.\n", __FUNCTION__); + BCE_CLRBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); + sc->bce_flags &= ~BCE_USING_TX_FLOW_CONTROL; + } + + /* ToDo: Update watermarks in bce_init_rx_context(). */ + + DBEXIT(BCE_VERBOSE_PHY); +} + + +/****************************************************************************/ +/* Acquire NVRAM lock. */ +/* */ +/* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ +/* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ +/* for use by the driver. */ +/* */ +/* Returns: */ +/* 0 on success, positive value on failure. */ +/****************************************************************************/ +static int +bce_acquire_nvram_lock(struct bce_softc *sc) +{ + u32 val; + int j, rc = 0; + + DBENTER(BCE_VERBOSE_NVRAM); + + /* Request access to the flash interface. */ + REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2); + for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { + val = REG_RD(sc, BCE_NVM_SW_ARB); + if (val & BCE_NVM_SW_ARB_ARB_ARB2) + break; + + DELAY(5); + } + + if (j >= NVRAM_TIMEOUT_COUNT) { + DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n"); + rc = EBUSY; + } + + DBEXIT(BCE_VERBOSE_NVRAM); + return (rc); +} + + +/****************************************************************************/ +/* Release NVRAM lock. */ +/* */ +/* When the caller is finished accessing NVRAM the lock must be released. */ +/* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ +/* for use by the driver. */ +/* */ +/* Returns: */ +/* 0 on success, positive value on failure. */ +/****************************************************************************/ +static int +bce_release_nvram_lock(struct bce_softc *sc) +{ + u32 val; + int j, rc = 0; + + DBENTER(BCE_VERBOSE_NVRAM); + + /* + * Relinquish nvram interface. + */ + REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2); + + for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { + val = REG_RD(sc, BCE_NVM_SW_ARB); + if (!(val & BCE_NVM_SW_ARB_ARB_ARB2)) + break; + + DELAY(5); + } + + if (j >= NVRAM_TIMEOUT_COUNT) { + DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n"); + rc = EBUSY; + } + + DBEXIT(BCE_VERBOSE_NVRAM); + return (rc); +} + + +#ifdef BCE_NVRAM_WRITE_SUPPORT +/****************************************************************************/ +/* Enable NVRAM write access. */ +/* */ +/* Before writing to NVRAM the caller must enable NVRAM writes. */ +/* */ +/* Returns: */ +/* 0 on success, positive value on failure. */ +/****************************************************************************/ +static int +bce_enable_nvram_write(struct bce_softc *sc) +{ + u32 val; + int rc = 0; + + DBENTER(BCE_VERBOSE_NVRAM); + + val = REG_RD(sc, BCE_MISC_CFG); + REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI); + + if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { + int j; + + REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); + REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT); + + for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { + DELAY(5); + + val = REG_RD(sc, BCE_NVM_COMMAND); + if (val & BCE_NVM_COMMAND_DONE) + break; + } + + if (j >= NVRAM_TIMEOUT_COUNT) { + DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n"); + rc = EBUSY; + } + } + + DBENTER(BCE_VERBOSE_NVRAM); + return (rc); +} + + +/****************************************************************************/ +/* Disable NVRAM write access. */ +/* */ +/* When the caller is finished writing to NVRAM write access must be */ +/* disabled. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_disable_nvram_write(struct bce_softc *sc) +{ + u32 val; + + DBENTER(BCE_VERBOSE_NVRAM); + + val = REG_RD(sc, BCE_MISC_CFG); + REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN); + + DBEXIT(BCE_VERBOSE_NVRAM); + +} +#endif + + +/****************************************************************************/ +/* Enable NVRAM access. */ +/* */ +/* Before accessing NVRAM for read or write operations the caller must */ +/* enabled NVRAM access. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_enable_nvram_access(struct bce_softc *sc) +{ + u32 val; + + DBENTER(BCE_VERBOSE_NVRAM); + + val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); + /* Enable both bits, even on read. */ + REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val | + BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN); + + DBEXIT(BCE_VERBOSE_NVRAM); +} + + +/****************************************************************************/ +/* Disable NVRAM access. */ +/* */ +/* When the caller is finished accessing NVRAM access must be disabled. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_disable_nvram_access(struct bce_softc *sc) +{ + u32 val; + + DBENTER(BCE_VERBOSE_NVRAM); + + val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); + + /* Disable both bits, even after read. */ + REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val & + ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN)); + + DBEXIT(BCE_VERBOSE_NVRAM); +} + + +#ifdef BCE_NVRAM_WRITE_SUPPORT +/****************************************************************************/ +/* Erase NVRAM page before writing. */ +/* */ +/* Non-buffered flash parts require that a page be erased before it is */ +/* written. */ +/* */ +/* Returns: */ +/* 0 on success, positive value on failure. */ +/****************************************************************************/ +static int +bce_nvram_erase_page(struct bce_softc *sc, u32 offset) +{ + u32 cmd; + int j, rc = 0; + + DBENTER(BCE_VERBOSE_NVRAM); + + /* Buffered flash doesn't require an erase. */ + if (sc->bce_flash_info->flags & BCE_NV_BUFFERED) + goto bce_nvram_erase_page_exit; + + /* Build an erase command. */ + cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR | + BCE_NVM_COMMAND_DOIT; + + /* + * Clear the DONE bit separately, set the NVRAM adress to erase, + * and issue the erase command. + */ + REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); + REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); + REG_WR(sc, BCE_NVM_COMMAND, cmd); + + /* Wait for completion. */ + for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { + u32 val; + + DELAY(5); + + val = REG_RD(sc, BCE_NVM_COMMAND); + if (val & BCE_NVM_COMMAND_DONE) + break; + } + + if (j >= NVRAM_TIMEOUT_COUNT) { + DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n"); + rc = EBUSY; + } + +bce_nvram_erase_page_exit: + DBEXIT(BCE_VERBOSE_NVRAM); + return (rc); +} +#endif /* BCE_NVRAM_WRITE_SUPPORT */ + + +/****************************************************************************/ +/* Read a dword (32 bits) from NVRAM. */ +/* */ +/* Read a 32 bit word from NVRAM. The caller is assumed to have already */ +/* obtained the NVRAM lock and enabled the controller for NVRAM access. */ +/* */ +/* Returns: */ +/* 0 on success and the 32 bit value read, positive value on failure. */ +/****************************************************************************/ +static int +bce_nvram_read_dword(struct bce_softc *sc, + u32 offset, u8 *ret_val, u32 cmd_flags) +{ + u32 cmd; + int i, rc = 0; + + DBENTER(BCE_EXTREME_NVRAM); + + /* Build the command word. */ + cmd = BCE_NVM_COMMAND_DOIT | cmd_flags; + + /* Calculate the offset for buffered flash if translation is used. */ + if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { + offset = ((offset / sc->bce_flash_info->page_size) << + sc->bce_flash_info->page_bits) + + (offset % sc->bce_flash_info->page_size); + } + + /* + * Clear the DONE bit separately, set the address to read, + * and issue the read. + */ + REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); + REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); + REG_WR(sc, BCE_NVM_COMMAND, cmd); + + /* Wait for completion. */ + for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { + u32 val; + + DELAY(5); + + val = REG_RD(sc, BCE_NVM_COMMAND); + if (val & BCE_NVM_COMMAND_DONE) { + val = REG_RD(sc, BCE_NVM_READ); + + val = bce_be32toh(val); + memcpy(ret_val, &val, 4); + break; + } + } + + /* Check for errors. */ + if (i >= NVRAM_TIMEOUT_COUNT) { + BCE_PRINTF("%s(%d): Timeout error reading NVRAM at " + "offset 0x%08X!\n", __FILE__, __LINE__, offset); + rc = EBUSY; + } + + DBEXIT(BCE_EXTREME_NVRAM); + return(rc); +} + + +#ifdef BCE_NVRAM_WRITE_SUPPORT +/****************************************************************************/ +/* Write a dword (32 bits) to NVRAM. */ +/* */ +/* Write a 32 bit word to NVRAM. The caller is assumed to have already */ +/* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ +/* enabled NVRAM write access. */ +/* */ +/* Returns: */ +/* 0 on success, positive value on failure. */ +/****************************************************************************/ +static int +bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val, + u32 cmd_flags) +{ + u32 cmd, val32; + int j, rc = 0; + + DBENTER(BCE_VERBOSE_NVRAM); + + /* Build the command word. */ + cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags; + + /* Calculate the offset for buffered flash if translation is used. */ + if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { + offset = ((offset / sc->bce_flash_info->page_size) << + sc->bce_flash_info->page_bits) + + (offset % sc->bce_flash_info->page_size); + } + + /* + * Clear the DONE bit separately, convert NVRAM data to big-endian, + * set the NVRAM address to write, and issue the write command + */ + REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); + memcpy(&val32, val, 4); + val32 = htobe32(val32); + REG_WR(sc, BCE_NVM_WRITE, val32); + REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); + REG_WR(sc, BCE_NVM_COMMAND, cmd); + + /* Wait for completion. */ + for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { + DELAY(5); + + if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE) + break; + } + if (j >= NVRAM_TIMEOUT_COUNT) { + BCE_PRINTF("%s(%d): Timeout error writing NVRAM at " + "offset 0x%08X\n", __FILE__, __LINE__, offset); + rc = EBUSY; + } + + DBEXIT(BCE_VERBOSE_NVRAM); + return (rc); +} +#endif /* BCE_NVRAM_WRITE_SUPPORT */ + + +/****************************************************************************/ +/* Initialize NVRAM access. */ +/* */ +/* Identify the NVRAM device in use and prepare the NVRAM interface to */ +/* access that device. */ +/* */ +/* Returns: */ +/* 0 on success, positive value on failure. */ +/****************************************************************************/ +static int +bce_init_nvram(struct bce_softc *sc) +{ + u32 val; + int j, entry_count, rc = 0; + struct flash_spec *flash; + + DBENTER(BCE_VERBOSE_NVRAM); + + if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || + (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { + sc->bce_flash_info = &flash_5709; + goto bce_init_nvram_get_flash_size; + } + + /* Determine the selected interface. */ + val = REG_RD(sc, BCE_NVM_CFG1); + + entry_count = sizeof(flash_table) / sizeof(struct flash_spec); + + /* + * Flash reconfiguration is required to support additional + * NVRAM devices not directly supported in hardware. + * Check if the flash interface was reconfigured + * by the bootcode. + */ + + if (val & 0x40000000) { + /* Flash interface reconfigured by bootcode. */ + + DBPRINT(sc,BCE_INFO_LOAD, + "bce_init_nvram(): Flash WAS reconfigured.\n"); + + for (j = 0, flash = &flash_table[0]; j < entry_count; + j++, flash++) { + if ((val & FLASH_BACKUP_STRAP_MASK) == + (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { + sc->bce_flash_info = flash; + break; + } + } + } else { + /* Flash interface not yet reconfigured. */ + u32 mask; + + DBPRINT(sc, BCE_INFO_LOAD, "%s(): Flash was NOT reconfigured.\n", + __FUNCTION__); + + if (val & (1 << 23)) + mask = FLASH_BACKUP_STRAP_MASK; + else + mask = FLASH_STRAP_MASK; + + /* Look for the matching NVRAM device configuration data. */ + for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) { + + /* Check if the device matches any of the known devices. */ + if ((val & mask) == (flash->strapping & mask)) { + /* Found a device match. */ + sc->bce_flash_info = flash; + + /* Request access to the flash interface. */ + if ((rc = bce_acquire_nvram_lock(sc)) != 0) + return rc; + + /* Reconfigure the flash interface. */ + bce_enable_nvram_access(sc); + REG_WR(sc, BCE_NVM_CFG1, flash->config1); + REG_WR(sc, BCE_NVM_CFG2, flash->config2); + REG_WR(sc, BCE_NVM_CFG3, flash->config3); + REG_WR(sc, BCE_NVM_WRITE1, flash->write1); + bce_disable_nvram_access(sc); + bce_release_nvram_lock(sc); + + break; + } + } + } + + /* Check if a matching device was found. */ + if (j == entry_count) { + sc->bce_flash_info = NULL; + BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n", + __FILE__, __LINE__); + DBEXIT(BCE_VERBOSE_NVRAM); + return (ENODEV); + } + +bce_init_nvram_get_flash_size: + /* Write the flash config data to the shared memory interface. */ + val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2); + val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK; + if (val) + sc->bce_flash_size = val; + else + sc->bce_flash_size = sc->bce_flash_info->total_size; + + DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n", + __FUNCTION__, sc->bce_flash_info->name, + sc->bce_flash_info->total_size); + + DBEXIT(BCE_VERBOSE_NVRAM); + return rc; +} + + +/****************************************************************************/ +/* Read an arbitrary range of data from NVRAM. */ +/* */ +/* Prepares the NVRAM interface for access and reads the requested data */ +/* into the supplied buffer. */ +/* */ +/* Returns: */ +/* 0 on success and the data read, positive value on failure. */ +/****************************************************************************/ +static int +bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf, + int buf_size) +{ + int rc = 0; + u32 cmd_flags, offset32, len32, extra; + + DBENTER(BCE_VERBOSE_NVRAM); + + if (buf_size == 0) + goto bce_nvram_read_exit; + + /* Request access to the flash interface. */ + if ((rc = bce_acquire_nvram_lock(sc)) != 0) + goto bce_nvram_read_exit; + + /* Enable access to flash interface */ + bce_enable_nvram_access(sc); + + len32 = buf_size; + offset32 = offset; + extra = 0; + + cmd_flags = 0; + + if (offset32 & 3) { + u8 buf[4]; + u32 pre_len; + + offset32 &= ~3; + pre_len = 4 - (offset & 3); + + if (pre_len >= len32) { + pre_len = len32; + cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST; + } + else { + cmd_flags = BCE_NVM_COMMAND_FIRST; + } + + rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); + + if (rc) + return rc; + + memcpy(ret_buf, buf + (offset & 3), pre_len); + + offset32 += 4; + ret_buf += pre_len; + len32 -= pre_len; + } + + if (len32 & 3) { + extra = 4 - (len32 & 3); + len32 = (len32 + 4) & ~3; + } + + if (len32 == 4) { + u8 buf[4]; + + if (cmd_flags) + cmd_flags = BCE_NVM_COMMAND_LAST; + else + cmd_flags = BCE_NVM_COMMAND_FIRST | + BCE_NVM_COMMAND_LAST; + + rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); + + memcpy(ret_buf, buf, 4 - extra); + } + else if (len32 > 0) { + u8 buf[4]; + + /* Read the first word. */ + if (cmd_flags) + cmd_flags = 0; + else + cmd_flags = BCE_NVM_COMMAND_FIRST; + + rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); + + /* Advance to the next dword. */ + offset32 += 4; + ret_buf += 4; + len32 -= 4; + + while (len32 > 4 && rc == 0) { + rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0); + + /* Advance to the next dword. */ + offset32 += 4; + ret_buf += 4; + len32 -= 4; + } + + if (rc) + goto bce_nvram_read_locked_exit; + + cmd_flags = BCE_NVM_COMMAND_LAST; + rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); + + memcpy(ret_buf, buf, 4 - extra); + } + +bce_nvram_read_locked_exit: + /* Disable access to flash interface and release the lock. */ + bce_disable_nvram_access(sc); + bce_release_nvram_lock(sc); + +bce_nvram_read_exit: + DBEXIT(BCE_VERBOSE_NVRAM); + return rc; +} + + +#ifdef BCE_NVRAM_WRITE_SUPPORT +/****************************************************************************/ +/* Write an arbitrary range of data from NVRAM. */ +/* */ +/* Prepares the NVRAM interface for write access and writes the requested */ +/* data from the supplied buffer. The caller is responsible for */ +/* calculating any appropriate CRCs. */ +/* */ +/* Returns: */ +/* 0 on success, positive value on failure. */ +/****************************************************************************/ +static int +bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf, + int buf_size) +{ + u32 written, offset32, len32; + u8 *buf, start[4], end[4]; + int rc = 0; + int align_start, align_end; + + DBENTER(BCE_VERBOSE_NVRAM); + + buf = data_buf; + offset32 = offset; + len32 = buf_size; + align_start = align_end = 0; + + if ((align_start = (offset32 & 3))) { + offset32 &= ~3; + len32 += align_start; + if ((rc = bce_nvram_read(sc, offset32, start, 4))) + goto bce_nvram_write_exit; + } + + if (len32 & 3) { + if ((len32 > 4) || !align_start) { + align_end = 4 - (len32 & 3); + len32 += align_end; + if ((rc = bce_nvram_read(sc, offset32 + len32 - 4, + end, 4))) { + goto bce_nvram_write_exit; + } + } + } + + if (align_start || align_end) { + buf = malloc(len32, M_DEVBUF, M_NOWAIT); + if (buf == 0) { + rc = ENOMEM; + goto bce_nvram_write_exit; + } + + if (align_start) { + memcpy(buf, start, 4); + } + + if (align_end) { + memcpy(buf + len32 - 4, end, 4); + } + memcpy(buf + align_start, data_buf, buf_size); + } + + written = 0; + while ((written < len32) && (rc == 0)) { + u32 page_start, page_end, data_start, data_end; + u32 addr, cmd_flags; + int i; + u8 flash_buffer[264]; + + /* Find the page_start addr */ + page_start = offset32 + written; + page_start -= (page_start % sc->bce_flash_info->page_size); + /* Find the page_end addr */ + page_end = page_start + sc->bce_flash_info->page_size; + /* Find the data_start addr */ + data_start = (written == 0) ? offset32 : page_start; + /* Find the data_end addr */ + data_end = (page_end > offset32 + len32) ? + (offset32 + len32) : page_end; + + /* Request access to the flash interface. */ + if ((rc = bce_acquire_nvram_lock(sc)) != 0) + goto bce_nvram_write_exit; + + /* Enable access to flash interface */ + bce_enable_nvram_access(sc); + + cmd_flags = BCE_NVM_COMMAND_FIRST; + if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { + int j; + + /* Read the whole page into the buffer + * (non-buffer flash only) */ + for (j = 0; j < sc->bce_flash_info->page_size; j += 4) { + if (j == (sc->bce_flash_info->page_size - 4)) { + cmd_flags |= BCE_NVM_COMMAND_LAST; + } + rc = bce_nvram_read_dword(sc, + page_start + j, + &flash_buffer[j], + cmd_flags); + + if (rc) + goto bce_nvram_write_locked_exit; + + cmd_flags = 0; + } + } + + /* Enable writes to flash interface (unlock write-protect) */ + if ((rc = bce_enable_nvram_write(sc)) != 0) + goto bce_nvram_write_locked_exit; + + /* Erase the page */ + if ((rc = bce_nvram_erase_page(sc, page_start)) != 0) + goto bce_nvram_write_locked_exit; + + /* Re-enable the write again for the actual write */ + bce_enable_nvram_write(sc); + + /* Loop to write back the buffer data from page_start to + * data_start */ + i = 0; + if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { + for (addr = page_start; addr < data_start; + addr += 4, i += 4) { + + rc = bce_nvram_write_dword(sc, addr, + &flash_buffer[i], cmd_flags); + + if (rc != 0) + goto bce_nvram_write_locked_exit; + + cmd_flags = 0; + } + } + + /* Loop to write the new data from data_start to data_end */ + for (addr = data_start; addr < data_end; addr += 4, i++) { + if ((addr == page_end - 4) || + ((sc->bce_flash_info->flags & BCE_NV_BUFFERED) && + (addr == data_end - 4))) { + + cmd_flags |= BCE_NVM_COMMAND_LAST; + } + rc = bce_nvram_write_dword(sc, addr, buf, + cmd_flags); + + if (rc != 0) + goto bce_nvram_write_locked_exit; + + cmd_flags = 0; + buf += 4; + } + + /* Loop to write back the buffer data from data_end + * to page_end */ + if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { + for (addr = data_end; addr < page_end; + addr += 4, i += 4) { + + if (addr == page_end-4) { + cmd_flags = BCE_NVM_COMMAND_LAST; + } + rc = bce_nvram_write_dword(sc, addr, + &flash_buffer[i], cmd_flags); + + if (rc != 0) + goto bce_nvram_write_locked_exit; + + cmd_flags = 0; + } + } + + /* Disable writes to flash interface (lock write-protect) */ + bce_disable_nvram_write(sc); + + /* Disable access to flash interface */ + bce_disable_nvram_access(sc); + bce_release_nvram_lock(sc); + + /* Increment written */ + written += data_end - data_start; + } + + goto bce_nvram_write_exit; + +bce_nvram_write_locked_exit: + bce_disable_nvram_write(sc); + bce_disable_nvram_access(sc); + bce_release_nvram_lock(sc); + +bce_nvram_write_exit: + if (align_start || align_end) + free(buf, M_DEVBUF); + + DBEXIT(BCE_VERBOSE_NVRAM); + return (rc); +} +#endif /* BCE_NVRAM_WRITE_SUPPORT */ + + +/****************************************************************************/ +/* Verifies that NVRAM is accessible and contains valid data. */ +/* */ +/* Reads the configuration data from NVRAM and verifies that the CRC is */ +/* correct. */ +/* */ +/* Returns: */ +/* 0 on success, positive value on failure. */ +/****************************************************************************/ +static int +bce_nvram_test(struct bce_softc *sc) +{ + u32 buf[BCE_NVRAM_SIZE / 4]; + u8 *data = (u8 *) buf; + int rc = 0; + u32 magic, csum; + + DBENTER(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); + + /* + * Check that the device NVRAM is valid by reading + * the magic value at offset 0. + */ + if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) { + BCE_PRINTF("%s(%d): Unable to read NVRAM!\n", + __FILE__, __LINE__); + goto bce_nvram_test_exit; + } + + /* + * Verify that offset 0 of the NVRAM contains + * a valid magic number. + */ + magic = bce_be32toh(buf[0]); + if (magic != BCE_NVRAM_MAGIC) { + rc = ENODEV; + BCE_PRINTF("%s(%d): Invalid NVRAM magic value! " + "Expected: 0x%08X, Found: 0x%08X\n", + __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic); + goto bce_nvram_test_exit; + } + + /* + * Verify that the device NVRAM includes valid + * configuration data. + */ + if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) { + BCE_PRINTF("%s(%d): Unable to read manufacturing " + "Information from NVRAM!\n", __FILE__, __LINE__); + goto bce_nvram_test_exit; + } + + csum = ether_crc32_le(data, 0x100); + if (csum != BCE_CRC32_RESIDUAL) { + rc = ENODEV; + BCE_PRINTF("%s(%d): Invalid manufacturing information " + "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", + __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum); + goto bce_nvram_test_exit; + } + + csum = ether_crc32_le(data + 0x100, 0x100); + if (csum != BCE_CRC32_RESIDUAL) { + rc = ENODEV; + BCE_PRINTF("%s(%d): Invalid feature configuration " + "information NVRAM CRC! Expected: 0x%08X, " + "Found: 08%08X\n", __FILE__, __LINE__, + BCE_CRC32_RESIDUAL, csum); + } + +bce_nvram_test_exit: + DBEXIT(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); + return rc; +} + + +/****************************************************************************/ +/* Identifies the current media type of the controller and sets the PHY */ +/* address. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_get_media(struct bce_softc *sc) +{ + u32 val; + + DBENTER(BCE_VERBOSE_PHY); + + /* Assume PHY address for copper controllers. */ + sc->bce_phy_addr = 1; + + if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { + u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL); + u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID; + u32 strap; + + /* + * The BCM5709S is software configurable + * for Copper or SerDes operation. + */ + if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { + DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " + "for copper.\n"); + goto bce_get_media_exit; + } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { + DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " + "for dual media.\n"); + sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; + goto bce_get_media_exit; + } + + if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) + strap = (val & + BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; + else + strap = (val & + BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8; + + if (pci_get_function(sc->bce_dev) == 0) { + switch (strap) { + case 0x4: + case 0x5: + case 0x6: + DBPRINT(sc, BCE_INFO_LOAD, + "BCM5709 s/w configured for SerDes.\n"); + sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; + break; + default: + DBPRINT(sc, BCE_INFO_LOAD, + "BCM5709 s/w configured for Copper.\n"); + break; + } + } else { + switch (strap) { + case 0x1: + case 0x2: + case 0x4: + DBPRINT(sc, BCE_INFO_LOAD, + "BCM5709 s/w configured for SerDes.\n"); + sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; + break; + default: + DBPRINT(sc, BCE_INFO_LOAD, + "BCM5709 s/w configured for Copper.\n"); + break; + } + } + + } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) + sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; + + if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) { + + sc->bce_flags |= BCE_NO_WOL_FLAG; + + if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) + sc->bce_phy_flags |= BCE_PHY_IEEE_CLAUSE_45_FLAG; + + if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { + /* 5708S/09S/16S use a separate PHY for SerDes. */ + sc->bce_phy_addr = 2; + + val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); + if (val & BCE_SHARED_HW_CFG_PHY_2_5G) { + sc->bce_phy_flags |= + BCE_PHY_2_5G_CAPABLE_FLAG; + DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb " + "capable adapter\n"); + } + } + } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) || + (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) + sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG; + +bce_get_media_exit: + DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY), + "Using PHY address %d.\n", sc->bce_phy_addr); + + DBEXIT(BCE_VERBOSE_PHY); +} + + +/****************************************************************************/ +/* Performs PHY initialization required before MII drivers access the */ +/* device. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_init_media(struct bce_softc *sc) +{ + if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { + /* + * Configure 5709S/5716S PHYs to use traditional IEEE + * Clause 22 method. Otherwise we have no way to attach + * the PHY in mii(4) layer. PHY specific configuration + * is done in mii layer. + */ + + /* Select auto-negotiation MMD of the PHY. */ + bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, + BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT); + bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, + BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD); + + /* Set IEEE0 block of AN MMD (assumed in brgphy(4) code). */ + bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, + BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); + } +} + + +/****************************************************************************/ +/* Free any DMA memory owned by the driver. */ +/* */ +/* Scans through each data structre that requires DMA memory and frees */ +/* the memory if allocated. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_dma_free(struct bce_softc *sc) +{ + int i; + + DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); + + /* Free, unmap, and destroy the status block. */ + if (sc->status_block != NULL) { + bus_dmamem_free( + sc->status_tag, + sc->status_block, + sc->status_map); + sc->status_block = NULL; + } + + if (sc->status_map != NULL) { + bus_dmamap_unload( + sc->status_tag, + sc->status_map); + bus_dmamap_destroy(sc->status_tag, + sc->status_map); + sc->status_map = NULL; + } + + if (sc->status_tag != NULL) { + bus_dma_tag_destroy(sc->status_tag); + sc->status_tag = NULL; + } + + + /* Free, unmap, and destroy the statistics block. */ + if (sc->stats_block != NULL) { + bus_dmamem_free( + sc->stats_tag, + sc->stats_block, + sc->stats_map); + sc->stats_block = NULL; + } + + if (sc->stats_map != NULL) { + bus_dmamap_unload( + sc->stats_tag, + sc->stats_map); + bus_dmamap_destroy(sc->stats_tag, + sc->stats_map); + sc->stats_map = NULL; + } + + if (sc->stats_tag != NULL) { + bus_dma_tag_destroy(sc->stats_tag); + sc->stats_tag = NULL; + } + + + /* Free, unmap and destroy all context memory pages. */ + if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || + (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { + for (i = 0; i < sc->ctx_pages; i++ ) { + if (sc->ctx_block[i] != NULL) { + bus_dmamem_free( + sc->ctx_tag, + sc->ctx_block[i], + sc->ctx_map[i]); + sc->ctx_block[i] = NULL; + } + + if (sc->ctx_map[i] != NULL) { + bus_dmamap_unload( + sc->ctx_tag, + sc->ctx_map[i]); + bus_dmamap_destroy( + sc->ctx_tag, + sc->ctx_map[i]); + sc->ctx_map[i] = NULL; + } + } + + /* Destroy the context memory tag. */ + if (sc->ctx_tag != NULL) { + bus_dma_tag_destroy(sc->ctx_tag); + sc->ctx_tag = NULL; + } + } + + + /* Free, unmap and destroy all TX buffer descriptor chain pages. */ + for (i = 0; i < TX_PAGES; i++ ) { + if (sc->tx_bd_chain[i] != NULL) { + bus_dmamem_free( + sc->tx_bd_chain_tag, + sc->tx_bd_chain[i], + sc->tx_bd_chain_map[i]); + sc->tx_bd_chain[i] = NULL; + } + + if (sc->tx_bd_chain_map[i] != NULL) { + bus_dmamap_unload( + sc->tx_bd_chain_tag, + sc->tx_bd_chain_map[i]); + bus_dmamap_destroy( + sc->tx_bd_chain_tag, + sc->tx_bd_chain_map[i]); + sc->tx_bd_chain_map[i] = NULL; + } + } + + /* Destroy the TX buffer descriptor tag. */ + if (sc->tx_bd_chain_tag != NULL) { + bus_dma_tag_destroy(sc->tx_bd_chain_tag); + sc->tx_bd_chain_tag = NULL; + } + + + /* Free, unmap and destroy all RX buffer descriptor chain pages. */ + for (i = 0; i < RX_PAGES; i++ ) { + if (sc->rx_bd_chain[i] != NULL) { + bus_dmamem_free( + sc->rx_bd_chain_tag, + sc->rx_bd_chain[i], + sc->rx_bd_chain_map[i]); + sc->rx_bd_chain[i] = NULL; + } + + if (sc->rx_bd_chain_map[i] != NULL) { + bus_dmamap_unload( + sc->rx_bd_chain_tag, + sc->rx_bd_chain_map[i]); + bus_dmamap_destroy( + sc->rx_bd_chain_tag, + sc->rx_bd_chain_map[i]); + sc->rx_bd_chain_map[i] = NULL; + } + } + + /* Destroy the RX buffer descriptor tag. */ + if (sc->rx_bd_chain_tag != NULL) { + bus_dma_tag_destroy(sc->rx_bd_chain_tag); + sc->rx_bd_chain_tag = NULL; + } + + +#ifdef BCE_JUMBO_HDRSPLIT + /* Free, unmap and destroy all page buffer descriptor chain pages. */ + for (i = 0; i < PG_PAGES; i++ ) { + if (sc->pg_bd_chain[i] != NULL) { + bus_dmamem_free( + sc->pg_bd_chain_tag, + sc->pg_bd_chain[i], + sc->pg_bd_chain_map[i]); + sc->pg_bd_chain[i] = NULL; + } + + if (sc->pg_bd_chain_map[i] != NULL) { + bus_dmamap_unload( + sc->pg_bd_chain_tag, + sc->pg_bd_chain_map[i]); + bus_dmamap_destroy( + sc->pg_bd_chain_tag, + sc->pg_bd_chain_map[i]); + sc->pg_bd_chain_map[i] = NULL; + } + } + + /* Destroy the page buffer descriptor tag. */ + if (sc->pg_bd_chain_tag != NULL) { + bus_dma_tag_destroy(sc->pg_bd_chain_tag); + sc->pg_bd_chain_tag = NULL; + } +#endif + + + /* Unload and destroy the TX mbuf maps. */ + for (i = 0; i < TOTAL_TX_BD; i++) { + if (sc->tx_mbuf_map[i] != NULL) { + bus_dmamap_unload(sc->tx_mbuf_tag, + sc->tx_mbuf_map[i]); + bus_dmamap_destroy(sc->tx_mbuf_tag, + sc->tx_mbuf_map[i]); + sc->tx_mbuf_map[i] = NULL; + } + } + + /* Destroy the TX mbuf tag. */ + if (sc->tx_mbuf_tag != NULL) { + bus_dma_tag_destroy(sc->tx_mbuf_tag); + sc->tx_mbuf_tag = NULL; + } + + /* Unload and destroy the RX mbuf maps. */ + for (i = 0; i < TOTAL_RX_BD; i++) { + if (sc->rx_mbuf_map[i] != NULL) { + bus_dmamap_unload(sc->rx_mbuf_tag, + sc->rx_mbuf_map[i]); + bus_dmamap_destroy(sc->rx_mbuf_tag, + sc->rx_mbuf_map[i]); + sc->rx_mbuf_map[i] = NULL; + } + } + + /* Destroy the RX mbuf tag. */ + if (sc->rx_mbuf_tag != NULL) { + bus_dma_tag_destroy(sc->rx_mbuf_tag); + sc->rx_mbuf_tag = NULL; + } + +#ifdef BCE_JUMBO_HDRSPLIT + /* Unload and destroy the page mbuf maps. */ + for (i = 0; i < TOTAL_PG_BD; i++) { + if (sc->pg_mbuf_map[i] != NULL) { + bus_dmamap_unload(sc->pg_mbuf_tag, + sc->pg_mbuf_map[i]); + bus_dmamap_destroy(sc->pg_mbuf_tag, + sc->pg_mbuf_map[i]); + sc->pg_mbuf_map[i] = NULL; + } + } + + /* Destroy the page mbuf tag. */ + if (sc->pg_mbuf_tag != NULL) { + bus_dma_tag_destroy(sc->pg_mbuf_tag); + sc->pg_mbuf_tag = NULL; + } +#endif + + /* Destroy the parent tag */ + if (sc->parent_tag != NULL) { + bus_dma_tag_destroy(sc->parent_tag); + sc->parent_tag = NULL; + } + + DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); +} + + +/****************************************************************************/ +/* Get DMA memory from the OS. */ +/* */ +/* Validates that the OS has provided DMA buffers in response to a */ +/* bus_dmamap_load() call and saves the physical address of those buffers. */ +/* When the callback is used the OS will return 0 for the mapping function */ +/* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */ +/* failures back to the caller. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) +{ + bus_addr_t *busaddr = arg; + + KASSERT(nseg == 1, ("%s(): Too many segments returned (%d)!", + __FUNCTION__, nseg)); + /* Simulate a mapping failure. */ + DBRUNIF(DB_RANDOMTRUE(dma_map_addr_failed_sim_control), + error = ENOMEM); + + /* ToDo: How to increment debug sim_count variable here? */ + + /* Check for an error and signal the caller that an error occurred. */ + if (error) { + *busaddr = 0; + } else { + *busaddr = segs->ds_addr; + } + + return; +} + + +/****************************************************************************/ +/* Allocate any DMA memory needed by the driver. */ +/* */ +/* Allocates DMA memory needed for the various global structures needed by */ +/* hardware. */ +/* */ +/* Memory alignment requirements: */ +/* +-----------------+----------+----------+----------+----------+ */ +/* | | 5706 | 5708 | 5709 | 5716 | */ +/* +-----------------+----------+----------+----------+----------+ */ +/* |Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ +/* |Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ +/* |RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */ +/* |PG Buffers | none | none | none | none | */ +/* |TX Buffers | none | none | none | none | */ +/* |Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */ +/* |Context Memory | | | | | */ +/* +-----------------+----------+----------+----------+----------+ */ +/* */ +/* (1) Must align with CPU page size (BCM_PAGE_SZIE). */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_dma_alloc(device_t dev) +{ + struct bce_softc *sc; + int i, error, rc = 0; + bus_size_t max_size, max_seg_size; + int max_segments; + + sc = device_get_softc(dev); + + DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); + + /* + * Allocate the parent bus DMA tag appropriate for PCI. + */ + if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, BCE_DMA_BOUNDARY, + sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, + BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, + &sc->parent_tag)) { + BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n", + __FILE__, __LINE__); + rc = ENOMEM; + goto bce_dma_alloc_exit; + } + + /* + * Create a DMA tag for the status block, allocate and clear the + * memory, map the memory into DMA space, and fetch the physical + * address of the block. + */ + if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, + BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, + NULL, NULL, BCE_STATUS_BLK_SZ, 1, BCE_STATUS_BLK_SZ, + 0, NULL, NULL, &sc->status_tag)) { + BCE_PRINTF("%s(%d): Could not allocate status block " + "DMA tag!\n", __FILE__, __LINE__); + rc = ENOMEM; + goto bce_dma_alloc_exit; + } + + if(bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block, + BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, + &sc->status_map)) { + BCE_PRINTF("%s(%d): Could not allocate status block " + "DMA memory!\n", __FILE__, __LINE__); + rc = ENOMEM; + goto bce_dma_alloc_exit; + } + + error = bus_dmamap_load(sc->status_tag, sc->status_map, + sc->status_block, BCE_STATUS_BLK_SZ, bce_dma_map_addr, + &sc->status_block_paddr, BUS_DMA_NOWAIT); + + if (error) { + BCE_PRINTF("%s(%d): Could not map status block " + "DMA memory!\n", __FILE__, __LINE__); + rc = ENOMEM; + goto bce_dma_alloc_exit; + } + + DBPRINT(sc, BCE_INFO_LOAD, "%s(): status_block_paddr = 0x%jX\n", + __FUNCTION__, (uintmax_t) sc->status_block_paddr); + + /* + * Create a DMA tag for the statistics block, allocate and clear the + * memory, map the memory into DMA space, and fetch the physical + * address of the block. + */ + if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, + BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, + NULL, NULL, BCE_STATS_BLK_SZ, 1, BCE_STATS_BLK_SZ, + 0, NULL, NULL, &sc->stats_tag)) { + BCE_PRINTF("%s(%d): Could not allocate statistics block " + "DMA tag!\n", __FILE__, __LINE__); + rc = ENOMEM; + goto bce_dma_alloc_exit; + } + + if (bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block, + BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->stats_map)) { + BCE_PRINTF("%s(%d): Could not allocate statistics block " + "DMA memory!\n", __FILE__, __LINE__); + rc = ENOMEM; + goto bce_dma_alloc_exit; + } + + error = bus_dmamap_load(sc->stats_tag, sc->stats_map, + sc->stats_block, BCE_STATS_BLK_SZ, bce_dma_map_addr, + &sc->stats_block_paddr, BUS_DMA_NOWAIT); + + if(error) { + BCE_PRINTF("%s(%d): Could not map statistics block " + "DMA memory!\n", __FILE__, __LINE__); + rc = ENOMEM; + goto bce_dma_alloc_exit; + } + + DBPRINT(sc, BCE_INFO_LOAD, "%s(): stats_block_paddr = 0x%jX\n", + __FUNCTION__, (uintmax_t) sc->stats_block_paddr); + + /* BCM5709 uses host memory as cache for context memory. */ + if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || + (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { + sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; + if (sc->ctx_pages == 0) + sc->ctx_pages = 1; + + DBRUNIF((sc->ctx_pages > 512), + BCE_PRINTF("%s(%d): Too many CTX pages! %d > 512\n", + __FILE__, __LINE__, sc->ctx_pages)); + + /* + * Create a DMA tag for the context pages, + * allocate and clear the memory, map the + * memory into DMA space, and fetch the + * physical address of the block. + */ + if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, + BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, + NULL, NULL, BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE, + 0, NULL, NULL, &sc->ctx_tag)) { + BCE_PRINTF("%s(%d): Could not allocate CTX " + "DMA tag!\n", __FILE__, __LINE__); + rc = ENOMEM; + goto bce_dma_alloc_exit; + } + + for (i = 0; i < sc->ctx_pages; i++) { + + if(bus_dmamem_alloc(sc->ctx_tag, + (void **)&sc->ctx_block[i], + BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, + &sc->ctx_map[i])) { + BCE_PRINTF("%s(%d): Could not allocate CTX " + "DMA memory!\n", __FILE__, __LINE__); + rc = ENOMEM; + goto bce_dma_alloc_exit; + } + + error = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i], + sc->ctx_block[i], BCM_PAGE_SIZE, bce_dma_map_addr, + &sc->ctx_paddr[i], BUS_DMA_NOWAIT); + + if (error) { + BCE_PRINTF("%s(%d): Could not map CTX " + "DMA memory!\n", __FILE__, __LINE__); + rc = ENOMEM; + goto bce_dma_alloc_exit; + } + + DBPRINT(sc, BCE_INFO_LOAD, "%s(): ctx_paddr[%d] " + "= 0x%jX\n", __FUNCTION__, i, + (uintmax_t) sc->ctx_paddr[i]); + } + } + + /* + * Create a DMA tag for the TX buffer descriptor chain, + * allocate and clear the memory, and fetch the + * physical address of the block. + */ + if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, BCE_DMA_BOUNDARY, + sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, + BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ, 0, + NULL, NULL, &sc->tx_bd_chain_tag)) { + BCE_PRINTF("%s(%d): Could not allocate TX descriptor " + "chain DMA tag!\n", __FILE__, __LINE__); + rc = ENOMEM; + goto bce_dma_alloc_exit; + } + + for (i = 0; i < TX_PAGES; i++) { + + if(bus_dmamem_alloc(sc->tx_bd_chain_tag, + (void **)&sc->tx_bd_chain[i], + BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, + &sc->tx_bd_chain_map[i])) { + BCE_PRINTF("%s(%d): Could not allocate TX descriptor " + "chain DMA memory!\n", __FILE__, __LINE__); + rc = ENOMEM; + goto bce_dma_alloc_exit; + } + + error = bus_dmamap_load(sc->tx_bd_chain_tag, + sc->tx_bd_chain_map[i], sc->tx_bd_chain[i], + BCE_TX_CHAIN_PAGE_SZ, bce_dma_map_addr, + &sc->tx_bd_chain_paddr[i], BUS_DMA_NOWAIT); + + if (error) { + BCE_PRINTF("%s(%d): Could not map TX descriptor " + "chain DMA memory!\n", __FILE__, __LINE__); + rc = ENOMEM; + goto bce_dma_alloc_exit; + } + + DBPRINT(sc, BCE_INFO_LOAD, "%s(): tx_bd_chain_paddr[%d] = " + "0x%jX\n", __FUNCTION__, i, + (uintmax_t) sc->tx_bd_chain_paddr[i]); + } + + /* Check the required size before mapping to conserve resources. */ + if (bce_tso_enable) { + max_size = BCE_TSO_MAX_SIZE; + max_segments = BCE_MAX_SEGMENTS; + max_seg_size = BCE_TSO_MAX_SEG_SIZE; + } else { + max_size = MCLBYTES * BCE_MAX_SEGMENTS; + max_segments = BCE_MAX_SEGMENTS; + max_seg_size = MCLBYTES; + } + + /* Create a DMA tag for TX mbufs. */ + if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, + sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, max_size, + max_segments, max_seg_size, 0, NULL, NULL, &sc->tx_mbuf_tag)) { + BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n", + __FILE__, __LINE__); + rc = ENOMEM; + goto bce_dma_alloc_exit; + } + + /* Create DMA maps for the TX mbufs clusters. */ + for (i = 0; i < TOTAL_TX_BD; i++) { + if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT, + &sc->tx_mbuf_map[i])) { + BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA " + "map!\n", __FILE__, __LINE__); + rc = ENOMEM; + goto bce_dma_alloc_exit; + } + } + + /* + * Create a DMA tag for the RX buffer descriptor chain, + * allocate and clear the memory, and fetch the physical + * address of the blocks. + */ + if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, + BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, + sc->max_bus_addr, NULL, NULL, + BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ, + 0, NULL, NULL, &sc->rx_bd_chain_tag)) { + BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain " + "DMA tag!\n", __FILE__, __LINE__); + rc = ENOMEM; + goto bce_dma_alloc_exit; + } + + for (i = 0; i < RX_PAGES; i++) { + + if (bus_dmamem_alloc(sc->rx_bd_chain_tag, + (void **)&sc->rx_bd_chain[i], + BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, + &sc->rx_bd_chain_map[i])) { + BCE_PRINTF("%s(%d): Could not allocate RX descriptor " + "chain DMA memory!\n", __FILE__, __LINE__); + rc = ENOMEM; + goto bce_dma_alloc_exit; + } + + error = bus_dmamap_load(sc->rx_bd_chain_tag, + sc->rx_bd_chain_map[i], sc->rx_bd_chain[i], + BCE_RX_CHAIN_PAGE_SZ, bce_dma_map_addr, + &sc->rx_bd_chain_paddr[i], BUS_DMA_NOWAIT); + + if (error) { + BCE_PRINTF("%s(%d): Could not map RX descriptor " + "chain DMA memory!\n", __FILE__, __LINE__); + rc = ENOMEM; + goto bce_dma_alloc_exit; + } + + DBPRINT(sc, BCE_INFO_LOAD, "%s(): rx_bd_chain_paddr[%d] = " + "0x%jX\n", __FUNCTION__, i, + (uintmax_t) sc->rx_bd_chain_paddr[i]); + } + + /* + * Create a DMA tag for RX mbufs. + */ +#ifdef BCE_JUMBO_HDRSPLIT + max_size = max_seg_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ? + MCLBYTES : sc->rx_bd_mbuf_alloc_size); +#else + max_size = max_seg_size = MJUM9BYTES; +#endif + max_segments = 1; + + DBPRINT(sc, BCE_INFO_LOAD, "%s(): Creating rx_mbuf_tag " + "(max size = 0x%jX max segments = %d, max segment " + "size = 0x%jX)\n", __FUNCTION__, (uintmax_t) max_size, + max_segments, (uintmax_t) max_seg_size); + + if (bus_dma_tag_create(sc->parent_tag, BCE_RX_BUF_ALIGN, + BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, + max_size, max_segments, max_seg_size, 0, NULL, NULL, + &sc->rx_mbuf_tag)) { + BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n", + __FILE__, __LINE__); + rc = ENOMEM; + goto bce_dma_alloc_exit; + } + + /* Create DMA maps for the RX mbuf clusters. */ + for (i = 0; i < TOTAL_RX_BD; i++) { + if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT, + &sc->rx_mbuf_map[i])) { + BCE_PRINTF("%s(%d): Unable to create RX mbuf " + "DMA map!\n", __FILE__, __LINE__); + rc = ENOMEM; + goto bce_dma_alloc_exit; + } + } + +#ifdef BCE_JUMBO_HDRSPLIT + /* + * Create a DMA tag for the page buffer descriptor chain, + * allocate and clear the memory, and fetch the physical + * address of the blocks. + */ + if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, + BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, sc->max_bus_addr, + NULL, NULL, BCE_PG_CHAIN_PAGE_SZ, 1, BCE_PG_CHAIN_PAGE_SZ, + 0, NULL, NULL, &sc->pg_bd_chain_tag)) { + BCE_PRINTF("%s(%d): Could not allocate page descriptor " + "chain DMA tag!\n", __FILE__, __LINE__); + rc = ENOMEM; + goto bce_dma_alloc_exit; + } + + for (i = 0; i < PG_PAGES; i++) { + + if (bus_dmamem_alloc(sc->pg_bd_chain_tag, + (void **)&sc->pg_bd_chain[i], + BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, + &sc->pg_bd_chain_map[i])) { + BCE_PRINTF("%s(%d): Could not allocate page " + "descriptor chain DMA memory!\n", + __FILE__, __LINE__); + rc = ENOMEM; + goto bce_dma_alloc_exit; + } + + error = bus_dmamap_load(sc->pg_bd_chain_tag, + sc->pg_bd_chain_map[i], sc->pg_bd_chain[i], + BCE_PG_CHAIN_PAGE_SZ, bce_dma_map_addr, + &sc->pg_bd_chain_paddr[i], BUS_DMA_NOWAIT); + + if (error) { + BCE_PRINTF("%s(%d): Could not map page descriptor " + "chain DMA memory!\n", __FILE__, __LINE__); + rc = ENOMEM; + goto bce_dma_alloc_exit; + } + + DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_chain_paddr[%d] = " + "0x%jX\n", __FUNCTION__, i, + (uintmax_t) sc->pg_bd_chain_paddr[i]); + } + + /* + * Create a DMA tag for page mbufs. + */ + max_size = max_seg_size = ((sc->pg_bd_mbuf_alloc_size < MCLBYTES) ? + MCLBYTES : sc->pg_bd_mbuf_alloc_size); + + if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, + sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, + max_size, 1, max_seg_size, 0, NULL, NULL, &sc->pg_mbuf_tag)) { + BCE_PRINTF("%s(%d): Could not allocate page mbuf " + "DMA tag!\n", __FILE__, __LINE__); + rc = ENOMEM; + goto bce_dma_alloc_exit; + } + + /* Create DMA maps for the page mbuf clusters. */ + for (i = 0; i < TOTAL_PG_BD; i++) { + if (bus_dmamap_create(sc->pg_mbuf_tag, BUS_DMA_NOWAIT, + &sc->pg_mbuf_map[i])) { + BCE_PRINTF("%s(%d): Unable to create page mbuf " + "DMA map!\n", __FILE__, __LINE__); + rc = ENOMEM; + goto bce_dma_alloc_exit; + } + } +#endif + +bce_dma_alloc_exit: + DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); + return(rc); +} + + +/****************************************************************************/ +/* Release all resources used by the driver. */ +/* */ +/* Releases all resources acquired by the driver including interrupts, */ +/* interrupt handler, interfaces, mutexes, and DMA memory. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_release_resources(struct bce_softc *sc) +{ + device_t dev; + + DBENTER(BCE_VERBOSE_RESET); + + dev = sc->bce_dev; + + bce_dma_free(sc); + + if (sc->bce_intrhand != NULL) { + DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n"); + bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand); + } + + if (sc->bce_res_irq != NULL) { + DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n"); + bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid, + sc->bce_res_irq); + } + + if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) { + DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n"); + pci_release_msi(dev); + } + + if (sc->bce_res_mem != NULL) { + DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n"); + bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), + sc->bce_res_mem); + } + + if (sc->bce_ifp != NULL) { + DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n"); + if_free(sc->bce_ifp); + } + + if (mtx_initialized(&sc->bce_mtx)) + BCE_LOCK_DESTROY(sc); + + DBEXIT(BCE_VERBOSE_RESET); +} + + +/****************************************************************************/ +/* Firmware synchronization. */ +/* */ +/* Before performing certain events such as a chip reset, synchronize with */ +/* the firmware first. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_fw_sync(struct bce_softc *sc, u32 msg_data) +{ + int i, rc = 0; + u32 val; + + DBENTER(BCE_VERBOSE_RESET); + + /* Don't waste any time if we've timed out before. */ + if (sc->bce_fw_timed_out == TRUE) { + rc = EBUSY; + goto bce_fw_sync_exit; + } + + /* Increment the message sequence number. */ + sc->bce_fw_wr_seq++; + msg_data |= sc->bce_fw_wr_seq; + + DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = " + "0x%08X\n", msg_data); + + /* Send the message to the bootcode driver mailbox. */ + bce_shmem_wr(sc, BCE_DRV_MB, msg_data); + + /* Wait for the bootcode to acknowledge the message. */ + for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { + /* Check for a response in the bootcode firmware mailbox. */ + val = bce_shmem_rd(sc, BCE_FW_MB); + if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ)) + break; + DELAY(1000); + } + + /* If we've timed out, tell bootcode that we've stopped waiting. */ + if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) && + ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) { + + BCE_PRINTF("%s(%d): Firmware synchronization timeout! " + "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); + + msg_data &= ~BCE_DRV_MSG_CODE; + msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT; + + bce_shmem_wr(sc, BCE_DRV_MB, msg_data); + + sc->bce_fw_timed_out = TRUE; + rc = EBUSY; + } + +bce_fw_sync_exit: + DBEXIT(BCE_VERBOSE_RESET); + return (rc); +} + + +/****************************************************************************/ +/* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_load_rv2p_fw(struct bce_softc *sc, u32 *rv2p_code, + u32 rv2p_code_len, u32 rv2p_proc) +{ + int i; + u32 val; + + DBENTER(BCE_VERBOSE_RESET); + + /* Set the page size used by RV2P. */ + if (rv2p_proc == RV2P_PROC2) { + BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE); + } + + for (i = 0; i < rv2p_code_len; i += 8) { + REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code); + rv2p_code++; + REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code); + rv2p_code++; + + if (rv2p_proc == RV2P_PROC1) { + val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR; + REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val); + } + else { + val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR; + REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val); + } + } + + /* Reset the processor, un-stall is done later. */ + if (rv2p_proc == RV2P_PROC1) { + REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET); + } + else { + REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET); + } + + DBEXIT(BCE_VERBOSE_RESET); +} + + +/****************************************************************************/ +/* Load RISC processor firmware. */ +/* */ +/* Loads firmware from the file if_bcefw.h into the scratchpad memory */ +/* associated with a particular processor. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg, + struct fw_info *fw) +{ + u32 offset; + + DBENTER(BCE_VERBOSE_RESET); + + bce_halt_cpu(sc, cpu_reg); + + /* Load the Text area. */ + offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); + if (fw->text) { + int j; + + for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { + REG_WR_IND(sc, offset, fw->text[j]); + } + } + + /* Load the Data area. */ + offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); + if (fw->data) { + int j; + + for (j = 0; j < (fw->data_len / 4); j++, offset += 4) { + REG_WR_IND(sc, offset, fw->data[j]); + } + } + + /* Load the SBSS area. */ + offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); + if (fw->sbss) { + int j; + + for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) { + REG_WR_IND(sc, offset, fw->sbss[j]); + } + } + + /* Load the BSS area. */ + offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); + if (fw->bss) { + int j; + + for (j = 0; j < (fw->bss_len/4); j++, offset += 4) { + REG_WR_IND(sc, offset, fw->bss[j]); + } + } + + /* Load the Read-Only area. */ + offset = cpu_reg->spad_base + + (fw->rodata_addr - cpu_reg->mips_view_base); + if (fw->rodata) { + int j; + + for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) { + REG_WR_IND(sc, offset, fw->rodata[j]); + } + } + + /* Clear the pre-fetch instruction and set the FW start address. */ + REG_WR_IND(sc, cpu_reg->inst, 0); + REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); + + DBEXIT(BCE_VERBOSE_RESET); +} + + +/****************************************************************************/ +/* Starts the RISC processor. */ +/* */ +/* Assumes the CPU starting address has already been set. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) +{ + u32 val; + + DBENTER(BCE_VERBOSE_RESET); + + /* Start the CPU. */ + val = REG_RD_IND(sc, cpu_reg->mode); + val &= ~cpu_reg->mode_value_halt; + REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); + REG_WR_IND(sc, cpu_reg->mode, val); + + DBEXIT(BCE_VERBOSE_RESET); +} + + +/****************************************************************************/ +/* Halts the RISC processor. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) +{ + u32 val; + + DBENTER(BCE_VERBOSE_RESET); + + /* Halt the CPU. */ + val = REG_RD_IND(sc, cpu_reg->mode); + val |= cpu_reg->mode_value_halt; + REG_WR_IND(sc, cpu_reg->mode, val); + REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); + + DBEXIT(BCE_VERBOSE_RESET); +} + + +/****************************************************************************/ +/* Initialize the RX CPU. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_start_rxp_cpu(struct bce_softc *sc) +{ + struct cpu_reg cpu_reg; + + DBENTER(BCE_VERBOSE_RESET); + + cpu_reg.mode = BCE_RXP_CPU_MODE; + cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; + cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; + cpu_reg.state = BCE_RXP_CPU_STATE; + cpu_reg.state_value_clear = 0xffffff; + cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; + cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; + cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; + cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; + cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; + cpu_reg.spad_base = BCE_RXP_SCRATCH; + cpu_reg.mips_view_base = 0x8000000; + + DBPRINT(sc, BCE_INFO_RESET, "Starting RX firmware.\n"); + bce_start_cpu(sc, &cpu_reg); + + DBEXIT(BCE_VERBOSE_RESET); +} + + +/****************************************************************************/ +/* Initialize the RX CPU. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_init_rxp_cpu(struct bce_softc *sc) +{ + struct cpu_reg cpu_reg; + struct fw_info fw; + + DBENTER(BCE_VERBOSE_RESET); + + cpu_reg.mode = BCE_RXP_CPU_MODE; + cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; + cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; + cpu_reg.state = BCE_RXP_CPU_STATE; + cpu_reg.state_value_clear = 0xffffff; + cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; + cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; + cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; + cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; + cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; + cpu_reg.spad_base = BCE_RXP_SCRATCH; + cpu_reg.mips_view_base = 0x8000000; + + if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || + (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { + fw.ver_major = bce_RXP_b09FwReleaseMajor; + fw.ver_minor = bce_RXP_b09FwReleaseMinor; + fw.ver_fix = bce_RXP_b09FwReleaseFix; + fw.start_addr = bce_RXP_b09FwStartAddr; + + fw.text_addr = bce_RXP_b09FwTextAddr; + fw.text_len = bce_RXP_b09FwTextLen; + fw.text_index = 0; + fw.text = bce_RXP_b09FwText; + + fw.data_addr = bce_RXP_b09FwDataAddr; + fw.data_len = bce_RXP_b09FwDataLen; + fw.data_index = 0; + fw.data = bce_RXP_b09FwData; + + fw.sbss_addr = bce_RXP_b09FwSbssAddr; + fw.sbss_len = bce_RXP_b09FwSbssLen; + fw.sbss_index = 0; + fw.sbss = bce_RXP_b09FwSbss; + + fw.bss_addr = bce_RXP_b09FwBssAddr; + fw.bss_len = bce_RXP_b09FwBssLen; + fw.bss_index = 0; + fw.bss = bce_RXP_b09FwBss; + + fw.rodata_addr = bce_RXP_b09FwRodataAddr; + fw.rodata_len = bce_RXP_b09FwRodataLen; + fw.rodata_index = 0; + fw.rodata = bce_RXP_b09FwRodata; + } else { + fw.ver_major = bce_RXP_b06FwReleaseMajor; + fw.ver_minor = bce_RXP_b06FwReleaseMinor; + fw.ver_fix = bce_RXP_b06FwReleaseFix; + fw.start_addr = bce_RXP_b06FwStartAddr; + + fw.text_addr = bce_RXP_b06FwTextAddr; + fw.text_len = bce_RXP_b06FwTextLen; + fw.text_index = 0; + fw.text = bce_RXP_b06FwText; + + fw.data_addr = bce_RXP_b06FwDataAddr; + fw.data_len = bce_RXP_b06FwDataLen; + fw.data_index = 0; + fw.data = bce_RXP_b06FwData; + + fw.sbss_addr = bce_RXP_b06FwSbssAddr; + fw.sbss_len = bce_RXP_b06FwSbssLen; + fw.sbss_index = 0; + fw.sbss = bce_RXP_b06FwSbss; + + fw.bss_addr = bce_RXP_b06FwBssAddr; + fw.bss_len = bce_RXP_b06FwBssLen; + fw.bss_index = 0; + fw.bss = bce_RXP_b06FwBss; + + fw.rodata_addr = bce_RXP_b06FwRodataAddr; + fw.rodata_len = bce_RXP_b06FwRodataLen; + fw.rodata_index = 0; + fw.rodata = bce_RXP_b06FwRodata; + } + + DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n"); + bce_load_cpu_fw(sc, &cpu_reg, &fw); + + /* Delay RXP start until initialization is complete. */ + + DBEXIT(BCE_VERBOSE_RESET); +} + + +/****************************************************************************/ +/* Initialize the TX CPU. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_init_txp_cpu(struct bce_softc *sc) +{ + struct cpu_reg cpu_reg; + struct fw_info fw; + + DBENTER(BCE_VERBOSE_RESET); + + cpu_reg.mode = BCE_TXP_CPU_MODE; + cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT; + cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA; + cpu_reg.state = BCE_TXP_CPU_STATE; + cpu_reg.state_value_clear = 0xffffff; + cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE; + cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK; + cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER; + cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION; + cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT; + cpu_reg.spad_base = BCE_TXP_SCRATCH; + cpu_reg.mips_view_base = 0x8000000; + + if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || + (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { + fw.ver_major = bce_TXP_b09FwReleaseMajor; + fw.ver_minor = bce_TXP_b09FwReleaseMinor; + fw.ver_fix = bce_TXP_b09FwReleaseFix; + fw.start_addr = bce_TXP_b09FwStartAddr; + + fw.text_addr = bce_TXP_b09FwTextAddr; + fw.text_len = bce_TXP_b09FwTextLen; + fw.text_index = 0; + fw.text = bce_TXP_b09FwText; + + fw.data_addr = bce_TXP_b09FwDataAddr; + fw.data_len = bce_TXP_b09FwDataLen; + fw.data_index = 0; + fw.data = bce_TXP_b09FwData; + + fw.sbss_addr = bce_TXP_b09FwSbssAddr; + fw.sbss_len = bce_TXP_b09FwSbssLen; + fw.sbss_index = 0; + fw.sbss = bce_TXP_b09FwSbss; + + fw.bss_addr = bce_TXP_b09FwBssAddr; + fw.bss_len = bce_TXP_b09FwBssLen; + fw.bss_index = 0; + fw.bss = bce_TXP_b09FwBss; + + fw.rodata_addr = bce_TXP_b09FwRodataAddr; + fw.rodata_len = bce_TXP_b09FwRodataLen; + fw.rodata_index = 0; + fw.rodata = bce_TXP_b09FwRodata; + } else { + fw.ver_major = bce_TXP_b06FwReleaseMajor; + fw.ver_minor = bce_TXP_b06FwReleaseMinor; + fw.ver_fix = bce_TXP_b06FwReleaseFix; + fw.start_addr = bce_TXP_b06FwStartAddr; + + fw.text_addr = bce_TXP_b06FwTextAddr; + fw.text_len = bce_TXP_b06FwTextLen; + fw.text_index = 0; + fw.text = bce_TXP_b06FwText; + + fw.data_addr = bce_TXP_b06FwDataAddr; + fw.data_len = bce_TXP_b06FwDataLen; + fw.data_index = 0; + fw.data = bce_TXP_b06FwData; + + fw.sbss_addr = bce_TXP_b06FwSbssAddr; + fw.sbss_len = bce_TXP_b06FwSbssLen; + fw.sbss_index = 0; + fw.sbss = bce_TXP_b06FwSbss; + + fw.bss_addr = bce_TXP_b06FwBssAddr; + fw.bss_len = bce_TXP_b06FwBssLen; + fw.bss_index = 0; + fw.bss = bce_TXP_b06FwBss; + + fw.rodata_addr = bce_TXP_b06FwRodataAddr; + fw.rodata_len = bce_TXP_b06FwRodataLen; + fw.rodata_index = 0; + fw.rodata = bce_TXP_b06FwRodata; + } + + DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n"); + bce_load_cpu_fw(sc, &cpu_reg, &fw); + bce_start_cpu(sc, &cpu_reg); + + DBEXIT(BCE_VERBOSE_RESET); +} + + +/****************************************************************************/ +/* Initialize the TPAT CPU. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_init_tpat_cpu(struct bce_softc *sc) +{ + struct cpu_reg cpu_reg; + struct fw_info fw; + + DBENTER(BCE_VERBOSE_RESET); + + cpu_reg.mode = BCE_TPAT_CPU_MODE; + cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT; + cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA; + cpu_reg.state = BCE_TPAT_CPU_STATE; + cpu_reg.state_value_clear = 0xffffff; + cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE; + cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK; + cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER; + cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION; + cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT; + cpu_reg.spad_base = BCE_TPAT_SCRATCH; + cpu_reg.mips_view_base = 0x8000000; + + if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || + (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { + fw.ver_major = bce_TPAT_b09FwReleaseMajor; + fw.ver_minor = bce_TPAT_b09FwReleaseMinor; + fw.ver_fix = bce_TPAT_b09FwReleaseFix; + fw.start_addr = bce_TPAT_b09FwStartAddr; + + fw.text_addr = bce_TPAT_b09FwTextAddr; + fw.text_len = bce_TPAT_b09FwTextLen; + fw.text_index = 0; + fw.text = bce_TPAT_b09FwText; + + fw.data_addr = bce_TPAT_b09FwDataAddr; + fw.data_len = bce_TPAT_b09FwDataLen; + fw.data_index = 0; + fw.data = bce_TPAT_b09FwData; + + fw.sbss_addr = bce_TPAT_b09FwSbssAddr; + fw.sbss_len = bce_TPAT_b09FwSbssLen; + fw.sbss_index = 0; + fw.sbss = bce_TPAT_b09FwSbss; + + fw.bss_addr = bce_TPAT_b09FwBssAddr; + fw.bss_len = bce_TPAT_b09FwBssLen; + fw.bss_index = 0; + fw.bss = bce_TPAT_b09FwBss; + + fw.rodata_addr = bce_TPAT_b09FwRodataAddr; + fw.rodata_len = bce_TPAT_b09FwRodataLen; + fw.rodata_index = 0; + fw.rodata = bce_TPAT_b09FwRodata; + } else { + fw.ver_major = bce_TPAT_b06FwReleaseMajor; + fw.ver_minor = bce_TPAT_b06FwReleaseMinor; + fw.ver_fix = bce_TPAT_b06FwReleaseFix; + fw.start_addr = bce_TPAT_b06FwStartAddr; + + fw.text_addr = bce_TPAT_b06FwTextAddr; + fw.text_len = bce_TPAT_b06FwTextLen; + fw.text_index = 0; + fw.text = bce_TPAT_b06FwText; + + fw.data_addr = bce_TPAT_b06FwDataAddr; + fw.data_len = bce_TPAT_b06FwDataLen; + fw.data_index = 0; + fw.data = bce_TPAT_b06FwData; + + fw.sbss_addr = bce_TPAT_b06FwSbssAddr; + fw.sbss_len = bce_TPAT_b06FwSbssLen; + fw.sbss_index = 0; + fw.sbss = bce_TPAT_b06FwSbss; + + fw.bss_addr = bce_TPAT_b06FwBssAddr; + fw.bss_len = bce_TPAT_b06FwBssLen; + fw.bss_index = 0; + fw.bss = bce_TPAT_b06FwBss; + + fw.rodata_addr = bce_TPAT_b06FwRodataAddr; + fw.rodata_len = bce_TPAT_b06FwRodataLen; + fw.rodata_index = 0; + fw.rodata = bce_TPAT_b06FwRodata; + } + + DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n"); + bce_load_cpu_fw(sc, &cpu_reg, &fw); + bce_start_cpu(sc, &cpu_reg); + + DBEXIT(BCE_VERBOSE_RESET); +} + + +/****************************************************************************/ +/* Initialize the CP CPU. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_init_cp_cpu(struct bce_softc *sc) +{ + struct cpu_reg cpu_reg; + struct fw_info fw; + + DBENTER(BCE_VERBOSE_RESET); + + cpu_reg.mode = BCE_CP_CPU_MODE; + cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT; + cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA; + cpu_reg.state = BCE_CP_CPU_STATE; + cpu_reg.state_value_clear = 0xffffff; + cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE; + cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK; + cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER; + cpu_reg.inst = BCE_CP_CPU_INSTRUCTION; + cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT; + cpu_reg.spad_base = BCE_CP_SCRATCH; + cpu_reg.mips_view_base = 0x8000000; + + if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || + (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { + fw.ver_major = bce_CP_b09FwReleaseMajor; + fw.ver_minor = bce_CP_b09FwReleaseMinor; + fw.ver_fix = bce_CP_b09FwReleaseFix; + fw.start_addr = bce_CP_b09FwStartAddr; + + fw.text_addr = bce_CP_b09FwTextAddr; + fw.text_len = bce_CP_b09FwTextLen; + fw.text_index = 0; + fw.text = bce_CP_b09FwText; + + fw.data_addr = bce_CP_b09FwDataAddr; + fw.data_len = bce_CP_b09FwDataLen; + fw.data_index = 0; + fw.data = bce_CP_b09FwData; + + fw.sbss_addr = bce_CP_b09FwSbssAddr; + fw.sbss_len = bce_CP_b09FwSbssLen; + fw.sbss_index = 0; + fw.sbss = bce_CP_b09FwSbss; + + fw.bss_addr = bce_CP_b09FwBssAddr; + fw.bss_len = bce_CP_b09FwBssLen; + fw.bss_index = 0; + fw.bss = bce_CP_b09FwBss; + + fw.rodata_addr = bce_CP_b09FwRodataAddr; + fw.rodata_len = bce_CP_b09FwRodataLen; + fw.rodata_index = 0; + fw.rodata = bce_CP_b09FwRodata; + } else { + fw.ver_major = bce_CP_b06FwReleaseMajor; + fw.ver_minor = bce_CP_b06FwReleaseMinor; + fw.ver_fix = bce_CP_b06FwReleaseFix; + fw.start_addr = bce_CP_b06FwStartAddr; + + fw.text_addr = bce_CP_b06FwTextAddr; + fw.text_len = bce_CP_b06FwTextLen; + fw.text_index = 0; + fw.text = bce_CP_b06FwText; + + fw.data_addr = bce_CP_b06FwDataAddr; + fw.data_len = bce_CP_b06FwDataLen; + fw.data_index = 0; + fw.data = bce_CP_b06FwData; + + fw.sbss_addr = bce_CP_b06FwSbssAddr; + fw.sbss_len = bce_CP_b06FwSbssLen; + fw.sbss_index = 0; + fw.sbss = bce_CP_b06FwSbss; + + fw.bss_addr = bce_CP_b06FwBssAddr; + fw.bss_len = bce_CP_b06FwBssLen; + fw.bss_index = 0; + fw.bss = bce_CP_b06FwBss; + + fw.rodata_addr = bce_CP_b06FwRodataAddr; + fw.rodata_len = bce_CP_b06FwRodataLen; + fw.rodata_index = 0; + fw.rodata = bce_CP_b06FwRodata; + } + + DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n"); + bce_load_cpu_fw(sc, &cpu_reg, &fw); + bce_start_cpu(sc, &cpu_reg); + + DBEXIT(BCE_VERBOSE_RESET); +} + + +/****************************************************************************/ +/* Initialize the COM CPU. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_init_com_cpu(struct bce_softc *sc) +{ + struct cpu_reg cpu_reg; + struct fw_info fw; + + DBENTER(BCE_VERBOSE_RESET); + + cpu_reg.mode = BCE_COM_CPU_MODE; + cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT; + cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA; + cpu_reg.state = BCE_COM_CPU_STATE; + cpu_reg.state_value_clear = 0xffffff; + cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE; + cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK; + cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER; + cpu_reg.inst = BCE_COM_CPU_INSTRUCTION; + cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT; + cpu_reg.spad_base = BCE_COM_SCRATCH; + cpu_reg.mips_view_base = 0x8000000; + + if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || + (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { + fw.ver_major = bce_COM_b09FwReleaseMajor; + fw.ver_minor = bce_COM_b09FwReleaseMinor; + fw.ver_fix = bce_COM_b09FwReleaseFix; + fw.start_addr = bce_COM_b09FwStartAddr; + + fw.text_addr = bce_COM_b09FwTextAddr; + fw.text_len = bce_COM_b09FwTextLen; + fw.text_index = 0; + fw.text = bce_COM_b09FwText; + + fw.data_addr = bce_COM_b09FwDataAddr; + fw.data_len = bce_COM_b09FwDataLen; + fw.data_index = 0; + fw.data = bce_COM_b09FwData; + + fw.sbss_addr = bce_COM_b09FwSbssAddr; + fw.sbss_len = bce_COM_b09FwSbssLen; + fw.sbss_index = 0; + fw.sbss = bce_COM_b09FwSbss; + + fw.bss_addr = bce_COM_b09FwBssAddr; + fw.bss_len = bce_COM_b09FwBssLen; + fw.bss_index = 0; + fw.bss = bce_COM_b09FwBss; + + fw.rodata_addr = bce_COM_b09FwRodataAddr; + fw.rodata_len = bce_COM_b09FwRodataLen; + fw.rodata_index = 0; + fw.rodata = bce_COM_b09FwRodata; + } else { + fw.ver_major = bce_COM_b06FwReleaseMajor; + fw.ver_minor = bce_COM_b06FwReleaseMinor; + fw.ver_fix = bce_COM_b06FwReleaseFix; + fw.start_addr = bce_COM_b06FwStartAddr; + + fw.text_addr = bce_COM_b06FwTextAddr; + fw.text_len = bce_COM_b06FwTextLen; + fw.text_index = 0; + fw.text = bce_COM_b06FwText; + + fw.data_addr = bce_COM_b06FwDataAddr; + fw.data_len = bce_COM_b06FwDataLen; + fw.data_index = 0; + fw.data = bce_COM_b06FwData; + + fw.sbss_addr = bce_COM_b06FwSbssAddr; + fw.sbss_len = bce_COM_b06FwSbssLen; + fw.sbss_index = 0; + fw.sbss = bce_COM_b06FwSbss; + + fw.bss_addr = bce_COM_b06FwBssAddr; + fw.bss_len = bce_COM_b06FwBssLen; + fw.bss_index = 0; + fw.bss = bce_COM_b06FwBss; + + fw.rodata_addr = bce_COM_b06FwRodataAddr; + fw.rodata_len = bce_COM_b06FwRodataLen; + fw.rodata_index = 0; + fw.rodata = bce_COM_b06FwRodata; + } + + DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n"); + bce_load_cpu_fw(sc, &cpu_reg, &fw); + bce_start_cpu(sc, &cpu_reg); + + DBEXIT(BCE_VERBOSE_RESET); +} + + +/****************************************************************************/ +/* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */ +/* */ +/* Loads the firmware for each CPU and starts the CPU. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_init_cpus(struct bce_softc *sc) +{ + DBENTER(BCE_VERBOSE_RESET); + + if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || + (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { + + if ((BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax)) { + bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1, + sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1); + bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2, + sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2); + } else { + bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1, + sizeof(bce_xi_rv2p_proc1), RV2P_PROC1); + bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2, + sizeof(bce_xi_rv2p_proc2), RV2P_PROC2); + } + + } else { + bce_load_rv2p_fw(sc, bce_rv2p_proc1, + sizeof(bce_rv2p_proc1), RV2P_PROC1); + bce_load_rv2p_fw(sc, bce_rv2p_proc2, + sizeof(bce_rv2p_proc2), RV2P_PROC2); + } + + bce_init_rxp_cpu(sc); + bce_init_txp_cpu(sc); + bce_init_tpat_cpu(sc); + bce_init_com_cpu(sc); + bce_init_cp_cpu(sc); + + DBEXIT(BCE_VERBOSE_RESET); +} + + +/****************************************************************************/ +/* Initialize context memory. */ +/* */ +/* Clears the memory associated with each Context ID (CID). */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static int +bce_init_ctx(struct bce_softc *sc) +{ + u32 offset, val, vcid_addr; + int i, j, rc, retry_cnt; + + rc = 0; + DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); + + if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || + (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { + retry_cnt = CTX_INIT_RETRY_COUNT; + + DBPRINT(sc, BCE_INFO_CTX, "Initializing 5709 context.\n"); + + /* + * BCM5709 context memory may be cached + * in host memory so prepare the host memory + * for access. + */ + val = BCE_CTX_COMMAND_ENABLED | + BCE_CTX_COMMAND_MEM_INIT | (1 << 12); + val |= (BCM_PAGE_BITS - 8) << 16; + REG_WR(sc, BCE_CTX_COMMAND, val); + + /* Wait for mem init command to complete. */ + for (i = 0; i < retry_cnt; i++) { + val = REG_RD(sc, BCE_CTX_COMMAND); + if (!(val & BCE_CTX_COMMAND_MEM_INIT)) + break; + DELAY(2); + } + if ((val & BCE_CTX_COMMAND_MEM_INIT) != 0) { + BCE_PRINTF("%s(): Context memory initialization failed!\n", + __FUNCTION__); + rc = EBUSY; + goto init_ctx_fail; + } + + for (i = 0; i < sc->ctx_pages; i++) { + /* Set the physical address of the context memory. */ + REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0, + BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) | + BCE_CTX_HOST_PAGE_TBL_DATA0_VALID); + REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1, + BCE_ADDR_HI(sc->ctx_paddr[i])); + REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i | + BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); + + /* Verify the context memory write was successful. */ + for (j = 0; j < retry_cnt; j++) { + val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL); + if ((val & + BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) + break; + DELAY(5); + } + if ((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) != 0) { + BCE_PRINTF("%s(): Failed to initialize " + "context page %d!\n", __FUNCTION__, i); + rc = EBUSY; + goto init_ctx_fail; + } + } + } else { + + DBPRINT(sc, BCE_INFO, "Initializing 5706/5708 context.\n"); + + /* + * For the 5706/5708, context memory is local to + * the controller, so initialize the controller + * context memory. + */ + + vcid_addr = GET_CID_ADDR(96); + while (vcid_addr) { + + vcid_addr -= PHY_CTX_SIZE; + + REG_WR(sc, BCE_CTX_VIRT_ADDR, 0); + REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); + + for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) { + CTX_WR(sc, 0x00, offset, 0); + } + + REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr); + REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); + } + + } +init_ctx_fail: + DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); + return (rc); +} + + +/****************************************************************************/ +/* Fetch the permanent MAC address of the controller. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_get_mac_addr(struct bce_softc *sc) +{ + u32 mac_lo = 0, mac_hi = 0; + + DBENTER(BCE_VERBOSE_RESET); + + /* + * The NetXtreme II bootcode populates various NIC + * power-on and runtime configuration items in a + * shared memory area. The factory configured MAC + * address is available from both NVRAM and the + * shared memory area so we'll read the value from + * shared memory for speed. + */ + + mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER); + mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER); + + if ((mac_lo == 0) && (mac_hi == 0)) { + BCE_PRINTF("%s(%d): Invalid Ethernet address!\n", + __FILE__, __LINE__); + } else { + sc->eaddr[0] = (u_char)(mac_hi >> 8); + sc->eaddr[1] = (u_char)(mac_hi >> 0); + sc->eaddr[2] = (u_char)(mac_lo >> 24); + sc->eaddr[3] = (u_char)(mac_lo >> 16); + sc->eaddr[4] = (u_char)(mac_lo >> 8); + sc->eaddr[5] = (u_char)(mac_lo >> 0); + } + + DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet " + "address = %6D\n", sc->eaddr, ":"); + DBEXIT(BCE_VERBOSE_RESET); +} + + +/****************************************************************************/ +/* Program the MAC address. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_set_mac_addr(struct bce_softc *sc) +{ + u32 val; + u8 *mac_addr = sc->eaddr; + + /* ToDo: Add support for setting multiple MAC addresses. */ + + DBENTER(BCE_VERBOSE_RESET); + DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = " + "%6D\n", sc->eaddr, ":"); + + val = (mac_addr[0] << 8) | mac_addr[1]; + + REG_WR(sc, BCE_EMAC_MAC_MATCH0, val); + + val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | + (mac_addr[4] << 8) | mac_addr[5]; + + REG_WR(sc, BCE_EMAC_MAC_MATCH1, val); + + DBEXIT(BCE_VERBOSE_RESET); +} + + +/****************************************************************************/ +/* Stop the controller. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_stop(struct bce_softc *sc) +{ + struct ifnet *ifp; + + DBENTER(BCE_VERBOSE_RESET); + + BCE_LOCK_ASSERT(sc); + + ifp = sc->bce_ifp; + + callout_stop(&sc->bce_tick_callout); + + /* Disable the transmit/receive blocks. */ + REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT); + REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); + DELAY(20); + + bce_disable_intr(sc); + + /* Free RX buffers. */ +#ifdef BCE_JUMBO_HDRSPLIT + bce_free_pg_chain(sc); +#endif + bce_free_rx_chain(sc); + + /* Free TX buffers. */ + bce_free_tx_chain(sc); + + sc->watchdog_timer = 0; + + sc->bce_link_up = FALSE; + + ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); + + DBEXIT(BCE_VERBOSE_RESET); +} + + +static int +bce_reset(struct bce_softc *sc, u32 reset_code) +{ + u32 val; + int i, rc = 0; + + DBENTER(BCE_VERBOSE_RESET); + + DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n", + __FUNCTION__, reset_code); + + /* Wait for pending PCI transactions to complete. */ + REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, + BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | + BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | + BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | + BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); + val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); + DELAY(5); + + /* Disable DMA */ + if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || + (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { + val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); + val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; + REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); + } + + /* Assume bootcode is running. */ + sc->bce_fw_timed_out = FALSE; + sc->bce_drv_cardiac_arrest = FALSE; + + /* Give the firmware a chance to prepare for the reset. */ + rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code); + if (rc) + goto bce_reset_exit; + + /* Set a firmware reminder that this is a soft reset. */ + bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE, BCE_DRV_RESET_SIGNATURE_MAGIC); + + /* Dummy read to force the chip to complete all current transactions. */ + val = REG_RD(sc, BCE_MISC_ID); + + /* Chip reset. */ + if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || + (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { + REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET); + REG_RD(sc, BCE_MISC_COMMAND); + DELAY(5); + + val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | + BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; + + pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4); + } else { + val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | + BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | + BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; + REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val); + + /* Allow up to 30us for reset to complete. */ + for (i = 0; i < 10; i++) { + val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG); + if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | + BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { + break; + } + DELAY(10); + } + + /* Check that reset completed successfully. */ + if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | + BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { + BCE_PRINTF("%s(%d): Reset failed!\n", + __FILE__, __LINE__); + rc = EBUSY; + goto bce_reset_exit; + } + } + + /* Make sure byte swapping is properly configured. */ + val = REG_RD(sc, BCE_PCI_SWAP_DIAG0); + if (val != 0x01020304) { + BCE_PRINTF("%s(%d): Byte swap is incorrect!\n", + __FILE__, __LINE__); + rc = ENODEV; + goto bce_reset_exit; + } + + /* Just completed a reset, assume that firmware is running again. */ + sc->bce_fw_timed_out = FALSE; + sc->bce_drv_cardiac_arrest = FALSE; + + /* Wait for the firmware to finish its initialization. */ + rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code); + if (rc) + BCE_PRINTF("%s(%d): Firmware did not complete " + "initialization!\n", __FILE__, __LINE__); + +bce_reset_exit: + DBEXIT(BCE_VERBOSE_RESET); + return (rc); +} + + +static int +bce_chipinit(struct bce_softc *sc) +{ + u32 val; + int rc = 0; + + DBENTER(BCE_VERBOSE_RESET); + + bce_disable_intr(sc); + + /* + * Initialize DMA byte/word swapping, configure the number of DMA + * channels and PCI clock compensation delay. + */ + val = BCE_DMA_CONFIG_DATA_BYTE_SWAP | + BCE_DMA_CONFIG_DATA_WORD_SWAP | +#if BYTE_ORDER == BIG_ENDIAN + BCE_DMA_CONFIG_CNTL_BYTE_SWAP | +#endif + BCE_DMA_CONFIG_CNTL_WORD_SWAP | + DMA_READ_CHANS << 12 | + DMA_WRITE_CHANS << 16; + + val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY; + + if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) + val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP; + + /* + * This setting resolves a problem observed on certain Intel PCI + * chipsets that cannot handle multiple outstanding DMA operations. + * See errata E9_5706A1_65. + */ + if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && + (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) && + !(sc->bce_flags & BCE_PCIX_FLAG)) + val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA; + + REG_WR(sc, BCE_DMA_CONFIG, val); + + /* Enable the RX_V2P and Context state machines before access. */ + REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, + BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | + BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | + BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); + + /* Initialize context mapping and zero out the quick contexts. */ + if ((rc = bce_init_ctx(sc)) != 0) + goto bce_chipinit_exit; + + /* Initialize the on-boards CPUs */ + bce_init_cpus(sc); + + /* Enable management frames (NC-SI) to flow to the MCP. */ + if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { + val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) | BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; + REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); + } + + /* Prepare NVRAM for access. */ + if ((rc = bce_init_nvram(sc)) != 0) + goto bce_chipinit_exit; + + /* Set the kernel bypass block size */ + val = REG_RD(sc, BCE_MQ_CONFIG); + val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE; + val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; + + /* Enable bins used on the 5709. */ + if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || + (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { + val |= BCE_MQ_CONFIG_BIN_MQ_MODE; + if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1) + val |= BCE_MQ_CONFIG_HALT_DIS; + } + + REG_WR(sc, BCE_MQ_CONFIG, val); + + val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); + REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val); + REG_WR(sc, BCE_MQ_KNL_WIND_END, val); + + /* Set the page size and clear the RV2P processor stall bits. */ + val = (BCM_PAGE_BITS - 8) << 24; + REG_WR(sc, BCE_RV2P_CONFIG, val); + + /* Configure page size. */ + val = REG_RD(sc, BCE_TBDR_CONFIG); + val &= ~BCE_TBDR_CONFIG_PAGE_SIZE; + val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; + REG_WR(sc, BCE_TBDR_CONFIG, val); + + /* Set the perfect match control register to default. */ + REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0); + +bce_chipinit_exit: + DBEXIT(BCE_VERBOSE_RESET); + + return(rc); +} + + +/****************************************************************************/ +/* Initialize the controller in preparation to send/receive traffic. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_blockinit(struct bce_softc *sc) +{ + u32 reg, val; + int rc = 0; + + DBENTER(BCE_VERBOSE_RESET); + + /* Load the hardware default MAC address. */ + bce_set_mac_addr(sc); + + /* Set the Ethernet backoff seed value */ + val = sc->eaddr[0] + (sc->eaddr[1] << 8) + + (sc->eaddr[2] << 16) + (sc->eaddr[3] ) + + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); + REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val); + + sc->last_status_idx = 0; + sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE; + + /* Set up link change interrupt generation. */ + REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK); + + /* Program the physical address of the status block. */ + REG_WR(sc, BCE_HC_STATUS_ADDR_L, + BCE_ADDR_LO(sc->status_block_paddr)); + REG_WR(sc, BCE_HC_STATUS_ADDR_H, + BCE_ADDR_HI(sc->status_block_paddr)); + + /* Program the physical address of the statistics block. */ + REG_WR(sc, BCE_HC_STATISTICS_ADDR_L, + BCE_ADDR_LO(sc->stats_block_paddr)); + REG_WR(sc, BCE_HC_STATISTICS_ADDR_H, + BCE_ADDR_HI(sc->stats_block_paddr)); + + /* Program various host coalescing parameters. */ + REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, + (sc->bce_tx_quick_cons_trip_int << 16) | sc->bce_tx_quick_cons_trip); + REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, + (sc->bce_rx_quick_cons_trip_int << 16) | sc->bce_rx_quick_cons_trip); + REG_WR(sc, BCE_HC_COMP_PROD_TRIP, + (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip); + REG_WR(sc, BCE_HC_TX_TICKS, + (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks); + REG_WR(sc, BCE_HC_RX_TICKS, + (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks); + REG_WR(sc, BCE_HC_COM_TICKS, + (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks); + REG_WR(sc, BCE_HC_CMD_TICKS, + (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks); + REG_WR(sc, BCE_HC_STATS_TICKS, + (sc->bce_stats_ticks & 0xffff00)); + REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ + + /* Configure the Host Coalescing block. */ + val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE | + BCE_HC_CONFIG_COLLECT_STATS; + +#if 0 + /* ToDo: Add MSI-X support. */ + if (sc->bce_flags & BCE_USING_MSIX_FLAG) { + u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) + + BCE_HC_SB_CONFIG_1; + + REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL); + + REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE | + BCE_HC_SB_CONFIG_1_ONE_SHOT); + + REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF, + (sc->tx_quick_cons_trip_int << 16) | + sc->tx_quick_cons_trip); + + REG_WR(sc, base + BCE_HC_TX_TICKS_OFF, + (sc->tx_ticks_int << 16) | sc->tx_ticks); + + val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; + } + + /* + * Tell the HC block to automatically set the + * INT_MASK bit after an MSI/MSI-X interrupt + * is generated so the driver doesn't have to. + */ + if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG) + val |= BCE_HC_CONFIG_ONE_SHOT; + + /* Set the MSI-X status blocks to 128 byte boundaries. */ + if (sc->bce_flags & BCE_USING_MSIX_FLAG) + val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; +#endif + + REG_WR(sc, BCE_HC_CONFIG, val); + + /* Clear the internal statistics counters. */ + REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); + + /* Verify that bootcode is running. */ + reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE); + + DBRUNIF(DB_RANDOMTRUE(bootcode_running_failure_sim_control), + BCE_PRINTF("%s(%d): Simulating bootcode failure.\n", + __FILE__, __LINE__); + reg = 0); + + if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) != + BCE_DEV_INFO_SIGNATURE_MAGIC) { + BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, " + "Expected: 08%08X\n", __FILE__, __LINE__, + (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK), + BCE_DEV_INFO_SIGNATURE_MAGIC); + rc = ENODEV; + goto bce_blockinit_exit; + } + + /* Enable DMA */ + if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || + (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { + val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); + val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; + REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); + } + + /* Allow bootcode to apply additional fixes before enabling MAC. */ + rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | + BCE_DRV_MSG_CODE_RESET); + + /* Enable link state change interrupt generation. */ + REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); + + /* Enable the RXP. */ + bce_start_rxp_cpu(sc); + + /* Disable management frames (NC-SI) from flowing to the MCP. */ + if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { + val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) & + ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; + REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); + } + + /* Enable all remaining blocks in the MAC. */ + if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || + (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) + REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, + BCE_MISC_ENABLE_DEFAULT_XI); + else + REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, + BCE_MISC_ENABLE_DEFAULT); + + REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); + DELAY(20); + + /* Save the current host coalescing block settings. */ + sc->hc_command = REG_RD(sc, BCE_HC_COMMAND); + +bce_blockinit_exit: + DBEXIT(BCE_VERBOSE_RESET); + + return (rc); +} + + +/****************************************************************************/ +/* Encapsulate an mbuf into the rx_bd chain. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_get_rx_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod, + u16 *chain_prod, u32 *prod_bseq) +{ + bus_dmamap_t map; + bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; + struct mbuf *m_new = NULL; + struct rx_bd *rxbd; + int nsegs, error, rc = 0; +#ifdef BCE_DEBUG + u16 debug_chain_prod = *chain_prod; +#endif + + DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); + + /* Make sure the inputs are valid. */ + DBRUNIF((*chain_prod > MAX_RX_BD), + BCE_PRINTF("%s(%d): RX producer out of range: " + "0x%04X > 0x%04X\n", __FILE__, __LINE__, + *chain_prod, (u16) MAX_RX_BD)); + + DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " + "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, + *prod, *chain_prod, *prod_bseq); + + /* Update some debug statistic counters */ + DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), + sc->rx_low_watermark = sc->free_rx_bd); + DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), + sc->rx_empty_count++); + + /* Check whether this is a new mbuf allocation. */ + if (m == NULL) { + + /* Simulate an mbuf allocation failure. */ + DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), + sc->mbuf_alloc_failed_count++; + sc->mbuf_alloc_failed_sim_count++; + rc = ENOBUFS; + goto bce_get_rx_buf_exit); + + /* This is a new mbuf allocation. */ +#ifdef BCE_JUMBO_HDRSPLIT + MGETHDR(m_new, M_DONTWAIT, MT_DATA); +#else + if (sc->rx_bd_mbuf_alloc_size <= MCLBYTES) + m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + else + m_new = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, + sc->rx_bd_mbuf_alloc_size); +#endif + + if (m_new == NULL) { + sc->mbuf_alloc_failed_count++; + rc = ENOBUFS; + goto bce_get_rx_buf_exit; + } + + DBRUN(sc->debug_rx_mbuf_alloc++); + } else { + /* Reuse an existing mbuf. */ + m_new = m; + } + + /* Make sure we have a valid packet header. */ + M_ASSERTPKTHDR(m_new); + + /* Initialize the mbuf size and pad if necessary for alignment. */ + m_new->m_pkthdr.len = m_new->m_len = sc->rx_bd_mbuf_alloc_size; + m_adj(m_new, sc->rx_bd_mbuf_align_pad); + + /* ToDo: Consider calling m_fragment() to test error handling. */ + + /* Map the mbuf cluster into device memory. */ + map = sc->rx_mbuf_map[*chain_prod]; + error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag, map, m_new, + segs, &nsegs, BUS_DMA_NOWAIT); + + /* Handle any mapping errors. */ + if (error) { + BCE_PRINTF("%s(%d): Error mapping mbuf into RX " + "chain (%d)!\n", __FILE__, __LINE__, error); + + sc->dma_map_addr_rx_failed_count++; + m_freem(m_new); + + DBRUN(sc->debug_rx_mbuf_alloc--); + + rc = ENOBUFS; + goto bce_get_rx_buf_exit; + } + + /* All mbufs must map to a single segment. */ + KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!", + __FUNCTION__, nsegs)); + + /* Setup the rx_bd for the segment. */ + rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; + + rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); + rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); + rxbd->rx_bd_len = htole32(segs[0].ds_len); + rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); + *prod_bseq += segs[0].ds_len; + + /* Save the mbuf and update our counter. */ + sc->rx_mbuf_ptr[*chain_prod] = m_new; + sc->free_rx_bd -= nsegs; + + DBRUNMSG(BCE_INSANE_RECV, + bce_dump_rx_mbuf_chain(sc, debug_chain_prod, nsegs)); + + DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " + "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", + __FUNCTION__, *prod, *chain_prod, *prod_bseq); + +bce_get_rx_buf_exit: + DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); + + return(rc); +} + + +#ifdef BCE_JUMBO_HDRSPLIT +/****************************************************************************/ +/* Encapsulate an mbuf cluster into the page chain. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_get_pg_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod, + u16 *prod_idx) +{ + bus_dmamap_t map; + bus_addr_t busaddr; + struct mbuf *m_new = NULL; + struct rx_bd *pgbd; + int error, rc = 0; +#ifdef BCE_DEBUG + u16 debug_prod_idx = *prod_idx; +#endif + + DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); + + /* Make sure the inputs are valid. */ + DBRUNIF((*prod_idx > MAX_PG_BD), + BCE_PRINTF("%s(%d): page producer out of range: " + "0x%04X > 0x%04X\n", __FILE__, __LINE__, + *prod_idx, (u16) MAX_PG_BD)); + + DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " + "chain_prod = 0x%04X\n", __FUNCTION__, *prod, *prod_idx); + + /* Update counters if we've hit a new low or run out of pages. */ + DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark), + sc->pg_low_watermark = sc->free_pg_bd); + DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++); + + /* Check whether this is a new mbuf allocation. */ + if (m == NULL) { + + /* Simulate an mbuf allocation failure. */ + DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), + sc->mbuf_alloc_failed_count++; + sc->mbuf_alloc_failed_sim_count++; + rc = ENOBUFS; + goto bce_get_pg_buf_exit); + + /* This is a new mbuf allocation. */ + m_new = m_getcl(M_DONTWAIT, MT_DATA, 0); + if (m_new == NULL) { + sc->mbuf_alloc_failed_count++; + rc = ENOBUFS; + goto bce_get_pg_buf_exit; + } + + DBRUN(sc->debug_pg_mbuf_alloc++); + } else { + /* Reuse an existing mbuf. */ + m_new = m; + m_new->m_data = m_new->m_ext.ext_buf; + } + + m_new->m_len = sc->pg_bd_mbuf_alloc_size; + + /* ToDo: Consider calling m_fragment() to test error handling. */ + + /* Map the mbuf cluster into device memory. */ + map = sc->pg_mbuf_map[*prod_idx]; + error = bus_dmamap_load(sc->pg_mbuf_tag, map, mtod(m_new, void *), + sc->pg_bd_mbuf_alloc_size, bce_dma_map_addr, + &busaddr, BUS_DMA_NOWAIT); + + /* Handle any mapping errors. */ + if (error) { + BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n", + __FILE__, __LINE__); + + m_freem(m_new); + DBRUN(sc->debug_pg_mbuf_alloc--); + + rc = ENOBUFS; + goto bce_get_pg_buf_exit; + } + + /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREREAD) here? */ + + /* + * The page chain uses the same rx_bd data structure + * as the receive chain but doesn't require a byte sequence (bseq). + */ + pgbd = &sc->pg_bd_chain[PG_PAGE(*prod_idx)][PG_IDX(*prod_idx)]; + + pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(busaddr)); + pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(busaddr)); + pgbd->rx_bd_len = htole32(sc->pg_bd_mbuf_alloc_size); + pgbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); + + /* Save the mbuf and update our counter. */ + sc->pg_mbuf_ptr[*prod_idx] = m_new; + sc->free_pg_bd--; + + DBRUNMSG(BCE_INSANE_RECV, + bce_dump_pg_mbuf_chain(sc, debug_prod_idx, 1)); + + DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " + "prod_idx = 0x%04X\n", __FUNCTION__, *prod, *prod_idx); + +bce_get_pg_buf_exit: + DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); + + return(rc); +} +#endif /* BCE_JUMBO_HDRSPLIT */ + + +/****************************************************************************/ +/* Initialize the TX context memory. */ +/* */ +/* Returns: */ +/* Nothing */ +/****************************************************************************/ +static void +bce_init_tx_context(struct bce_softc *sc) +{ + u32 val; + + DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); + + /* Initialize the context ID for an L2 TX chain. */ + if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || + (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { + /* Set the CID type to support an L2 connection. */ + val = BCE_L2CTX_TX_TYPE_TYPE_L2_XI | + BCE_L2CTX_TX_TYPE_SIZE_L2_XI; + CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val); + val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI | (8 << 16); + CTX_WR(sc, GET_CID_ADDR(TX_CID), + BCE_L2CTX_TX_CMD_TYPE_XI, val); + + /* Point the hardware to the first page in the chain. */ + val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); + CTX_WR(sc, GET_CID_ADDR(TX_CID), + BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val); + val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); + CTX_WR(sc, GET_CID_ADDR(TX_CID), + BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val); + } else { + /* Set the CID type to support an L2 connection. */ + val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2; + CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val); + val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16); + CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val); + + /* Point the hardware to the first page in the chain. */ + val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); + CTX_WR(sc, GET_CID_ADDR(TX_CID), + BCE_L2CTX_TX_TBDR_BHADDR_HI, val); + val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); + CTX_WR(sc, GET_CID_ADDR(TX_CID), + BCE_L2CTX_TX_TBDR_BHADDR_LO, val); + } + + DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); +} + + +/****************************************************************************/ +/* Allocate memory and initialize the TX data structures. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_init_tx_chain(struct bce_softc *sc) +{ + struct tx_bd *txbd; + int i, rc = 0; + + DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); + + /* Set the initial TX producer/consumer indices. */ + sc->tx_prod = 0; + sc->tx_cons = 0; + sc->tx_prod_bseq = 0; + sc->used_tx_bd = 0; + sc->max_tx_bd = USABLE_TX_BD; + DBRUN(sc->tx_hi_watermark = 0); + DBRUN(sc->tx_full_count = 0); + + /* + * The NetXtreme II supports a linked-list structre called + * a Buffer Descriptor Chain (or BD chain). A BD chain + * consists of a series of 1 or more chain pages, each of which + * consists of a fixed number of BD entries. + * The last BD entry on each page is a pointer to the next page + * in the chain, and the last pointer in the BD chain + * points back to the beginning of the chain. + */ + + /* Set the TX next pointer chain entries. */ + for (i = 0; i < TX_PAGES; i++) { + int j; + + txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; + + /* Check if we've reached the last page. */ + if (i == (TX_PAGES - 1)) + j = 0; + else + j = i + 1; + + txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j])); + txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j])); + } + + bce_init_tx_context(sc); + + DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD)); + DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); + + return(rc); +} + + +/****************************************************************************/ +/* Free memory and clear the TX data structures. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_free_tx_chain(struct bce_softc *sc) +{ + int i; + + DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); + + /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ + for (i = 0; i < TOTAL_TX_BD; i++) { + if (sc->tx_mbuf_ptr[i] != NULL) { + if (sc->tx_mbuf_map[i] != NULL) + bus_dmamap_sync(sc->tx_mbuf_tag, + sc->tx_mbuf_map[i], + BUS_DMASYNC_POSTWRITE); + m_freem(sc->tx_mbuf_ptr[i]); + sc->tx_mbuf_ptr[i] = NULL; + DBRUN(sc->debug_tx_mbuf_alloc--); + } + } + + /* Clear each TX chain page. */ + for (i = 0; i < TX_PAGES; i++) + bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ); + + sc->used_tx_bd = 0; + + /* Check if we lost any mbufs in the process. */ + DBRUNIF((sc->debug_tx_mbuf_alloc), + BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs " + "from tx chain!\n", __FILE__, __LINE__, + sc->debug_tx_mbuf_alloc)); + + DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); +} + + +/****************************************************************************/ +/* Initialize the RX context memory. */ +/* */ +/* Returns: */ +/* Nothing */ +/****************************************************************************/ +static void +bce_init_rx_context(struct bce_softc *sc) +{ + u32 val; + + DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); + + /* Init the type, size, and BD cache levels for the RX context. */ + val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | + BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | + (0x02 << BCE_L2CTX_RX_BD_PRE_READ_SHIFT); + + /* + * Set the level for generating pause frames + * when the number of available rx_bd's gets + * too low (the low watermark) and the level + * when pause frames can be stopped (the high + * watermark). + */ + if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || + (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { + u32 lo_water, hi_water; + + if (sc->bce_flags && BCE_USING_TX_FLOW_CONTROL) { + lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT; + } else { + lo_water = 0; + } + + if (lo_water >= USABLE_RX_BD) { + lo_water = 0; + } + + hi_water = USABLE_RX_BD / 4; + + if (hi_water <= lo_water) { + lo_water = 0; + } + + lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE; + hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE; + + if (hi_water > 0xf) + hi_water = 0xf; + else if (hi_water == 0) + lo_water = 0; + + val |= (lo_water << BCE_L2CTX_RX_LO_WATER_MARK_SHIFT) | + (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT); + } + + CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val); + + /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ + if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || + (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { + val = REG_RD(sc, BCE_MQ_MAP_L2_5); + REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM); + } + + /* Point the hardware to the first page in the chain. */ + val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]); + CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val); + val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]); + CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val); + + DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); +} + + +/****************************************************************************/ +/* Allocate memory and initialize the RX data structures. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_init_rx_chain(struct bce_softc *sc) +{ + struct rx_bd *rxbd; + int i, rc = 0; + + DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | + BCE_VERBOSE_CTX); + + /* Initialize the RX producer and consumer indices. */ + sc->rx_prod = 0; + sc->rx_cons = 0; + sc->rx_prod_bseq = 0; + sc->free_rx_bd = USABLE_RX_BD; + sc->max_rx_bd = USABLE_RX_BD; + + /* Initialize the RX next pointer chain entries. */ + for (i = 0; i < RX_PAGES; i++) { + int j; + + rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; + + /* Check if we've reached the last page. */ + if (i == (RX_PAGES - 1)) + j = 0; + else + j = i + 1; + + /* Setup the chain page pointers. */ + rxbd->rx_bd_haddr_hi = + htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j])); + rxbd->rx_bd_haddr_lo = + htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j])); + } + + /* Fill up the RX chain. */ + bce_fill_rx_chain(sc); + + DBRUN(sc->rx_low_watermark = USABLE_RX_BD); + DBRUN(sc->rx_empty_count = 0); + for (i = 0; i < RX_PAGES; i++) { + bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i], + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + } + + bce_init_rx_context(sc); + + DBRUNMSG(BCE_EXTREME_RECV, bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD)); + DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | + BCE_VERBOSE_CTX); + + /* ToDo: Are there possible failure modes here? */ + + return(rc); +} + + +/****************************************************************************/ +/* Add mbufs to the RX chain until its full or an mbuf allocation error */ +/* occurs. */ +/* */ +/* Returns: */ +/* Nothing */ +/****************************************************************************/ +static void +bce_fill_rx_chain(struct bce_softc *sc) +{ + u16 prod, prod_idx; + u32 prod_bseq; + + DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | + BCE_VERBOSE_CTX); + + /* Get the RX chain producer indices. */ + prod = sc->rx_prod; + prod_bseq = sc->rx_prod_bseq; + + /* Keep filling the RX chain until it's full. */ + while (sc->free_rx_bd > 0) { + prod_idx = RX_CHAIN_IDX(prod); + if (bce_get_rx_buf(sc, NULL, &prod, &prod_idx, &prod_bseq)) { + /* Bail out if we can't add an mbuf to the chain. */ + break; + } + prod = NEXT_RX_BD(prod); + } + + /* Save the RX chain producer indices. */ + sc->rx_prod = prod; + sc->rx_prod_bseq = prod_bseq; + + /* We should never end up pointing to a next page pointer. */ + DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), + BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n", + __FUNCTION__, sc->rx_prod)); + + /* Write the mailbox and tell the chip about the waiting rx_bd's. */ + REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + + BCE_L2MQ_RX_HOST_BDIDX, sc->rx_prod); + REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + + BCE_L2MQ_RX_HOST_BSEQ, sc->rx_prod_bseq); + + DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | + BCE_VERBOSE_CTX); +} + + +/****************************************************************************/ +/* Free memory and clear the RX data structures. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_free_rx_chain(struct bce_softc *sc) +{ + int i; + + DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); + + /* Free any mbufs still in the RX mbuf chain. */ + for (i = 0; i < TOTAL_RX_BD; i++) { + if (sc->rx_mbuf_ptr[i] != NULL) { + if (sc->rx_mbuf_map[i] != NULL) + bus_dmamap_sync(sc->rx_mbuf_tag, + sc->rx_mbuf_map[i], + BUS_DMASYNC_POSTREAD); + m_freem(sc->rx_mbuf_ptr[i]); + sc->rx_mbuf_ptr[i] = NULL; + DBRUN(sc->debug_rx_mbuf_alloc--); + } + } + + /* Clear each RX chain page. */ + for (i = 0; i < RX_PAGES; i++) + if (sc->rx_bd_chain[i] != NULL) { + bzero((char *)sc->rx_bd_chain[i], + BCE_RX_CHAIN_PAGE_SZ); + } + + sc->free_rx_bd = sc->max_rx_bd; + + /* Check if we lost any mbufs in the process. */ + DBRUNIF((sc->debug_rx_mbuf_alloc), + BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n", + __FUNCTION__, sc->debug_rx_mbuf_alloc)); + + DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); +} + + +#ifdef BCE_JUMBO_HDRSPLIT +/****************************************************************************/ +/* Allocate memory and initialize the page data structures. */ +/* Assumes that bce_init_rx_chain() has not already been called. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_init_pg_chain(struct bce_softc *sc) +{ + struct rx_bd *pgbd; + int i, rc = 0; + u32 val; + + DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | + BCE_VERBOSE_CTX); + + /* Initialize the page producer and consumer indices. */ + sc->pg_prod = 0; + sc->pg_cons = 0; + sc->free_pg_bd = USABLE_PG_BD; + sc->max_pg_bd = USABLE_PG_BD; + DBRUN(sc->pg_low_watermark = sc->max_pg_bd); + DBRUN(sc->pg_empty_count = 0); + + /* Initialize the page next pointer chain entries. */ + for (i = 0; i < PG_PAGES; i++) { + int j; + + pgbd = &sc->pg_bd_chain[i][USABLE_PG_BD_PER_PAGE]; + + /* Check if we've reached the last page. */ + if (i == (PG_PAGES - 1)) + j = 0; + else + j = i + 1; + + /* Setup the chain page pointers. */ + pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j])); + pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j])); + } + + /* Setup the MQ BIN mapping for host_pg_bidx. */ + if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || + (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) + REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT); + + CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0); + + /* Configure the rx_bd and page chain mbuf cluster size. */ + val = (sc->rx_bd_mbuf_data_len << 16) | sc->pg_bd_mbuf_alloc_size; + CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val); + + /* Configure the context reserved for jumbo support. */ + CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_RBDC_KEY, + BCE_L2CTX_RX_RBDC_JUMBO_KEY); + + /* Point the hardware to the first page in the page chain. */ + val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]); + CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_HI, val); + val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]); + CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_LO, val); + + /* Fill up the page chain. */ + bce_fill_pg_chain(sc); + + for (i = 0; i < PG_PAGES; i++) { + bus_dmamap_sync(sc->pg_bd_chain_tag, sc->pg_bd_chain_map[i], + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + } + + DBRUNMSG(BCE_EXTREME_RECV, bce_dump_pg_chain(sc, 0, TOTAL_PG_BD)); + DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | + BCE_VERBOSE_CTX); + return(rc); +} + + +/****************************************************************************/ +/* Add mbufs to the page chain until its full or an mbuf allocation error */ +/* occurs. */ +/* */ +/* Returns: */ +/* Nothing */ +/****************************************************************************/ +static void +bce_fill_pg_chain(struct bce_softc *sc) +{ + u16 prod, prod_idx; + + DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | + BCE_VERBOSE_CTX); + + /* Get the page chain prodcuer index. */ + prod = sc->pg_prod; + + /* Keep filling the page chain until it's full. */ + while (sc->free_pg_bd > 0) { + prod_idx = PG_CHAIN_IDX(prod); + if (bce_get_pg_buf(sc, NULL, &prod, &prod_idx)) { + /* Bail out if we can't add an mbuf to the chain. */ + break; + } + prod = NEXT_PG_BD(prod); + } + + /* Save the page chain producer index. */ + sc->pg_prod = prod; + + DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), + BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n", + __FUNCTION__, sc->pg_prod)); + + /* + * Write the mailbox and tell the chip about + * the new rx_bd's in the page chain. + */ + REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + + BCE_L2MQ_RX_HOST_PG_BDIDX, sc->pg_prod); + + DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | + BCE_VERBOSE_CTX); +} + + +/****************************************************************************/ +/* Free memory and clear the RX data structures. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_free_pg_chain(struct bce_softc *sc) +{ + int i; + + DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); + + /* Free any mbufs still in the mbuf page chain. */ + for (i = 0; i < TOTAL_PG_BD; i++) { + if (sc->pg_mbuf_ptr[i] != NULL) { + if (sc->pg_mbuf_map[i] != NULL) + bus_dmamap_sync(sc->pg_mbuf_tag, + sc->pg_mbuf_map[i], + BUS_DMASYNC_POSTREAD); + m_freem(sc->pg_mbuf_ptr[i]); + sc->pg_mbuf_ptr[i] = NULL; + DBRUN(sc->debug_pg_mbuf_alloc--); + } + } + + /* Clear each page chain pages. */ + for (i = 0; i < PG_PAGES; i++) + bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ); + + sc->free_pg_bd = sc->max_pg_bd; + + /* Check if we lost any mbufs in the process. */ + DBRUNIF((sc->debug_pg_mbuf_alloc), + BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n", + __FUNCTION__, sc->debug_pg_mbuf_alloc)); + + DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); +} +#endif /* BCE_JUMBO_HDRSPLIT */ + + +/****************************************************************************/ +/* Set media options. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_ifmedia_upd(struct ifnet *ifp) +{ + struct bce_softc *sc = ifp->if_softc; + int error; + + DBENTER(BCE_VERBOSE); + + BCE_LOCK(sc); + error = bce_ifmedia_upd_locked(ifp); + BCE_UNLOCK(sc); + + DBEXIT(BCE_VERBOSE); + return (error); +} + + +/****************************************************************************/ +/* Set media options. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static int +bce_ifmedia_upd_locked(struct ifnet *ifp) +{ + struct bce_softc *sc = ifp->if_softc; + struct mii_data *mii; + int error; + + DBENTER(BCE_VERBOSE_PHY); + + error = 0; + BCE_LOCK_ASSERT(sc); + + mii = device_get_softc(sc->bce_miibus); + + /* Make sure the MII bus has been enumerated. */ + if (mii) { + sc->bce_link_up = FALSE; + if (mii->mii_instance) { + struct mii_softc *miisc; + + LIST_FOREACH(miisc, &mii->mii_phys, mii_list) + mii_phy_reset(miisc); + } + error = mii_mediachg(mii); + } + + DBEXIT(BCE_VERBOSE_PHY); + return (error); +} + + +/****************************************************************************/ +/* Reports current media status. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) +{ + struct bce_softc *sc = ifp->if_softc; + struct mii_data *mii; + + DBENTER(BCE_VERBOSE_PHY); + + BCE_LOCK(sc); + + if ((ifp->if_flags & IFF_UP) == 0) { + BCE_UNLOCK(sc); + return; + } + mii = device_get_softc(sc->bce_miibus); + + mii_pollstat(mii); + ifmr->ifm_active = mii->mii_media_active; + ifmr->ifm_status = mii->mii_media_status; + + BCE_UNLOCK(sc); + + DBEXIT(BCE_VERBOSE_PHY); +} + + +/****************************************************************************/ +/* Handles PHY generated interrupt events. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_phy_intr(struct bce_softc *sc) +{ + u32 new_link_state, old_link_state; + + DBENTER(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); + + DBRUN(sc->phy_interrupts++); + + new_link_state = sc->status_block->status_attn_bits & + STATUS_ATTN_BITS_LINK_STATE; + old_link_state = sc->status_block->status_attn_bits_ack & + STATUS_ATTN_BITS_LINK_STATE; + + /* Handle any changes if the link state has changed. */ + if (new_link_state != old_link_state) { + + /* Update the status_attn_bits_ack field. */ + if (new_link_state) { + REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD, + STATUS_ATTN_BITS_LINK_STATE); + DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now UP.\n", + __FUNCTION__); + } + else { + REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD, + STATUS_ATTN_BITS_LINK_STATE); + DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n", + __FUNCTION__); + } + + /* + * Assume link is down and allow + * tick routine to update the state + * based on the actual media state. + */ + sc->bce_link_up = FALSE; + callout_stop(&sc->bce_tick_callout); + bce_tick(sc); + } + + /* Acknowledge the link change interrupt. */ + REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE); + + DBEXIT(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); +} + + +/****************************************************************************/ +/* Reads the receive consumer value from the status block (skipping over */ +/* chain page pointer if necessary). */ +/* */ +/* Returns: */ +/* hw_cons */ +/****************************************************************************/ +static inline u16 +bce_get_hw_rx_cons(struct bce_softc *sc) +{ + u16 hw_cons; + + rmb(); + hw_cons = sc->status_block->status_rx_quick_consumer_index0; + if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) + hw_cons++; + + return hw_cons; +} + +/****************************************************************************/ +/* Handles received frame interrupt events. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_rx_intr(struct bce_softc *sc) +{ + struct ifnet *ifp = sc->bce_ifp; + struct l2_fhdr *l2fhdr; + struct ether_vlan_header *vh; + unsigned int pkt_len; + u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons; + u32 status; +#ifdef BCE_JUMBO_HDRSPLIT + unsigned int rem_len; + u16 sw_pg_cons, sw_pg_cons_idx; +#endif + + DBENTER(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); + DBRUN(sc->interrupts_rx++); + DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, " + "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", + __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); + + /* Prepare the RX chain pages to be accessed by the host CPU. */ + for (int i = 0; i < RX_PAGES; i++) + bus_dmamap_sync(sc->rx_bd_chain_tag, + sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD); + +#ifdef BCE_JUMBO_HDRSPLIT + /* Prepare the page chain pages to be accessed by the host CPU. */ + for (int i = 0; i < PG_PAGES; i++) + bus_dmamap_sync(sc->pg_bd_chain_tag, + sc->pg_bd_chain_map[i], BUS_DMASYNC_POSTREAD); +#endif + + /* Get the hardware's view of the RX consumer index. */ + hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); + + /* Get working copies of the driver's view of the consumer indices. */ + sw_rx_cons = sc->rx_cons; + +#ifdef BCE_JUMBO_HDRSPLIT + sw_pg_cons = sc->pg_cons; +#endif + + /* Update some debug statistics counters */ + DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), + sc->rx_low_watermark = sc->free_rx_bd); + DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), + sc->rx_empty_count++); + + /* Scan through the receive chain as long as there is work to do */ + /* ToDo: Consider setting a limit on the number of packets processed. */ + rmb(); + while (sw_rx_cons != hw_rx_cons) { + struct mbuf *m0; + + /* Convert the producer/consumer indices to an actual rx_bd index. */ + sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons); + + /* Unmap the mbuf from DMA space. */ + bus_dmamap_sync(sc->rx_mbuf_tag, + sc->rx_mbuf_map[sw_rx_cons_idx], + BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(sc->rx_mbuf_tag, + sc->rx_mbuf_map[sw_rx_cons_idx]); + + /* Remove the mbuf from the RX chain. */ + m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx]; + sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL; + DBRUN(sc->debug_rx_mbuf_alloc--); + sc->free_rx_bd++; + + if(m0 == NULL) { + DBPRINT(sc, BCE_EXTREME_RECV, + "%s(): Oops! Empty mbuf pointer " + "found in sc->rx_mbuf_ptr[0x%04X]!\n", + __FUNCTION__, sw_rx_cons_idx); + goto bce_rx_int_next_rx; + } + + /* + * Frames received on the NetXteme II are prepended + * with an l2_fhdr structure which provides status + * information about the received frame (including + * VLAN tags and checksum info). The frames are + * also automatically adjusted to align the IP + * header (i.e. two null bytes are inserted before + * the Ethernet header). As a result the data + * DMA'd by the controller into the mbuf looks + * like this: + * + * +---------+-----+---------------------+-----+ + * | l2_fhdr | pad | packet data | FCS | + * +---------+-----+---------------------+-----+ + * + * The l2_fhdr needs to be checked and skipped and + * the FCS needs to be stripped before sending the + * packet up the stack. + */ + l2fhdr = mtod(m0, struct l2_fhdr *); + + /* Get the packet data + FCS length and the status. */ + pkt_len = l2fhdr->l2_fhdr_pkt_len; + status = l2fhdr->l2_fhdr_status; + + /* + * Skip over the l2_fhdr and pad, resulting in the + * following data in the mbuf: + * +---------------------+-----+ + * | packet data | FCS | + * +---------------------+-----+ + */ + m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN); + +#ifdef BCE_JUMBO_HDRSPLIT + /* + * Check whether the received frame fits in a single + * mbuf or not (i.e. packet data + FCS <= + * sc->rx_bd_mbuf_data_len bytes). + */ + if (pkt_len > m0->m_len) { + /* + * The received frame is larger than a single mbuf. + * If the frame was a TCP frame then only the TCP + * header is placed in the mbuf, the remaining + * payload (including FCS) is placed in the page + * chain, the SPLIT flag is set, and the header + * length is placed in the IP checksum field. + * If the frame is not a TCP frame then the mbuf + * is filled and the remaining bytes are placed + * in the page chain. + */ + + DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large " + "packet.\n", __FUNCTION__); + + /* + * When the page chain is enabled and the TCP + * header has been split from the TCP payload, + * the ip_xsum structure will reflect the length + * of the TCP header, not the IP checksum. Set + * the packet length of the mbuf accordingly. + */ + if (status & L2_FHDR_STATUS_SPLIT) + m0->m_len = l2fhdr->l2_fhdr_ip_xsum; + + rem_len = pkt_len - m0->m_len; + + /* Pull mbufs off the page chain for the remaining data. */ + while (rem_len > 0) { + struct mbuf *m_pg; + + sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons); + + /* Remove the mbuf from the page chain. */ + m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx]; + sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL; + DBRUN(sc->debug_pg_mbuf_alloc--); + sc->free_pg_bd++; + + /* Unmap the page chain mbuf from DMA space. */ + bus_dmamap_sync(sc->pg_mbuf_tag, + sc->pg_mbuf_map[sw_pg_cons_idx], + BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(sc->pg_mbuf_tag, + sc->pg_mbuf_map[sw_pg_cons_idx]); + + /* Adjust the mbuf length. */ + if (rem_len < m_pg->m_len) { + /* The mbuf chain is complete. */ + m_pg->m_len = rem_len; + rem_len = 0; + } else { + /* More packet data is waiting. */ + rem_len -= m_pg->m_len; + } + + /* Concatenate the mbuf cluster to the mbuf. */ + m_cat(m0, m_pg); + + sw_pg_cons = NEXT_PG_BD(sw_pg_cons); + } + + /* Set the total packet length. */ + m0->m_pkthdr.len = pkt_len; + + } else { + /* + * The received packet is small and fits in a + * single mbuf (i.e. the l2_fhdr + pad + packet + + * FCS <= MHLEN). In other words, the packet is + * 154 bytes or less in size. + */ + + DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a small " + "packet.\n", __FUNCTION__); + + /* Set the total packet length. */ + m0->m_pkthdr.len = m0->m_len = pkt_len; + } +#else + /* Set the total packet length. */ + m0->m_pkthdr.len = m0->m_len = pkt_len; +#endif + + /* Remove the trailing Ethernet FCS. */ + m_adj(m0, -ETHER_CRC_LEN); + + /* Check that the resulting mbuf chain is valid. */ + DBRUN(m_sanity(m0, FALSE)); + DBRUNIF(((m0->m_len < ETHER_HDR_LEN) | + (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)), + BCE_PRINTF("Invalid Ethernet frame size!\n"); + m_print(m0, 128)); + + DBRUNIF(DB_RANDOMTRUE(l2fhdr_error_sim_control), + sc->l2fhdr_error_sim_count++; + status = status | L2_FHDR_ERRORS_PHY_DECODE); + + /* Check the received frame for errors. */ + if (status & (L2_FHDR_ERRORS_BAD_CRC | + L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT | + L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) { + + /* Log the error and release the mbuf. */ + ifp->if_ierrors++; + sc->l2fhdr_error_count++; + + m_freem(m0); + m0 = NULL; + goto bce_rx_int_next_rx; + } + + /* Send the packet to the appropriate interface. */ + m0->m_pkthdr.rcvif = ifp; + + /* Assume no hardware checksum. */ + m0->m_pkthdr.csum_flags = 0; + + /* Validate the checksum if offload enabled. */ + if (ifp->if_capenable & IFCAP_RXCSUM) { + + /* Check for an IP datagram. */ + if (!(status & L2_FHDR_STATUS_SPLIT) && + (status & L2_FHDR_STATUS_IP_DATAGRAM)) { + m0->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; + DBRUN(sc->csum_offload_ip++); + /* Check if the IP checksum is valid. */ + if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) + m0->m_pkthdr.csum_flags |= + CSUM_IP_VALID; + } + + /* Check for a valid TCP/UDP frame. */ + if (status & (L2_FHDR_STATUS_TCP_SEGMENT | + L2_FHDR_STATUS_UDP_DATAGRAM)) { + + /* Check for a good TCP/UDP checksum. */ + if ((status & (L2_FHDR_ERRORS_TCP_XSUM | + L2_FHDR_ERRORS_UDP_XSUM)) == 0) { + DBRUN(sc->csum_offload_tcp_udp++); + m0->m_pkthdr.csum_data = + l2fhdr->l2_fhdr_tcp_udp_xsum; + m0->m_pkthdr.csum_flags |= + (CSUM_DATA_VALID + | CSUM_PSEUDO_HDR); + } + } + } + + /* Attach the VLAN tag. */ + if (status & L2_FHDR_STATUS_L2_VLAN_TAG) { + if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { +#if __FreeBSD_version < 700000 + VLAN_INPUT_TAG(ifp, m0, + l2fhdr->l2_fhdr_vlan_tag, continue); +#else + m0->m_pkthdr.ether_vtag = + l2fhdr->l2_fhdr_vlan_tag; + m0->m_flags |= M_VLANTAG; +#endif + } else { + /* + * bce(4) controllers can't disable VLAN + * tag stripping if management firmware + * (ASF/IPMI/UMP) is running. So we always + * strip VLAN tag and manually reconstruct + * the VLAN frame by appending stripped + * VLAN tag in driver if VLAN tag stripping + * was disabled. + * + * TODO: LLC SNAP handling. + */ + bcopy(mtod(m0, uint8_t *), + mtod(m0, uint8_t *) - ETHER_VLAN_ENCAP_LEN, + ETHER_ADDR_LEN * 2); + m0->m_data -= ETHER_VLAN_ENCAP_LEN; + vh = mtod(m0, struct ether_vlan_header *); + vh->evl_encap_proto = htons(ETHERTYPE_VLAN); + vh->evl_tag = htons(l2fhdr->l2_fhdr_vlan_tag); + m0->m_pkthdr.len += ETHER_VLAN_ENCAP_LEN; + m0->m_len += ETHER_VLAN_ENCAP_LEN; + } + } + + /* Increment received packet statistics. */ + ifp->if_ipackets++; + +bce_rx_int_next_rx: + sw_rx_cons = NEXT_RX_BD(sw_rx_cons); + + /* If we have a packet, pass it up the stack */ + if (m0) { + /* Make sure we don't lose our place when we release the lock. */ + sc->rx_cons = sw_rx_cons; +#ifdef BCE_JUMBO_HDRSPLIT + sc->pg_cons = sw_pg_cons; +#endif + + BCE_UNLOCK(sc); + (*ifp->if_input)(ifp, m0); + BCE_LOCK(sc); + + /* Recover our place. */ + sw_rx_cons = sc->rx_cons; +#ifdef BCE_JUMBO_HDRSPLIT + sw_pg_cons = sc->pg_cons; +#endif + } + + /* Refresh hw_cons to see if there's new work */ + if (sw_rx_cons == hw_rx_cons) + hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); + } + +#ifdef BCE_JUMBO_HDRSPLIT + /* No new packets. Refill the page chain. */ + sc->pg_cons = sw_pg_cons; + bce_fill_pg_chain(sc); +#endif + + /* No new packets. Refill the RX chain. */ + sc->rx_cons = sw_rx_cons; + bce_fill_rx_chain(sc); + + /* Prepare the page chain pages to be accessed by the NIC. */ + for (int i = 0; i < RX_PAGES; i++) + bus_dmamap_sync(sc->rx_bd_chain_tag, + sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE); + +#ifdef BCE_JUMBO_HDRSPLIT + for (int i = 0; i < PG_PAGES; i++) + bus_dmamap_sync(sc->pg_bd_chain_tag, + sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE); +#endif + + DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, " + "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", + __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); + DBEXIT(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); +} + + +/****************************************************************************/ +/* Reads the transmit consumer value from the status block (skipping over */ +/* chain page pointer if necessary). */ +/* */ +/* Returns: */ +/* hw_cons */ +/****************************************************************************/ +static inline u16 +bce_get_hw_tx_cons(struct bce_softc *sc) +{ + u16 hw_cons; + + mb(); + hw_cons = sc->status_block->status_tx_quick_consumer_index0; + if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) + hw_cons++; + + return hw_cons; +} + + +/****************************************************************************/ +/* Handles transmit completion interrupt events. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_tx_intr(struct bce_softc *sc) +{ + struct ifnet *ifp = sc->bce_ifp; + u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; + + DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); + DBRUN(sc->interrupts_tx++); + DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, " + "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", + __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); + + BCE_LOCK_ASSERT(sc); + + /* Get the hardware's view of the TX consumer index. */ + hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); + sw_tx_cons = sc->tx_cons; + + /* Prevent speculative reads of the status block. */ + bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, + BUS_SPACE_BARRIER_READ); + + /* Cycle through any completed TX chain page entries. */ + while (sw_tx_cons != hw_tx_cons) { +#ifdef BCE_DEBUG + struct tx_bd *txbd = NULL; +#endif + sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); + + DBPRINT(sc, BCE_INFO_SEND, + "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, " + "sw_tx_chain_cons = 0x%04X\n", + __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); + + DBRUNIF((sw_tx_chain_cons > MAX_TX_BD), + BCE_PRINTF("%s(%d): TX chain consumer out of range! " + " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons, + (int) MAX_TX_BD); + bce_breakpoint(sc)); + + DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)] + [TX_IDX(sw_tx_chain_cons)]); + + DBRUNIF((txbd == NULL), + BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n", + __FILE__, __LINE__, sw_tx_chain_cons); + bce_breakpoint(sc)); + + DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__); + bce_dump_txbd(sc, sw_tx_chain_cons, txbd)); + + /* + * Free the associated mbuf. Remember + * that only the last tx_bd of a packet + * has an mbuf pointer and DMA map. + */ + if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) { + + /* Validate that this is the last tx_bd. */ + DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)), + BCE_PRINTF("%s(%d): tx_bd END flag not set but " + "txmbuf == NULL!\n", __FILE__, __LINE__); + bce_breakpoint(sc)); + + DBRUNMSG(BCE_INFO_SEND, + BCE_PRINTF("%s(): Unloading map/freeing mbuf " + "from tx_bd[0x%04X]\n", __FUNCTION__, + sw_tx_chain_cons)); + + /* Unmap the mbuf. */ + bus_dmamap_unload(sc->tx_mbuf_tag, + sc->tx_mbuf_map[sw_tx_chain_cons]); + + /* Free the mbuf. */ + m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]); + sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL; + DBRUN(sc->debug_tx_mbuf_alloc--); + + ifp->if_opackets++; + } + + sc->used_tx_bd--; + sw_tx_cons = NEXT_TX_BD(sw_tx_cons); + + /* Refresh hw_cons to see if there's new work. */ + hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); + + /* Prevent speculative reads of the status block. */ + bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, + BUS_SPACE_BARRIER_READ); + } + + /* Clear the TX timeout timer. */ + sc->watchdog_timer = 0; + + /* Clear the tx hardware queue full flag. */ + if (sc->used_tx_bd < sc->max_tx_bd) { + DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE), + DBPRINT(sc, BCE_INFO_SEND, + "%s(): Open TX chain! %d/%d (used/total)\n", + __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd)); + ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; + } + + sc->tx_cons = sw_tx_cons; + + DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, " + "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", + __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); + DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); +} + + +/****************************************************************************/ +/* Disables interrupt generation. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_disable_intr(struct bce_softc *sc) +{ + DBENTER(BCE_VERBOSE_INTR); + + REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT); + REG_RD(sc, BCE_PCICFG_INT_ACK_CMD); + + DBEXIT(BCE_VERBOSE_INTR); +} + + +/****************************************************************************/ +/* Enables interrupt generation. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_enable_intr(struct bce_softc *sc, int coal_now) +{ + DBENTER(BCE_VERBOSE_INTR); + + REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, + BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | + BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); + + REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, + BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); + + /* Force an immediate interrupt (whether there is new data or not). */ + if (coal_now) + REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW); + + DBEXIT(BCE_VERBOSE_INTR); +} + + +/****************************************************************************/ +/* Handles controller initialization. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_init_locked(struct bce_softc *sc) +{ + struct ifnet *ifp; + u32 ether_mtu = 0; + + DBENTER(BCE_VERBOSE_RESET); + + BCE_LOCK_ASSERT(sc); + + ifp = sc->bce_ifp; + + /* Check if the driver is still running and bail out if it is. */ + if (ifp->if_drv_flags & IFF_DRV_RUNNING) + goto bce_init_locked_exit; + + bce_stop(sc); + + if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { + BCE_PRINTF("%s(%d): Controller reset failed!\n", + __FILE__, __LINE__); + goto bce_init_locked_exit; + } + + if (bce_chipinit(sc)) { + BCE_PRINTF("%s(%d): Controller initialization failed!\n", + __FILE__, __LINE__); + goto bce_init_locked_exit; + } + + if (bce_blockinit(sc)) { + BCE_PRINTF("%s(%d): Block initialization failed!\n", + __FILE__, __LINE__); + goto bce_init_locked_exit; + } + + /* Load our MAC address. */ + bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN); + bce_set_mac_addr(sc); + + /* + * Calculate and program the hardware Ethernet MTU + * size. Be generous on the receive if we have room. + */ +#ifdef BCE_JUMBO_HDRSPLIT + if (ifp->if_mtu <= (sc->rx_bd_mbuf_data_len + + sc->pg_bd_mbuf_alloc_size)) + ether_mtu = sc->rx_bd_mbuf_data_len + + sc->pg_bd_mbuf_alloc_size; +#else + if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len) + ether_mtu = sc->rx_bd_mbuf_data_len; +#endif + else + ether_mtu = ifp->if_mtu; + + ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; + + DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n", + __FUNCTION__, ether_mtu); + + /* Program the mtu, enabling jumbo frame support if necessary. */ + if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)) + REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, + min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) | + BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA); + else + REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu); + + DBPRINT(sc, BCE_INFO_LOAD, + "%s(): rx_bd_mbuf_alloc_size = %d, rx_bce_mbuf_data_len = %d, " + "rx_bd_mbuf_align_pad = %d\n", __FUNCTION__, + sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len, + sc->rx_bd_mbuf_align_pad); + + /* Program appropriate promiscuous/multicast filtering. */ + bce_set_rx_mode(sc); + +#ifdef BCE_JUMBO_HDRSPLIT + DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_mbuf_alloc_size = %d\n", + __FUNCTION__, sc->pg_bd_mbuf_alloc_size); + + /* Init page buffer descriptor chain. */ + bce_init_pg_chain(sc); +#endif + + /* Init RX buffer descriptor chain. */ + bce_init_rx_chain(sc); + + /* Init TX buffer descriptor chain. */ + bce_init_tx_chain(sc); + + /* Enable host interrupts. */ + bce_enable_intr(sc, 1); + + bce_ifmedia_upd_locked(ifp); + + /* Let the OS know the driver is up and running. */ + ifp->if_drv_flags |= IFF_DRV_RUNNING; + ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; + + callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); + +bce_init_locked_exit: + DBEXIT(BCE_VERBOSE_RESET); +} + + +/****************************************************************************/ +/* Initialize the controller just enough so that any management firmware */ +/* running on the device will continue to operate correctly. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_mgmt_init_locked(struct bce_softc *sc) +{ + struct ifnet *ifp; + + DBENTER(BCE_VERBOSE_RESET); + + BCE_LOCK_ASSERT(sc); + + /* Bail out if management firmware is not running. */ + if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) { + DBPRINT(sc, BCE_VERBOSE_SPECIAL, + "No management firmware running...\n"); + goto bce_mgmt_init_locked_exit; + } + + ifp = sc->bce_ifp; + + /* Enable all critical blocks in the MAC. */ + REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT); + REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); + DELAY(20); + + bce_ifmedia_upd_locked(ifp); + +bce_mgmt_init_locked_exit: + DBEXIT(BCE_VERBOSE_RESET); +} + + +/****************************************************************************/ +/* Handles controller initialization when called from an unlocked routine. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_init(void *xsc) +{ + struct bce_softc *sc = xsc; + + DBENTER(BCE_VERBOSE_RESET); + + BCE_LOCK(sc); + bce_init_locked(sc); + BCE_UNLOCK(sc); + + DBEXIT(BCE_VERBOSE_RESET); +} + + +/****************************************************************************/ +/* Modifies an mbuf for TSO on the hardware. */ +/* */ +/* Returns: */ +/* Pointer to a modified mbuf. */ +/****************************************************************************/ +static struct mbuf * +bce_tso_setup(struct bce_softc *sc, struct mbuf **m_head, u16 *flags) +{ + struct mbuf *m; + struct ether_header *eh; + struct ip *ip; + struct tcphdr *th; + u16 etype; + int hdr_len, ip_hlen = 0, tcp_hlen = 0, ip_len = 0; + + DBRUN(sc->tso_frames_requested++); + + /* Controller may modify mbuf chains. */ + if (M_WRITABLE(*m_head) == 0) { + m = m_dup(*m_head, M_DONTWAIT); + m_freem(*m_head); + if (m == NULL) { + sc->mbuf_alloc_failed_count++; + *m_head = NULL; + return (NULL); + } + *m_head = m; + } + + /* + * For TSO the controller needs two pieces of info, + * the MSS and the IP+TCP options length. + */ + m = m_pullup(*m_head, sizeof(struct ether_header) + sizeof(struct ip)); + if (m == NULL) { + *m_head = NULL; + return (NULL); + } + eh = mtod(m, struct ether_header *); + etype = ntohs(eh->ether_type); + + /* Check for supported TSO Ethernet types (only IPv4 for now) */ + switch (etype) { + case ETHERTYPE_IP: + ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); + /* TSO only supported for TCP protocol. */ + if (ip->ip_p != IPPROTO_TCP) { + BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n", + __FILE__, __LINE__); + m_freem(*m_head); + *m_head = NULL; + return (NULL); + } + + /* Get IP header length in bytes (min 20) */ + ip_hlen = ip->ip_hl << 2; + m = m_pullup(*m_head, sizeof(struct ether_header) + ip_hlen + + sizeof(struct tcphdr)); + if (m == NULL) { + *m_head = NULL; + return (NULL); + } + + /* Get the TCP header length in bytes (min 20) */ + ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); + th = (struct tcphdr *)((caddr_t)ip + ip_hlen); + tcp_hlen = (th->th_off << 2); + + /* Make sure all IP/TCP options live in the same buffer. */ + m = m_pullup(*m_head, sizeof(struct ether_header)+ ip_hlen + + tcp_hlen); + if (m == NULL) { + *m_head = NULL; + return (NULL); + } + + /* IP header length and checksum will be calc'd by hardware */ + ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); + ip_len = ip->ip_len; + ip->ip_len = 0; + ip->ip_sum = 0; + break; + case ETHERTYPE_IPV6: + BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n", + __FILE__, __LINE__); + m_freem(*m_head); + *m_head = NULL; + return (NULL); + /* NOT REACHED */ + default: + BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n", + __FILE__, __LINE__); + m_freem(*m_head); + *m_head = NULL; + return (NULL); + } + + hdr_len = sizeof(struct ether_header) + ip_hlen + tcp_hlen; + + DBPRINT(sc, BCE_EXTREME_SEND, "%s(): hdr_len = %d, e_hlen = %d, " + "ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n", + __FUNCTION__, hdr_len, (int) sizeof(struct ether_header), ip_hlen, + tcp_hlen, ip_len); + + /* Set the LSO flag in the TX BD */ + *flags |= TX_BD_FLAGS_SW_LSO; + + /* Set the length of IP + TCP options (in 32 bit words) */ + *flags |= (((ip_hlen + tcp_hlen - sizeof(struct ip) - + sizeof(struct tcphdr)) >> 2) << 8); + + DBRUN(sc->tso_frames_completed++); + return (*m_head); +} + + +/****************************************************************************/ +/* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ +/* memory visible to the controller. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/* Modified: */ +/* m_head: May be set to NULL if MBUF is excessively fragmented. */ +/****************************************************************************/ +static int +bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head) +{ + bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; + bus_dmamap_t map; + struct tx_bd *txbd = NULL; + struct mbuf *m0; + u16 prod, chain_prod, mss = 0, vlan_tag = 0, flags = 0; + u32 prod_bseq; + +#ifdef BCE_DEBUG + u16 debug_prod; +#endif + + int i, error, nsegs, rc = 0; + + DBENTER(BCE_VERBOSE_SEND); + + /* Make sure we have room in the TX chain. */ + if (sc->used_tx_bd >= sc->max_tx_bd) + goto bce_tx_encap_exit; + + /* Transfer any checksum offload flags to the bd. */ + m0 = *m_head; + if (m0->m_pkthdr.csum_flags) { + if (m0->m_pkthdr.csum_flags & CSUM_TSO) { + m0 = bce_tso_setup(sc, m_head, &flags); + if (m0 == NULL) { + DBRUN(sc->tso_frames_failed++); + goto bce_tx_encap_exit; + } + mss = htole16(m0->m_pkthdr.tso_segsz); + } else { + if (m0->m_pkthdr.csum_flags & CSUM_IP) + flags |= TX_BD_FLAGS_IP_CKSUM; + if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) + flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; + } + } + + /* Transfer any VLAN tags to the bd. */ + if (m0->m_flags & M_VLANTAG) { + flags |= TX_BD_FLAGS_VLAN_TAG; + vlan_tag = m0->m_pkthdr.ether_vtag; + } + + /* Map the mbuf into DMAable memory. */ + prod = sc->tx_prod; + chain_prod = TX_CHAIN_IDX(prod); + map = sc->tx_mbuf_map[chain_prod]; + + /* Map the mbuf into our DMA address space. */ + error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0, + segs, &nsegs, BUS_DMA_NOWAIT); + + /* Check if the DMA mapping was successful */ + if (error == EFBIG) { + sc->mbuf_frag_count++; + + /* Try to defrag the mbuf. */ + m0 = m_collapse(*m_head, M_DONTWAIT, BCE_MAX_SEGMENTS); + if (m0 == NULL) { + /* Defrag was unsuccessful */ + m_freem(*m_head); + *m_head = NULL; + sc->mbuf_alloc_failed_count++; + rc = ENOBUFS; + goto bce_tx_encap_exit; + } + + /* Defrag was successful, try mapping again */ + *m_head = m0; + error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, + map, m0, segs, &nsegs, BUS_DMA_NOWAIT); + + /* Still getting an error after a defrag. */ + if (error == ENOMEM) { + /* Insufficient DMA buffers available. */ + sc->dma_map_addr_tx_failed_count++; + rc = error; + goto bce_tx_encap_exit; + } else if (error != 0) { + /* Release it and return an error. */ + BCE_PRINTF("%s(%d): Unknown error mapping mbuf into " + "TX chain!\n", __FILE__, __LINE__); + m_freem(m0); + *m_head = NULL; + sc->dma_map_addr_tx_failed_count++; + rc = ENOBUFS; + goto bce_tx_encap_exit; + } + } else if (error == ENOMEM) { + /* Insufficient DMA buffers available. */ + sc->dma_map_addr_tx_failed_count++; + rc = error; + goto bce_tx_encap_exit; + } else if (error != 0) { + m_freem(m0); + *m_head = NULL; + sc->dma_map_addr_tx_failed_count++; + rc = error; + goto bce_tx_encap_exit; + } + + /* Make sure there's room in the chain */ + if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) { + bus_dmamap_unload(sc->tx_mbuf_tag, map); + rc = ENOBUFS; + goto bce_tx_encap_exit; + } + + /* prod points to an empty tx_bd at this point. */ + prod_bseq = sc->tx_prod_bseq; + +#ifdef BCE_DEBUG + debug_prod = chain_prod; +#endif + + DBPRINT(sc, BCE_INFO_SEND, + "%s(start): prod = 0x%04X, chain_prod = 0x%04X, " + "prod_bseq = 0x%08X\n", + __FUNCTION__, prod, chain_prod, prod_bseq); + + /* + * Cycle through each mbuf segment that makes up + * the outgoing frame, gathering the mapping info + * for that segment and creating a tx_bd for + * the mbuf. + */ + for (i = 0; i < nsegs ; i++) { + + chain_prod = TX_CHAIN_IDX(prod); + txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)] + [TX_IDX(chain_prod)]; + + txbd->tx_bd_haddr_lo = + htole32(BCE_ADDR_LO(segs[i].ds_addr)); + txbd->tx_bd_haddr_hi = + htole32(BCE_ADDR_HI(segs[i].ds_addr)); + txbd->tx_bd_mss_nbytes = htole32(mss << 16) | + htole16(segs[i].ds_len); + txbd->tx_bd_vlan_tag = htole16(vlan_tag); + txbd->tx_bd_flags = htole16(flags); + prod_bseq += segs[i].ds_len; + if (i == 0) + txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START); + prod = NEXT_TX_BD(prod); + } + + /* Set the END flag on the last TX buffer descriptor. */ + txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END); + + DBRUNMSG(BCE_EXTREME_SEND, + bce_dump_tx_chain(sc, debug_prod, nsegs)); + + /* + * Ensure that the mbuf pointer for this transmission + * is placed at the array index of the last + * descriptor in this chain. This is done + * because a single map is used for all + * segments of the mbuf and we don't want to + * unload the map before all of the segments + * have been freed. + */ + sc->tx_mbuf_ptr[chain_prod] = m0; + sc->used_tx_bd += nsegs; + + /* Update some debug statistic counters */ + DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), + sc->tx_hi_watermark = sc->used_tx_bd); + DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++); + DBRUNIF(sc->debug_tx_mbuf_alloc++); + + DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1)); + + /* prod points to the next free tx_bd at this point. */ + sc->tx_prod = prod; + sc->tx_prod_bseq = prod_bseq; + + /* Tell the chip about the waiting TX frames. */ + REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + + BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod); + REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + + BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq); + +bce_tx_encap_exit: + DBEXIT(BCE_VERBOSE_SEND); + return(rc); +} + + +/****************************************************************************/ +/* Main transmit routine when called from another routine with a lock. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_start_locked(struct ifnet *ifp) +{ + struct bce_softc *sc = ifp->if_softc; + struct mbuf *m_head = NULL; + int count = 0; + u16 tx_prod, tx_chain_prod; + + DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); + + BCE_LOCK_ASSERT(sc); + + /* prod points to the next free tx_bd. */ + tx_prod = sc->tx_prod; + tx_chain_prod = TX_CHAIN_IDX(tx_prod); + + DBPRINT(sc, BCE_INFO_SEND, + "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, " + "tx_prod_bseq = 0x%08X\n", + __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); + + /* If there's no link or the transmit queue is empty then just exit. */ + if (sc->bce_link_up == FALSE) { + DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n", + __FUNCTION__); + goto bce_start_locked_exit; + } + + if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { + DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n", + __FUNCTION__); + goto bce_start_locked_exit; + } + + /* + * Keep adding entries while there is space in the ring. + */ + while (sc->used_tx_bd < sc->max_tx_bd) { + + /* Check for any frames to send. */ + IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); + + /* Stop when the transmit queue is empty. */ + if (m_head == NULL) + break; + + /* + * Pack the data into the transmit ring. If we + * don't have room, place the mbuf back at the + * head of the queue and set the OACTIVE flag + * to wait for the NIC to drain the chain. + */ + if (bce_tx_encap(sc, &m_head)) { + if (m_head != NULL) + IFQ_DRV_PREPEND(&ifp->if_snd, m_head); + ifp->if_drv_flags |= IFF_DRV_OACTIVE; + DBPRINT(sc, BCE_INFO_SEND, + "TX chain is closed for business! Total " + "tx_bd used = %d\n", sc->used_tx_bd); + break; + } + + count++; + + /* Send a copy of the frame to any BPF listeners. */ + ETHER_BPF_MTAP(ifp, m_head); + } + + /* Exit if no packets were dequeued. */ + if (count == 0) { + DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were " + "dequeued\n", __FUNCTION__); + goto bce_start_locked_exit; + } + + DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): Inserted %d frames into " + "send queue.\n", __FUNCTION__, count); + + /* Set the tx timeout. */ + sc->watchdog_timer = BCE_TX_TIMEOUT; + + DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID)); + DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc)); + +bce_start_locked_exit: + DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); + return; +} + + +/****************************************************************************/ +/* Main transmit routine when called from another routine without a lock. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_start(struct ifnet *ifp) +{ + struct bce_softc *sc = ifp->if_softc; + + DBENTER(BCE_VERBOSE_SEND); + + BCE_LOCK(sc); + bce_start_locked(ifp); + BCE_UNLOCK(sc); + + DBEXIT(BCE_VERBOSE_SEND); +} + + +/****************************************************************************/ +/* Handles any IOCTL calls from the operating system. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data) +{ + struct bce_softc *sc = ifp->if_softc; + struct ifreq *ifr = (struct ifreq *) data; + struct mii_data *mii; + int mask, error = 0, reinit; + + DBENTER(BCE_VERBOSE_MISC); + + switch(command) { + + /* Set the interface MTU. */ + case SIOCSIFMTU: + /* Check that the MTU setting is supported. */ + if ((ifr->ifr_mtu < BCE_MIN_MTU) || + (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) { + error = EINVAL; + break; + } + + DBPRINT(sc, BCE_INFO_MISC, + "SIOCSIFMTU: Changing MTU from %d to %d\n", + (int) ifp->if_mtu, (int) ifr->ifr_mtu); + + BCE_LOCK(sc); + ifp->if_mtu = ifr->ifr_mtu; + reinit = 0; + if (ifp->if_drv_flags & IFF_DRV_RUNNING) { + /* + * Because allocation size is used in RX + * buffer allocation, stop controller if + * it is already running. + */ + bce_stop(sc); + reinit = 1; + } +#ifdef BCE_JUMBO_HDRSPLIT + /* No buffer allocation size changes are necessary. */ +#else + /* Recalculate our buffer allocation sizes. */ + if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + + ETHER_CRC_LEN) > MCLBYTES) { + sc->rx_bd_mbuf_alloc_size = MJUM9BYTES; + sc->rx_bd_mbuf_align_pad = + roundup2(MJUM9BYTES, 16) - MJUM9BYTES; + sc->rx_bd_mbuf_data_len = + sc->rx_bd_mbuf_alloc_size - + sc->rx_bd_mbuf_align_pad; + } else { + sc->rx_bd_mbuf_alloc_size = MCLBYTES; + sc->rx_bd_mbuf_align_pad = + roundup2(MCLBYTES, 16) - MCLBYTES; + sc->rx_bd_mbuf_data_len = + sc->rx_bd_mbuf_alloc_size - + sc->rx_bd_mbuf_align_pad; + } +#endif + + if (reinit != 0) + bce_init_locked(sc); + BCE_UNLOCK(sc); + break; + + /* Set interface flags. */ + case SIOCSIFFLAGS: + DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n"); + + BCE_LOCK(sc); + + /* Check if the interface is up. */ + if (ifp->if_flags & IFF_UP) { + if (ifp->if_drv_flags & IFF_DRV_RUNNING) { + /* Change promiscuous/multicast flags as necessary. */ + bce_set_rx_mode(sc); + } else { + /* Start the HW */ + bce_init_locked(sc); + } + } else { + /* The interface is down, check if driver is running. */ + if (ifp->if_drv_flags & IFF_DRV_RUNNING) { + bce_stop(sc); + + /* If MFW is running, restart the controller a bit. */ + if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { + bce_reset(sc, BCE_DRV_MSG_CODE_RESET); + bce_chipinit(sc); + bce_mgmt_init_locked(sc); + } + } + } + + BCE_UNLOCK(sc); + break; + + /* Add/Delete multicast address */ + case SIOCADDMULTI: + case SIOCDELMULTI: + DBPRINT(sc, BCE_VERBOSE_MISC, + "Received SIOCADDMULTI/SIOCDELMULTI\n"); + + BCE_LOCK(sc); + if (ifp->if_drv_flags & IFF_DRV_RUNNING) + bce_set_rx_mode(sc); + BCE_UNLOCK(sc); + + break; + + /* Set/Get Interface media */ + case SIOCSIFMEDIA: + case SIOCGIFMEDIA: + DBPRINT(sc, BCE_VERBOSE_MISC, + "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n"); + + mii = device_get_softc(sc->bce_miibus); + error = ifmedia_ioctl(ifp, ifr, + &mii->mii_media, command); + break; + + /* Set interface capability */ + case SIOCSIFCAP: + mask = ifr->ifr_reqcap ^ ifp->if_capenable; + DBPRINT(sc, BCE_INFO_MISC, + "Received SIOCSIFCAP = 0x%08X\n", (u32) mask); + + /* Toggle the TX checksum capabilities enable flag. */ + if (mask & IFCAP_TXCSUM && + ifp->if_capabilities & IFCAP_TXCSUM) { + ifp->if_capenable ^= IFCAP_TXCSUM; + if (IFCAP_TXCSUM & ifp->if_capenable) + ifp->if_hwassist |= BCE_IF_HWASSIST; + else + ifp->if_hwassist &= ~BCE_IF_HWASSIST; + } + + /* Toggle the RX checksum capabilities enable flag. */ + if (mask & IFCAP_RXCSUM && + ifp->if_capabilities & IFCAP_RXCSUM) + ifp->if_capenable ^= IFCAP_RXCSUM; + + /* Toggle the TSO capabilities enable flag. */ + if (bce_tso_enable && (mask & IFCAP_TSO4) && + ifp->if_capabilities & IFCAP_TSO4) { + ifp->if_capenable ^= IFCAP_TSO4; + if (IFCAP_TSO4 & ifp->if_capenable) + ifp->if_hwassist |= CSUM_TSO; + else + ifp->if_hwassist &= ~CSUM_TSO; + } + + if (mask & IFCAP_VLAN_HWCSUM && + ifp->if_capabilities & IFCAP_VLAN_HWCSUM) + ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; + + if ((mask & IFCAP_VLAN_HWTSO) != 0 && + (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) + ifp->if_capenable ^= IFCAP_VLAN_HWTSO; + /* + * Don't actually disable VLAN tag stripping as + * management firmware (ASF/IPMI/UMP) requires the + * feature. If VLAN tag stripping is disabled driver + * will manually reconstruct the VLAN frame by + * appending stripped VLAN tag. + */ + if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && + (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)) { + ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; + if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) + == 0) + ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; + } + VLAN_CAPABILITIES(ifp); + break; + default: + /* We don't know how to handle the IOCTL, pass it on. */ + error = ether_ioctl(ifp, command, data); + break; + } + + DBEXIT(BCE_VERBOSE_MISC); + return(error); +} + + +/****************************************************************************/ +/* Transmit timeout handler. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_watchdog(struct bce_softc *sc) +{ + DBENTER(BCE_EXTREME_SEND); + + BCE_LOCK_ASSERT(sc); + + /* If the watchdog timer hasn't expired then just exit. */ + if (sc->watchdog_timer == 0 || --sc->watchdog_timer) + goto bce_watchdog_exit; + + /* If pause frames are active then don't reset the hardware. */ + /* ToDo: Should we reset the timer here? */ + if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED) + goto bce_watchdog_exit; + + BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n", + __FILE__, __LINE__); + + DBRUNMSG(BCE_INFO, + bce_dump_driver_state(sc); + bce_dump_status_block(sc); + bce_dump_stats_block(sc); + bce_dump_ftqs(sc); + bce_dump_txp_state(sc, 0); + bce_dump_rxp_state(sc, 0); + bce_dump_tpat_state(sc, 0); + bce_dump_cp_state(sc, 0); + bce_dump_com_state(sc, 0)); + + DBRUN(bce_breakpoint(sc)); + + sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; + + bce_init_locked(sc); + sc->bce_ifp->if_oerrors++; + +bce_watchdog_exit: + DBEXIT(BCE_EXTREME_SEND); +} + + +/* + * Interrupt handler. + */ +/****************************************************************************/ +/* Main interrupt entry point. Verifies that the controller generated the */ +/* interrupt and then calls a separate routine for handle the various */ +/* interrupt causes (PHY, TX, RX). */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static void +bce_intr(void *xsc) +{ + struct bce_softc *sc; + struct ifnet *ifp; + u32 status_attn_bits; + u16 hw_rx_cons, hw_tx_cons; + + sc = xsc; + ifp = sc->bce_ifp; + + DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); + DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc)); + DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_stats_block(sc)); + + BCE_LOCK(sc); + + DBRUN(sc->interrupts_generated++); + + /* Synchnorize before we read from interface's status block */ + bus_dmamap_sync(sc->status_tag, sc->status_map, + BUS_DMASYNC_POSTREAD); + + /* + * If the hardware status block index + * matches the last value read by the + * driver and we haven't asserted our + * interrupt then there's nothing to do. + */ + if ((sc->status_block->status_idx == sc->last_status_idx) && + (REG_RD(sc, BCE_PCICFG_MISC_STATUS) & + BCE_PCICFG_MISC_STATUS_INTA_VALUE)) { + DBPRINT(sc, BCE_VERBOSE_INTR, "%s(): Spurious interrupt.\n", + __FUNCTION__); + goto bce_intr_exit; + } + + /* Ack the interrupt and stop others from occuring. */ + REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, + BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | + BCE_PCICFG_INT_ACK_CMD_MASK_INT); + + /* Check if the hardware has finished any work. */ + hw_rx_cons = bce_get_hw_rx_cons(sc); + hw_tx_cons = bce_get_hw_tx_cons(sc); + + /* Keep processing data as long as there is work to do. */ + for (;;) { + + status_attn_bits = sc->status_block->status_attn_bits; + + DBRUNIF(DB_RANDOMTRUE(unexpected_attention_sim_control), + BCE_PRINTF("Simulating unexpected status attention " + "bit set."); + sc->unexpected_attention_sim_count++; + status_attn_bits = status_attn_bits | + STATUS_ATTN_BITS_PARITY_ERROR); + + /* Was it a link change interrupt? */ + if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != + (sc->status_block->status_attn_bits_ack & + STATUS_ATTN_BITS_LINK_STATE)) { + bce_phy_intr(sc); + + /* Clear transient updates during link state change. */ + REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | + BCE_HC_COMMAND_COAL_NOW_WO_INT); + REG_RD(sc, BCE_HC_COMMAND); + } + + /* If any other attention is asserted, the chip is toast. */ + if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != + (sc->status_block->status_attn_bits_ack & + ~STATUS_ATTN_BITS_LINK_STATE))) { + + sc->unexpected_attention_count++; + + BCE_PRINTF("%s(%d): Fatal attention detected: " + "0x%08X\n", __FILE__, __LINE__, + sc->status_block->status_attn_bits); + + DBRUNMSG(BCE_FATAL, + if (unexpected_attention_sim_control == 0) + bce_breakpoint(sc)); + + bce_init_locked(sc); + goto bce_intr_exit; + } + + /* Check for any completed RX frames. */ + if (hw_rx_cons != sc->hw_rx_cons) + bce_rx_intr(sc); + + /* Check for any completed TX frames. */ + if (hw_tx_cons != sc->hw_tx_cons) + bce_tx_intr(sc); + + /* Save status block index value for the next interrupt. */ + sc->last_status_idx = sc->status_block->status_idx; + + /* + * Prevent speculative reads from getting + * ahead of the status block. + */ + bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, + BUS_SPACE_BARRIER_READ); + + /* + * If there's no work left then exit the + * interrupt service routine. + */ + hw_rx_cons = bce_get_hw_rx_cons(sc); + hw_tx_cons = bce_get_hw_tx_cons(sc); + + if ((hw_rx_cons == sc->hw_rx_cons) && + (hw_tx_cons == sc->hw_tx_cons)) + break; + + } + + bus_dmamap_sync(sc->status_tag, sc->status_map, + BUS_DMASYNC_PREREAD); + + /* Re-enable interrupts. */ + bce_enable_intr(sc, 0); + + /* Handle any frames that arrived while handling the interrupt. */ + if (ifp->if_drv_flags & IFF_DRV_RUNNING && + !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) + bce_start_locked(ifp); + +bce_intr_exit: + BCE_UNLOCK(sc); + + DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); +} + + +/****************************************************************************/ +/* Programs the various packet receive modes (broadcast and multicast). */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_set_rx_mode(struct bce_softc *sc) +{ + struct ifnet *ifp; + struct ifmultiaddr *ifma; + u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; + u32 rx_mode, sort_mode; + int h, i; + + DBENTER(BCE_VERBOSE_MISC); + + BCE_LOCK_ASSERT(sc); + + ifp = sc->bce_ifp; + + /* Initialize receive mode default settings. */ + rx_mode = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS | + BCE_EMAC_RX_MODE_KEEP_VLAN_TAG); + sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN; + + /* + * ASF/IPMI/UMP firmware requires that VLAN tag stripping + * be enbled. + */ + if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) && + (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))) + rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG; + + /* + * Check for promiscuous, all multicast, or selected + * multicast address filtering. + */ + if (ifp->if_flags & IFF_PROMISC) { + DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n"); + + /* Enable promiscuous mode. */ + rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS; + sort_mode |= BCE_RPM_SORT_USER0_PROM_EN; + } else if (ifp->if_flags & IFF_ALLMULTI) { + DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n"); + + /* Enable all multicast addresses. */ + for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { + REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), 0xffffffff); + } + sort_mode |= BCE_RPM_SORT_USER0_MC_EN; + } else { + /* Accept one or more multicast(s). */ + DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n"); + + if_maddr_rlock(ifp); + TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { + if (ifma->ifma_addr->sa_family != AF_LINK) + continue; + h = ether_crc32_le(LLADDR((struct sockaddr_dl *) + ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF; + hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); + } + if_maddr_runlock(ifp); + + for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) + REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]); + + sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN; + } + + /* Only make changes if the recive mode has actually changed. */ + if (rx_mode != sc->rx_mode) { + DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: " + "0x%08X\n", rx_mode); + + sc->rx_mode = rx_mode; + REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode); + } + + /* Disable and clear the exisitng sort before enabling a new sort. */ + REG_WR(sc, BCE_RPM_SORT_USER0, 0x0); + REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode); + REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA); + + DBEXIT(BCE_VERBOSE_MISC); +} + + +/****************************************************************************/ +/* Called periodically to updates statistics from the controllers */ +/* statistics block. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_stats_update(struct bce_softc *sc) +{ + struct ifnet *ifp; + struct statistics_block *stats; + + DBENTER(BCE_EXTREME_MISC); + + ifp = sc->bce_ifp; + + stats = (struct statistics_block *) sc->stats_block; + + /* + * Certain controllers don't report + * carrier sense errors correctly. + * See errata E11_5708CA0_1165. + */ + if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && + !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) + ifp->if_oerrors += + (u_long) stats->stat_Dot3StatsCarrierSenseErrors; + + /* + * Update the sysctl statistics from the + * hardware statistics. + */ + sc->stat_IfHCInOctets = + ((u64) stats->stat_IfHCInOctets_hi << 32) + + (u64) stats->stat_IfHCInOctets_lo; + + sc->stat_IfHCInBadOctets = + ((u64) stats->stat_IfHCInBadOctets_hi << 32) + + (u64) stats->stat_IfHCInBadOctets_lo; + + sc->stat_IfHCOutOctets = + ((u64) stats->stat_IfHCOutOctets_hi << 32) + + (u64) stats->stat_IfHCOutOctets_lo; + + sc->stat_IfHCOutBadOctets = + ((u64) stats->stat_IfHCOutBadOctets_hi << 32) + + (u64) stats->stat_IfHCOutBadOctets_lo; + + sc->stat_IfHCInUcastPkts = + ((u64) stats->stat_IfHCInUcastPkts_hi << 32) + + (u64) stats->stat_IfHCInUcastPkts_lo; + + sc->stat_IfHCInMulticastPkts = + ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) + + (u64) stats->stat_IfHCInMulticastPkts_lo; + + sc->stat_IfHCInBroadcastPkts = + ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) + + (u64) stats->stat_IfHCInBroadcastPkts_lo; + + sc->stat_IfHCOutUcastPkts = + ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) + + (u64) stats->stat_IfHCOutUcastPkts_lo; + + sc->stat_IfHCOutMulticastPkts = + ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) + + (u64) stats->stat_IfHCOutMulticastPkts_lo; + + sc->stat_IfHCOutBroadcastPkts = + ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) + + (u64) stats->stat_IfHCOutBroadcastPkts_lo; + + /* ToDo: Preserve counters beyond 32 bits? */ + /* ToDo: Read the statistics from auto-clear regs? */ + + sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = + stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; + + sc->stat_Dot3StatsCarrierSenseErrors = + stats->stat_Dot3StatsCarrierSenseErrors; + + sc->stat_Dot3StatsFCSErrors = + stats->stat_Dot3StatsFCSErrors; + + sc->stat_Dot3StatsAlignmentErrors = + stats->stat_Dot3StatsAlignmentErrors; + + sc->stat_Dot3StatsSingleCollisionFrames = + stats->stat_Dot3StatsSingleCollisionFrames; + + sc->stat_Dot3StatsMultipleCollisionFrames = + stats->stat_Dot3StatsMultipleCollisionFrames; + + sc->stat_Dot3StatsDeferredTransmissions = + stats->stat_Dot3StatsDeferredTransmissions; + + sc->stat_Dot3StatsExcessiveCollisions = + stats->stat_Dot3StatsExcessiveCollisions; + + sc->stat_Dot3StatsLateCollisions = + stats->stat_Dot3StatsLateCollisions; + + sc->stat_EtherStatsCollisions = + stats->stat_EtherStatsCollisions; + + sc->stat_EtherStatsFragments = + stats->stat_EtherStatsFragments; + + sc->stat_EtherStatsJabbers = + stats->stat_EtherStatsJabbers; + + sc->stat_EtherStatsUndersizePkts = + stats->stat_EtherStatsUndersizePkts; + + sc->stat_EtherStatsOversizePkts = + stats->stat_EtherStatsOversizePkts; + + sc->stat_EtherStatsPktsRx64Octets = + stats->stat_EtherStatsPktsRx64Octets; + + sc->stat_EtherStatsPktsRx65Octetsto127Octets = + stats->stat_EtherStatsPktsRx65Octetsto127Octets; + + sc->stat_EtherStatsPktsRx128Octetsto255Octets = + stats->stat_EtherStatsPktsRx128Octetsto255Octets; + + sc->stat_EtherStatsPktsRx256Octetsto511Octets = + stats->stat_EtherStatsPktsRx256Octetsto511Octets; + + sc->stat_EtherStatsPktsRx512Octetsto1023Octets = + stats->stat_EtherStatsPktsRx512Octetsto1023Octets; + + sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = + stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; + + sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = + stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; + + sc->stat_EtherStatsPktsTx64Octets = + stats->stat_EtherStatsPktsTx64Octets; + + sc->stat_EtherStatsPktsTx65Octetsto127Octets = + stats->stat_EtherStatsPktsTx65Octetsto127Octets; + + sc->stat_EtherStatsPktsTx128Octetsto255Octets = + stats->stat_EtherStatsPktsTx128Octetsto255Octets; + + sc->stat_EtherStatsPktsTx256Octetsto511Octets = + stats->stat_EtherStatsPktsTx256Octetsto511Octets; + + sc->stat_EtherStatsPktsTx512Octetsto1023Octets = + stats->stat_EtherStatsPktsTx512Octetsto1023Octets; + + sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = + stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; + + sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = + stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; + + sc->stat_XonPauseFramesReceived = + stats->stat_XonPauseFramesReceived; + + sc->stat_XoffPauseFramesReceived = + stats->stat_XoffPauseFramesReceived; + + sc->stat_OutXonSent = + stats->stat_OutXonSent; + + sc->stat_OutXoffSent = + stats->stat_OutXoffSent; + + sc->stat_FlowControlDone = + stats->stat_FlowControlDone; + + sc->stat_MacControlFramesReceived = + stats->stat_MacControlFramesReceived; + + sc->stat_XoffStateEntered = + stats->stat_XoffStateEntered; + + sc->stat_IfInFramesL2FilterDiscards = + stats->stat_IfInFramesL2FilterDiscards; + + sc->stat_IfInRuleCheckerDiscards = + stats->stat_IfInRuleCheckerDiscards; + + sc->stat_IfInFTQDiscards = + stats->stat_IfInFTQDiscards; + + sc->stat_IfInMBUFDiscards = + stats->stat_IfInMBUFDiscards; + + sc->stat_IfInRuleCheckerP4Hit = + stats->stat_IfInRuleCheckerP4Hit; + + sc->stat_CatchupInRuleCheckerDiscards = + stats->stat_CatchupInRuleCheckerDiscards; + + sc->stat_CatchupInFTQDiscards = + stats->stat_CatchupInFTQDiscards; + + sc->stat_CatchupInMBUFDiscards = + stats->stat_CatchupInMBUFDiscards; + + sc->stat_CatchupInRuleCheckerP4Hit = + stats->stat_CatchupInRuleCheckerP4Hit; + + sc->com_no_buffers = REG_RD_IND(sc, 0x120084); + + /* + * Update the interface statistics from the + * hardware statistics. + */ + ifp->if_collisions = + (u_long) sc->stat_EtherStatsCollisions; + + /* ToDo: This method loses soft errors. */ + ifp->if_ierrors = + (u_long) sc->stat_EtherStatsUndersizePkts + + (u_long) sc->stat_EtherStatsOversizePkts + + (u_long) sc->stat_IfInMBUFDiscards + + (u_long) sc->stat_Dot3StatsAlignmentErrors + + (u_long) sc->stat_Dot3StatsFCSErrors + + (u_long) sc->stat_IfInRuleCheckerDiscards + + (u_long) sc->stat_IfInFTQDiscards + + (u_long) sc->com_no_buffers; + + /* ToDo: This method loses soft errors. */ + ifp->if_oerrors = + (u_long) sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + + (u_long) sc->stat_Dot3StatsExcessiveCollisions + + (u_long) sc->stat_Dot3StatsLateCollisions; + + /* ToDo: Add additional statistics? */ + + DBEXIT(BCE_EXTREME_MISC); +} + + +/****************************************************************************/ +/* Periodic function to notify the bootcode that the driver is still */ +/* present. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_pulse(void *xsc) +{ + struct bce_softc *sc = xsc; + u32 msg; + + DBENTER(BCE_EXTREME_MISC); + + BCE_LOCK_ASSERT(sc); + + /* Tell the firmware that the driver is still running. */ + msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq; + bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg); + + /* Update the bootcode condition. */ + sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); + + /* Report whether the bootcode still knows the driver is running. */ + if (bootverbose) { + if (sc->bce_drv_cardiac_arrest == FALSE) { + if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) { + sc->bce_drv_cardiac_arrest = TRUE; + BCE_PRINTF("%s(): Warning: bootcode " + "thinks driver is absent! " + "(bc_state = 0x%08X)\n", + __FUNCTION__, sc->bc_state); + } + } else { + /* + * Not supported by all bootcode versions. + * (v5.0.11+ and v5.2.1+) Older bootcode + * will require the driver to reset the + * controller to clear this condition. + */ + if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) { + sc->bce_drv_cardiac_arrest = FALSE; + BCE_PRINTF("%s(): Bootcode found the " + "driver pulse! (bc_state = 0x%08X)\n", + __FUNCTION__, sc->bc_state); + } + } + } + + + /* Schedule the next pulse. */ + callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc); + + DBEXIT(BCE_EXTREME_MISC); +} + + +/****************************************************************************/ +/* Periodic function to perform maintenance tasks. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_tick(void *xsc) +{ + struct bce_softc *sc = xsc; + struct mii_data *mii; + struct ifnet *ifp; + + ifp = sc->bce_ifp; + + DBENTER(BCE_EXTREME_MISC); + + BCE_LOCK_ASSERT(sc); + + /* Schedule the next tick. */ + callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); + + /* Update the statistics from the hardware statistics block. */ + bce_stats_update(sc); + + /* Top off the receive and page chains. */ +#ifdef BCE_JUMBO_HDRSPLIT + bce_fill_pg_chain(sc); +#endif + bce_fill_rx_chain(sc); + + /* Check that chip hasn't hung. */ + bce_watchdog(sc); + + /* If link is up already up then we're done. */ + if (sc->bce_link_up == TRUE) + goto bce_tick_exit; + + /* Link is down. Check what the PHY's doing. */ + mii = device_get_softc(sc->bce_miibus); + mii_tick(mii); + + /* Check if the link has come up. */ + if ((mii->mii_media_status & IFM_ACTIVE) && + (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) { + DBPRINT(sc, BCE_VERBOSE_MISC, + "%s(): Link up!\n", __FUNCTION__); + sc->bce_link_up = TRUE; + if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || + IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX || + IFM_SUBTYPE(mii->mii_media_active) == IFM_2500_SX) && + bootverbose) + BCE_PRINTF("Gigabit link up!\n"); + + /* Now that link is up, handle any outstanding TX traffic. */ + if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { + DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found " + "pending TX traffic.\n", __FUNCTION__); + bce_start_locked(ifp); + } + } + +bce_tick_exit: + DBEXIT(BCE_EXTREME_MISC); + return; +} + + +#ifdef BCE_DEBUG +/****************************************************************************/ +/* Allows the driver state to be dumped through the sysctl interface. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS) +{ + int error; + int result; + struct bce_softc *sc; + + result = -1; + error = sysctl_handle_int(oidp, &result, 0, req); + + if (error || !req->newptr) + return (error); + + if (result == 1) { + sc = (struct bce_softc *)arg1; + bce_dump_driver_state(sc); + } + + return error; +} + + +/****************************************************************************/ +/* Allows the hardware state to be dumped through the sysctl interface. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS) +{ + int error; + int result; + struct bce_softc *sc; + + result = -1; + error = sysctl_handle_int(oidp, &result, 0, req); + + if (error || !req->newptr) + return (error); + + if (result == 1) { + sc = (struct bce_softc *)arg1; + bce_dump_hw_state(sc); + } + + return error; +} + + +/****************************************************************************/ +/* Allows the status block to be dumped through the sysctl interface. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_sysctl_status_block(SYSCTL_HANDLER_ARGS) +{ + int error; + int result; + struct bce_softc *sc; + + result = -1; + error = sysctl_handle_int(oidp, &result, 0, req); + + if (error || !req->newptr) + return (error); + + if (result == 1) { + sc = (struct bce_softc *)arg1; + bce_dump_status_block(sc); + } + + return error; +} + + +/****************************************************************************/ +/* Allows the stats block to be dumped through the sysctl interface. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_sysctl_stats_block(SYSCTL_HANDLER_ARGS) +{ + int error; + int result; + struct bce_softc *sc; + + result = -1; + error = sysctl_handle_int(oidp, &result, 0, req); + + if (error || !req->newptr) + return (error); + + if (result == 1) { + sc = (struct bce_softc *)arg1; + bce_dump_stats_block(sc); + } + + return error; +} + + +/****************************************************************************/ +/* Allows the stat counters to be cleared without unloading/reloading the */ +/* driver. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_sysctl_stats_clear(SYSCTL_HANDLER_ARGS) +{ + int error; + int result; + struct bce_softc *sc; + + result = -1; + error = sysctl_handle_int(oidp, &result, 0, req); + + if (error || !req->newptr) + return (error); + + if (result == 1) { + sc = (struct bce_softc *)arg1; + + /* Clear the internal H/W statistics counters. */ + REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); + + /* Reset the driver maintained statistics. */ + sc->interrupts_rx = + sc->interrupts_tx = 0; + sc->tso_frames_requested = + sc->tso_frames_completed = + sc->tso_frames_failed = 0; + sc->rx_empty_count = + sc->tx_full_count = 0; + sc->rx_low_watermark = USABLE_RX_BD; + sc->tx_hi_watermark = 0; + sc->l2fhdr_error_count = + sc->l2fhdr_error_sim_count = 0; + sc->mbuf_alloc_failed_count = + sc->mbuf_alloc_failed_sim_count = 0; + sc->dma_map_addr_rx_failed_count = + sc->dma_map_addr_tx_failed_count = 0; + sc->mbuf_frag_count = 0; + sc->csum_offload_tcp_udp = + sc->csum_offload_ip = 0; + sc->vlan_tagged_frames_rcvd = + sc->vlan_tagged_frames_stripped = 0; + + /* Clear firmware maintained statistics. */ + REG_WR_IND(sc, 0x120084, 0); + } + + return error; +} + + +/****************************************************************************/ +/* Allows the bootcode state to be dumped through the sysctl interface. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS) +{ + int error; + int result; + struct bce_softc *sc; + + result = -1; + error = sysctl_handle_int(oidp, &result, 0, req); + + if (error || !req->newptr) + return (error); + + if (result == 1) { + sc = (struct bce_softc *)arg1; + bce_dump_bc_state(sc); + } + + return error; +} + + +/****************************************************************************/ +/* Provides a sysctl interface to allow dumping the RX BD chain. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_sysctl_dump_rx_bd_chain(SYSCTL_HANDLER_ARGS) +{ + int error; + int result; + struct bce_softc *sc; + + result = -1; + error = sysctl_handle_int(oidp, &result, 0, req); + + if (error || !req->newptr) + return (error); + + if (result == 1) { + sc = (struct bce_softc *)arg1; + bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD); + } + + return error; +} + + +/****************************************************************************/ +/* Provides a sysctl interface to allow dumping the RX MBUF chain. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_sysctl_dump_rx_mbuf_chain(SYSCTL_HANDLER_ARGS) +{ + int error; + int result; + struct bce_softc *sc; + + result = -1; + error = sysctl_handle_int(oidp, &result, 0, req); + + if (error || !req->newptr) + return (error); + + if (result == 1) { + sc = (struct bce_softc *)arg1; + bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD); + } + + return error; +} + + +/****************************************************************************/ +/* Provides a sysctl interface to allow dumping the TX chain. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS) +{ + int error; + int result; + struct bce_softc *sc; + + result = -1; + error = sysctl_handle_int(oidp, &result, 0, req); + + if (error || !req->newptr) + return (error); + + if (result == 1) { + sc = (struct bce_softc *)arg1; + bce_dump_tx_chain(sc, 0, TOTAL_TX_BD); + } + + return error; +} + + +#ifdef BCE_JUMBO_HDRSPLIT +/****************************************************************************/ +/* Provides a sysctl interface to allow dumping the page chain. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_sysctl_dump_pg_chain(SYSCTL_HANDLER_ARGS) +{ + int error; + int result; + struct bce_softc *sc; + + result = -1; + error = sysctl_handle_int(oidp, &result, 0, req); + + if (error || !req->newptr) + return (error); + + if (result == 1) { + sc = (struct bce_softc *)arg1; + bce_dump_pg_chain(sc, 0, TOTAL_PG_BD); + } + + return error; +} +#endif + +/****************************************************************************/ +/* Provides a sysctl interface to allow reading arbitrary NVRAM offsets in */ +/* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS) +{ + struct bce_softc *sc = (struct bce_softc *)arg1; + int error; + u32 result; + u32 val[1]; + u8 *data = (u8 *) val; + + result = -1; + error = sysctl_handle_int(oidp, &result, 0, req); + if (error || (req->newptr == NULL)) + return (error); + + bce_nvram_read(sc, result, data, 4); + BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0])); + + return (error); +} + + +/****************************************************************************/ +/* Provides a sysctl interface to allow reading arbitrary registers in the */ +/* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS) +{ + struct bce_softc *sc = (struct bce_softc *)arg1; + int error; + u32 val, result; + + result = -1; + error = sysctl_handle_int(oidp, &result, 0, req); + if (error || (req->newptr == NULL)) + return (error); + + /* Make sure the register is accessible. */ + if (result < 0x8000) { + val = REG_RD(sc, result); + BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); + } else if (result < 0x0280000) { + val = REG_RD_IND(sc, result); + BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); + } + + return (error); +} + + +/****************************************************************************/ +/* Provides a sysctl interface to allow reading arbitrary PHY registers in */ +/* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS) +{ + struct bce_softc *sc; + device_t dev; + int error, result; + u16 val; + + result = -1; + error = sysctl_handle_int(oidp, &result, 0, req); + if (error || (req->newptr == NULL)) + return (error); + + /* Make sure the register is accessible. */ + if (result < 0x20) { + sc = (struct bce_softc *)arg1; + dev = sc->bce_dev; + val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result); + BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val); + } + return (error); +} + + +/****************************************************************************/ +/* Provides a sysctl interface to allow reading a CID. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS) +{ + struct bce_softc *sc; + int error, result; + + result = -1; + error = sysctl_handle_int(oidp, &result, 0, req); + if (error || (req->newptr == NULL)) + return (error); + + /* Make sure the register is accessible. */ + if (result <= TX_CID) { + sc = (struct bce_softc *)arg1; + bce_dump_ctx(sc, result); + } + + return (error); +} + + + /****************************************************************************/ +/* Provides a sysctl interface to forcing the driver to dump state and */ +/* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS) +{ + int error; + int result; + struct bce_softc *sc; + + result = -1; + error = sysctl_handle_int(oidp, &result, 0, req); + + if (error || !req->newptr) + return (error); + + if (result == 1) { + sc = (struct bce_softc *)arg1; + bce_breakpoint(sc); + } + + return error; +} +#endif + + +/****************************************************************************/ +/* Adds any sysctl parameters for tuning or debugging purposes. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static void +bce_add_sysctls(struct bce_softc *sc) +{ + struct sysctl_ctx_list *ctx; + struct sysctl_oid_list *children; + + DBENTER(BCE_VERBOSE_MISC); + + ctx = device_get_sysctl_ctx(sc->bce_dev); + children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev)); + +#ifdef BCE_DEBUG + SYSCTL_ADD_INT(ctx, children, OID_AUTO, + "l2fhdr_error_sim_control", + CTLFLAG_RW, &l2fhdr_error_sim_control, + 0, "Debug control to force l2fhdr errors"); + + SYSCTL_ADD_INT(ctx, children, OID_AUTO, + "l2fhdr_error_sim_count", + CTLFLAG_RD, &sc->l2fhdr_error_sim_count, + 0, "Number of simulated l2_fhdr errors"); +#endif + + SYSCTL_ADD_INT(ctx, children, OID_AUTO, + "l2fhdr_error_count", + CTLFLAG_RD, &sc->l2fhdr_error_count, + 0, "Number of l2_fhdr errors"); + +#ifdef BCE_DEBUG + SYSCTL_ADD_INT(ctx, children, OID_AUTO, + "mbuf_alloc_failed_sim_control", + CTLFLAG_RW, &mbuf_alloc_failed_sim_control, + 0, "Debug control to force mbuf allocation failures"); + + SYSCTL_ADD_INT(ctx, children, OID_AUTO, + "mbuf_alloc_failed_sim_count", + CTLFLAG_RD, &sc->mbuf_alloc_failed_sim_count, + 0, "Number of simulated mbuf cluster allocation failures"); +#endif + + SYSCTL_ADD_INT(ctx, children, OID_AUTO, + "mbuf_alloc_failed_count", + CTLFLAG_RD, &sc->mbuf_alloc_failed_count, + 0, "Number of mbuf allocation failures"); + + SYSCTL_ADD_INT(ctx, children, OID_AUTO, + "mbuf_frag_count", + CTLFLAG_RD, &sc->mbuf_frag_count, + 0, "Number of fragmented mbufs"); + +#ifdef BCE_DEBUG + SYSCTL_ADD_INT(ctx, children, OID_AUTO, + "dma_map_addr_failed_sim_control", + CTLFLAG_RW, &dma_map_addr_failed_sim_control, + 0, "Debug control to force DMA mapping failures"); + + /* ToDo: Figure out how to update this value in bce_dma_map_addr(). */ + SYSCTL_ADD_INT(ctx, children, OID_AUTO, + "dma_map_addr_failed_sim_count", + CTLFLAG_RD, &sc->dma_map_addr_failed_sim_count, + 0, "Number of simulated DMA mapping failures"); + +#endif + + SYSCTL_ADD_INT(ctx, children, OID_AUTO, + "dma_map_addr_rx_failed_count", + CTLFLAG_RD, &sc->dma_map_addr_rx_failed_count, + 0, "Number of RX DMA mapping failures"); + + SYSCTL_ADD_INT(ctx, children, OID_AUTO, + "dma_map_addr_tx_failed_count", + CTLFLAG_RD, &sc->dma_map_addr_tx_failed_count, + 0, "Number of TX DMA mapping failures"); + +#ifdef BCE_DEBUG + SYSCTL_ADD_INT(ctx, children, OID_AUTO, + "unexpected_attention_sim_control", + CTLFLAG_RW, &unexpected_attention_sim_control, + 0, "Debug control to simulate unexpected attentions"); + + SYSCTL_ADD_INT(ctx, children, OID_AUTO, + "unexpected_attention_sim_count", + CTLFLAG_RW, &sc->unexpected_attention_sim_count, + 0, "Number of simulated unexpected attentions"); +#endif + + SYSCTL_ADD_INT(ctx, children, OID_AUTO, + "unexpected_attention_count", + CTLFLAG_RW, &sc->unexpected_attention_count, + 0, "Number of unexpected attentions"); + +#ifdef BCE_DEBUG + SYSCTL_ADD_INT(ctx, children, OID_AUTO, + "debug_bootcode_running_failure", + CTLFLAG_RW, &bootcode_running_failure_sim_control, + 0, "Debug control to force bootcode running failures"); + + SYSCTL_ADD_INT(ctx, children, OID_AUTO, + "rx_low_watermark", + CTLFLAG_RD, &sc->rx_low_watermark, + 0, "Lowest level of free rx_bd's"); + + SYSCTL_ADD_INT(ctx, children, OID_AUTO, + "rx_empty_count", + CTLFLAG_RD, &sc->rx_empty_count, + 0, "Number of times the RX chain was empty"); + + SYSCTL_ADD_INT(ctx, children, OID_AUTO, + "tx_hi_watermark", + CTLFLAG_RD, &sc->tx_hi_watermark, + 0, "Highest level of used tx_bd's"); + + SYSCTL_ADD_INT(ctx, children, OID_AUTO, + "tx_full_count", + CTLFLAG_RD, &sc->tx_full_count, + 0, "Number of times the TX chain was full"); + + SYSCTL_ADD_INT(ctx, children, OID_AUTO, + "tso_frames_requested", + CTLFLAG_RD, &sc->tso_frames_requested, + 0, "Number of TSO frames requested"); + + SYSCTL_ADD_INT(ctx, children, OID_AUTO, + "tso_frames_completed", + CTLFLAG_RD, &sc->tso_frames_completed, + 0, "Number of TSO frames completed"); + + SYSCTL_ADD_INT(ctx, children, OID_AUTO, + "tso_frames_failed", + CTLFLAG_RD, &sc->tso_frames_failed, + 0, "Number of TSO frames failed"); + + SYSCTL_ADD_INT(ctx, children, OID_AUTO, + "csum_offload_ip", + CTLFLAG_RD, &sc->csum_offload_ip, + 0, "Number of IP checksum offload frames"); + + SYSCTL_ADD_INT(ctx, children, OID_AUTO, + "csum_offload_tcp_udp", + CTLFLAG_RD, &sc->csum_offload_tcp_udp, + 0, "Number of TCP/UDP checksum offload frames"); + + SYSCTL_ADD_INT(ctx, children, OID_AUTO, + "vlan_tagged_frames_rcvd", + CTLFLAG_RD, &sc->vlan_tagged_frames_rcvd, + 0, "Number of VLAN tagged frames received"); + + SYSCTL_ADD_INT(ctx, children, OID_AUTO, + "vlan_tagged_frames_stripped", + CTLFLAG_RD, &sc->vlan_tagged_frames_stripped, + 0, "Number of VLAN tagged frames stripped"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "interrupts_rx", + CTLFLAG_RD, &sc->interrupts_rx, + 0, "Number of RX interrupts"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "interrupts_tx", + CTLFLAG_RD, &sc->interrupts_tx, + 0, "Number of TX interrupts"); +#endif + + SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, + "stat_IfHcInOctets", + CTLFLAG_RD, &sc->stat_IfHCInOctets, + "Bytes received"); + + SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, + "stat_IfHCInBadOctets", + CTLFLAG_RD, &sc->stat_IfHCInBadOctets, + "Bad bytes received"); + + SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, + "stat_IfHCOutOctets", + CTLFLAG_RD, &sc->stat_IfHCOutOctets, + "Bytes sent"); + + SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, + "stat_IfHCOutBadOctets", + CTLFLAG_RD, &sc->stat_IfHCOutBadOctets, + "Bad bytes sent"); + + SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, + "stat_IfHCInUcastPkts", + CTLFLAG_RD, &sc->stat_IfHCInUcastPkts, + "Unicast packets received"); + + SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, + "stat_IfHCInMulticastPkts", + CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts, + "Multicast packets received"); + + SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, + "stat_IfHCInBroadcastPkts", + CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts, + "Broadcast packets received"); + + SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, + "stat_IfHCOutUcastPkts", + CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts, + "Unicast packets sent"); + + SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, + "stat_IfHCOutMulticastPkts", + CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts, + "Multicast packets sent"); + + SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, + "stat_IfHCOutBroadcastPkts", + CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts, + "Broadcast packets sent"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_emac_tx_stat_dot3statsinternalmactransmiterrors", + CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors, + 0, "Internal MAC transmit errors"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_Dot3StatsCarrierSenseErrors", + CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors, + 0, "Carrier sense errors"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_Dot3StatsFCSErrors", + CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors, + 0, "Frame check sequence errors"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_Dot3StatsAlignmentErrors", + CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors, + 0, "Alignment errors"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_Dot3StatsSingleCollisionFrames", + CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames, + 0, "Single Collision Frames"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_Dot3StatsMultipleCollisionFrames", + CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames, + 0, "Multiple Collision Frames"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_Dot3StatsDeferredTransmissions", + CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions, + 0, "Deferred Transmissions"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_Dot3StatsExcessiveCollisions", + CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions, + 0, "Excessive Collisions"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_Dot3StatsLateCollisions", + CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions, + 0, "Late Collisions"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsCollisions", + CTLFLAG_RD, &sc->stat_EtherStatsCollisions, + 0, "Collisions"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsFragments", + CTLFLAG_RD, &sc->stat_EtherStatsFragments, + 0, "Fragments"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsJabbers", + CTLFLAG_RD, &sc->stat_EtherStatsJabbers, + 0, "Jabbers"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsUndersizePkts", + CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts, + 0, "Undersize packets"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsOversizePkts", + CTLFLAG_RD, &sc->stat_EtherStatsOversizePkts, + 0, "stat_EtherStatsOversizePkts"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsPktsRx64Octets", + CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets, + 0, "Bytes received in 64 byte packets"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsPktsRx65Octetsto127Octets", + CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets, + 0, "Bytes received in 65 to 127 byte packets"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsPktsRx128Octetsto255Octets", + CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets, + 0, "Bytes received in 128 to 255 byte packets"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsPktsRx256Octetsto511Octets", + CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets, + 0, "Bytes received in 256 to 511 byte packets"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsPktsRx512Octetsto1023Octets", + CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets, + 0, "Bytes received in 512 to 1023 byte packets"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsPktsRx1024Octetsto1522Octets", + CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets, + 0, "Bytes received in 1024 t0 1522 byte packets"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsPktsRx1523Octetsto9022Octets", + CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets, + 0, "Bytes received in 1523 to 9022 byte packets"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsPktsTx64Octets", + CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets, + 0, "Bytes sent in 64 byte packets"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsPktsTx65Octetsto127Octets", + CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets, + 0, "Bytes sent in 65 to 127 byte packets"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsPktsTx128Octetsto255Octets", + CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets, + 0, "Bytes sent in 128 to 255 byte packets"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsPktsTx256Octetsto511Octets", + CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets, + 0, "Bytes sent in 256 to 511 byte packets"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsPktsTx512Octetsto1023Octets", + CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets, + 0, "Bytes sent in 512 to 1023 byte packets"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsPktsTx1024Octetsto1522Octets", + CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets, + 0, "Bytes sent in 1024 to 1522 byte packets"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsPktsTx1523Octetsto9022Octets", + CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets, + 0, "Bytes sent in 1523 to 9022 byte packets"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_XonPauseFramesReceived", + CTLFLAG_RD, &sc->stat_XonPauseFramesReceived, + 0, "XON pause frames receved"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_XoffPauseFramesReceived", + CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived, + 0, "XOFF pause frames received"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_OutXonSent", + CTLFLAG_RD, &sc->stat_OutXonSent, + 0, "XON pause frames sent"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_OutXoffSent", + CTLFLAG_RD, &sc->stat_OutXoffSent, + 0, "XOFF pause frames sent"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_FlowControlDone", + CTLFLAG_RD, &sc->stat_FlowControlDone, + 0, "Flow control done"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_MacControlFramesReceived", + CTLFLAG_RD, &sc->stat_MacControlFramesReceived, + 0, "MAC control frames received"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_XoffStateEntered", + CTLFLAG_RD, &sc->stat_XoffStateEntered, + 0, "XOFF state entered"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_IfInFramesL2FilterDiscards", + CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards, + 0, "Received L2 packets discarded"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_IfInRuleCheckerDiscards", + CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards, + 0, "Received packets discarded by rule"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_IfInFTQDiscards", + CTLFLAG_RD, &sc->stat_IfInFTQDiscards, + 0, "Received packet FTQ discards"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_IfInMBUFDiscards", + CTLFLAG_RD, &sc->stat_IfInMBUFDiscards, + 0, "Received packets discarded due to lack " + "of controller buffer memory"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_IfInRuleCheckerP4Hit", + CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit, + 0, "Received packets rule checker hits"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_CatchupInRuleCheckerDiscards", + CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards, + 0, "Received packets discarded in Catchup path"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_CatchupInFTQDiscards", + CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards, + 0, "Received packets discarded in FTQ in Catchup path"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_CatchupInMBUFDiscards", + CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards, + 0, "Received packets discarded in controller " + "buffer memory in Catchup path"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_CatchupInRuleCheckerP4Hit", + CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit, + 0, "Received packets rule checker hits in Catchup path"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "com_no_buffers", + CTLFLAG_RD, &sc->com_no_buffers, + 0, "Valid packets received but no RX buffers available"); + +#ifdef BCE_DEBUG + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, + "driver_state", CTLTYPE_INT | CTLFLAG_RW, + (void *)sc, 0, + bce_sysctl_driver_state, "I", "Drive state information"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, + "hw_state", CTLTYPE_INT | CTLFLAG_RW, + (void *)sc, 0, + bce_sysctl_hw_state, "I", "Hardware state information"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, + "status_block", CTLTYPE_INT | CTLFLAG_RW, + (void *)sc, 0, + bce_sysctl_status_block, "I", "Dump status block"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, + "stats_block", CTLTYPE_INT | CTLFLAG_RW, + (void *)sc, 0, + bce_sysctl_stats_block, "I", "Dump statistics block"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, + "stats_clear", CTLTYPE_INT | CTLFLAG_RW, + (void *)sc, 0, + bce_sysctl_stats_clear, "I", "Clear statistics block"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, + "bc_state", CTLTYPE_INT | CTLFLAG_RW, + (void *)sc, 0, + bce_sysctl_bc_state, "I", "Bootcode state information"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, + "dump_rx_bd_chain", CTLTYPE_INT | CTLFLAG_RW, + (void *)sc, 0, + bce_sysctl_dump_rx_bd_chain, "I", "Dump RX BD chain"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, + "dump_rx_mbuf_chain", CTLTYPE_INT | CTLFLAG_RW, + (void *)sc, 0, + bce_sysctl_dump_rx_mbuf_chain, "I", "Dump RX MBUF chain"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, + "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW, + (void *)sc, 0, + bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain"); + +#ifdef BCE_JUMBO_HDRSPLIT + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, + "dump_pg_chain", CTLTYPE_INT | CTLFLAG_RW, + (void *)sc, 0, + bce_sysctl_dump_pg_chain, "I", "Dump page chain"); +#endif + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, + "dump_ctx", CTLTYPE_INT | CTLFLAG_RW, + (void *)sc, 0, + bce_sysctl_dump_ctx, "I", "Dump context memory"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, + "breakpoint", CTLTYPE_INT | CTLFLAG_RW, + (void *)sc, 0, + bce_sysctl_breakpoint, "I", "Driver breakpoint"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, + "reg_read", CTLTYPE_INT | CTLFLAG_RW, + (void *)sc, 0, + bce_sysctl_reg_read, "I", "Register read"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, + "nvram_read", CTLTYPE_INT | CTLFLAG_RW, + (void *)sc, 0, + bce_sysctl_nvram_read, "I", "NVRAM read"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, + "phy_read", CTLTYPE_INT | CTLFLAG_RW, + (void *)sc, 0, + bce_sysctl_phy_read, "I", "PHY register read"); + +#endif + + DBEXIT(BCE_VERBOSE_MISC); +} + + +/****************************************************************************/ +/* BCE Debug Routines */ +/****************************************************************************/ +#ifdef BCE_DEBUG + +/****************************************************************************/ +/* Freezes the controller to allow for a cohesive state dump. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static __attribute__ ((noinline)) void +bce_freeze_controller(struct bce_softc *sc) +{ + u32 val; + val = REG_RD(sc, BCE_MISC_COMMAND); + val |= BCE_MISC_COMMAND_DISABLE_ALL; + REG_WR(sc, BCE_MISC_COMMAND, val); +} + + +/****************************************************************************/ +/* Unfreezes the controller after a freeze operation. This may not always */ +/* work and the controller will require a reset! */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static __attribute__ ((noinline)) void +bce_unfreeze_controller(struct bce_softc *sc) +{ + u32 val; + val = REG_RD(sc, BCE_MISC_COMMAND); + val |= BCE_MISC_COMMAND_ENABLE_ALL; + REG_WR(sc, BCE_MISC_COMMAND, val); +} + + +/****************************************************************************/ +/* Prints out Ethernet frame information from an mbuf. */ +/* */ +/* Partially decode an Ethernet frame to look at some important headers. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static __attribute__ ((noinline)) void +bce_dump_enet(struct bce_softc *sc, struct mbuf *m) +{ + struct ether_vlan_header *eh; + u16 etype; + int ehlen; + struct ip *ip; + struct tcphdr *th; + struct udphdr *uh; + struct arphdr *ah; + + BCE_PRINTF( + "-----------------------------" + " Frame Decode " + "-----------------------------\n"); + + eh = mtod(m, struct ether_vlan_header *); + + /* Handle VLAN encapsulation if present. */ + if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { + etype = ntohs(eh->evl_proto); + ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; + } else { + etype = ntohs(eh->evl_encap_proto); + ehlen = ETHER_HDR_LEN; + } + + /* ToDo: Add VLAN output. */ + BCE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, hlen = %d\n", + eh->evl_dhost, ":", eh->evl_shost, ":", etype, ehlen); + + switch (etype) { + case ETHERTYPE_IP: + ip = (struct ip *)(m->m_data + ehlen); + BCE_PRINTF("--ip: dest = 0x%08X , src = 0x%08X, " + "len = %d bytes, protocol = 0x%02X, xsum = 0x%04X\n", + ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr), + ntohs(ip->ip_len), ip->ip_p, ntohs(ip->ip_sum)); + + switch (ip->ip_p) { + case IPPROTO_TCP: + th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); + BCE_PRINTF("-tcp: dest = %d, src = %d, hlen = " + "%d bytes, flags = 0x%b, csum = 0x%04X\n", + ntohs(th->th_dport), ntohs(th->th_sport), + (th->th_off << 2), th->th_flags, + "\20\10CWR\07ECE\06URG\05ACK\04PSH\03RST" + "\02SYN\01FIN", ntohs(th->th_sum)); + break; + case IPPROTO_UDP: + uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2)); + BCE_PRINTF("-udp: dest = %d, src = %d, len = %d " + "bytes, csum = 0x%04X\n", ntohs(uh->uh_dport), + ntohs(uh->uh_sport), ntohs(uh->uh_ulen), + ntohs(uh->uh_sum)); + break; + case IPPROTO_ICMP: + BCE_PRINTF("icmp:\n"); + break; + default: + BCE_PRINTF("----: Other IP protocol.\n"); + } + break; + case ETHERTYPE_IPV6: + BCE_PRINTF("ipv6: No decode supported.\n"); + break; + case ETHERTYPE_ARP: + BCE_PRINTF("-arp: "); + ah = (struct arphdr *) (m->m_data + ehlen); + switch (ntohs(ah->ar_op)) { + case ARPOP_REVREQUEST: + printf("reverse ARP request\n"); + break; + case ARPOP_REVREPLY: + printf("reverse ARP reply\n"); + break; + case ARPOP_REQUEST: + printf("ARP request\n"); + break; + case ARPOP_REPLY: + printf("ARP reply\n"); + break; + default: + printf("other ARP operation\n"); + } + break; + default: + BCE_PRINTF("----: Other protocol.\n"); + } + + BCE_PRINTF( + "-----------------------------" + "--------------" + "-----------------------------\n"); +} + + +/****************************************************************************/ +/* Prints out information about an mbuf. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static __attribute__ ((noinline)) void +bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m) +{ + struct mbuf *mp = m; + + if (m == NULL) { + BCE_PRINTF("mbuf: null pointer\n"); + return; + } + + while (mp) { + BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, " + "m_data = %p\n", mp, mp->m_len, mp->m_flags, + "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", mp->m_data); + + if (mp->m_flags & M_PKTHDR) { + BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, " + "csum_flags = %b\n", mp->m_pkthdr.len, + mp->m_flags, "\20\12M_BCAST\13M_MCAST\14M_FRAG" + "\15M_FIRSTFRAG\16M_LASTFRAG\21M_VLANTAG" + "\22M_PROMISC\23M_NOFREE", + mp->m_pkthdr.csum_flags, + "\20\1CSUM_IP\2CSUM_TCP\3CSUM_UDP\4CSUM_IP_FRAGS" + "\5CSUM_FRAGMENT\6CSUM_TSO\11CSUM_IP_CHECKED" + "\12CSUM_IP_VALID\13CSUM_DATA_VALID" + "\14CSUM_PSEUDO_HDR"); + } + + if (mp->m_flags & M_EXT) { + BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ", + mp->m_ext.ext_buf, mp->m_ext.ext_size); + switch (mp->m_ext.ext_type) { + case EXT_CLUSTER: + printf("EXT_CLUSTER\n"); break; + case EXT_SFBUF: + printf("EXT_SFBUF\n"); break; + case EXT_JUMBO9: + printf("EXT_JUMBO9\n"); break; + case EXT_JUMBO16: + printf("EXT_JUMBO16\n"); break; + case EXT_PACKET: + printf("EXT_PACKET\n"); break; + case EXT_MBUF: + printf("EXT_MBUF\n"); break; + case EXT_NET_DRV: + printf("EXT_NET_DRV\n"); break; + case EXT_MOD_TYPE: + printf("EXT_MDD_TYPE\n"); break; + case EXT_DISPOSABLE: + printf("EXT_DISPOSABLE\n"); break; + case EXT_EXTREF: + printf("EXT_EXTREF\n"); break; + default: + printf("UNKNOWN\n"); + } + } + + mp = mp->m_next; + } +} + + +/****************************************************************************/ +/* Prints out the mbufs in the TX mbuf chain. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static __attribute__ ((noinline)) void +bce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) +{ + struct mbuf *m; + + BCE_PRINTF( + "----------------------------" + " tx mbuf data " + "----------------------------\n"); + + for (int i = 0; i < count; i++) { + m = sc->tx_mbuf_ptr[chain_prod]; + BCE_PRINTF("txmbuf[0x%04X]\n", chain_prod); + bce_dump_mbuf(sc, m); + chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); + } + + BCE_PRINTF( + "----------------------------" + "----------------" + "----------------------------\n"); +} + + +/****************************************************************************/ +/* Prints out the mbufs in the RX mbuf chain. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static __attribute__ ((noinline)) void +bce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) +{ + struct mbuf *m; + + BCE_PRINTF( + "----------------------------" + " rx mbuf data " + "----------------------------\n"); + + for (int i = 0; i < count; i++) { + m = sc->rx_mbuf_ptr[chain_prod]; + BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod); + bce_dump_mbuf(sc, m); + chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); + } + + + BCE_PRINTF( + "----------------------------" + "----------------" + "----------------------------\n"); +} + + +#ifdef BCE_JUMBO_HDRSPLIT +/****************************************************************************/ +/* Prints out the mbufs in the mbuf page chain. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static __attribute__ ((noinline)) void +bce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) +{ + struct mbuf *m; + + BCE_PRINTF( + "----------------------------" + " pg mbuf data " + "----------------------------\n"); + + for (int i = 0; i < count; i++) { + m = sc->pg_mbuf_ptr[chain_prod]; + BCE_PRINTF("pgmbuf[0x%04X]\n", chain_prod); + bce_dump_mbuf(sc, m); + chain_prod = PG_CHAIN_IDX(NEXT_PG_BD(chain_prod)); + } + + + BCE_PRINTF( + "----------------------------" + "----------------" + "----------------------------\n"); +} +#endif + + +/****************************************************************************/ +/* Prints out a tx_bd structure. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static __attribute__ ((noinline)) void +bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd) +{ + int i = 0; + + if (idx > MAX_TX_BD) + /* Index out of range. */ + BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); + else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) + /* TX Chain page pointer. */ + BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " + "pointer\n", idx, txbd->tx_bd_haddr_hi, + txbd->tx_bd_haddr_lo); + else { + /* Normal tx_bd entry. */ + BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, " + "mss_nbytes = 0x%08X, vlan tag = 0x%04X, flags = " + "0x%04X (", idx, txbd->tx_bd_haddr_hi, + txbd->tx_bd_haddr_lo, txbd->tx_bd_mss_nbytes, + txbd->tx_bd_vlan_tag, txbd->tx_bd_flags); + + if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) { + if (i>0) + printf("|"); + printf("CONN_FAULT"); + i++; + } + + if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) { + if (i>0) + printf("|"); + printf("TCP_UDP_CKSUM"); + i++; + } + + if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) { + if (i>0) + printf("|"); + printf("IP_CKSUM"); + i++; + } + + if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) { + if (i>0) + printf("|"); + printf("VLAN"); + i++; + } + + if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) { + if (i>0) + printf("|"); + printf("COAL_NOW"); + i++; + } + + if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) { + if (i>0) + printf("|"); + printf("DONT_GEN_CRC"); + i++; + } + + if (txbd->tx_bd_flags & TX_BD_FLAGS_START) { + if (i>0) + printf("|"); + printf("START"); + i++; + } + + if (txbd->tx_bd_flags & TX_BD_FLAGS_END) { + if (i>0) + printf("|"); + printf("END"); + i++; + } + + if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) { + if (i>0) + printf("|"); + printf("LSO"); + i++; + } + + if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) { + if (i>0) + printf("|"); + printf("SW_OPTION=%d", ((txbd->tx_bd_flags & + TX_BD_FLAGS_SW_OPTION_WORD) >> 8)); i++; + } + + if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) { + if (i>0) + printf("|"); + printf("SW_FLAGS"); + i++; + } + + if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) { + if (i>0) + printf("|"); + printf("SNAP)"); + } else { + printf(")\n"); + } + } +} + + +/****************************************************************************/ +/* Prints out a rx_bd structure. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static __attribute__ ((noinline)) void +bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd) +{ + if (idx > MAX_RX_BD) + /* Index out of range. */ + BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); + else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) + /* RX Chain page pointer. */ + BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " + "pointer\n", idx, rxbd->rx_bd_haddr_hi, + rxbd->rx_bd_haddr_lo); + else + /* Normal rx_bd entry. */ + BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " + "0x%08X, flags = 0x%08X\n", idx, rxbd->rx_bd_haddr_hi, + rxbd->rx_bd_haddr_lo, rxbd->rx_bd_len, + rxbd->rx_bd_flags); +} + + +#ifdef BCE_JUMBO_HDRSPLIT +/****************************************************************************/ +/* Prints out a rx_bd structure in the page chain. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static __attribute__ ((noinline)) void +bce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd) +{ + if (idx > MAX_PG_BD) + /* Index out of range. */ + BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx); + else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE) + /* Page Chain page pointer. */ + BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", + idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo); + else + /* Normal rx_bd entry. */ + BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " + "flags = 0x%08X\n", idx, + pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo, + pgbd->rx_bd_len, pgbd->rx_bd_flags); +} +#endif + + +/****************************************************************************/ +/* Prints out a l2_fhdr structure. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static __attribute__ ((noinline)) void +bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr) +{ + BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, " + "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, " + "tcp_udp_xsum = 0x%04X\n", idx, + l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB, + l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag, + l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum); +} + + +/****************************************************************************/ +/* Prints out context memory info. (Only useful for CID 0 to 16.) */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static __attribute__ ((noinline)) void +bce_dump_ctx(struct bce_softc *sc, u16 cid) +{ + if (cid > TX_CID) { + BCE_PRINTF(" Unknown CID\n"); + return; + } + + BCE_PRINTF( + "----------------------------" + " CTX Data " + "----------------------------\n"); + + BCE_PRINTF(" 0x%04X - (CID) Context ID\n", cid); + + if (cid == RX_CID) { + BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BDIDX) host rx " + "producer index\n", + CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BDIDX)); + BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BSEQ) host " + "byte sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), + BCE_L2CTX_RX_HOST_BSEQ)); + BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BSEQ) h/w byte sequence\n", + CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BSEQ)); + BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_HI) h/w buffer " + "descriptor address\n", + CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_HI)); + BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_LO) h/w buffer " + "descriptor address\n", + CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_LO)); + BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDIDX) h/w rx consumer " + "index\n", CTX_RD(sc, GET_CID_ADDR(cid), + BCE_L2CTX_RX_NX_BDIDX)); + BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_PG_BDIDX) host page " + "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), + BCE_L2CTX_RX_HOST_PG_BDIDX)); + BCE_PRINTF(" 0x%08X - (L2CTX_RX_PG_BUF_SIZE) host rx_bd/page " + "buffer size\n", CTX_RD(sc, GET_CID_ADDR(cid), + BCE_L2CTX_RX_PG_BUF_SIZE)); + BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_HI) h/w page " + "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), + BCE_L2CTX_RX_NX_PG_BDHADDR_HI)); + BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_LO) h/w page " + "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), + BCE_L2CTX_RX_NX_PG_BDHADDR_LO)); + BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDIDX) h/w page " + "consumer index\n", CTX_RD(sc, GET_CID_ADDR(cid), + BCE_L2CTX_RX_NX_PG_BDIDX)); + } else if (cid == TX_CID) { + if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || + (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { + BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE_XI) ctx type\n", + CTX_RD(sc, GET_CID_ADDR(cid), + BCE_L2CTX_TX_TYPE_XI)); + BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TX_TYPE_XI) ctx " + "cmd\n", CTX_RD(sc, GET_CID_ADDR(cid), + BCE_L2CTX_TX_CMD_TYPE_XI)); + BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI_XI) " + "h/w buffer descriptor address\n", + CTX_RD(sc, GET_CID_ADDR(cid), + BCE_L2CTX_TX_TBDR_BHADDR_HI_XI)); + BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO_XI) " + "h/w buffer descriptor address\n", + CTX_RD(sc, GET_CID_ADDR(cid), + BCE_L2CTX_TX_TBDR_BHADDR_LO_XI)); + BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) " + "host producer index\n", + CTX_RD(sc, GET_CID_ADDR(cid), + BCE_L2CTX_TX_HOST_BIDX_XI)); + BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) " + "host byte sequence\n", + CTX_RD(sc, GET_CID_ADDR(cid), + BCE_L2CTX_TX_HOST_BSEQ_XI)); + } else { + BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE) ctx type\n", + CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE)); + BCE_PRINTF(" 0x%08X - (L2CTX_TX_CMD_TYPE) ctx cmd\n", + CTX_RD(sc, GET_CID_ADDR(cid), + BCE_L2CTX_TX_CMD_TYPE)); + BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI) " + "h/w buffer descriptor address\n", + CTX_RD(sc, GET_CID_ADDR(cid), + BCE_L2CTX_TX_TBDR_BHADDR_HI)); + BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO) " + "h/w buffer descriptor address\n", + CTX_RD(sc, GET_CID_ADDR(cid), + BCE_L2CTX_TX_TBDR_BHADDR_LO)); + BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host " + "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), + BCE_L2CTX_TX_HOST_BIDX)); + BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte " + "sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), + BCE_L2CTX_TX_HOST_BSEQ)); + } + } + + BCE_PRINTF( + "----------------------------" + " Raw CTX " + "----------------------------\n"); + + for (int i = 0x0; i < 0x300; i += 0x10) { + BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i, + CTX_RD(sc, GET_CID_ADDR(cid), i), + CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4), + CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8), + CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc)); + } + + + BCE_PRINTF( + "----------------------------" + "----------------" + "----------------------------\n"); +} + + +/****************************************************************************/ +/* Prints out the FTQ data. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static __attribute__ ((noinline)) void +bce_dump_ftqs(struct bce_softc *sc) +{ + u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val; + + BCE_PRINTF( + "----------------------------" + " FTQ Data " + "----------------------------\n"); + + BCE_PRINTF(" FTQ Command Control Depth_Now " + "Max_Depth Valid_Cnt \n"); + BCE_PRINTF(" ------- ---------- ---------- ---------- " + "---------- ----------\n"); + + /* Setup the generic statistic counters for the FTQ valid count. */ + val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) | + (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT << 16) | + (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT << 8) | + (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT); + REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); + + val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT << 24) | + (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT << 16) | + (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT << 8) | + (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT); + REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val); + + val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT << 24) | + (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT << 16) | + (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT << 8) | + (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT); + REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val); + + val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT << 24) | + (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT << 16) | + (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT << 8) | + (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT); + REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val); + + /* Input queue to the Receive Lookup state machine */ + cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD); + ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL); + cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22; + max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12; + valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); + BCE_PRINTF(" RLUP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", + cmd, ctl, cur_depth, max_depth, valid_cnt); + + /* Input queue to the Receive Processor */ + cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD); + ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL); + cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22; + max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12; + valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); + BCE_PRINTF(" RXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", + cmd, ctl, cur_depth, max_depth, valid_cnt); + + /* Input queue to the Recevie Processor */ + cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD); + ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL); + cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22; + max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12; + valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); + BCE_PRINTF(" RXPC 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", + cmd, ctl, cur_depth, max_depth, valid_cnt); + + /* Input queue to the Receive Virtual to Physical state machine */ + cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD); + ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL); + cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22; + max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12; + valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); + BCE_PRINTF(" RV2PP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", + cmd, ctl, cur_depth, max_depth, valid_cnt); + + /* Input queue to the Recevie Virtual to Physical state machine */ + cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD); + ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL); + cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22; + max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12; + valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4); + BCE_PRINTF(" RV2PM 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", + cmd, ctl, cur_depth, max_depth, valid_cnt); + + /* Input queue to the Receive Virtual to Physical state machine */ + cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD); + ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL); + cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22; + max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12; + valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5); + BCE_PRINTF(" RV2PT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", + cmd, ctl, cur_depth, max_depth, valid_cnt); + + /* Input queue to the Receive DMA state machine */ + cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD); + ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL); + cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22; + max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12; + valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6); + BCE_PRINTF(" RDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", + cmd, ctl, cur_depth, max_depth, valid_cnt); + + /* Input queue to the Transmit Scheduler state machine */ + cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD); + ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL); + cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22; + max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12; + valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7); + BCE_PRINTF(" TSCH 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", + cmd, ctl, cur_depth, max_depth, valid_cnt); + + /* Input queue to the Transmit Buffer Descriptor state machine */ + cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD); + ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL); + cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22; + max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12; + valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8); + BCE_PRINTF(" TBDR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", + cmd, ctl, cur_depth, max_depth, valid_cnt); + + /* Input queue to the Transmit Processor */ + cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD); + ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL); + cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22; + max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12; + valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9); + BCE_PRINTF(" TXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", + cmd, ctl, cur_depth, max_depth, valid_cnt); + + /* Input queue to the Transmit DMA state machine */ + cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD); + ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL); + cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22; + max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12; + valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10); + BCE_PRINTF(" TDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", + cmd, ctl, cur_depth, max_depth, valid_cnt); + + /* Input queue to the Transmit Patch-Up Processor */ + cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD); + ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL); + cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22; + max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12; + valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11); + BCE_PRINTF(" TPAT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", + cmd, ctl, cur_depth, max_depth, valid_cnt); + + /* Input queue to the Transmit Assembler state machine */ + cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD); + ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL); + cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22; + max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12; + valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12); + BCE_PRINTF(" TAS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", + cmd, ctl, cur_depth, max_depth, valid_cnt); + + /* Input queue to the Completion Processor */ + cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD); + ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL); + cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22; + max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12; + valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13); + BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", + cmd, ctl, cur_depth, max_depth, valid_cnt); + + /* Input queue to the Completion Processor */ + cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD); + ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL); + cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22; + max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12; + valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14); + BCE_PRINTF(" COMT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", + cmd, ctl, cur_depth, max_depth, valid_cnt); + + /* Input queue to the Completion Processor */ + cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD); + ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL); + cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22; + max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12; + valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15); + BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", + cmd, ctl, cur_depth, max_depth, valid_cnt); + + /* Setup the generic statistic counters for the FTQ valid count. */ + val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT << 16) | + (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT << 8) | + (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT); + + if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || + (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) + val = val | + (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI << + 24); + REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); + + /* Input queue to the Management Control Processor */ + cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD); + ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL); + cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22; + max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12; + valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); + BCE_PRINTF(" MCP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", + cmd, ctl, cur_depth, max_depth, valid_cnt); + + /* Input queue to the Command Processor */ + cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD); + ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL); + cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22; + max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12; + valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); + BCE_PRINTF(" CP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", + cmd, ctl, cur_depth, max_depth, valid_cnt); + + /* Input queue to the Completion Scheduler state machine */ + cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD); + ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL); + cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22; + max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12; + valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); + BCE_PRINTF(" CS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", + cmd, ctl, cur_depth, max_depth, valid_cnt); + + if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || + (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { + /* Input queue to the RV2P Command Scheduler */ + cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD); + ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL); + cur_depth = (ctl & 0xFFC00000) >> 22; + max_depth = (ctl & 0x003FF000) >> 12; + valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); + BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", + cmd, ctl, cur_depth, max_depth, valid_cnt); + } + + BCE_PRINTF( + "----------------------------" + "----------------" + "----------------------------\n"); +} + + +/****************************************************************************/ +/* Prints out the TX chain. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static __attribute__ ((noinline)) void +bce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count) +{ + struct tx_bd *txbd; + + /* First some info about the tx_bd chain structure. */ + BCE_PRINTF( + "----------------------------" + " tx_bd chain " + "----------------------------\n"); + + BCE_PRINTF("page size = 0x%08X, tx chain pages = 0x%08X\n", + (u32) BCM_PAGE_SIZE, (u32) TX_PAGES); + BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", + (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE); + BCE_PRINTF("total tx_bd = 0x%08X\n", (u32) TOTAL_TX_BD); + + BCE_PRINTF( + "----------------------------" + " tx_bd data " + "----------------------------\n"); + + /* Now print out a decoded list of TX buffer descriptors. */ + for (int i = 0; i < count; i++) { + txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; + bce_dump_txbd(sc, tx_prod, txbd); + tx_prod++; + } + + BCE_PRINTF( + "----------------------------" + "----------------" + "----------------------------\n"); +} + + +/****************************************************************************/ +/* Prints out the RX chain. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static __attribute__ ((noinline)) void +bce_dump_rx_bd_chain(struct bce_softc *sc, u16 rx_prod, int count) +{ + struct rx_bd *rxbd; + + /* First some info about the rx_bd chain structure. */ + BCE_PRINTF( + "----------------------------" + " rx_bd chain " + "----------------------------\n"); + + BCE_PRINTF("page size = 0x%08X, rx chain pages = 0x%08X\n", + (u32) BCM_PAGE_SIZE, (u32) RX_PAGES); + + BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", + (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE); + + BCE_PRINTF("total rx_bd = 0x%08X\n", (u32) TOTAL_RX_BD); + + BCE_PRINTF( + "----------------------------" + " rx_bd data " + "----------------------------\n"); + + /* Now print out the rx_bd's themselves. */ + for (int i = 0; i < count; i++) { + rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; + bce_dump_rxbd(sc, rx_prod, rxbd); + rx_prod = RX_CHAIN_IDX(rx_prod + 1); + } + + BCE_PRINTF( + "----------------------------" + "----------------" + "----------------------------\n"); +} + + +#ifdef BCE_JUMBO_HDRSPLIT +/****************************************************************************/ +/* Prints out the page chain. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static __attribute__ ((noinline)) void +bce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count) +{ + struct rx_bd *pgbd; + + /* First some info about the page chain structure. */ + BCE_PRINTF( + "----------------------------" + " page chain " + "----------------------------\n"); + + BCE_PRINTF("page size = 0x%08X, pg chain pages = 0x%08X\n", + (u32) BCM_PAGE_SIZE, (u32) PG_PAGES); + + BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", + (u32) TOTAL_PG_BD_PER_PAGE, (u32) USABLE_PG_BD_PER_PAGE); + + BCE_PRINTF("total rx_bd = 0x%08X, max_pg_bd = 0x%08X\n", + (u32) TOTAL_PG_BD, (u32) MAX_PG_BD); + + BCE_PRINTF( + "----------------------------" + " page data " + "----------------------------\n"); + + /* Now print out the rx_bd's themselves. */ + for (int i = 0; i < count; i++) { + pgbd = &sc->pg_bd_chain[PG_PAGE(pg_prod)][PG_IDX(pg_prod)]; + bce_dump_pgbd(sc, pg_prod, pgbd); + pg_prod = PG_CHAIN_IDX(pg_prod + 1); + } + + BCE_PRINTF( + "----------------------------" + "----------------" + "----------------------------\n"); +} +#endif + + +#define BCE_PRINT_RX_CONS(arg) \ +if (sblk->status_rx_quick_consumer_index##arg) \ + BCE_PRINTF("0x%04X(0x%04X) - rx_quick_consumer_index%d\n", \ + sblk->status_rx_quick_consumer_index##arg, (u16) \ + RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index##arg), \ + arg); + + +#define BCE_PRINT_TX_CONS(arg) \ +if (sblk->status_tx_quick_consumer_index##arg) \ + BCE_PRINTF("0x%04X(0x%04X) - tx_quick_consumer_index%d\n", \ + sblk->status_tx_quick_consumer_index##arg, (u16) \ + TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index##arg), \ + arg); + +/****************************************************************************/ +/* Prints out the status block from host memory. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static __attribute__ ((noinline)) void +bce_dump_status_block(struct bce_softc *sc) +{ + struct status_block *sblk; + + sblk = sc->status_block; + + BCE_PRINTF( + "----------------------------" + " Status Block " + "----------------------------\n"); + + /* Theses indices are used for normal L2 drivers. */ + BCE_PRINTF(" 0x%08X - attn_bits\n", + sblk->status_attn_bits); + + BCE_PRINTF(" 0x%08X - attn_bits_ack\n", + sblk->status_attn_bits_ack); + + BCE_PRINT_RX_CONS(0); + BCE_PRINT_TX_CONS(0) + + BCE_PRINTF(" 0x%04X - status_idx\n", sblk->status_idx); + + /* Theses indices are not used for normal L2 drivers. */ + BCE_PRINT_RX_CONS(1); BCE_PRINT_RX_CONS(2); BCE_PRINT_RX_CONS(3); + BCE_PRINT_RX_CONS(4); BCE_PRINT_RX_CONS(5); BCE_PRINT_RX_CONS(6); + BCE_PRINT_RX_CONS(7); BCE_PRINT_RX_CONS(8); BCE_PRINT_RX_CONS(9); + BCE_PRINT_RX_CONS(10); BCE_PRINT_RX_CONS(11); BCE_PRINT_RX_CONS(12); + BCE_PRINT_RX_CONS(13); BCE_PRINT_RX_CONS(14); BCE_PRINT_RX_CONS(15); + + BCE_PRINT_TX_CONS(1); BCE_PRINT_TX_CONS(2); BCE_PRINT_TX_CONS(3); + + if (sblk->status_completion_producer_index || + sblk->status_cmd_consumer_index) + BCE_PRINTF("com_prod = 0x%08X, cmd_cons = 0x%08X\n", + sblk->status_completion_producer_index, + sblk->status_cmd_consumer_index); + + BCE_PRINTF( + "----------------------------" + "----------------" + "----------------------------\n"); +} + + +#define BCE_PRINT_64BIT_STAT(arg) \ +if (sblk->arg##_lo || sblk->arg##_hi) \ + BCE_PRINTF("0x%08X:%08X : %s\n", sblk->arg##_hi, \ + sblk->arg##_lo, #arg); + +#define BCE_PRINT_32BIT_STAT(arg) \ +if (sblk->arg) \ + BCE_PRINTF(" 0x%08X : %s\n", \ + sblk->arg, #arg); + +/****************************************************************************/ +/* Prints out the statistics block from host memory. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static __attribute__ ((noinline)) void +bce_dump_stats_block(struct bce_softc *sc) +{ + struct statistics_block *sblk; + + sblk = sc->stats_block; + + BCE_PRINTF( + "---------------" + " Stats Block (All Stats Not Shown Are 0) " + "---------------\n"); + + BCE_PRINT_64BIT_STAT(stat_IfHCInOctets); + BCE_PRINT_64BIT_STAT(stat_IfHCInBadOctets); + BCE_PRINT_64BIT_STAT(stat_IfHCOutOctets); + BCE_PRINT_64BIT_STAT(stat_IfHCOutBadOctets); + BCE_PRINT_64BIT_STAT(stat_IfHCInUcastPkts); + BCE_PRINT_64BIT_STAT(stat_IfHCInBroadcastPkts); + BCE_PRINT_64BIT_STAT(stat_IfHCInMulticastPkts); + BCE_PRINT_64BIT_STAT(stat_IfHCOutUcastPkts); + BCE_PRINT_64BIT_STAT(stat_IfHCOutBroadcastPkts); + BCE_PRINT_64BIT_STAT(stat_IfHCOutMulticastPkts); + BCE_PRINT_32BIT_STAT( + stat_emac_tx_stat_dot3statsinternalmactransmiterrors); + BCE_PRINT_32BIT_STAT(stat_Dot3StatsCarrierSenseErrors); + BCE_PRINT_32BIT_STAT(stat_Dot3StatsFCSErrors); + BCE_PRINT_32BIT_STAT(stat_Dot3StatsAlignmentErrors); + BCE_PRINT_32BIT_STAT(stat_Dot3StatsSingleCollisionFrames); + BCE_PRINT_32BIT_STAT(stat_Dot3StatsMultipleCollisionFrames); + BCE_PRINT_32BIT_STAT(stat_Dot3StatsDeferredTransmissions); + BCE_PRINT_32BIT_STAT(stat_Dot3StatsExcessiveCollisions); + BCE_PRINT_32BIT_STAT(stat_Dot3StatsLateCollisions); + BCE_PRINT_32BIT_STAT(stat_EtherStatsCollisions); + BCE_PRINT_32BIT_STAT(stat_EtherStatsFragments); + BCE_PRINT_32BIT_STAT(stat_EtherStatsJabbers); + BCE_PRINT_32BIT_STAT(stat_EtherStatsUndersizePkts); + BCE_PRINT_32BIT_STAT(stat_EtherStatsOversizePkts); + BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx64Octets); + BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx65Octetsto127Octets); + BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx128Octetsto255Octets); + BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx256Octetsto511Octets); + BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx512Octetsto1023Octets); + BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1024Octetsto1522Octets); + BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1523Octetsto9022Octets); + BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx64Octets); + BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx65Octetsto127Octets); + BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx128Octetsto255Octets); + BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx256Octetsto511Octets); + BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx512Octetsto1023Octets); + BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1024Octetsto1522Octets); + BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1523Octetsto9022Octets); + BCE_PRINT_32BIT_STAT(stat_XonPauseFramesReceived); + BCE_PRINT_32BIT_STAT(stat_XoffPauseFramesReceived); + BCE_PRINT_32BIT_STAT(stat_OutXonSent); + BCE_PRINT_32BIT_STAT(stat_OutXoffSent); + BCE_PRINT_32BIT_STAT(stat_FlowControlDone); + BCE_PRINT_32BIT_STAT(stat_MacControlFramesReceived); + BCE_PRINT_32BIT_STAT(stat_XoffStateEntered); + BCE_PRINT_32BIT_STAT(stat_IfInFramesL2FilterDiscards); + BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerDiscards); + BCE_PRINT_32BIT_STAT(stat_IfInFTQDiscards); + BCE_PRINT_32BIT_STAT(stat_IfInMBUFDiscards); + BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerP4Hit); + BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerDiscards); + BCE_PRINT_32BIT_STAT(stat_CatchupInFTQDiscards); + BCE_PRINT_32BIT_STAT(stat_CatchupInMBUFDiscards); + BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerP4Hit); + + BCE_PRINTF( + "----------------------------" + "----------------" + "----------------------------\n"); +} + + +/****************************************************************************/ +/* Prints out a summary of the driver state. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static __attribute__ ((noinline)) void +bce_dump_driver_state(struct bce_softc *sc) +{ + u32 val_hi, val_lo; + + BCE_PRINTF( + "-----------------------------" + " Driver State " + "-----------------------------\n"); + + val_hi = BCE_ADDR_HI(sc); + val_lo = BCE_ADDR_LO(sc); + BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual " + "address\n", val_hi, val_lo); + + val_hi = BCE_ADDR_HI(sc->bce_vhandle); + val_lo = BCE_ADDR_LO(sc->bce_vhandle); + BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual " + "address\n", val_hi, val_lo); + + val_hi = BCE_ADDR_HI(sc->status_block); + val_lo = BCE_ADDR_LO(sc->status_block); + BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block " + "virtual address\n", val_hi, val_lo); + + val_hi = BCE_ADDR_HI(sc->stats_block); + val_lo = BCE_ADDR_LO(sc->stats_block); + BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block " + "virtual address\n", val_hi, val_lo); + + val_hi = BCE_ADDR_HI(sc->tx_bd_chain); + val_lo = BCE_ADDR_LO(sc->tx_bd_chain); + BCE_PRINTF("0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain " + "virtual adddress\n", val_hi, val_lo); + + val_hi = BCE_ADDR_HI(sc->rx_bd_chain); + val_lo = BCE_ADDR_LO(sc->rx_bd_chain); + BCE_PRINTF("0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain " + "virtual address\n", val_hi, val_lo); + +#ifdef BCE_JUMBO_HDRSPLIT + val_hi = BCE_ADDR_HI(sc->pg_bd_chain); + val_lo = BCE_ADDR_LO(sc->pg_bd_chain); + BCE_PRINTF("0x%08X:%08X - (sc->pg_bd_chain) page chain " + "virtual address\n", val_hi, val_lo); +#endif + + val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr); + val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr); + BCE_PRINTF("0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain " + "virtual address\n", val_hi, val_lo); + + val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr); + val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr); + BCE_PRINTF("0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain " + "virtual address\n", val_hi, val_lo); + +#ifdef BCE_JUMBO_HDRSPLIT + val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr); + val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr); + BCE_PRINTF("0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain " + "virtual address\n", val_hi, val_lo); +#endif + + BCE_PRINTF(" 0x%08X - (sc->interrupts_generated) " + "h/w intrs\n", sc->interrupts_generated); + + BCE_PRINTF(" 0x%08X - (sc->interrupts_rx) " + "rx interrupts handled\n", sc->interrupts_rx); + + BCE_PRINTF(" 0x%08X - (sc->interrupts_tx) " + "tx interrupts handled\n", sc->interrupts_tx); + + BCE_PRINTF(" 0x%08X - (sc->phy_interrupts) " + "phy interrupts handled\n", sc->phy_interrupts); + + BCE_PRINTF(" 0x%08X - (sc->last_status_idx) " + "status block index\n", sc->last_status_idx); + + BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_prod) tx producer " + "index\n", sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod)); + + BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_cons) tx consumer " + "index\n", sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons)); + + BCE_PRINTF(" 0x%08X - (sc->tx_prod_bseq) tx producer " + "byte seq index\n", sc->tx_prod_bseq); + + BCE_PRINTF(" 0x%08X - (sc->debug_tx_mbuf_alloc) tx " + "mbufs allocated\n", sc->debug_tx_mbuf_alloc); + + BCE_PRINTF(" 0x%08X - (sc->used_tx_bd) used " + "tx_bd's\n", sc->used_tx_bd); + + BCE_PRINTF("0x%08X/%08X - (sc->tx_hi_watermark) tx hi " + "watermark\n", sc->tx_hi_watermark, sc->max_tx_bd); + + BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_prod) rx producer " + "index\n", sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod)); + + BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_cons) rx consumer " + "index\n", sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons)); + + BCE_PRINTF(" 0x%08X - (sc->rx_prod_bseq) rx producer " + "byte seq index\n", sc->rx_prod_bseq); + + BCE_PRINTF(" 0x%08X - (sc->debug_rx_mbuf_alloc) rx " + "mbufs allocated\n", sc->debug_rx_mbuf_alloc); + + BCE_PRINTF(" 0x%08X - (sc->free_rx_bd) free " + "rx_bd's\n", sc->free_rx_bd); + +#ifdef BCE_JUMBO_HDRSPLIT + BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_prod) page producer " + "index\n", sc->pg_prod, (u16) PG_CHAIN_IDX(sc->pg_prod)); + + BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_cons) page consumer " + "index\n", sc->pg_cons, (u16) PG_CHAIN_IDX(sc->pg_cons)); + + BCE_PRINTF(" 0x%08X - (sc->debug_pg_mbuf_alloc) page " + "mbufs allocated\n", sc->debug_pg_mbuf_alloc); + + BCE_PRINTF(" 0x%08X - (sc->free_pg_bd) free page " + "rx_bd's\n", sc->free_pg_bd); + + BCE_PRINTF("0x%08X/%08X - (sc->pg_low_watermark) page low " + "watermark\n", sc->pg_low_watermark, sc->max_pg_bd); +#endif + + BCE_PRINTF(" 0x%08X - (sc->mbuf_alloc_failed_count) " + "mbuf alloc failures\n", sc->mbuf_alloc_failed_count); + + BCE_PRINTF(" 0x%08X - (sc->bce_flags) " + "bce mac flags\n", sc->bce_flags); + + BCE_PRINTF(" 0x%08X - (sc->bce_phy_flags) " + "bce phy flags\n", sc->bce_phy_flags); + + BCE_PRINTF( + "----------------------------" + "----------------" + "----------------------------\n"); +} + + +/****************************************************************************/ +/* Prints out the hardware state through a summary of important register, */ +/* followed by a complete register dump. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static __attribute__ ((noinline)) void +bce_dump_hw_state(struct bce_softc *sc) +{ + u32 val; + + BCE_PRINTF( + "----------------------------" + " Hardware State " + "----------------------------\n"); + + BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); + + val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS); + BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n", + val, BCE_MISC_ENABLE_STATUS_BITS); + + val = REG_RD(sc, BCE_DMA_STATUS); + BCE_PRINTF("0x%08X - (0x%06X) dma_status\n", + val, BCE_DMA_STATUS); + + val = REG_RD(sc, BCE_CTX_STATUS); + BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n", + val, BCE_CTX_STATUS); + + val = REG_RD(sc, BCE_EMAC_STATUS); + BCE_PRINTF("0x%08X - (0x%06X) emac_status\n", + val, BCE_EMAC_STATUS); + + val = REG_RD(sc, BCE_RPM_STATUS); + BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n", + val, BCE_RPM_STATUS); + + /* ToDo: Create a #define for this constant. */ + val = REG_RD(sc, 0x2004); + BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n", + val, 0x2004); + + val = REG_RD(sc, BCE_RV2P_STATUS); + BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n", + val, BCE_RV2P_STATUS); + + /* ToDo: Create a #define for this constant. */ + val = REG_RD(sc, 0x2c04); + BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n", + val, 0x2c04); + + val = REG_RD(sc, BCE_TBDR_STATUS); + BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n", + val, BCE_TBDR_STATUS); + + val = REG_RD(sc, BCE_TDMA_STATUS); + BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n", + val, BCE_TDMA_STATUS); + + val = REG_RD(sc, BCE_HC_STATUS); + BCE_PRINTF("0x%08X - (0x%06X) hc_status\n", + val, BCE_HC_STATUS); + + val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); + BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", + val, BCE_TXP_CPU_STATE); + + val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); + BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", + val, BCE_TPAT_CPU_STATE); + + val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); + BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", + val, BCE_RXP_CPU_STATE); + + val = REG_RD_IND(sc, BCE_COM_CPU_STATE); + BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", + val, BCE_COM_CPU_STATE); + + val = REG_RD_IND(sc, BCE_MCP_CPU_STATE); + BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n", + val, BCE_MCP_CPU_STATE); + + val = REG_RD_IND(sc, BCE_CP_CPU_STATE); + BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", + val, BCE_CP_CPU_STATE); + + BCE_PRINTF( + "----------------------------" + "----------------" + "----------------------------\n"); + + BCE_PRINTF( + "----------------------------" + " Register Dump " + "----------------------------\n"); + + for (int i = 0x400; i < 0x8000; i += 0x10) { + BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", + i, REG_RD(sc, i), REG_RD(sc, i + 0x4), + REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); + } + + BCE_PRINTF( + "----------------------------" + "----------------" + "----------------------------\n"); +} + + +/****************************************************************************/ +/* Prints out the mailbox queue registers. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static __attribute__ ((noinline)) void +bce_dump_mq_regs(struct bce_softc *sc) +{ + BCE_PRINTF( + "----------------------------" + " MQ Regs " + "----------------------------\n"); + + BCE_PRINTF( + "----------------------------" + "----------------" + "----------------------------\n"); + + for (int i = 0x3c00; i < 0x4000; i += 0x10) { + BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", + i, REG_RD(sc, i), REG_RD(sc, i + 0x4), + REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); + } + + BCE_PRINTF( + "----------------------------" + "----------------" + "----------------------------\n"); +} + + +/****************************************************************************/ +/* Prints out the bootcode state. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static __attribute__ ((noinline)) void +bce_dump_bc_state(struct bce_softc *sc) +{ + u32 val; + + BCE_PRINTF( + "----------------------------" + " Bootcode State " + "----------------------------\n"); + + BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); + + val = bce_shmem_rd(sc, BCE_BC_RESET_TYPE); + BCE_PRINTF("0x%08X - (0x%06X) reset_type\n", + val, BCE_BC_RESET_TYPE); + + val = bce_shmem_rd(sc, BCE_BC_STATE); + BCE_PRINTF("0x%08X - (0x%06X) state\n", + val, BCE_BC_STATE); + + val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); + BCE_PRINTF("0x%08X - (0x%06X) condition\n", + val, BCE_BC_STATE_CONDITION); + + val = bce_shmem_rd(sc, BCE_BC_STATE_DEBUG_CMD); + BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n", + val, BCE_BC_STATE_DEBUG_CMD); + + BCE_PRINTF( + "----------------------------" + "----------------" + "----------------------------\n"); +} + + +/****************************************************************************/ +/* Prints out the TXP processor state. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static __attribute__ ((noinline)) void +bce_dump_txp_state(struct bce_softc *sc, int regs) +{ + u32 val; + u32 fw_version[3]; + + BCE_PRINTF( + "----------------------------" + " TXP State " + "----------------------------\n"); + + for (int i = 0; i < 3; i++) + fw_version[i] = htonl(REG_RD_IND(sc, + (BCE_TXP_SCRATCH + 0x10 + i * 4))); + BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); + + val = REG_RD_IND(sc, BCE_TXP_CPU_MODE); + BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n", + val, BCE_TXP_CPU_MODE); + + val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); + BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", + val, BCE_TXP_CPU_STATE); + + val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK); + BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n", + val, BCE_TXP_CPU_EVENT_MASK); + + if (regs) { + BCE_PRINTF( + "----------------------------" + " Register Dump " + "----------------------------\n"); + + for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) { + /* Skip the big blank spaces */ + if (i < 0x454000 && i > 0x5ffff) + BCE_PRINTF("0x%04X: 0x%08X 0x%08X " + "0x%08X 0x%08X\n", i, + REG_RD_IND(sc, i), + REG_RD_IND(sc, i + 0x4), + REG_RD_IND(sc, i + 0x8), + REG_RD_IND(sc, i + 0xC)); + } + } + + BCE_PRINTF( + "----------------------------" + "----------------" + "----------------------------\n"); +} + + +/****************************************************************************/ +/* Prints out the RXP processor state. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static __attribute__ ((noinline)) void +bce_dump_rxp_state(struct bce_softc *sc, int regs) +{ + u32 val; + u32 fw_version[3]; + + BCE_PRINTF( + "----------------------------" + " RXP State " + "----------------------------\n"); + + for (int i = 0; i < 3; i++) + fw_version[i] = htonl(REG_RD_IND(sc, + (BCE_RXP_SCRATCH + 0x10 + i * 4))); + + BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); + + val = REG_RD_IND(sc, BCE_RXP_CPU_MODE); + BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n", + val, BCE_RXP_CPU_MODE); + + val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); + BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", + val, BCE_RXP_CPU_STATE); + + val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK); + BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n", + val, BCE_RXP_CPU_EVENT_MASK); + + if (regs) { + BCE_PRINTF( + "----------------------------" + " Register Dump " + "----------------------------\n"); + + for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) { + /* Skip the big blank sapces */ + if (i < 0xc5400 && i > 0xdffff) + BCE_PRINTF("0x%04X: 0x%08X 0x%08X " + "0x%08X 0x%08X\n", i, + REG_RD_IND(sc, i), + REG_RD_IND(sc, i + 0x4), + REG_RD_IND(sc, i + 0x8), + REG_RD_IND(sc, i + 0xC)); + } + } + + BCE_PRINTF( + "----------------------------" + "----------------" + "----------------------------\n"); +} + + +/****************************************************************************/ +/* Prints out the TPAT processor state. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static __attribute__ ((noinline)) void +bce_dump_tpat_state(struct bce_softc *sc, int regs) +{ + u32 val; + u32 fw_version[3]; + + BCE_PRINTF( + "----------------------------" + " TPAT State " + "----------------------------\n"); + + for (int i = 0; i < 3; i++) + fw_version[i] = htonl(REG_RD_IND(sc, + (BCE_TPAT_SCRATCH + 0x410 + i * 4))); + + BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); + + val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE); + BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n", + val, BCE_TPAT_CPU_MODE); + + val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); + BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", + val, BCE_TPAT_CPU_STATE); + + val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK); + BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n", + val, BCE_TPAT_CPU_EVENT_MASK); + + if (regs) { + BCE_PRINTF( + "----------------------------" + " Register Dump " + "----------------------------\n"); + + for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) { + /* Skip the big blank spaces */ + if (i < 0x854000 && i > 0x9ffff) + BCE_PRINTF("0x%04X: 0x%08X 0x%08X " + "0x%08X 0x%08X\n", i, + REG_RD_IND(sc, i), + REG_RD_IND(sc, i + 0x4), + REG_RD_IND(sc, i + 0x8), + REG_RD_IND(sc, i + 0xC)); + } + } + + BCE_PRINTF( + "----------------------------" + "----------------" + "----------------------------\n"); +} + + +/****************************************************************************/ +/* Prints out the Command Procesor (CP) state. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static __attribute__ ((noinline)) void +bce_dump_cp_state(struct bce_softc *sc, int regs) +{ + u32 val; + u32 fw_version[3]; + + BCE_PRINTF( + "----------------------------" + " CP State " + "----------------------------\n"); + + for (int i = 0; i < 3; i++) + fw_version[i] = htonl(REG_RD_IND(sc, + (BCE_CP_SCRATCH + 0x10 + i * 4))); + + BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); + + val = REG_RD_IND(sc, BCE_CP_CPU_MODE); + BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n", + val, BCE_CP_CPU_MODE); + + val = REG_RD_IND(sc, BCE_CP_CPU_STATE); + BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", + val, BCE_CP_CPU_STATE); + + val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK); + BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val, + BCE_CP_CPU_EVENT_MASK); + + if (regs) { + BCE_PRINTF( + "----------------------------" + " Register Dump " + "----------------------------\n"); + + for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) { + /* Skip the big blank spaces */ + if (i < 0x185400 && i > 0x19ffff) + BCE_PRINTF("0x%04X: 0x%08X 0x%08X " + "0x%08X 0x%08X\n", i, + REG_RD_IND(sc, i), + REG_RD_IND(sc, i + 0x4), + REG_RD_IND(sc, i + 0x8), + REG_RD_IND(sc, i + 0xC)); + } + } + + BCE_PRINTF( + "----------------------------" + "----------------" + "----------------------------\n"); +} + + +/****************************************************************************/ +/* Prints out the Completion Procesor (COM) state. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static __attribute__ ((noinline)) void +bce_dump_com_state(struct bce_softc *sc, int regs) +{ + u32 val; + u32 fw_version[4]; + + BCE_PRINTF( + "----------------------------" + " COM State " + "----------------------------\n"); + + for (int i = 0; i < 3; i++) + fw_version[i] = htonl(REG_RD_IND(sc, + (BCE_COM_SCRATCH + 0x10 + i * 4))); + + BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); + + val = REG_RD_IND(sc, BCE_COM_CPU_MODE); + BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n", + val, BCE_COM_CPU_MODE); + + val = REG_RD_IND(sc, BCE_COM_CPU_STATE); + BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", + val, BCE_COM_CPU_STATE); + + val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK); + BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val, + BCE_COM_CPU_EVENT_MASK); + + if (regs) { + BCE_PRINTF( + "----------------------------" + " Register Dump " + "----------------------------\n"); + + for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) { + BCE_PRINTF("0x%04X: 0x%08X 0x%08X " + "0x%08X 0x%08X\n", i, + REG_RD_IND(sc, i), + REG_RD_IND(sc, i + 0x4), + REG_RD_IND(sc, i + 0x8), + REG_RD_IND(sc, i + 0xC)); + } + } + + BCE_PRINTF( + "----------------------------" + "----------------" + "----------------------------\n"); +} + + +/****************************************************************************/ +/* Prints out the Receive Virtual 2 Physical (RV2P) state. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static __attribute__ ((noinline)) void +bce_dump_rv2p_state(struct bce_softc *sc) +{ + u32 val, pc1, pc2, fw_ver_high, fw_ver_low; + + BCE_PRINTF( + "----------------------------" + " RV2P State " + "----------------------------\n"); + + /* Stall the RV2P processors. */ + val = REG_RD_IND(sc, BCE_RV2P_CONFIG); + val |= BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2; + REG_WR_IND(sc, BCE_RV2P_CONFIG, val); + + /* Read the firmware version. */ + val = 0x00000001; + REG_WR_IND(sc, BCE_RV2P_PROC1_ADDR_CMD, val); + fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); + fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & + BCE_RV2P_INSTR_HIGH_HIGH; + BCE_PRINTF("RV2P1 Firmware version - 0x%08X:0x%08X\n", + fw_ver_high, fw_ver_low); + + val = 0x00000001; + REG_WR_IND(sc, BCE_RV2P_PROC2_ADDR_CMD, val); + fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); + fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & + BCE_RV2P_INSTR_HIGH_HIGH; + BCE_PRINTF("RV2P2 Firmware version - 0x%08X:0x%08X\n", + fw_ver_high, fw_ver_low); + + /* Resume the RV2P processors. */ + val = REG_RD_IND(sc, BCE_RV2P_CONFIG); + val &= ~(BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2); + REG_WR_IND(sc, BCE_RV2P_CONFIG, val); + + /* Fetch the program counter value. */ + val = 0x68007800; + REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); + val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); + pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); + pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; + BCE_PRINTF("0x%08X - RV2P1 program counter (1st read)\n", pc1); + BCE_PRINTF("0x%08X - RV2P2 program counter (1st read)\n", pc2); + + /* Fetch the program counter value again to see if it is advancing. */ + val = 0x68007800; + REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); + val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); + pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); + pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; + BCE_PRINTF("0x%08X - RV2P1 program counter (2nd read)\n", pc1); + BCE_PRINTF("0x%08X - RV2P2 program counter (2nd read)\n", pc2); + + BCE_PRINTF( + "----------------------------" + "----------------" + "----------------------------\n"); +} + + +/****************************************************************************/ +/* Prints out the driver state and then enters the debugger. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static __attribute__ ((noinline)) void +bce_breakpoint(struct bce_softc *sc) +{ + + /* + * Unreachable code to silence compiler warnings + * about unused functions. + */ + if (0) { + bce_freeze_controller(sc); + bce_unfreeze_controller(sc); + bce_dump_enet(sc, NULL); + bce_dump_txbd(sc, 0, NULL); + bce_dump_rxbd(sc, 0, NULL); + bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD); + bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD); + bce_dump_l2fhdr(sc, 0, NULL); + bce_dump_ctx(sc, RX_CID); + bce_dump_ftqs(sc); + bce_dump_tx_chain(sc, 0, USABLE_TX_BD); + bce_dump_rx_bd_chain(sc, 0, USABLE_RX_BD); + bce_dump_status_block(sc); + bce_dump_stats_block(sc); + bce_dump_driver_state(sc); + bce_dump_hw_state(sc); + bce_dump_bc_state(sc); + bce_dump_txp_state(sc, 0); + bce_dump_rxp_state(sc, 0); + bce_dump_tpat_state(sc, 0); + bce_dump_cp_state(sc, 0); + bce_dump_com_state(sc, 0); + bce_dump_rv2p_state(sc); + +#ifdef BCE_JUMBO_HDRSPLIT + bce_dump_pgbd(sc, 0, NULL); + bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD); + bce_dump_pg_chain(sc, 0, USABLE_PG_BD); +#endif + } + + bce_dump_status_block(sc); + bce_dump_driver_state(sc); + + /* Call the debugger. */ + breakpoint(); + + return; +} +#endif + diff --git a/freebsd/dev/bce/if_bcefw.h b/freebsd/dev/bce/if_bcefw.h new file mode 100644 index 00000000..c41ff10a --- /dev/null +++ b/freebsd/dev/bce/if_bcefw.h @@ -0,0 +1,14594 @@ +/*- + * Copyright (c) 2006-2010 Broadcom Corporation + * David Christensen . All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Broadcom Corporation nor the name of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written consent. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * This file contains firmware data derived from proprietary unpublished + * source code, Copyright (c) 2004, 2005, 2007, 2008 Broadcom Corporation. + * + * Permission is hereby granted for the distribution of this firmware data + * in hexadecimal or equivalent format, provided this copyright notice is + * accompanying it. + */ + +/* Firmware release 4.6.17 for BCM5706 and BCM5708 (b06). */ +/* Firmware release 4.6.16 for BCM5709 and BCM5716 (b09). */ +int bce_COM_b06FwReleaseMajor = 0x1; +int bce_COM_b06FwReleaseMinor = 0x0; +int bce_COM_b06FwReleaseFix = 0x0; +u32 bce_COM_b06FwStartAddr = 0x080000f8; +u32 bce_COM_b06FwTextAddr = 0x08000000; +int bce_COM_b06FwTextLen = 0x4df0; +u32 bce_COM_b06FwDataAddr = 0x00000000; +int bce_COM_b06FwDataLen = 0x0; +u32 bce_COM_b06FwRodataAddr = 0x08004df0; +int bce_COM_b06FwRodataLen = 0x14; +u32 bce_COM_b06FwBssAddr = 0x08004e58; +int bce_COM_b06FwBssLen = 0xbc; +u32 bce_COM_b06FwSbssAddr = 0x08004e20; +int bce_COM_b06FwSbssLen = 0x38; +u32 bce_COM_b06FwSDataAddr = 0x00000000; +int bce_COM_b06FwSDataLen = 0x0; +u32 bce_COM_b06FwText[(0x4df0/4) + 1] = { +0xa00003e, 0x0, 0x0, +0xd, 0x636f6d34, 0x2e362e31, 0x37000000, +0x4061102, 0x0, 0x3, 0x14, +0x32, 0x3, 0x0, 0x0, +0x0, 0x0, 0x0, 0x10, +0x136, 0xea60, 0x1, 0x0, +0x0, 0x0, 0x8, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x2, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x10, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x10000003, 0x0, 0xd, 0xd, +0x3c020800, 0x24424e20, 0x3c030800, 0x24634f14, +0xac400000, 0x43202b, 0x1480fffd, 0x24420004, +0x3c1d0800, 0x37bd7ffc, 0x3a0f021, 0x3c100800, +0x261000f8, 0x3c1c0800, 0x279c4e20, 0xe0002bd, +0x0, 0xd, 0x3c036010, 0x8c645000, +0x2402ff7f, 0x3c1a8000, 0x822024, 0x3484380c, +0x24020037, 0xac645000, 0xaf420008, 0x24020c80, +0xaf420024, 0x3c1b8008, 0x3c060800, 0x24c607e8, +0x3c020800, 0x24424e58, 0x2404001b, 0x2484ffff, +0xac460000, 0x481fffd, 0x24420004, 0x3c020800, +0x24420380, 0x3c010800, 0xac224e60, 0x3c020800, +0x24420680, 0x3c010800, 0xac224e64, 0x3c020800, +0x24420dcc, 0x3c010800, 0xac224ea0, 0x3c020800, +0x24420a5c, 0x3c030800, 0x24630954, 0x3c040800, +0x24840990, 0x3c050800, 0x24a53c70, 0x3c010800, +0xac224ea8, 0x3c020800, 0x24420570, 0x3c010800, +0xac264ea4, 0x3c010800, 0xac254eb4, 0x3c010800, +0xac234ebc, 0x3c010800, 0xac224ec0, 0x3c010800, +0xac244ec4, 0x3c010800, 0xac234e5c, 0x3c010800, +0xac204e68, 0x3c010800, 0xac204e6c, 0x3c010800, +0xac204e70, 0x3c010800, 0xac204e74, 0x3c010800, +0xac204e78, 0x3c010800, 0xac204e7c, 0x3c010800, +0xac204e80, 0x3c010800, 0xac244e84, 0x3c010800, +0xac204e88, 0x3c010800, 0xac204e8c, 0x3c010800, +0xac204e90, 0x3c010800, 0xac204e94, 0x3c010800, +0xac204e98, 0x3c010800, 0xac264e9c, 0x3c010800, +0xac204eac, 0x3c010800, 0xac254eb0, 0x3c010800, +0xac234eb8, 0xa000707, 0x0, 0x3c030800, +0x8c630020, 0x8f820008, 0x10430003, 0x0, +0xa00053f, 0xaf830008, 0x3e00008, 0x0, +0x27bdffe8, 0xafb00010, 0xafbf0014, 0x27500100, +0x92020009, 0x1040001a, 0x24030001, 0x3c020800, +0x8c420020, 0x10400016, 0x1821, 0xe000577, +0x0, 0x96030008, 0x3c060800, 0x94c64ed6, +0x8e040018, 0x8f820020, 0x9605000c, 0x31c00, +0x661825, 0xac440000, 0xac450004, 0x24040001, +0xac400008, 0xac40000c, 0xac400010, 0xac400014, +0xac400018, 0xe00059c, 0xac43001c, 0x1821, +0x8fbf0014, 0x8fb00010, 0x601021, 0x3e00008, +0x27bd0018, 0x27bdffe8, 0xafbf0010, 0x97420108, +0x30437000, 0x24022000, 0x1062000a, 0x28642001, +0x54800012, 0x8fbf0010, 0x24024000, 0x10620008, +0x24026000, 0x1062000a, 0x8fbf0010, 0xa0000fb, +0x1021, 0x8fbf0010, 0xa0000bb, 0x27bd0018, +0xe000409, 0x0, 0xa0000fa, 0x8fbf0010, +0xe000fc9, 0x0, 0x8fbf0010, 0x1021, +0x3e00008, 0x27bd0018, 0x3c020800, 0x8c420020, +0x27bdffe8, 0x10400027, 0xafbf0010, 0xe000577, +0x0, 0x97420108, 0x9743010c, 0x8f850020, +0x3042003e, 0x3063ffff, 0x21400, 0x431025, +0xaca20000, 0x8f420100, 0x3c060800, 0x94c64ed6, +0x8fbf0010, 0xaca20004, 0x97430116, 0x9744010e, +0x3c022000, 0x31c00, 0x3084ffff, 0x641825, +0xaca30008, 0xc23025, 0x97420110, 0x97430112, +0x24040001, 0x21400, 0x3063ffff, 0x431025, +0xaca2000c, 0x97420114, 0x27bd0018, 0x3042ffff, +0xaca20010, 0xaca00014, 0xaca00018, 0xa00059c, +0xaca6001c, 0x8fbf0010, 0x3e00008, 0x27bd0018, +0x3c020800, 0x8c420020, 0x27bdffe8, 0x1040002a, +0xafbf0010, 0xe000577, 0x0, 0x97420108, +0x9743010c, 0x8f850020, 0x3042003e, 0x3063ffff, +0x21400, 0x431025, 0xaca20000, 0x8f420100, +0x3c060800, 0x94c64ed6, 0x8fbf0010, 0xaca20004, +0x97430116, 0x9744010e, 0x3c022000, 0x31c00, +0x3084ffff, 0x641825, 0xaca30008, 0xc23025, +0x97420110, 0x97430112, 0x24040001, 0x21400, +0x3063ffff, 0x431025, 0xaca2000c, 0x97420114, +0x27bd0018, 0x3042ffff, 0xaca20010, 0x8f420118, +0xaca20014, 0x9342010b, 0x304200ff, 0xaca20018, +0xa00059c, 0xaca6001c, 0x8fbf0010, 0x3e00008, +0x27bd0018, 0x27bdffe0, 0xafb00010, 0xafbf0018, +0xafb10014, 0x27500100, 0x9203000b, 0x2402001a, +0x96110008, 0x14620035, 0x2021, 0x32220001, +0x10400009, 0x0, 0x8e020000, 0x96030014, +0x211c2, 0x21040, 0x5a1021, 0xa4430080, +0xa000179, 0x32220002, 0xe00012b, 0x0, +0x3c020800, 0x8c420040, 0x24420001, 0x3c010800, +0xac220040, 0x32220002, 0x2202b, 0x3c020800, +0x8c420044, 0x32230004, 0x24420001, 0x3c010800, +0xac220044, 0x1060001a, 0x8fbf0018, 0x8f4202b8, +0x4410008, 0x24040001, 0x3c020800, 0x8c420060, +0x24420001, 0x3c010800, 0xac220060, 0xa00019c, +0x8fb10014, 0x8e020020, 0x96030016, 0x2021, +0xaf420280, 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0x8f820028, +0x3442021, 0x24840940, 0xaf460814, 0xaf85002c, +0xaf840038, 0xac430118, 0x93830040, 0x24020003, +0x1462003b, 0x24020001, 0x24020026, 0x10e2003d, +0x28e20027, 0x10400013, 0x24020032, 0x24020022, +0x10e20038, 0x28e20023, 0x10400008, 0x24020024, +0x24020020, 0x10e20024, 0x24020021, 0x10e2001e, +0x2202021, 0xa001a7f, 0x2402000b, 0x10e2002d, +0x24020025, 0x10e20010, 0x2202021, 0xa001a7f, +0x2402000b, 0x10e2001a, 0x28e20033, 0x10400006, +0x2402003f, 0x24020031, 0x10e2000b, 0x2202021, +0xa001a7f, 0x2402000b, 0x10e20011, 0x2202021, +0xa001a7f, 0x2402000b, 0xe00176c, 0x2202021, +0xa001a9a, 0x408021, 0xe0018ee, 0x2202021, +0xa001a9a, 0x408021, 0xe00198f, 0x2202021, +0xa001a9a, 0x408021, 0x1509000e, 0x0, +0xe001813, 0x2202021, 0xa001a9a, 0x408021, +0xe00158b, 0xa382004c, 0xa001a9a, 0x408021, +0x14620017, 0x2002021, 0x24020023, 0x14e20005, +0x2402000b, 0xe001885, 0x2202021, 0xa001a9a, +0x408021, 0x2202021, 0xa382004c, 0xe00158b, +0x2410ffff, 0xa001a9b, 0x2002021, 0x30a500ff, +0xe001489, 0x24060001, 0x97830042, 0x8f820044, +0xa7800042, 0x431023, 0xaf820044, 0x2002021, +0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x801021, +0x3e00008, 0x27bd0020, 0x27bdffe0, 0xafb10014, +0xafbf0018, 0xafb00010, 0x8f460128, 0x3c030800, +0x8c6331a0, 0x2402ff80, 0xaf860050, 0xc31821, +0x3065007f, 0x3452821, 0x621824, 0x3c02000a, +0xaf430024, 0xa22821, 0x90a20062, 0x808821, +0xaf850028, 0x304200ff, 0x21102, 0xa3820040, +0x90a200bc, 0x30420002, 0x14400002, 0x24030034, +0x24030030, 0x8f820028, 0xa3830030, 0x93830040, +0x8c4200c0, 0xa380004c, 0xaf820044, 0x24020004, +0x10620030, 0x8f840044, 0x8e240004, 0x5080002d, +0x8f840044, 0x8e220010, 0x3083ffff, 0xa7840042, +0x1060001f, 0xaf820048, 0x8f830028, 0x2405ff80, +0x2202021, 0x90620063, 0xa21024, 0x304200ff, +0x1440000d, 0x0, 0xe001a06, 0x97900042, +0x10400010, 0x401821, 0x2402fffd, 0x54620011, +0x8e230020, 0x2002821, 0xe00142a, 0x2202021, +0xa001aec, 0x8e230020, 0x90620063, 0xa21024, +0x304200ff, 0x10400003, 0x2202021, 0xe00174e, +0x0, 0x97820042, 0x1440ffe4, 0x8f830028, +0x8e230020, 0x30620004, 0x10400006, 0x8f840044, +0x2402fffb, 0x621024, 0xe00143e, 0xae220020, +0x8f840044, 0x8f830028, 0x8fbf0018, 0x8fb10014, +0x8fb00010, 0x24020001, 0x27bd0020, 0x3e00008, +0xac6400c0, 0x30a500ff, 0x24030001, 0x24a90001, +0x69102b, 0x1040000c, 0x4021, 0x240a0001, +0xa31023, 0x4a3804, 0x24630001, 0x30820001, +0x69302b, 0x10400002, 0x42042, 0x1074025, +0x54c0fff8, 0xa31023, 0x3e00008, 0x1001021, +0x27bdffe0, 0x3c021edc, 0xafb20018, 0xafb10014, +0xafbf001c, 0xafb00010, 0x34526f41, 0x8821, +0x24050008, 0xe001afc, 0x2202021, 0x118080, +0x3c070800, 0x24e77194, 0x21600, 0x2071821, +0xac620000, 0x2821, 0x24a20001, 0x3045ffff, +0x8c620000, 0x2ca60008, 0x4410002, 0x22040, +0x922026, 0x14c0fff8, 0xac640000, 0x2078021, +0x8e040000, 0xe001afc, 0x24050020, 0x26230001, +0x3071ffff, 0x2e230100, 0x1460ffe5, 0xae020000, +0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, +0x3e00008, 0x27bd0020, 0x3c020800, 0x24426a84, +0x3c010800, 0xac227188, 0x3c020800, 0x24425000, +0x3c010800, 0xac22718c, 0x24020006, 0x3c010800, +0xa0227190, 0xa001b0f, 0x0, 0x27bdffd8, +0xafb3001c, 0xafb20018, 0xafbf0020, 0xafb10014, +0xafb00010, 0x8f510140, 0x8f480148, 0x89402, +0x324300ff, 0x311300ff, 0x8f4201b8, 0x440fffe, +0x27500180, 0xae110000, 0x8f420144, 0xae020004, +0x24020002, 0xa6120008, 0xa202000b, 0x24020014, +0xae130024, 0x10620025, 0x28620015, 0x10400008, +0x24020015, 0x24020010, 0x10620030, 0x24020012, +0x10620009, 0x8fbf0020, 0xa001c30, 0x8fb3001c, +0x10620067, 0x24020022, 0x10620037, 0x8fbf0020, +0xa001c30, 0x8fb3001c, 0x3c020800, 0x8c4231a0, +0x2403ff80, 0x2221021, 0x431024, 0xaf420024, +0x3c020800, 0x8c4231a0, 0x2221021, 0x3042007f, +0x3421821, 0x3c02000a, 0x621821, 0x166000b3, +0xaf830028, 0x90620062, 0x3042000f, 0x34420030, +0xa0620062, 0xa001c2f, 0x8fbf0020, 0x3c046000, +0x8c832c08, 0x3c02f003, 0x3442ffff, 0x621824, +0xac832c08, 0x3c020800, 0x8c4231a0, 0x8c832c08, +0x24420074, 0x21082, 0x21480, 0x621825, +0xac832c08, 0xa001c2f, 0x8fbf0020, 0x3c020800, +0x8c4231a0, 0x2403ff80, 0x2221021, 0x431024, +0xaf420024, 0x3c020800, 0x8c4231a0, 0x3c03000a, +0x2221021, 0x3042007f, 0x3421021, 0x431021, +0xa001c2e, 0xaf820028, 0x3c020800, 0x8c4231a0, +0x2404ff80, 0x2221021, 0x441024, 0xaf420024, +0x3c020800, 0x8c4231a0, 0x2221021, 0x3042007f, +0x3421821, 0x3c02000a, 0x621821, 0x90620063, +0x821024, 0x304200ff, 0x1040007c, 0xaf830028, +0x24620088, 0x94430012, 0x3c020800, 0x8c4231a8, +0x30633fff, 0x31980, 0x2221021, 0x431021, +0x3043007f, 0x3431821, 0x441024, 0x3c04000c, +0x641821, 0xaf420028, 0xe00155a, 0xaf83002c, +0x8f4201b8, 0x440fffe, 0x0, 0xae110000, +0x8f420144, 0xae020004, 0x24020002, 0xa6120008, +0xa202000b, 0xae130024, 0xa001c2f, 0x8fbf0020, +0x2406ff80, 0x2261024, 0xaf420020, 0x3c020800, +0x8c4231a0, 0x31043fff, 0x42180, 0x2221021, +0x461024, 0xaf420024, 0x3c030800, 0x8c6331a8, +0x3c020800, 0x8c4231a0, 0x3227007f, 0x2231821, +0x2221021, 0x641821, 0x3042007f, 0x3064007f, +0x3422821, 0x3c02000a, 0x661824, 0xa22821, +0x3442021, 0x3c02000c, 0x822021, 0xaf430028, +0x3c020008, 0x3471821, 0x629021, 0xaf850028, +0xaf84002c, 0xe00155a, 0x1008021, 0x8f4201b8, +0x440fffe, 0x8f82002c, 0x8f840028, 0x27450180, +0x9042000d, 0xacb10000, 0xa4b00006, 0x21600, +0x21603, 0x21027, 0x237c2, 0x14c00016, +0x24820088, 0x94420012, 0x32033fff, 0x30423fff, +0x14430012, 0x24026082, 0x90830063, 0x2402ff80, +0x431024, 0x304200ff, 0x5040000c, 0x24026082, +0x90820062, 0x3042000f, 0x34420040, 0xa0820062, +0x24026084, 0xa4a20008, 0x2402000d, 0xa0a20005, +0xa001c19, 0x3c022700, 0x24026082, 0xa4a20008, +0xa0a00005, 0x3c022700, 0x61c00, 0x621825, +0x24020002, 0xa0a2000b, 0xaca30010, 0xaca00014, +0xaca00024, 0xaca00028, 0xaca0002c, 0x8e42004c, +0x8f84002c, 0xaca20018, 0x9083000d, 0x2402ff80, +0x431024, 0x304200ff, 0x10400005, 0x8fbf0020, +0x9082000d, 0x3042007f, 0xa082000d, 0x8fbf0020, +0x8fb3001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, +0x3c021000, 0x27bd0028, 0x3e00008, 0xaf4201b8, +0x0 }; +u32 bce_RXP_b06FwData[(0x0/4) + 1] = { 0x0 }; +u32 bce_RXP_b06FwRodata[(0x24/4) + 1] = { +0x8004c28, +0x8004c28, 0x8004ba0, 0x8004bd8, 0x8004c0c, +0x8004c30, 0x8004c30, 0x8004c30, 0x8004b10, +0x0 }; +u32 bce_RXP_b06FwBss[(0x450/4) + 1] = { 0x0 }; +u32 bce_RXP_b06FwSbss[(0x54/4) + 1] = { 0x0 }; +u32 bce_RXP_b06FwSdata[(0x0/4) + 1] = { 0x0 }; + + +int bce_TPAT_b06FwReleaseMajor = 0x1; +int bce_TPAT_b06FwReleaseMinor = 0x0; +int bce_TPAT_b06FwReleaseFix = 0x0; +u32 bce_TPAT_b06FwStartAddr = 0x08000488; +u32 bce_TPAT_b06FwTextAddr = 0x08000400; +int bce_TPAT_b06FwTextLen = 0x175c; +u32 bce_TPAT_b06FwDataAddr = 0x00000000; +int bce_TPAT_b06FwDataLen = 0x0; +u32 bce_TPAT_b06FwRodataAddr = 0x00000000; +int bce_TPAT_b06FwRodataLen = 0x0; +u32 bce_TPAT_b06FwBssAddr = 0x08001bc4; +int bce_TPAT_b06FwBssLen = 0x450; +u32 bce_TPAT_b06FwSbssAddr = 0x08001b80; +int bce_TPAT_b06FwSbssLen = 0x44; +u32 bce_TPAT_b06FwSDataAddr = 0x00000000; +int bce_TPAT_b06FwSDataLen = 0x0; +u32 bce_TPAT_b06FwText[(0x175c/4) + 1] = { +0xa000122, 0x0, 0x0, +0xd, 0x74706134, 0x2e362e31, 0x37000000, +0x4061101, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x10000003, 0x0, 0xd, 0xd, +0x3c020800, 0x24421b80, 0x3c030800, 0x24632014, +0xac400000, 0x43202b, 0x1480fffd, 0x24420004, +0x3c1d0800, 0x37bd2ffc, 0x3a0f021, 0x3c100800, +0x26100488, 0x3c1c0800, 0x279c1b80, 0xe00015a, +0x0, 0xd, 0x3084ffff, 0x30820007, +0x8f850018, 0x10400002, 0x24830007, 0x3064fff8, +0x853021, 0x30c41fff, 0x3441821, 0x247b4000, +0xaf85001c, 0xaf840018, 0x3e00008, 0xaf440084, +0x3084ffff, 0x30820007, 0x8f850020, 0x8f860028, +0x10400002, 0x24830007, 0x3064fff8, 0x852021, +0x86182b, 0x14600002, 0xaf850024, 0x862023, +0x3442821, 0x34068000, 0xaf840020, 0xaf440080, +0xa62021, 0x3e00008, 0xaf840038, 0x27bdffd8, +0xafb3001c, 0xafb20018, 0xafb00010, 0xafbf0024, +0xafb40020, 0xafb10014, 0x3c086008, 0x8d145000, +0x2418ff7f, 0x3c1a8000, 0x2989824, 0x3672380c, +0xad125000, 0x8f510008, 0x3c07601c, 0x3c086000, +0x36300001, 0xaf500008, 0xaf800018, 0xaf400080, +0xaf400084, 0x8ce60008, 0x8d0f0808, 0x3c076016, +0x8cec0000, 0x31eefff0, 0x39ca0010, 0x3c0dffff, +0x340b8000, 0x3c030080, 0x34b4821, 0x2d440001, +0x18d2824, 0x3c025353, 0x3c010800, 0xac230420, +0xaf890038, 0xaf860028, 0xaf840010, 0x275b4000, +0x14a20003, 0x34e37c00, 0x8cf90004, 0x3281821, +0x8c7f007c, 0x8c650078, 0x3c028000, 0x34520070, +0xaf85003c, 0xaf9f0040, 0x3c130800, 0x26731bc4, +0x240a021, 0x8e480000, 0x8f460000, 0x38c30001, +0x30640001, 0x10800017, 0xaf880034, 0x2804821, +0x8d2d0000, 0x3c190800, 0x8f39045c, 0x3c110800, +0x8e310458, 0x1a8f823, 0x33f7821, 0x4021, +0x2283821, 0x1ff802b, 0xf07021, 0x3c010800, +0xac2f045c, 0x3c010800, 0xac2e0458, 0x8f4c0000, +0x398b0001, 0x316a0001, 0x1540ffed, 0x1a04021, +0xaf8d0034, 0x8e4e0000, 0x3c0c0800, 0x8d8c045c, +0x3c0a0800, 0x8d4a0458, 0x1c86823, 0x18d2821, +0x5821, 0xad302b, 0x14b2021, 0x861021, +0x3c010800, 0xac25045c, 0x3c010800, 0xac220458, +0x8f450108, 0x8f440100, 0x30a92000, 0xaf850000, +0xaf84000c, 0x1120000a, 0xa03021, 0x3c070800, +0x8ce7042c, 0x24ef0001, 0x3c010800, 0xac2f042c, +0x3c104000, 0xaf500138, 0xa000190, 0x0, +0x30b00200, 0x16000014, 0x24110f00, 0x10910012, +0x24070d00, 0x10870233, 0x30b00006, 0x5200fff5, +0x3c104000, 0x936d0000, 0x240c0010, 0x31a600f0, +0x10cc0269, 0x240e0070, 0x10ce02dd, 0x8f8b0014, +0x25670001, 0xaf870014, 0x3c104000, 0xaf500138, +0xa000190, 0x0, 0x97480104, 0x1100ffe5, +0x3c104000, 0x30b84000, 0x170000a2, 0x0, +0x8f590178, 0x720fffe, 0x8f870038, 0x24090008, +0x24050800, 0x8ce30008, 0xaf450178, 0xa7490140, +0xa7400142, 0x97420104, 0x8f860000, 0x3049ffff, +0x30df0001, 0x13e002d5, 0x1204021, 0x2524fffe, +0x240a0002, 0xa74a0146, 0x3088ffff, 0xa7440148, +0x3c0b0800, 0x8d6b043c, 0x156002c4, 0x8f8f000c, +0x30c30020, 0x14600002, 0x24040009, 0x24040001, +0x30cd0c00, 0x240c0400, 0x51ac0001, 0x34840004, +0xa744014a, 0x3c050800, 0x8ca50420, 0x3c020048, +0x3c190001, 0xa2f825, 0x30d80002, 0x3f92825, +0x13000004, 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+0x148fffc9, 0x0, 0x97420104, 0x960b0002, +0x3c050800, 0x8ca5046c, 0x3049ffff, 0x316affff, +0x3c110800, 0x8e310468, 0x12a3821, 0x24f2fffe, +0xb24021, 0x12ffc3, 0x112c82b, 0x23fc021, +0x3192021, 0x3c010800, 0xac28046c, 0x3c010800, +0xac240468, 0xa00064d, 0x0, 0xa4102b, +0x10400009, 0x24030001, 0x52840, 0xa4102b, +0x4a00003, 0x31840, 0x5440fffc, 0x52840, +0x10600007, 0x0, 0x85302b, 0x14c00002, +0x31842, 0x852023, 0x1460fffb, 0x52842, +0x3e00008, 0x801021, 0x8f85002c, 0x27bdffe8, +0x53027, 0x2cc30001, 0x2ca40002, 0x831025, +0x10400003, 0xafbf0010, 0x2405007f, 0xaf85002c, +0x52827, 0x30a5ffff, 0xe000574, 0x240426f5, +0x8f830030, 0x240402bd, 0x403021, 0x83382b, +0x10e00009, 0x24050001, 0x42040, 0x83102b, +0x4800003, 0x52840, 0x5440fffc, 0x42040, +0x10a00008, 0xc35021, 0x64402b, 0x15000002, +0x52842, 0x641823, 0x14a0fffb, 0x42042, +0xc35021, 0x8fbf0010, 0xa4c02, 0x312200ff, +0x27bd0018, 0xaf8a002c, 0x3e00008, 0xaf890030, +0x0 }; +u32 bce_TPAT_b06FwData[(0x0/4) + 1] = { 0x0 }; +u32 bce_TPAT_b06FwRodata[(0x0/4) + 1] = { 0x0 }; +u32 bce_TPAT_b06FwBss[(0x450/4) + 1] = { 0x0 }; +u32 bce_TPAT_b06FwSbss[(0x44/4) + 1] = { 0x0 }; +u32 bce_TPAT_b06FwSdata[(0x0/4) + 1] = { 0x0 }; + + +int bce_TXP_b06FwReleaseMajor = 0x1; +int bce_TXP_b06FwReleaseMinor = 0x0; +int bce_TXP_b06FwReleaseFix = 0x0; +u32 bce_TXP_b06FwStartAddr = 0x08000098; +u32 bce_TXP_b06FwTextAddr = 0x08000000; +int bce_TXP_b06FwTextLen = 0x3a74; +u32 bce_TXP_b06FwDataAddr = 0x00000000; +int bce_TXP_b06FwDataLen = 0x0; +u32 bce_TXP_b06FwRodataAddr = 0x00000000; +int bce_TXP_b06FwRodataLen = 0x0; +u32 bce_TXP_b06FwBssAddr = 0x08003b08; +int bce_TXP_b06FwBssLen = 0x14c; +u32 bce_TXP_b06FwSbssAddr = 0x08003aa0; +int bce_TXP_b06FwSbssLen = 0x68; +u32 bce_TXP_b06FwSDataAddr = 0x00000000; +int bce_TXP_b06FwSDataLen = 0x0; +u32 bce_TXP_b06FwText[(0x3a74/4) + 1] = { +0xa000026, 0x0, 0x0, +0xd, 0x74787034, 0x2e362e31, 0x37000000, +0x4061100, 0xa, 0x136, 0xea60, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x1d, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x10000003, 0x0, 0xd, 0xd, +0x3c020800, 0x24423aa0, 0x3c030800, 0x24633c54, +0xac400000, 0x43202b, 0x1480fffd, 0x24420004, +0x3c1d0800, 0x37bd7ffc, 0x3a0f021, 0x3c100800, +0x26100098, 0x3c1c0800, 0x279c3aa0, 0xe000305, +0x0, 0xd, 0x8f830038, 0x3c088000, +0x35070070, 0x8ce50000, 0x833025, 0x3c029000, +0xc22025, 0xaf850030, 0xaf440020, 0x8f490020, +0x520fffe, 0x3c038000, 0x34620070, 0x8c450000, +0x8f860030, 0x3c190800, 0x8f39007c, 0x3c0e0800, +0x8dce0078, 0xa62023, 0x3245821, 0x7821, +0x164682b, 0x1cf6021, 0x18d5021, 0x3c010800, +0xac2b007c, 0x3c010800, 0xac2a0078, 0x3e00008, +0x0, 0xa00003d, 0x24040001, 0x8f840038, +0x3c058000, 0x34a20001, 0x821825, 0x3e00008, +0xaf430020, 0x3e00008, 0x1021, 0x3084ffff, +0x30a5ffff, 0x10800007, 0x1821, 0x30820001, +0x10400002, 0x42042, 0x651821, 0x1480fffb, +0x52840, 0x3e00008, 0x601021, 0x10c00007, +0x0, 0x8ca20000, 0x24c6ffff, 0x24a50004, +0xac820000, 0x14c0fffb, 0x24840004, 0x3e00008, +0x0, 0x10a00008, 0x24a3ffff, 0xac860000, +0x0, 0x0, 0x2402ffff, 0x2463ffff, +0x1462fffa, 0x24840004, 0x3e00008, 0x0, +0x308affff, 0x93a80013, 0xa74a0144, 0x97490e16, +0x30c600ff, 0x3c021000, 0xa7490146, 0xaf450148, +0xa3460152, 0xa748015a, 0xaf470160, 0x8fa40018, +0x8fa30014, 0xa7440158, 0xaf430154, 0x3e00008, +0xaf420178, 0x3e00008, 0x0, 0x3c038000, +0x34620070, 0x8c490000, 0x8f88003c, 0x24840007, +0x27bdfff8, 0x3084fff8, 0xaf890030, 0x974d008a, +0x31acffff, 0xafac0000, 0x8fab0000, 0x1685023, +0x2547ffff, 0x30e61fff, 0xc4282b, 0x14a0fff7, +0x3c0c8000, 0x358b0070, 0x8d6a0000, 0x3c070800, +0x8ce70084, 0x3c060800, 0x8cc60080, 0x81082, +0x1491823, 0x27880, 0xe37021, 0x2021, +0x1c3c82b, 0xc4c021, 0x1fa4021, 0x3194821, +0x25024000, 0x27bd0008, 0x3c010800, 0xac2e0084, +0x3c010800, 0xac290080, 0x3e00008, 0x0, +0x8f82003c, 0x24860007, 0x30c5fff8, 0xa21821, +0x30641fff, 0x3e00008, 0xaf84003c, 0x3c0e20ff, +0x27bdffe0, 0x3c1a8000, 0x3c0f8008, 0x35cdfffd, +0xafbf0018, 0xafb10014, 0xafb00010, 0xaf8f0044, +0xaf4d0e00, 0x0, 0x0, 0x0, +0x0, 0x0, 0x3c0c00ff, 0x358bfffd, +0xaf4b0e00, 0x3c066004, 0x8cc95000, 0x240aff7f, +0x3c116000, 0x12a4024, 0x3507380c, 0xacc75000, +0x8e240438, 0x24050009, 0xaf450008, 0x3083ffff, +0x38622f71, 0x2450c0b3, 0xaf80004c, 0xe000064, +0xaf80003c, 0x52000001, 0xae20442c, 0xe000460, +0x0, 0x8fbf0018, 0x8fb10014, 0x8fb00010, +0xa000e77, 0x27bd0020, 0x27bdffd0, 0xafb20028, +0xafb10024, 0xafbf002c, 0xafb00020, 0x93620008, +0x809021, 0xa08821, 0x1440002d, 0x24040010, +0xe00009a, 0x0, 0x8f8e004c, 0x3c103200, +0x31c600ff, 0x67c00, 0x1f06025, 0x25cd0001, +0xaf8d004c, 0xac4c0000, 0x936b0009, 0x9369000a, +0x316a00ff, 0xa3c00, 0x312800ff, 0xe82025, +0xac440004, 0x8f83004c, 0x6400043, 0xac430008, +0xac40000c, 0x97980040, 0x33050008, 0x14a00002, +0x26280006, 0x26280002, 0x97420e14, 0x8f450e1c, +0x8f670004, 0x937f0002, 0x3044ffff, 0x33f900ff, +0xafb90010, 0x8f710014, 0xafa80018, 0xe000087, +0xafb10014, 0x8fbf002c, 0x8fb20028, 0x8fb10024, +0x8fb00020, 0x24040010, 0xa0000c3, 0x27bd0030, +0x93690009, 0x9368000b, 0x312300ff, 0x310200ff, +0x628021, 0x261f000a, 0x33f0ffff, 0xe00009a, +0x2002021, 0x8f86004c, 0x3c0d4100, 0x24d90001, +0xaf99004c, 0x93780009, 0x30c600ff, 0x67400, +0x330500ff, 0x24af0002, 0x1cf6025, 0x18d5825, +0xac4b0000, 0x8f6a000c, 0x97440e14, 0x1523825, +0xac470004, 0x8f450e1c, 0x8f670004, 0x93690002, +0x3084ffff, 0x312800ff, 0xafa80010, 0x8f630014, +0xafb10018, 0xe000087, 0xafa30014, 0x2002021, +0x8fbf002c, 0x8fb20028, 0x8fb10024, 0x8fb00020, +0xa0000c3, 0x27bd0030, 0x3c128000, 0xa000114, +0xac52000c, 0x27bdffd8, 0xafb3001c, 0xafbf0020, +0xafb20018, 0xafb10014, 0xafb00010, 0x93620008, +0x14400081, 0x809821, 0xaf60000c, 0x97850040, +0x30a44000, 0x1080008b, 0x24030016, 0x24104007, +0xa363000a, 0xaf700014, 0x938f0042, 0x8f6c0014, +0x31ee0007, 0xe6a40, 0x18d5825, 0xaf6b0014, +0x978a0040, 0x8f680014, 0x31490010, 0x1093825, +0xaf670014, 0x97860040, 0x30c30008, 0x5060008d, +0x2821, 0x8f660014, 0x3c031000, 0x3c028100, +0xc32825, 0xaf650014, 0x97440e0a, 0x2418000e, +0x3405fffc, 0x309fffff, 0x3e2c825, 0xaf790004, +0xa3780002, 0x9372000a, 0x26510004, 0xa371000a, +0x97830040, 0x9364000a, 0x30661f00, 0x61183, +0x44f821, 0x27f90028, 0xa3790009, 0x97580e0c, +0xa7780010, 0x93720009, 0x26510002, 0x32300007, +0x107823, 0x31ee0007, 0xa36e000b, 0x936d0009, +0x976c0010, 0x8f900034, 0x97890040, 0x31ab00ff, +0x16c5021, 0x1454021, 0x31270040, 0x10e00005, +0x3105ffff, 0xb0382b, 0x3c068000, 0x10e00014, +0x8821, 0x205402b, 0x15000033, 0x2021, +0x8f4a0e14, 0xaf4a0e10, 0x8f490e1c, 0xaf490e18, +0xaf450e00, 0x8f4c0000, 0x318b0008, 0x1160fffd, +0x0, 0x974d0e08, 0xa08021, 0x3021, +0xa78d0040, 0x8f450e04, 0x24110001, 0xaf850034, +0x976e0010, 0x31d2ffff, 0x8e640000, 0x901023, +0x14400009, 0xae620000, 0x8f6a0014, 0x8f870048, +0x35490040, 0xaf690014, 0x8f480e10, 0xace80020, +0x8f430e18, 0xace30024, 0xc02021, 0xe0000f5, +0x2002821, 0x8e660000, 0x14c00005, 0x0, +0x8f6b0014, 0x240cffbf, 0x16c9824, 0xaf730014, +0x8f6d000c, 0x1b22821, 0xaf65000c, 0x93720008, +0x16400003, 0x0, 0x16200031, 0x0, +0xa3710008, 0x2002021, 0x8fbf0020, 0x8fb3001c, +0x8fb20018, 0x8fb10014, 0x8fb00010, 0x801021, +0x3e00008, 0x27bd0028, 0x8f900034, 0x97910040, +0x3c068000, 0x2009021, 0x322f0040, 0x15e0ffd2, +0x8821, 0x977f0010, 0x8f980034, 0x33f9ffff, +0x1738ffed, 0x2021, 0x3021, 0xa0001b9, +0x24110001, 0x2403000e, 0x24104007, 0xa363000a, +0xaf700014, 0x938f0042, 0x8f6c0014, 0x31ee0007, +0xe6a40, 0x18d5825, 0xaf6b0014, 0x978a0040, +0x8f680014, 0x31490010, 0x1093825, 0xaf670014, +0x97860040, 0x30c30008, 0x1460ff76, 0x0, +0x2821, 0xaf600004, 0xa000187, 0xa3600002, +0x8f6f0014, 0x3c19efff, 0x3738fffe, 0x1f87024, +0xa0001d7, 0xaf6e0014, 0x8f870038, 0x8f8a0044, +0x27bdffe0, 0x8f860048, 0xafb00018, 0xafbf001c, +0x8f450104, 0x8d4900ac, 0xaf470080, 0x8cc80020, +0xa93823, 0x8021, 0xaf480e10, 0x8f440e10, +0x4821, 0xaf440e14, 0x8cc20024, 0xaf420e18, +0x8f430e18, 0xaf430e1c, 0x10e00036, 0x2d390001, +0x936b0008, 0x1160004f, 0x0, 0x976e0010, +0x31cdffff, 0xed602b, 0x1580004a, 0x0, +0x97780010, 0x330fffff, 0xaf4f0e00, 0x8f5f0000, +0x33f90008, 0x1320fffd, 0x0, 0x97420e08, +0x8f460e04, 0x3045ffff, 0x30a30001, 0x1060008a, +0x0, 0xd, 0x30a8a040, 0x24040040, +0x1104003b, 0x30a9a000, 0x11200085, 0x0, +0x936c0008, 0x51800009, 0x27a40010, 0x976f0010, +0x31eeffff, 0xce682b, 0x11a00004, 0x27a40010, +0x30b80040, 0x1300007a, 0x0, 0xafa70010, +0xa7850040, 0xaf860034, 0xe000158, 0x0, +0x404821, 0x1440ffd0, 0x8fa70010, 0x8f420e14, +0x8f840048, 0xac820020, 0x8f470e1c, 0xac870024, +0x2d390001, 0x3303025, 0x10c00017, 0x8fbf001c, +0x8f840038, 0x24100f00, 0x10900085, 0x0, +0x8f4f0178, 0x5e0fffe, 0x24180f00, 0x1098006f, +0x0, 0x8f470e14, 0x24020240, 0x3c101000, +0xaf470144, 0x8f490e1c, 0xaf490148, 0xa3400152, +0xa740015a, 0xaf400160, 0xa7400158, 0xaf420154, +0xaf500178, 0x8fbf001c, 0x8fb00018, 0x3e00008, +0x27bd0020, 0xaf470e00, 0xa00022e, 0x0, +0x8f490178, 0x520fffe, 0x240a0800, 0x8f84003c, +0xaf4a0178, 0x9758008a, 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0x240b0001, 0x4821, 0x240a0001, +0x3c088000, 0x35070070, 0x8ce30000, 0xaf830030, +0x8f4c0178, 0x580fffe, 0x3c0e8000, 0x3c040800, +0x90843b6c, 0x35c70070, 0x8cec0000, 0x3c050800, +0x8ca50074, 0xa3a40003, 0x3c190800, 0x8f390070, +0x8fad0000, 0x1833023, 0xa63821, 0x1021, +0x3227821, 0xe6c02b, 0x1f86021, 0x1ae4025, +0xafa80000, 0x3c010800, 0xac270074, 0x3c010800, +0xac2c0070, 0x9346010a, 0x3c040800, 0x90843b6d, +0xa3a00002, 0xa3a60001, 0x8fa30000, 0x3c0580ff, +0x3099007f, 0x34a2ffff, 0x627824, 0x19c600, +0x1f87025, 0x240d3000, 0xaf4e014c, 0x27bd0008, +0xaf4d0154, 0xa7400158, 0xaf4b0148, 0xa7490144, +0xa74a0146, 0x3c091000, 0x240aff80, 0xa34a0152, +0x3e00008, 0xaf490178, 0x8f4b0e18, 0x97460e12, +0x97450e10, 0x30caffff, 0xa000e2f, 0x30a9ffff, +0x8f850018, 0x24020080, 0x90a40085, 0x308300c0, +0x10620005, 0x8f86001c, 0x8f880004, 0x8f870008, +0xacc800c8, 0xacc700c4, 0x3e00008, 0x0, +0x3c0a0800, 0x254a37cc, 0x3c090800, 0x25293898, +0x3c080800, 0x25082c4c, 0x3c070800, 0x24e739ac, +0x3c060800, 0x24c6363c, 0x3c050800, 0x24a533b4, +0x3c040800, 0x24842fdc, 0x3c030800, 0x246336d4, +0x3c020800, 0x244234a8, 0x3c010800, 0xac2a3c38, +0x3c010800, 0xac293c34, 0x3c010800, 0xac283c30, +0x3c010800, 0xac273c3c, 0x3c010800, 0xac263c4c, +0x3c010800, 0xac253c44, 0x3c010800, 0xac243c40, +0x3c010800, 0xac233c50, 0x3c010800, 0xac223c48, +0x3e00008, 0x0, 0x0 }; +u32 bce_TXP_b06FwData[(0x0/4) + 1] = { 0x0 }; +u32 bce_TXP_b06FwRodata[(0x0/4) + 1] = { 0x0 }; +u32 bce_TXP_b06FwBss[(0x14c/4) + 1] = { 0x0 }; +u32 bce_TXP_b06FwSbss[(0x68/4) + 1] = { 0x0 }; +u32 bce_TXP_b06FwSdata[(0x0/4) + 1] = { 0x0 }; + + +int bce_CP_b06FwReleaseMajor = 0x1; +int bce_CP_b06FwReleaseMinor = 0x0; +int bce_CP_b06FwReleaseFix = 0x0; +u32 bce_CP_b06FwStartAddr = 0x08000080; +u32 bce_CP_b06FwTextAddr = 0x08000000; +int bce_CP_b06FwTextLen = 0x56cc; +u32 bce_CP_b06FwDataAddr = 0x08005820; +int bce_CP_b06FwDataLen = 0x84; +u32 bce_CP_b06FwRodataAddr = 0x080056cc; +int bce_CP_b06FwRodataLen = 0x134; +u32 bce_CP_b06FwBssAddr = 0x08005998; +int bce_CP_b06FwBssLen = 0x5d8; +u32 bce_CP_b06FwSbssAddr = 0x080058a4; +int bce_CP_b06FwSbssLen = 0xf1; +u32 bce_CP_b06FwSDataAddr = 0x00000000; +int bce_CP_b06FwSDataLen = 0x0; +u32 bce_CP_b06FwText[(0x56cc/4) + 1] = { +0xa000020, 0x0, 0x0, +0xd, 0x6370342e, 0x362e3137, 0x0, +0x4061104, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x20, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x1, +0x2b, 0x0, 0x10000003, 0x0, +0xd, 0xd, 0x3c020800, 0x244258a4, +0x3c030800, 0x24635f70, 0xac400000, 0x43202b, +0x1480fffd, 0x24420004, 0x3c1d0800, 0x37bd7ffc, +0x3a0f021, 0x3c100800, 0x26100080, 0x3c1c0800, +0x279c58a4, 0xe00019c, 0x0, 0xd, +0x27bdffe8, 0x3c096018, 0xafbf0010, 0x8d2c5000, +0x240dff7f, 0x24080031, 0x18d5824, 0x356a380c, +0x24070c00, 0x3c1a8000, 0xad2a5000, 0x3c04800a, +0xaf480008, 0x3c1b8008, 0xaf470024, 0xe000924, +0xaf840010, 0xe0008e7, 0x0, 0xe000834, +0x0, 0xe00125e, 0x0, 0x3c046016, +0x8c850000, 0x3c06ffff, 0x3c025353, 0xa61824, +0x1062003f, 0x34867c00, 0x94c201f2, 0xa780002c, +0x10400003, 0xa78000cc, 0x38581e1e, 0xa798002c, +0x94c201f8, 0x10400004, 0x978300cc, 0x38591e1e, +0xa79900cc, 0x978300cc, 0x2c7f0067, 0x53e00001, +0x24030066, 0x9784002c, 0x2c820401, 0x14400002, +0x602821, 0x24040400, 0x3c076000, 0x8ce90438, +0x2403103c, 0x3128ffff, 0x11030017, 0x30b9ffff, +0x5720000c, 0xa38000ce, 0x24020050, 0xa38200ce, +0x939f00ce, 0x13e0000a, 0x8fbf0010, 0x27bd0018, +0xa78000cc, 0xa780002c, 0xa7800034, 0x3e00008, +0xa78000e6, 0x939f00ce, 0x17e0fff8, 0x8fbf0010, +0x27bd0018, 0xa78500cc, 0xa784002c, 0xa7800034, +0x3e00008, 0xa78000e6, 0xa38000ce, 0x8ccb003c, +0x316a0001, 0x1140000e, 0x0, 0x30a7ffff, +0x10e0ffe6, 0x24020050, 0x8ccc00c8, 0x31860001, +0x14c0ffe4, 0x939f00ce, 0xa000072, 0x24020051, +0x8c8f0004, 0x3c0e6000, 0xa000055, 0x1ee3021, +0x8cef0808, 0x240d5708, 0xf7402, 0x11cd0004, +0x30b8ffff, 0x24050066, 0xa000073, 0x24040400, +0x1700ffd4, 0x939f00ce, 0xa000072, 0x24020050, +0x8f860010, 0x3089ffff, 0x93940, 0x8cc30010, +0x3c080050, 0xe82025, 0xaf430038, 0x8cc50014, +0x27420400, 0xaf82001c, 0xaf45003c, 0xaf440030, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x8f4b0000, 0x316a0020, 0x1140fffd, 0x0, +0x3e00008, 0x0, 0x8f840010, 0x948a001a, +0x8c870024, 0x3149ffff, 0x940c0, 0xe83021, +0xaf46003c, 0x8c850024, 0x8f43003c, 0xa31023, +0x18400029, 0x0, 0x8c8b0020, 0x25620001, +0x3c0d0050, 0x35ac0008, 0xaf420038, 0xaf4c0030, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x8f4f0000, 0x31ee0020, 0x11c0fffd, 0x0, +0x8f4a0400, 0x3c080020, 0xac8a0010, 0x8f490404, +0xac890014, 0xaf480030, 0x0, 0x94860018, +0x9487001c, 0xc71821, 0xa4830018, 0x9485001a, +0x24a20001, 0xa482001a, 0x9498001a, 0x9499001e, +0x13380003, 0x0, 0x3e00008, 0x0, +0x3e00008, 0xa480001a, 0x8c820020, 0xa0000cc, +0x3c0d0050, 0xa0000bd, 0x0, 0x3c030800, +0x8c630020, 0x8f820018, 0x27bdffe8, 0x10620008, +0xafbf0010, 0xe0000f4, 0xaf830018, 0x3c030800, +0x8c630020, 0x24040001, 0x10640004, 0x8f890010, +0x8fbf0010, 0x3e00008, 0x27bd0018, 0x8fbf0010, +0x3c076012, 0xa520000a, 0x9528000a, 0x34e50010, +0x27bd0018, 0x3106ffff, 0x3e00008, 0xaca60090, +0x3c020800, 0x8c420020, 0x27bdffc8, 0xafbf0034, +0xafbe0030, 0xafb7002c, 0xafb60028, 0xafb50024, +0xafb40020, 0xafb3001c, 0xafb20018, 0xafb10014, +0x10400050, 0xafb00010, 0x8f840010, 0x94860006, +0x9483000a, 0xc32823, 0x30b6ffff, 0x12c0004a, +0x8fbf0034, 0x94890018, 0x948a000a, 0x12a4023, +0x3102ffff, 0x2c2382b, 0x14e00002, 0x2c02021, +0x402021, 0x2c8c0005, 0x15800002, 0x80a021, +0x24140004, 0xe0000a3, 0x2802021, 0x8f870010, +0x2809821, 0xaf800014, 0x94ed000a, 0x2808821, +0x1280004e, 0x31b2ffff, 0x3c177000, 0x3c154000, +0x3c1e6000, 0x8f8f001c, 0x8dee0000, 0x1d71824, +0x50750050, 0x2202021, 0x2a3802b, 0x16000035, +0x3c182000, 0x50780047, 0x2202021, 0x24100001, +0x8f830014, 0x14600039, 0x2915823, 0x230f823, +0x250c821, 0x33f1ffff, 0x1620ffee, 0x3332ffff, +0x8f870010, 0x3c110020, 0xaf510030, 0x0, +0x94e6000a, 0x3c1e6012, 0x37d50010, 0x2662821, +0xa4e5000a, 0x94e2000a, 0x94f2000a, 0x94f40018, +0x3057ffff, 0x1292003b, 0xaeb70090, 0x8ced0014, +0x8ce40010, 0x137140, 0x1ae4021, 0xe5fc3, +0x10e502b, 0x8b4821, 0x12a1821, 0xace80014, +0xace30010, 0x2d33823, 0x30f6ffff, 0x16c0ffb9, +0x8f840010, 0x8fbf0034, 0x8fbe0030, 0x8fb7002c, +0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, +0x8fb20018, 0x8fb10014, 0x8fb00010, 0x3e00008, +0x27bd0038, 0x107e001b, 0x0, 0x1477ffcc, +0x24100001, 0xe0015a9, 0x0, 0x8f830014, +0x1060ffcb, 0x230f823, 0x2915823, 0x8f870010, +0x1702021, 0xa000187, 0x3093ffff, 0x8f830014, +0x1460ffcb, 0x3c110020, 0xaf510030, 0xa000153, +0x0, 0xe00079b, 0x2402821, 0xa000147, +0x408021, 0xe000341, 0x2402821, 0xa000147, +0x408021, 0xe001471, 0x2202021, 0xa000147, +0x408021, 0xe0000bd, 0x0, 0xa000169, +0x2d33823, 0x27bdffe8, 0xafb00010, 0xafbf0014, +0xe000037, 0x0, 0x3c028000, 0x34500070, +0xa0001aa, 0x8e060000, 0x8f4f0000, 0x39ee0001, +0x31c20001, 0x10400024, 0x8f8600a8, 0x8e070000, +0x3c0c0800, 0x8d8c003c, 0x3c090800, 0x8d290038, +0xe66823, 0x18d2821, 0x5021, 0xad302b, +0x12a4021, 0x1062021, 0x3c010800, 0xac25003c, +0xaf8700a8, 0x3c010800, 0xac240038, 0xe0000f6, +0x0, 0x3c030800, 0x8c630070, 0x1060ffe6, +0x602021, 0x3c050800, 0x8ca50068, 0x3c060800, +0x8cc6006c, 0xe001538, 0x0, 0x3c010800, +0xac200070, 0x8f4f0000, 0x39ee0001, 0x31c20001, +0x1440ffde, 0x8f8600a8, 0x8e0a0000, 0x8f8b00a8, +0x3c050800, 0x8ca5003c, 0x3c040800, 0x8c840038, +0x14b4823, 0xa93821, 0x821821, 0xe9402b, +0x681021, 0x3c010800, 0xac27003c, 0x3c010800, +0xac220038, 0x8f5f0100, 0x2419ff00, 0x24180c00, +0x3f92024, 0x10980012, 0xaf840000, 0xaf440020, +0x936d0000, 0x240c0020, 0x31a600ff, 0x10cc0012, +0x240e0050, 0x10ce0004, 0x3c194000, 0xaf590138, +0xa0001a3, 0x0, 0xe0011d4, 0x0, +0x3c194000, 0xaf590138, 0xa0001a3, 0x0, +0xe00010f, 0x0, 0x3c194000, 0xaf590138, +0xa0001a3, 0x0, 0x8f580100, 0x802821, +0x330f00ff, 0x1e02021, 0xe0002ee, 0xaf8f0004, +0x3c194000, 0xaf590138, 0xa0001a3, 0x0, +0xa4102b, 0x24030001, 0x10400009, 0x3021, +0x52840, 0xa4102b, 0x4a00003, 0x31840, +0x5440fffc, 0x52840, 0x5060000a, 0x4182b, +0x85382b, 0x54e00004, 0x31842, 0xc33025, +0x852023, 0x31842, 0x1460fff9, 0x52842, +0x4182b, 0x3e00008, 0xc31021, 0x3084ffff, +0x30a5ffff, 0x8f4201b8, 0x440fffe, 0x3c074080, +0x873025, 0x3c031000, 0xaf400180, 0xaf450184, +0xaf460188, 0x3e00008, 0xaf4301b8, 0x3084ffff, +0x8f4201b8, 0x440fffe, 0x3c074038, 0x8ca60000, +0x872825, 0x3c031000, 0xaf460180, 0xaf450188, +0x3e00008, 0xaf4301b8, 0x8f830038, 0x8f860030, +0x1066000b, 0x804021, 0x3c070800, 0x24e75a18, +0x328c0, 0xa71021, 0x8c440000, 0x24630001, +0x10880005, 0x3063000f, 0x5466fffa, 0x328c0, +0x3e00008, 0x1021, 0x3c070800, 0x24e75a1c, +0xa73021, 0x3e00008, 0x8cc20000, 0x3c039000, +0x34620001, 0x822025, 0xaf440020, 0x8f450020, +0x4a0fffe, 0x0, 0x3e00008, 0x0, +0x3c038000, 0x34620001, 0x822025, 0x3e00008, +0xaf440020, 0x27bdffe0, 0xafb10014, 0x3091ffff, +0xafb00010, 0xafbf0018, 0x12200015, 0xa08021, +0x8ca50000, 0x10a00013, 0x24040002, 0xe000c6b, +0x24060140, 0xae000000, 0x8f4201b8, 0x440000d, +0x2821, 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0xaf8500d4, 0x3c010800, 0xac290060, +0x3c010800, 0xac280064, 0x3c010800, 0xac270054, +0x3c010800, 0xac230058, 0x3c010800, 0xac26005c, +0x3e00008, 0x0, 0x308300ff, 0x30c6ffff, +0x30e400ff, 0x8f4201b8, 0x440fffe, 0x34c00, +0x1243825, 0x3c086000, 0xe82025, 0x3c031000, +0xaf450180, 0xaf460184, 0xaf440188, 0x3e00008, +0xaf4301b8, 0x8f86001c, 0x3c096012, 0x35270010, +0x8ccb0004, 0x3c0c600e, 0x35850010, 0x316a0006, +0x2d480001, 0xace800c4, 0x8cc40004, 0xaca43180, +0x8cc20008, 0x94c30002, 0xaca23184, 0x3e00008, +0xa78300e4, 0x3c030800, 0x8c630050, 0x8f8400e8, +0x8f86001c, 0x2402ff80, 0x64c021, 0x302c824, +0xaf590028, 0x8ccd0004, 0x3305007f, 0xba7821, +0x3c0e000c, 0x1ee2821, 0xacad0058, 0x8cc80008, +0xaf8500d0, 0x3c076012, 0xaca8005c, 0x8ccc0010, +0x34e80010, 0xacac000c, 0x8ccb000c, 0xacab0008, +0x94aa0014, 0x3c020800, 0x8c420044, 0x25490001, +0xa4a90014, 0x94a40014, 0x3083ffff, 0x10620017, +0x8f8400d0, 0x3c0a0800, 0x8d4a0040, 0xa4aa0012, +0x8cce0018, 0xac8e0024, 0x8ccd0014, 0xac8d0020, +0x8cc70018, 0xac87002c, 0x8ccc0014, 0x24060001, +0xac8c0028, 0x8d0b00bc, 0x5166001a, 0x8d0200b4, +0x8d0200b8, 0xa482003a, 0x948f003a, 0xa48f003c, +0x948800d4, 0x3e00008, 0x3102ffff, 0x3c090800, +0x8d290024, 0xa4a00014, 0x8f8400d0, 0xa4a90012, +0x8cce0018, 0xac8e0024, 0x8ccd0014, 0xac8d0020, +0x8cc70018, 0xac87002c, 0x8ccc0014, 0x24060001, +0xac8c0028, 0x8d0b00bc, 0x5566ffea, 0x8d0200b8, +0x8d0200b4, 0xa482003a, 0x948f003a, 0xa48f003c, +0x948800d4, 0x3e00008, 0x3102ffff, 0x8f86001c, +0x3c0c0800, 0x8d8c0050, 0x240bff80, 0x8ccd0008, +0x3c03000c, 0xd51c0, 0x18a4021, 0x10b4824, +0xaf8a00e8, 0xaf490028, 0x90c70007, 0x3105007f, +0xba1021, 0x432821, 0x30e40004, 0x1080002f, +0xaf8500d0, 0x90cf0007, 0x31ee0008, 0x11c0003c, +0x0, 0x8cd9000c, 0x8cc40014, 0x324c02b, +0x13000026, 0x0, 0x8cc2000c, 0xaca20064, +0x8ccd0018, 0x2402fff8, 0xacad0068, 0x8ccc0010, +0xacac0080, 0x8ccb000c, 0xacab0084, 0x8cca001c, +0xacaa007c, 0x90a900bc, 0x1224024, 0xa0a800bc, +0x90c30007, 0x30670008, 0x10e00004, 0x8f8500d0, +0x90af00bc, 0x35ee0001, 0xa0ae00bc, 0x90d90007, +0x33380001, 0x1300000f, 0x8f8400d0, 0x24070020, +0x908200bc, 0x34490002, 0xa08900bc, 0x8f8400d0, +0x90880062, 0x310300f0, 0x14670006, 0x240a0034, +0xac8a00c0, 0xa001334, 0x0, 0xa00130e, +0x8cc20014, 0x90cb0007, 0x31660002, 0x10c00005, +0x0, 0x908d00bc, 0x35ac0004, 0xa08c00bc, +0x8f8400d0, 0x90980113, 0x330f003f, 0xa08f0113, +0x8f8e00d0, 0x95c500d4, 0x3e00008, 0x30a2ffff, +0xaca00064, 0xa00130f, 0x0, 0x27bdffd8, +0xafb00010, 0x8f90001c, 0xafbf0024, 0xafb40020, +0xafb20018, 0xafb10014, 0xafb3001c, 0x9613000e, +0x3c07600a, 0x3c146006, 0x3264ffff, 0x36930010, +0xe001261, 0x34f40410, 0x8f8400d4, 0x3c11600e, +0xe0009aa, 0x36310010, 0x920e0015, 0x3c070800, +0x8ce70060, 0x3c126012, 0x31cd000f, 0xa38d00f0, +0x8e0e0004, 0x8e0d0008, 0x96080012, 0x961f0010, +0x9619001a, 0x9618001e, 0x960f001c, 0x310cffff, +0x33ebffff, 0x332affff, 0x3309ffff, 0x31e6ffff, +0x3c010800, 0xac2b0040, 0x3c010800, 0xac2c0024, +0x3c010800, 0xac2a0044, 0xae293178, 0xae26317c, +0x92020015, 0x96030016, 0x36520010, 0x304400ff, +0x3065ffff, 0x3c060800, 0x8cc60064, 0xae243188, +0xae4500b4, 0x92080014, 0x96190018, 0x241f0001, +0x11fc004, 0x332fffff, 0x3c050800, 0x8ca50058, +0xae5800b8, 0xae4f00bc, 0x920c0014, 0xaf8e00d8, +0xaf8d00dc, 0x318b00ff, 0xae4b00c0, 0x920a0015, +0xae670048, 0xae66004c, 0x314900ff, 0xae4900c8, +0xae65007c, 0x3c030800, 0x8c630050, 0x3c040800, +0x8c84004c, 0x3c080800, 0x8d080054, 0x3c020800, +0x8c42005c, 0x8fbf0024, 0xae630080, 0x8fb00010, +0xae830074, 0x8fb3001c, 0xae22319c, 0xae4200dc, +0xae2731a0, 0xae2631a4, 0xae24318c, 0xae233190, +0xae283194, 0xae253198, 0xae870050, 0xae860054, +0xae850070, 0x8fb10014, 0xae4700e0, 0xae4600e4, +0xae4400cc, 0xae4300d0, 0xae4800d4, 0xae4500d8, +0x8fb40020, 0x8fb20018, 0x3e00008, 0x27bd0028, +0x27bdffe0, 0xafb10014, 0xafbf0018, 0x24110001, +0xe000854, 0xafb00010, 0x10510005, 0x978400e6, +0x978300cc, 0x83102b, 0x14400008, 0x8f8500d4, +0x24070002, 0x8fbf0018, 0x8fb10014, 0x8fb00010, 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0x914d0062, +0x31ac000f, 0x358b0010, 0xa14b0062, 0x8f8600d0, +0x90c90063, 0x3128007f, 0xa0c80063, 0x8f8400d0, +0x2406ffff, 0x90850063, 0xa31024, 0xa0820063, +0x8f9100d0, 0xe01021, 0x923f00bc, 0x37f90001, +0xa23900bc, 0x8f8a00d0, 0x938f00f0, 0xad580064, +0xad5000c0, 0x914e00d3, 0xf6900, 0x31cc000f, +0x18d5825, 0xa14b00d3, 0x8f8500d0, 0x8f8900dc, +0xaca900e8, 0x8f8800d8, 0x8fbf0018, 0x8fb10014, +0x8fb00010, 0x27bd0020, 0xaca800ec, 0xa4a600d6, +0xa4a000e0, 0xa4a000e2, 0x3e00008, 0x0, +0x27bdffe0, 0xafb00010, 0x8f90001c, 0xafb10014, +0xafbf0018, 0x8e190004, 0x3c180800, 0x8f180050, +0x240fff80, 0x1989c0, 0x2387021, 0x31cd007f, +0x1cf6024, 0x1ba5021, 0x3c0b000c, 0xaf4c0028, +0x14b4021, 0x950900d4, 0x950400d6, 0x8e070004, +0x3131ffff, 0xaf8800d0, 0xe000922, 0x721c0, +0x8e060004, 0x8f8300c8, 0x629c0, 0xaf450020, +0x9064003e, 0x30820040, 0x14400006, 0x8f8400d0, +0x341fffff, 0x948300d6, 0x3062ffff, 0x145f0004, +0x0, 0x948400d6, 0xe0008b7, 0x3084ffff, +0x8e050004, 0x2203021, 0x8fbf0018, 0x8fb10014, +0x8fb00010, 0x24040022, 0x3821, 0x529c0, +0xa001285, 0x27bd0020, 0x27bdffe0, 0xafb10014, +0x3091ffff, 0xafb00010, 0xafbf0018, 0x1220001d, +0x8021, 0x8f86001c, 0x8cc50000, 0x24030006, +0x53f02, 0x51402, 0x30e40007, 0x14830015, +0x304500ff, 0x2ca80006, 0x1100004d, 0x55880, +0x3c0c0800, 0x258c57e8, 0x16c5021, 0x8d490000, +0x1200008, 0x0, 0x8f8e00ec, 0x240d0001, +0x11cd0059, 0x0, 0x260b0001, 0x3170ffff, +0x24ca0020, 0x211202b, 0x1403021, 0x1480ffe6, +0xaf8a001c, 0x2001021, 0x8fbf0018, 0x8fb10014, +0x8fb00010, 0x3e00008, 0x27bd0020, 0x938700ce, +0x14e00038, 0x24040014, 0xe001346, 0x0, +0x8f86001c, 0x24020001, 0xa00148d, 0xaf8200ec, +0x8f8900ec, 0x24080002, 0x1128003b, 0x24040013, +0x2821, 0x3021, 0x24070001, 0xe001285, +0x0, 0xa00148d, 0x8f86001c, 0x8f8700ec, +0x24050002, 0x14e5fff6, 0x24040012, 0xe0012f2, +0x0, 0x8f8500e8, 0x403021, 0x24040012, +0xe001285, 0x3821, 0xa00148d, 0x8f86001c, +0x8f8300ec, 0x241f0003, 0x147fffd0, 0x260b0001, +0xe0012a4, 0x0, 0x8f8500e8, 0x403021, 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0x0, 0x0, 0x0, +0x8f4f0000, 0x31e80010, 0x1100fffd, 0x0, +0x8f42003c, 0x8f43003c, 0x49c821, 0x323c02b, +0x13000004, 0x0, 0x8f4c0038, 0x25860001, +0xaf460038, 0x8f47003c, 0xa92823, 0xe96821, +0xaf4d003c, 0x14a0ffce, 0x2ca20080, 0x3e00008, +0x0, 0x27bdffd0, 0x3c020002, 0xafb10014, +0x3c11000c, 0xaf450038, 0xafb3001c, 0xaf46003c, +0x809821, 0xaf420030, 0x24050088, 0xaf440028, +0x3512021, 0xafbf0028, 0xafb50024, 0xafb40020, +0xafb20018, 0xe0014ff, 0xafb00010, 0x3c1f0800, +0x8fff004c, 0x3c180800, 0x8f180064, 0x2410ff80, +0x3f3a821, 0x32b9007f, 0x2b07824, 0x18a0c0, +0x33a7021, 0x189140, 0x1d12021, 0xaf4f0028, +0xe0014ff, 0x2542821, 0x3c0d0800, 0x8dad0050, +0x24050120, 0x1b35821, 0x316c007f, 0x1705024, +0x19a4821, 0x1312021, 0xe0014ff, 0xaf4a0028, +0x3c080800, 0x8d080054, 0x3c050800, 0x8ca50064, +0x1133821, 0x30e6007f, 0xf01824, 0xda2021, +0x912021, 0xaf430028, 0xe0014ff, 0x52940, +0x3c020800, 0x8c420058, 0x3c100800, 0x8e100060, +0x1200001c, 0x538821, 0x2415ff80, 0xa001582, +0x3c14000c, 0x3226007f, 0x2351824, 0xda2021, +0x2402821, 0xaf430028, 0x942021, 0xe0014ff, +0x2610ffc0, 0x1200000f, 0x2328821, 0x2e050041, +0x10a0fff4, 0x24121000, 0x3226007f, 0x109180, +0x2351824, 0xda2021, 0x2402821, 0xaf430028, +0x942021, 0xe0014ff, 0x8021, 0x1600fff3, +0x2328821, 0x3c0b0800, 0x8d6b005c, 0x240aff80, +0x24050002, 0x1734021, 0x10a4824, 0xaf490028, +0x3c040800, 0x94840062, 0x3110007f, 0x21a8821, +0x3c07000c, 0xe000cb9, 0x2279821, 0x402821, +0x2602021, 0x8fbf0028, 0x8fb50024, 0x8fb40020, +0x8fb3001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, +0xa0014ff, 0x27bd0030, 0x8f83001c, 0x8c620004, +0x10400003, 0x0, 0x3e00008, 0x0, +0x8c640010, 0x8c650008, 0xa001538, 0x8c66000c, +0x0 }; +u32 bce_CP_b06FwData[(0x84/4) + 1] = { +0x0, +0x1b, 0xf, 0xa, 0x8, +0x6, 0x5, 0x5, 0x4, +0x4, 0x3, 0x3, 0x3, +0x3, 0x3, 0x2, 0x2, +0x2, 0x2, 0x2, 0x2, +0x2, 0x2, 0x2, 0x2, +0x2, 0x2, 0x2, 0x2, +0x2, 0x1, 0x1, 0x1, +0x0 }; +u32 bce_CP_b06FwRodata[(0x134/4) + 1] = { +0x8000f30, 0x8000d88, 0x8000fc4, +0x800106c, 0x8000f58, 0x8000f98, 0x80011a4, +0x8000da4, 0x80011c8, 0x8000df4, 0x8001498, +0x8001440, 0x8000da4, 0x8000da4, 0x8000da4, +0x8001254, 0x8001254, 0x8000da4, 0x8000da4, +0x80016e0, 0x8000da4, 0x8000da4, 0x8000da4, +0x8000da4, 0x80013d4, 0x8000da4, 0x8000da4, +0x8000da4, 0x8000da4, 0x8000da4, 0x8000da4, +0x8000da4, 0x8000da4, 0x8000da4, 0x8000da4, +0x8000da4, 0x8000da4, 0x8000da4, 0x8000da4, +0x8000fb8, 0x8000da4, 0x8000da4, 0x8001690, +0x8000da4, 0x8000da4, 0x8000da4, 0x8000da4, +0x8000da4, 0x8000da4, 0x8000da4, 0x8000da4, +0x8000da4, 0x8000da4, 0x8000da4, 0x8000da4, +0x8000da4, 0x8000da4, 0x8000da4, 0x8000da4, +0x8000da4, 0x80015bc, 0x8000da4, 0x8000da4, +0x8001348, 0x80012b8, 0x8002e50, 0x8002e58, +0x8002e20, 0x8002e2c, 0x8002e38, 0x8002e44, +0x800532c, 0x80052ec, 0x80052b8, 0x800528c, +0x8005268, 0x8005224, 0x0 }; +u32 bce_CP_b06FwBss[(0x5d8/4) + 1] = { 0x0 }; +u32 bce_CP_b06FwSbss[(0xf1/4) + 1] = { 0x0 }; +u32 bce_CP_b06FwSdata[(0x0/4) + 1] = { 0x0 }; + + +u32 bce_rv2p_proc1[] = { + 0x00000010, 0xb1800002, + 0x0000001f, 0x01030100, + 0x00000008, 0xac000001, + 0x00000000, 0x05000000, + 0x0000000c, 0x2f800001, + 0x00000000, 0x2b000000, + 0x00000000, 0x2b800000, + 0x00000010, 0x203f0063, + 0x00000010, 0x213f0003, + 0x00000010, 0x20bf0032, + 0x00000018, 0x8000fffd, + 0x00000010, 0xb1b8b00d, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x03d80000, + 0x00000000, 0x2c380000, + 0x00000010, 0x91d40000, + 0x00000008, 0x06005555, + 0x00000018, 0x80000075, + 0x00000018, 0x8000010b, + 0x00000008, 0x02000002, + 0x0000000f, 0x42e0001c, + 0x00000010, 0x91840a11, + 0x00000010, 0x2c62000b, + 0x00000018, 0x8000001e, + 0x00000008, 0x02000002, + 0x0000000f, 0x42e0001c, + 0x00000010, 0x91840a18, + 0x00000008, 0x2c8000b1, + 0x00000008, 0x2d000009, + 0x00000010, 0x91d40000, + 0x00000008, 0x2d800107, + 0x00000018, 0x8000006f, + 0x00000018, 0x80000015, + 0x00000008, 0xb1000001, + 0x00000008, 0x2c8000b0, + 0x00000008, 0x2d000008, + 0x00000008, 0x2d800001, + 0x00000018, 0x80000069, + 0x0000000b, 0x2fdf0002, + 0x0000000c, 0x1f800002, + 0x00000000, 0x2c070000, + 0x00000010, 0x91de0000, + 0x00000000, 0x05000000, + 0x00000018, 0x8000ffdc, + 0x0000000b, 0x2fdf0002, + 0x0000000c, 0x1f800000, + 0x00000000, 0x2c070000, + 0x00000010, 0x91de0000, + 0x00000000, 0x05000000, + 0x00000018, 0x8000ffd6, + 0x0000000c, 0x1f800002, + 0x00000000, 0x05000000, + 0x00000018, 0x8000ffd3, + 0x0000000c, 0x29800002, + 0x0000000c, 0x1f800002, + 0x00000000, 0x2adf0000, + 0x00000008, 0x2a000005, + 0x00000008, 0x05005555, + 0x00000018, 0x8000ffcd, + 0x00000008, 0x0224003c, + 0x00000018, 0x00040000, + 0x00000018, 0x8000001c, + 0x00000018, 0x8000001e, + 0x00000018, 0x80000052, + 0x00000018, 0x8000009e, + 0x00000018, 0x8000009d, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x800000df, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000015, + 0x00000018, 0x8000001b, + 0x00000018, 0x80000000, + 0x00000018, 0x800000b4, + 0x00000018, 0x8000002e, + 0x00000018, 0x800000df, + 0x00000018, 0x8000010a, + 0x00000018, 0x800000d5, + 0x00000018, 0x8000012e, + 0x00000018, 0x8000003b, + 0x00000018, 0x80000000, + 0x00000018, 0x80000071, + 0x0000000c, 0x1f800001, + 0x00000000, 0x05000000, + 0x00000018, 0x8000ffac, + 0x00000010, 0x91d40000, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000008, 0x2a000002, + 0x00000000, 0x05000000, + 0x00000018, 0x8000ffa6, + 0x00000010, 0x91d40000, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000000, 0x29420000, + 0x00000008, 0x2a000002, + 0x00000000, 0x05000000, + 0x00000018, 0x8000ff9f, + 0x00000018, 0x8000ff9e, + 0x00000010, 0xb1bcb00a, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x03d80000, + 0x00000000, 0x2c3c0000, + 0x00000010, 0x91d40000, + 0x00000008, 0x06005555, + 0x00000018, 0x80000016, + 0x00000018, 0x800000ac, + 0x00000010, 0x2c6201ba, + 0x00000018, 0x80000005, + 0x00000008, 0x2c8000b1, + 0x00000008, 0x2d000009, + 0x00000010, 0x91d40000, + 0x00000008, 0x2d800107, + 0x0000000c, 0x29800000, + 0x0000000c, 0x1f800000, + 0x00000010, 0x91de0000, + 0x00000000, 0x2adf0000, + 0x00000008, 0x2a000006, + 0x00000008, 0x05005555, + 0x00000018, 0x8000ff89, + 0x00000010, 0x91d40000, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000008, 0x2a00000b, + 0x00000000, 0x05000000, + 0x00000018, 0x8000ff83, + 0x00000018, 0x00020000, + 0x00000000, 0x06820000, + 0x00000010, 0xb18a0006, + 0x00000000, 0x860c1400, + 0x00000010, 0xb18c0004, + 0x00000000, 0x05000000, + 0x00000008, 0x2a000001, + 0x00000010, 0x91d40000, + 0x00000018, 0x000d0000, + 0x00000000, 0x05020000, + 0x00000010, 0x91de0000, + 0x00000018, 0x000a0000, + 0x00000010, 0xb1a0b013, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c200000, + 0x00000008, 0x2c800000, + 0x00000008, 0x2d000000, + 0x00000010, 0x91d40000, + 0x00000008, 0x06005555, + 0x00000018, 0x8000ffee, + 0x00000008, 0x2d80011c, + 0x00000010, 0x001f0000, + 0x00000010, 0x91de0000, + 0x0000000f, 0x47600008, + 0x0000000f, 0x060e0001, + 0x00000000, 0x0f580000, + 0x00000000, 0x0a640000, + 0x00000000, 0x0ae50000, + 0x00000009, 0x0b66ffff, + 0x00000000, 0x0d610000, + 0x00000018, 0x80000013, + 0x0000000f, 0x47600008, + 0x0000000b, 0x2fdf0002, + 0x00000008, 0x2c800000, + 0x00000008, 0x2d000000, + 0x00000010, 0x91d40000, + 0x00000008, 0x2d80011c, + 0x0000000f, 0x060e0001, + 0x00000010, 0x001f0000, + 0x00000000, 0x0f580000, + 0x00000010, 0x91de0000, + 0x00000000, 0x0a640000, + 0x00000000, 0x0ae50000, + 0x00000009, 0x0b66ffff, + 0x00000000, 0x0d610000, + 0x00000000, 0x02620000, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x31040000, + 0x00000000, 0x309a0000, + 0x00000000, 0x0c961800, + 0x00000009, 0x0c99ffff, + 0x00000004, 0xcc993400, + 0x00000010, 0xb1963202, + 0x00000008, 0x0f800000, + 0x0000000c, 0x29800001, + 0x00000010, 0x00220002, + 0x0000000c, 0x29520001, + 0x0000000c, 0x29520000, + 0x00000008, 0x0200000e, + 0x00000008, 0x0280001a, + 0x00000010, 0xb1c40a02, + 0x00000008, 0x02000003, + 0x00000008, 0x22000001, + 0x0000000c, 0x1f800001, + 0x00000000, 0x2adf0000, + 0x00000000, 0x2a000800, + 0x00000008, 0x05005555, + 0x00000018, 0x8000ff3f, + 0x0000000b, 0x2fdf0002, + 0x00000010, 0x91d40000, + 0x00000008, 0x2a000001, + 0x00000000, 0x2c200000, + 0x00000008, 0x2c800000, + 0x00000008, 0x2d000000, + 0x00000008, 0x2d80011c, + 0x00000010, 0x91d40000, + 0x00000010, 0x91de0000, + 0x00000008, 0x2c800006, + 0x00000008, 0x2d000006, + 0x00000000, 0x30800000, + 0x00000000, 0x31000000, + 0x00000008, 0x2d800006, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000010, 0x91de0000, + 0x00000000, 0x2adf0000, + 0x00000008, 0x2a000010, + 0x00000000, 0x05000000, + 0x00000018, 0x8000ff2a, + 0x00000010, 0x91a0b009, + 0x00000008, 0x2c8000b1, + 0x00000008, 0x2d000009, + 0x00000010, 0x91d40000, + 0x00000008, 0x2d800107, + 0x00000018, 0x8000ffab, + 0x00000018, 0x80000010, + 0x00000008, 0xac000001, + 0x00000018, 0x8000000b, + 0x00000000, 0x0380b000, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c004000, + 0x00000010, 0x91d40000, + 0x00000008, 0x06005555, + 0x00000018, 0x8000ff9a, + 0x00000018, 0x80000030, + 0x00000018, 0x80000006, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c000e00, + 0x00000008, 0x2a000007, + 0x00000008, 0x05005555, + 0x00000018, 0x8000ff14, + 0x00000000, 0x06820000, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000010, 0x0ce70007, + 0x00000009, 0x0562ffff, + 0x00000010, 0xba6c1405, + 0x00000000, 0x2adf0000, + 0x00000000, 0x21000000, + 0x00000008, 0x2a000005, + 0x00000010, 0x91d40000, + 0x00000008, 0x2c8000b0, + 0x00000008, 0x2d000008, + 0x0000000c, 0x31620018, + 0x00000008, 0x2d800001, + 0x00000018, 0x8000ff8c, + 0x00000018, 0x000d0000, + 0x00000010, 0xb1a0b00e, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x03d80000, + 0x00000000, 0x2c200000, + 0x00000010, 0x91d40000, + 0x00000018, 0x80000014, + 0x00000010, 0x2c620002, + 0x00000018, 0x8000000b, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c070000, + 0x0000000c, 0x1f800001, + 0x00000010, 0x91de0000, + 0x00000000, 0x05000000, + 0x00000018, 0x8000fef6, + 0x00000008, 0x2c8000b1, + 0x00000008, 0x2d000009, + 0x00000010, 0x91d40000, + 0x00000008, 0x2d800107, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000010, 0x91de0000, + 0x00000000, 0x2adf0000, + 0x00000008, 0x2a00000a, + 0x00000000, 0x05000000, + 0x00000018, 0x8000feeb, + 0x00000000, 0x05020000, + 0x00000008, 0x2c8000b0, + 0x00000008, 0x2d000008, + 0x00000008, 0x2d800150, + 0x00000000, 0x00000000, + 0x00000010, 0x205f0000, + 0x00000008, 0x2c800000, + 0x00000008, 0x2d000000, + 0x00000008, 0x2d800108, + 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, + 0x00000018, 0x000a0000, + 0x00000010, 0x91d40000, + 0x00000008, 0x0600aaaa, + 0x00000018, 0x8000ff5b, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000008, 0x2a000009, + 0x00000008, 0x0500aaaa, + 0x00000018, 0x8000fed7, + 0x00000010, 0x91d40000, + 0x00000008, 0x06005555, + 0x00000018, 0x8000ff53, + 0x00000010, 0x91a03c02, + 0x00000010, 0xb1e66207, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c310000, + 0x00000009, 0x2cb1007f, + 0x00000008, 0x2cd90000, + 0x00000008, 0x2d000000, + 0x00000008, 0x2d80010d, + 0x00000010, 0xb1a80006, + 0x00000010, 0x205f0000, + 0x00000000, 0x2c200000, + 0x00000000, 0x2ca70000, + 0x00000008, 0x2d000010, + 0x00000008, 0x2d800108, + 0x00000018, 0x8000ff4c, + 0x00000010, 0xb1a60010, + 0x00000010, 0x001f0000, + 0x0000000f, 0x0f300007, + 0x00000000, 0x0a600000, + 0x00000000, 0x0ae10000, + 0x0000000f, 0x4b620008, + 0x00000009, 0x0b1600ff, + 0x00000000, 0x0d620000, + 0x00000009, 0x0d1a00ff, + 0x00000010, 0x07300003, + 0x0000000c, 0x0d1a0008, + 0x0000000c, 0x0b160008, + 0x0000000f, 0x4ce30018, + 0x00000000, 0x0c992c00, + 0x00000004, 0xcc993400, + 0x00000008, 0x0f800000, + 0x0000000c, 0x29800001, + 0x00000000, 0x33310000, + 0x00000008, 0x22000016, + 0x00000000, 0x2adf0000, + 0x00000008, 0x2a00000c, + 0x00000010, 0x009f0000, + 0x00000000, 0x0f200000, + 0x0000000c, 0x1f800001, + 0x00000008, 0x05005555, + 0x00000018, 0x8000feab, + 0x00000010, 0x91d40000, + 0x00000008, 0x0600aaaa, + 0x00000018, 0x8000ff27, + 0x0000000f, 0x47220008, + 0x00000009, 0x070e000f, + 0x00000008, 0x070e0008, + 0x00000008, 0x02800001, + 0x00000007, 0x02851c00, + 0x00000008, 0x82850001, + 0x00000000, 0x02854c00, + 0x00000007, 0x42851c00, + 0x00000003, 0xc3aa5200, + 0x00000000, 0x03b10e00, + 0x00000007, 0x4b071c00, + 0x0000000f, 0x0f300007, + 0x0000000f, 0x0a960003, + 0x00000000, 0x0a955c00, + 0x00000000, 0x4a005a00, + 0x00000000, 0x0c960a00, + 0x00000009, 0x0c99ffff, + 0x00000008, 0x0d00ffff, + 0x00000010, 0xb1963202, + 0x00000008, 0x0f800005, + 0x00000010, 0xb1a80008, + 0x00000010, 0x205f0000, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c200000, + 0x00000000, 0x2ca70000, + 0x00000008, 0x2d000010, + 0x00000008, 0x2d800108, + 0x00000018, 0x8000ff13, + 0x0000000c, 0x29800001, + 0x00000010, 0x001f0000, + 0x0000000c, 0x1f800001, + 0x00000000, 0x2adf0000, + 0x00000008, 0x2a00000d, + 0x00000008, 0x0500aaaa, + 0x00000018, 0x8000fe85, + 0x00000010, 0x91d40000, + 0x00000008, 0x06005555, + 0x00000018, 0x8000ff01, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000008, 0x2a000007, + 0x00000008, 0x05005555, + 0x00000018, 0x8000fe7d, + 0x00000008, 0x03050004, + 0x00000006, 0x83040c00, + 0x00000008, 0x02850200, + 0x00000000, 0x86050c00, + 0x00000001, 0x860c0e00, + 0x00000008, 0x02040004, + 0x00000000, 0x02041800, + 0x00000000, 0x83871800, + 0x00000018, 0x00020000, +}; + + +u32 bce_rv2p_proc2[] = { + 0x00000010, 0xb1800004, + 0x0000001f, 0x01030100, + 0x00000008, 0x050000ff, + 0x00000018, 0x00020000, + 0x00000000, 0x2a000000, + 0x00000010, 0xb1d40000, + 0x0000000c, 0x29800001, + 0x00000008, 0x02540008, + 0x00000018, 0x00040000, + 0x00000018, 0x80000010, + 0x00000018, 0x80000011, + 0x00000018, 0x8000003a, + 0x00000018, 0x80000104, + 0x00000018, 0x80000103, + 0x00000018, 0x80000102, + 0x00000018, 0x80000102, + 0x00000018, 0x80000000, + 0x00000018, 0x80000114, + 0x00000018, 0x800000fe, + 0x00000018, 0x8000000c, + 0x00000018, 0x80000118, + 0x00000018, 0x8000016a, + 0x00000018, 0x80000067, + 0x00000018, 0x800000da, + 0x00000018, 0x800000e7, + 0x00000000, 0x2a000000, + 0x00000018, 0x8000ffeb, + 0x00000000, 0x2a000000, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x00000018, 0x8000ffe7, + 0x00000000, 0x2a000000, + 0x00000018, 0x8000ffe5, + 0x00000018, 0x00020000, + 0x00000000, 0x05020000, + 0x00000010, 0x91963421, + 0x00000010, 0x205f0000, + 0x00000000, 0x2c1e0000, + 0x00000008, 0x2c800006, + 0x00000008, 0x2d000006, + 0x00000008, 0x2d800102, + 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, + 0x00000000, 0x0d610000, + 0x00000018, 0x000a0000, + 0x00000000, 0x05020000, + 0x00000010, 0x91963416, + 0x00000010, 0x205f0000, + 0x00000000, 0x09d80000, + 0x00000000, 0x2c1e0000, + 0x00000008, 0x2c8000b2, + 0x00000008, 0x2d00000a, + 0x00000008, 0x2d800102, + 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, + 0x00000000, 0x0d620000, + 0x00000000, 0x2c130000, + 0x00000018, 0x000a0000, + 0x00000000, 0x05020000, + 0x00000010, 0x91963409, + 0x00000010, 0x205f0000, + 0x00000000, 0x2c1e0000, + 0x00000008, 0x2c800006, + 0x00000008, 0x2d00006a, + 0x00000008, 0x2d800102, + 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, + 0x00000000, 0x0d7a0000, + 0x00000018, 0x000a0000, + 0x00000010, 0x91de0000, + 0x00000010, 0x001f0000, + 0x00000000, 0x2f80aa00, + 0x00000000, 0x2a000000, + 0x00000000, 0x0d610000, + 0x00000000, 0x03620000, + 0x00000000, 0x2c400000, + 0x00000000, 0x02638c00, + 0x00000000, 0x26460000, + 0x00000008, 0x02040012, + 0x00000010, 0xb9060827, + 0x00000000, 0x0f580000, + 0x00000000, 0x0a640000, + 0x00000000, 0x0ae50000, + 0x00000009, 0x0b66ffff, + 0x00000000, 0x0c000000, + 0x00000000, 0x0b800000, + 0x00000008, 0x0cc60012, + 0x00000018, 0x8000ffcb, + 0x00000008, 0x0f800003, + 0x00000000, 0x00000000, + 0x00000010, 0x009f0000, + 0x00000008, 0x27110012, + 0x00000000, 0x66900000, + 0x00000008, 0xa31b0012, + 0x00000010, 0xb1980003, + 0x00000010, 0x001f0000, + 0x00000008, 0x0f800004, + 0x00000008, 0x22000003, + 0x00000008, 0x2c80000c, + 0x00000008, 0x2d00000c, + 0x00000010, 0x009f0000, + 0x00000000, 0x25960000, + 0x0000000c, 0x29800000, + 0x00000000, 0x06660000, + 0x00000000, 0x86611800, + 0x00000009, 0x0260000f, + 0x0000000f, 0x02040002, + 0x00000010, 0xb60c0803, + 0x0000000c, 0x1fbf0000, + 0x0000000c, 0x33660010, + 0x00000000, 0x32140000, + 0x00000000, 0x32950000, + 0x00000005, 0x73662c00, + 0x00000000, 0x31e32e00, + 0x00000008, 0x2d800010, + 0x00000010, 0x20530000, + 0x00000010, 0x91de0000, + 0x00000018, 0x8000ff90, + 0x00000000, 0x23000000, + 0x00000009, 0x25e6ffff, + 0x00000008, 0x2200000b, + 0x0000000c, 0x69520000, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x00000018, 0x8000ff89, + 0x00000010, 0x91de0000, + 0x00000010, 0x001f0000, + 0x00000000, 0x2f80aa00, + 0x00000000, 0x2a000000, + 0x00000000, 0x2c400000, + 0x00000008, 0x2c800040, + 0x00000008, 0x2d000020, + 0x00000008, 0x2d80011c, + 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, + 0x0000000f, 0x42ea0010, + 0x00000010, 0x004f0004, + 0x00000010, 0xb7469200, + 0x00000008, 0x02490012, + 0x00000010, 0xb5840a00, + 0x00000000, 0x0d610000, + 0x00000010, 0xba66345a, + 0x00000000, 0x03620000, + 0x00000010, 0xb8630c58, + 0x00000008, 0x83050012, + 0x00000010, 0x004f0002, + 0x00000000, 0x03490000, + 0x00000001, 0x83068c00, + 0x00000000, 0x83c60c00, + 0x00000010, 0xb1870010, + 0x00000000, 0x0b6e0000, + 0x00000018, 0x8000ff6b, + 0x00000001, 0x06691400, + 0x00000010, 0x918c0002, + 0x00000008, 0xb4e90001, + 0x00000010, 0xb1e92c4c, + 0x00000000, 0x86692c00, + 0x00000000, 0x02000000, + 0x00000009, 0x02eaffff, + 0x00000010, 0x000c0002, + 0x00000000, 0x02040a00, + 0x0000000f, 0x460c0001, + 0x0000000f, 0x02850001, + 0x00000010, 0x918c01fc, + 0x00000010, 0xb7040e43, + 0x00000000, 0x2c400000, + 0x00000000, 0x0f400000, + 0x00000000, 0x0d610000, + 0x00000000, 0x0a640000, + 0x00000000, 0x0ae50000, + 0x00000009, 0x0b66ffff, + 0x00000000, 0x0c000000, + 0x00000000, 0x0b800000, + 0x00000008, 0x0c860012, + 0x00000008, 0x0f800003, + 0x0000000c, 0x29520000, + 0x00000010, 0x009f0000, + 0x00000008, 0x27110012, + 0x00000000, 0x66900000, + 0x00000000, 0x26460000, + 0x00000000, 0x23060000, + 0x00000010, 0xb1980005, + 0x00000010, 0x001f0000, + 0x00000008, 0x0f800004, + 0x00000000, 0x00000000, + 0x00000010, 0x001f0000, + 0x00000000, 0x32140000, + 0x00000000, 0x32950000, + 0x00000000, 0x31e32e00, + 0x00000005, 0x73662c00, + 0x00000000, 0x25960000, + 0x00000010, 0xb1870016, + 0x0000000c, 0x29800000, + 0x0000000f, 0x0f6b0007, + 0x00000000, 0x0d690000, + 0x00000000, 0x0a6c0000, + 0x00000000, 0x0aed0000, + 0x00000000, 0x0b6e0000, + 0x00000000, 0x0b800000, + 0x00000000, 0x0c870000, + 0x00000008, 0x0f800003, + 0x00000010, 0x20530000, + 0x0000000c, 0x69520001, + 0x00000010, 0x001f0000, + 0x00000000, 0x22c58c00, + 0x00000000, 0x231b0000, + 0x00000000, 0x27110000, + 0x00000000, 0x26900000, + 0x00000010, 0xb8170e03, + 0x0000000c, 0x29800000, + 0x00000018, 0x8000fff6, + 0x00000010, 0xb1980002, + 0x00000008, 0x0f800004, + 0x00000008, 0x2200001a, + 0x00000008, 0x2c80000c, + 0x00000008, 0x2d00000c, + 0x00000008, 0x2d800010, + 0x00000010, 0x001f0000, + 0x00000000, 0x0d6e0000, + 0x00000003, 0xe7cf3400, + 0x0000000c, 0x29800000, + 0x00000010, 0x91de0000, + 0x00000010, 0xb1870007, + 0x00000000, 0x36140000, + 0x00000000, 0x36950000, + 0x00000000, 0x37160000, + 0x00000008, 0x2c800050, + 0x00000008, 0x2d000030, + 0x00000008, 0x2d80000c, + 0x00000010, 0x20530000, + 0x00000018, 0x8000ff1f, + 0x00000000, 0x26460000, + 0x00000000, 0x23000000, + 0x00000009, 0x25e6ffff, + 0x00000000, 0x0b6e0000, + 0x00000003, 0xe7cf2c00, + 0x00000008, 0x2200001b, + 0x0000000c, 0x69520000, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x00000018, 0x8000ff15, + 0x00000000, 0x2fd50000, + 0x00000000, 0x2a000000, + 0x00000010, 0x003f000b, + 0x00000000, 0x06660000, + 0x00000000, 0x86611800, + 0x00000009, 0x026000f0, + 0x00000010, 0xb70c0807, + 0x0000000c, 0x73660010, + 0x00000008, 0x2c800018, + 0x00000008, 0x2d000018, + 0x00000008, 0x2d800002, + 0x0000000c, 0x5fbf0000, + 0x00000010, 0x91de0000, + 0x00000018, 0x8000ff07, + 0x00000000, 0x2fd50000, + 0x00000000, 0x2a000000, + 0x00000000, 0x2c400000, + 0x0000000c, 0x29800000, + 0x00000010, 0x91de0000, + 0x00000008, 0x2c80001a, + 0x00000008, 0x2d00001a, + 0x00000000, 0x33000000, + 0x00000008, 0x2d800002, + 0x00000000, 0x31800000, + 0x00000010, 0x91de0000, + 0x00000008, 0x2c80000c, + 0x00000008, 0x2d00000c, + 0x00000008, 0x2d800004, + 0x00000010, 0x20530000, + 0x00000010, 0x91de0000, + 0x00000018, 0x8000fef6, + 0x00000018, 0x8000fef5, + 0x00000000, 0x2a000000, + 0x00000010, 0x001f0000, + 0x00000000, 0x0f008000, + 0x00000008, 0x0f800007, + 0x00000018, 0x80000014, + 0x00000000, 0x05020000, + 0x00000008, 0x22000009, + 0x00000000, 0x286d0000, + 0x00000000, 0x29000000, + 0x0000000f, 0x65680010, + 0x00000003, 0xf66c9400, + 0x00000010, 0xb972a004, + 0x0000000c, 0x73e70019, + 0x0000000c, 0x21420004, + 0x00000000, 0x3bf60000, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x00000008, 0x22000008, + 0x0000000c, 0x61420004, + 0x00000018, 0x000a0000, + 0x00000000, 0x2a000000, + 0x00000010, 0x001f0000, + 0x0000000f, 0x0f470007, + 0x00000008, 0x0f800008, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x00000018, 0x8000feda, + 0x00000010, 0x91de0000, + 0x00000000, 0x2fd50000, + 0x00000010, 0x001f0000, + 0x00000000, 0x33510000, + 0x00000000, 0x2a000000, + 0x00000010, 0xb1c60023, + 0x0000000f, 0x0f500007, + 0x00000000, 0x0a600000, + 0x00000000, 0x0ae10000, + 0x0000000f, 0x4b620008, + 0x00000009, 0x0b1600ff, + 0x0000000f, 0x4c620010, + 0x00000000, 0x0d620000, + 0x00000009, 0x0d1a00ff, + 0x00000010, 0x07500003, + 0x0000000c, 0x0d1a0008, + 0x0000000c, 0x0b160008, + 0x00000000, 0x0cc60000, + 0x00000000, 0x0b800000, + 0x00000000, 0x06980000, + 0x00000008, 0x0f800003, + 0x00000010, 0x06c20004, + 0x0000000c, 0x29000002, + 0x00000010, 0x26420002, + 0x0000000c, 0x29520003, + 0x00000008, 0x22000001, + 0x00000010, 0x009f0000, + 0x00000000, 0x231b0000, + 0x00000000, 0x27111a00, + 0x00000000, 0x66900000, + 0x0000000c, 0x29520000, + 0x00000010, 0xb1973209, + 0x0000000c, 0x29800000, + 0x00000000, 0x06980000, + 0x00000010, 0x20530000, + 0x0000000c, 0x29520003, + 0x00000000, 0x22c58c00, + 0x00000010, 0x001f0000, + 0x00000008, 0x0f800003, + 0x00000018, 0x8000fff3, + 0x00000010, 0xb1c80013, + 0x00000010, 0xb1c60003, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x0000000c, 0x29520000, + 0x0000000c, 0x29520003, + 0x00000010, 0x06c20002, + 0x0000000c, 0x29520002, + 0x00000000, 0x22c58c00, + 0x00000000, 0x27650000, + 0x00000000, 0x26e40000, + 0x00000008, 0x22000016, + 0x00000010, 0xb1c60003, + 0x00000000, 0x23480000, + 0x00000010, 0xb1800005, + 0x00000000, 0x23480000, + 0x0000000c, 0x29800000, + 0x0000000f, 0x0f500007, + 0x00000018, 0x80000012, + 0x00000008, 0x22000016, + 0x0000000c, 0x29800000, + 0x00000000, 0x30140000, + 0x00000000, 0x30950000, + 0x00000010, 0x07500003, + 0x00000009, 0x0b1600ff, + 0x00000009, 0x0d1a00ff, + 0x0000000f, 0x31160008, + 0x00000000, 0x31623400, + 0x00000003, 0xf1623000, + 0x00000010, 0x205f0000, + 0x00000000, 0x2c510000, + 0x00000009, 0x2cd1007f, + 0x00000008, 0x2cd90000, + 0x00000008, 0x2d000000, + 0x00000008, 0x2d80000c, + 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, + 0x00000010, 0x05c20003, + 0x00000000, 0x33000000, + 0x00000008, 0x0f800007, + 0x00000010, 0x20530000, + 0x00000010, 0x009f0000, + 0x00000018, 0x8000fe87, + 0x00000000, 0x2fd50000, + 0x00000000, 0x2a000000, + 0x0000000f, 0x0f500007, + 0x00000010, 0xb1c6002d, + 0x0000000f, 0x47420008, + 0x00000009, 0x070e000f, + 0x00000008, 0x070e0008, + 0x00000010, 0x001f0000, + 0x00000008, 0x09000001, + 0x00000007, 0x09121c00, + 0x00000003, 0xcbca9200, + 0x00000000, 0x0b97a200, + 0x00000007, 0x42171c00, + 0x00000000, 0x0b040000, + 0x0000000f, 0x0a840003, + 0x00000000, 0x0a959c00, + 0x00000000, 0x4a009a00, + 0x00000008, 0x82120001, + 0x00000001, 0x0c170800, + 0x00000000, 0x0c978c00, + 0x00000000, 0x02180000, + 0x00000008, 0x0d00ffff, + 0x00000008, 0x0f800006, + 0x0000000c, 0x29000000, + 0x00000010, 0x06c20004, + 0x0000000c, 0x29520002, + 0x00000010, 0x26420002, + 0x0000000c, 0x29520003, + 0x00000008, 0x22000001, + 0x00000010, 0x009f0000, + 0x00000010, 0xb197320c, + 0x00000000, 0x231b0000, + 0x00000000, 0x27110800, + 0x00000000, 0x66900000, + 0x0000000c, 0x29800000, + 0x00000000, 0x02180000, + 0x00000010, 0x20530000, + 0x0000000c, 0x29520003, + 0x00000000, 0x22c53600, + 0x00000010, 0x001f0000, + 0x00000008, 0x0f800006, + 0x00000018, 0x8000fff4, + 0x00000000, 0x231b0000, + 0x00000000, 0x27110800, + 0x00000000, 0x66900000, + 0x00000010, 0xb1c8000b, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x0000000c, 0x29520000, + 0x0000000c, 0x29520003, + 0x00000010, 0x06c20002, + 0x0000000c, 0x29520002, + 0x00000000, 0x22c58c00, + 0x00000000, 0x27650000, + 0x00000000, 0x26e40000, + 0x00000000, 0x23480000, + 0x00000008, 0x22000017, + 0x0000000c, 0x29800000, + 0x00000010, 0x001f0000, + 0x00000010, 0x20530000, + 0x00000018, 0x8000fe4a, +}; + + +int bce_TXP_b09FwReleaseMajor = 0x1; +int bce_TXP_b09FwReleaseMinor = 0x0; +int bce_TXP_b09FwReleaseFix = 0x0; +u32 bce_TXP_b09FwStartAddr = 0x08000098; +u32 bce_TXP_b09FwTextAddr = 0x08000000; +int bce_TXP_b09FwTextLen = 0x3afc; +u32 bce_TXP_b09FwDataAddr = 0x00000000; +int bce_TXP_b09FwDataLen = 0x0; +u32 bce_TXP_b09FwRodataAddr = 0x08003afc; +int bce_TXP_b09FwRodataLen = 0x30; +u32 bce_TXP_b09FwBssAddr = 0x08003bcc; +int bce_TXP_b09FwBssLen = 0x24c; +u32 bce_TXP_b09FwSbssAddr = 0x08003b60; +int bce_TXP_b09FwSbssLen = 0x6c; +u32 bce_TXP_b09FwSDataAddr = 0x00000000; +int bce_TXP_b09FwSDataLen = 0x0; +u32 bce_TXP_b09FwText[(0x3afc/4) + 1] = { +0xa000026, +0x0, 0x0, 0xd, 0x74787034, +0x2e362e31, 0x36000000, 0x4061000, 0xa, +0x136, 0xea60, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x1d, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x10000003, 0x0, +0xd, 0xd, 0x3c020800, 0x24423b60, +0x3c030800, 0x24633e18, 0xac400000, 0x43202b, +0x1480fffd, 0x24420004, 0x3c1d0800, 0x37bd7ffc, +0x3a0f021, 0x3c100800, 0x26100098, 0x3c1c0800, +0x279c3b60, 0xe0004ae, 0x0, 0xd, +0x3c058000, 0x8f830030, 0x34a80070, 0x8d070000, +0x833025, 0x3c029000, 0xc22025, 0xaca40020, +0xaf870024, 0x3c048000, 0x8c890020, 0x520fffe, +0x0, 0x34840070, 0x8c850000, 0x3c180800, +0x8f18007c, 0x3c0d0800, 0x8dad0078, 0xa7c823, +0x3195021, 0x7021, 0x159602b, 0x1ae5821, +0x16c3821, 0x3c010800, 0xac2a007c, 0x3c010800, +0xac270078, 0x3e00008, 0x0, 0xa00003d, +0x24040001, 0x8f850030, 0x3c048000, 0x34830001, +0xa31025, 0x3e00008, 0xac820020, 0x3e00008, +0x1021, 0x3084ffff, 0x30a5ffff, 0x10800007, +0x1821, 0x30820001, 0x10400002, 0x42042, +0x651821, 0x1480fffb, 0x52840, 0x3e00008, +0x601021, 0x10c00007, 0x0, 0x8ca20000, +0x24c6ffff, 0x24a50004, 0xac820000, 0x14c0fffb, +0x24840004, 0x3e00008, 0x0, 0x10a00008, +0x24a3ffff, 0xac860000, 0x0, 0x0, +0x2402ffff, 0x2463ffff, 0x1462fffa, 0x24840004, +0x3e00008, 0x0, 0x90aa0031, 0x8fab0010, +0x8cac0040, 0x3c0300ff, 0x8d680004, 0xad6c0020, +0x8cad0044, 0xe06021, 0x3462ffff, 0xad6d0024, +0x8ca70048, 0x3c09ff00, 0x109c024, 0xad670028, +0x8cae004c, 0x182c824, 0x3197825, 0xad6f0004, +0xad6e002c, 0x8cad0038, 0x314a00ff, 0xad6d001c, +0x94a90032, 0x3128ffff, 0xad680010, 0x90a70030, +0xa5600002, 0xa1600004, 0xa1670000, 0x90a30032, +0x306200ff, 0x21982, 0x10600005, 0x24050001, +0x1065000e, 0x0, 0x3e00008, 0xa16a0001, +0x8cd80028, 0x354a0080, 0xad780018, 0x8ccf0014, +0xad6f0014, 0x8cce0030, 0xad6e0008, 0x8cc4002c, +0xa16a0001, 0x3e00008, 0xad64000c, 0x8ccd001c, +0xad6d0018, 0x8cc90014, 0xad690014, 0x8cc80024, +0xad680008, 0x8cc70020, 0xad67000c, 0x8cc20014, +0x8c830070, 0x43c82b, 0x13200007, 0x0, +0x8cc20014, 0x144cffe4, 0x0, 0x354a0080, +0x3e00008, 0xa16a0001, 0x8c820070, 0xa0000c6, +0x0, 0x90890030, 0x27bdfff8, 0x8fa8001c, +0xa3a90000, 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0x3e00008, 0x27bd0020, 0x3c010800, +0xa4203bdc, 0x1040ff95, 0x2001821, 0xa000c10, +0xc01821, 0xa000c08, 0x24030030, 0x3c050800, +0x8ca53bd4, 0xb0682b, 0x11a0ffa8, 0x0, +0x3c040800, 0x94843bdc, 0x857821, 0x1e7702b, +0x11c00007, 0x2ca20004, 0x3c1f6000, 0x8ff95404, +0x3338003f, 0x1700ffe3, 0x24040042, 0x2ca20004, +0x1040ff9a, 0x24040042, 0xa000c73, 0x8fbf0018, +0x1528ffb9, 0x0, 0x8cc20018, 0x3c188000, +0x24190002, 0x58f825, 0xacdf0018, 0x37040a00, +0xa0d90068, 0x9089003c, 0x240f0004, 0xa01021, +0x31280020, 0x3c010800, 0xa02f3c31, 0x11000002, +0x24050010, 0x24020001, 0x3c010800, 0xac223bcc, +0xa000c69, 0x3c1f8000, 0x8f880014, 0x8c890060, +0x109282b, 0x14a00002, 0x1008821, 0x8c910060, +0x3c0b8000, 0x8d640e18, 0x240a0001, 0x2202821, +0x2203021, 0xa38a0008, 0xe000ad9, 0x2208021, +0xa000bf7, 0xaf820018, 0xa1823, 0x12200007, +0x30640003, 0x3c0d8000, 0x35a70980, 0x90ec007c, +0x318b0004, 0x15600019, 0x248e0004, 0x3c010800, +0xa4243bf2, 0x3c180800, 0x97183bf2, 0x3052021, +0xc4782b, 0x11e0ff6c, 0x8f840010, 0x2ca60005, +0x14c0ffa4, 0x24040042, 0x30b90003, 0x17200002, +0xb91823, 0x24a3fffc, 0x3c010800, 0xac233bd4, +0x3c010800, 0xa4203bf2, 0xa000c36, 0x602821, +0xac3824, 0xa000c5c, 0xec1826, 0x3c010800, +0xa42e3bf2, 0xa000cc6, 0x0, 0x3c010800, +0xac203bd4, 0xa000c72, 0x24040042, 0x8f830014, +0x3c0b8000, 0x356a0a00, 0x14600006, 0x1021, +0x91460030, 0x24050005, 0x30c400ff, 0x10850003, +0x0, 0x3e00008, 0x0, 0x91490048, +0x312800ff, 0x839c2, 0x14e0fffa, 0x3c048008, +0x3c060800, 0x94c63bdc, 0x3c030800, 0x8c633bf4, +0x3c050800, 0x8ca53bd4, 0x3c180800, 0x97183bf2, +0x66c821, 0x8c8e0004, 0x3257821, 0x1f86821, +0x1ae6023, 0x1980001d, 0x0, 0x9158004c, +0x8f8d0020, 0x956e0e10, 0x330f00ff, 0x8da90004, +0x1cf3023, 0x8daa0000, 0x30cfffff, 0xf6100, +0x12c2821, 0x3821, 0x1472021, 0xac182b, +0x83c821, 0xada50004, 0xadb90000, 0x91b8000a, +0x1f87021, 0xa1ae000a, 0x956c0e12, 0x8f8a0020, +0xa54c0008, 0x95490038, 0x25280001, 0xa5480038, +0x9147000d, 0x34eb0008, 0xa14b000d, 0x3e00008, +0x0, 0x27bdffd8, 0xafb00018, 0x938f0008, +0x8fb00014, 0x3c087fff, 0x8f870010, 0x3c0c8000, +0x3518ffff, 0xafbf0020, 0xafb1001c, 0x35990a00, +0x2181824, 0x932a003c, 0xf5fc0, 0x3c02bfff, +0x2cf00001, 0x3449ffff, 0x6bf825, 0x3c080800, +0x8d083bf4, 0x8f99001c, 0x3c180800, 0x97183bea, +0x3e95824, 0x107f80, 0x3c07efff, 0x3c05f0ff, +0x16f1825, 0x3c118000, 0x31490020, 0x34e2ffff, +0x34adffff, 0x362e0980, 0x27a50010, 0x24060002, +0x1194023, 0x270a0002, 0x621824, 0x808021, +0x15200002, 0x5821, 0x8d8b0e1c, 0xa7aa0012, +0x500003a, 0x24070000, 0x30ef00ff, 0xf3f00, +0x674025, 0x3c028008, 0xafa80014, 0x344b0080, +0x916a0068, 0x3c0f0800, 0x91ef3bf1, 0x3c09dfff, +0x353fffff, 0xa602b, 0x3c020800, 0x94423be4, +0xa3af0011, 0x11fc024, 0xccf40, 0x3191825, +0x8fa70010, 0xafa30014, 0x3c1f0800, 0x93ff3bf3, +0xa7a20016, 0x8fa80014, 0xed4824, 0x3c0b0100, +0x3c0a0fff, 0x12bc825, 0x33f80003, 0x354cffff, +0x10d7824, 0x3c027000, 0x32c3824, 0x181e00, +0xe24825, 0x1e35825, 0xafab0014, 0xafa90010, +0x91df007c, 0xa3bf0015, 0xe000072, 0x0, +0x362d0a00, 0x91a6003c, 0x30c40020, 0x10800006, +0x26020008, 0x3c110800, 0x96313be0, 0x262effff, +0x3c010800, 0xa42e3be0, 0x8fbf0020, 0x8fb1001c, +0x8fb00018, 0x3e00008, 0x27bd0028, 0x8f8a0018, +0x16a602b, 0x5580ffc4, 0x24070001, 0xa000d50, +0x30ef00ff, 0x93830008, 0x3c028000, 0x27bdffd8, +0x34480a00, 0x805021, 0xafbf0020, 0x34460ac0, +0x1002821, 0x1060000e, 0x34440980, 0x91070030, +0x240b0005, 0x8f89000c, 0x30ec003f, 0x118b000b, +0x3821, 0xafa90010, 0x3c0b8008, 0x8d69006c, +0xafaa0018, 0xe00013a, 0xafa90014, 0xa3800008, +0x8fbf0020, 0x3e00008, 0x27bd0028, 0x8d1f0048, +0x3c180800, 0x8f183bd4, 0x8f990014, 0x3c027fff, +0x8d080044, 0x3443ffff, 0xafa90010, 0x3c0b8008, +0x8d69006c, 0x3e37024, 0x3197821, 0x1cf6823, +0x1a83821, 0xafaa0018, 0xe00013a, 0xafa90014, +0xa000da5, 0xa3800008, 0x3c058000, 0x34a60a00, +0x90c7003c, 0x3c060800, 0x94c63bf2, 0x3c020800, +0x8c423bec, 0x30e30020, 0x62400, 0x10600031, +0x444825, 0x3c088008, 0x35050080, 0x90a30068, +0x6821, 0x240c0001, 0x5021, 0x240b0001, +0x3c188000, 0x370f0070, 0x8de80000, 0x3c078000, +0xaf880024, 0x8cf90178, 0x720fffe, 0x34e50070, +0x8ca20000, 0x3c030800, 0x8c630074, 0x3c0f0800, +0x8def0070, 0x482023, 0x642821, 0xc021, +0xa4302b, 0x1f87021, 0x1c64021, 0x3c010800, +0xac250074, 0x3c010800, 0xac280070, 0xacec0148, +0x3c020800, 0x8c423bf4, 0xa4ea0144, 0xa4eb0146, +0xace2014c, 0x3c040800, 0x90843bf1, 0x3c038008, +0xa0e40152, 0xace90154, 0xa4ed0158, 0x346d0080, +0x91ac004c, 0x3c091000, 0xa0ec016d, 0x3e00008, +0xace90178, 0x8cac0e1c, 0x3c0b0800, 0x8d6b3bd4, +0x94aa0e16, 0x94ae0e14, 0x1666821, 0x314bffff, +0xa000dcd, 0x31caffff, 0x3c048000, 0x34830a00, +0x9065003c, 0x30a20020, 0x1040002b, 0x0, +0x5821, 0x5021, 0x4821, 0x3c088000, +0x35040070, 0x8c880000, 0x3c078000, 0xaf880024, +0x8cec0178, 0x580fffe, 0x34ee0070, 0x8dcd0000, +0x3c050800, 0x8ca50074, 0x3c040800, 0x8c840070, +0x1a86023, 0xacc021, 0x1021, 0x30c302b, +0x82c821, 0x3267821, 0x3c010800, 0xac380074, +0x3c010800, 0xac2f0070, 0xaceb0148, 0x3c0e0800, +0x8dce3bf4, 0x240dff91, 0x240b0040, 0xa4e90144, +0xa4ea0146, 0xacee014c, 0xa0ed0152, 0xaceb0154, +0xa4e00158, 0x90ea0109, 0x3c091000, 0xa0ea016d, +0x3e00008, 0xace90178, 0x8c8b0e18, 0x94870e12, +0x94860e10, 0x30eaffff, 0xa000e08, 0x30c9ffff, +0x3c048000, 0x34830a00, 0x9065003c, 0x30a20020, +0x10400039, 0x27bdfff8, 0x240c0001, 0x5021, +0x240b0001, 0x3c088000, 0x35040070, 0x8c890000, +0x3c088000, 0xaf890024, 0x8d0d0178, 0x5a0fffe, +0x350e0070, 0x8dc70000, 0x3c050800, 0x8ca50074, +0x3c040800, 0x8c840070, 0xe96823, 0xadc021, +0x1021, 0x30d302b, 0x82c821, 0x3267821, +0x3c010800, 0xac380074, 0x3c010800, 0xac2f0070, +0x91090109, 0x3c0e0800, 0x91ce3c31, 0x3c0380ff, +0xa3a90003, 0x8fad0000, 0x31c7007f, 0x3462ffff, +0x1a82025, 0xafa40000, 0x9106010a, 0xa3a00002, +0x7ce00, 0xa3a60001, 0x8fa50000, 0x240e3000, +0x3c091000, 0xa2c024, 0x3197825, 0xad0f014c, +0x27bd0008, 0xad0e0154, 0xa5000158, 0xad0c0148, +0xa50a0144, 0x240aff80, 0xa50b0146, 0xa10a0152, +0x3e00008, 0xad090178, 0x8c8c0e18, 0x94870e12, +0x94860e10, 0x30ebffff, 0xa000e3e, 0x30caffff, +0x27bdffe8, 0xafb00010, 0x3c108000, 0xafbf0014, +0x36180a00, 0x970f0032, 0xe000ad5, 0x31e43fff, +0x8e0e0100, 0x240dff80, 0x3c042000, 0x1c25821, +0x16d6024, 0xc4940, 0x316a007f, 0x12a4025, +0x1043825, 0x3c048008, 0xae070830, 0x34860080, +0x90c50068, 0x24030002, 0x30a200ff, 0x10430004, +0x8f9f000c, 0x8f990010, 0xac9f0068, 0xac990064, +0x8fbf0014, 0x8fb00010, 0x3e00008, 0x27bd0018, +0x3c0a0800, 0x254a37fc, 0x3c090800, 0x252938d4, +0x3c080800, 0x25082c74, 0x3c070800, 0x24e739e4, +0x3c060800, 0x24c63638, 0x3c050800, 0x24a53390, +0x3c040800, 0x24842fa0, 0x3c030800, 0x246336ec, +0x3c020800, 0x24423488, 0x3c010800, 0xac2a3dfc, +0x3c010800, 0xac293df8, 0x3c010800, 0xac283df4, +0x3c010800, 0xac273e00, 0x3c010800, 0xac263e10, +0x3c010800, 0xac253e08, 0x3c010800, 0xac243e04, +0x3c010800, 0xac233e14, 0x3c010800, 0xac223e0c, +0x3e00008, 0x0, 0x0 }; +u32 bce_TXP_b09FwData[(0x0/4) + 1] = { 0x0 }; +u32 bce_TXP_b09FwRodata[(0x30/4) + 1] = { +0x80000940, 0x80000900, 0x80080100, +0x80080080, 0x80080000, 0x800e0000, 0x80080080, +0x80080000, 0x80000a80, 0x80000a00, 0x80000980, +0x80000900, 0x0 }; +u32 bce_TXP_b09FwBss[(0x24c/4) + 1] = { 0x0 }; +u32 bce_TXP_b09FwSbss[(0x6c/4) + 1] = { 0x0 }; +u32 bce_TXP_b09FwSdata[(0x0/4) + 1] = { 0x0 }; + + +int bce_TPAT_b09FwReleaseMajor = 0x1; +int bce_TPAT_b09FwReleaseMinor = 0x0; +int bce_TPAT_b09FwReleaseFix = 0x0; +u32 bce_TPAT_b09FwStartAddr = 0x08000488; +u32 bce_TPAT_b09FwTextAddr = 0x08000400; +int bce_TPAT_b09FwTextLen = 0x13a4; +u32 bce_TPAT_b09FwDataAddr = 0x00000000; +int bce_TPAT_b09FwDataLen = 0x0; +u32 bce_TPAT_b09FwRodataAddr = 0x080017a4; +int bce_TPAT_b09FwRodataLen = 0x4; +u32 bce_TPAT_b09FwBssAddr = 0x08001800; +int bce_TPAT_b09FwBssLen = 0x12b4; +u32 bce_TPAT_b09FwSbssAddr = 0x080017c0; +int bce_TPAT_b09FwSbssLen = 0x40; +u32 bce_TPAT_b09FwSDataAddr = 0x00000000; +int bce_TPAT_b09FwSDataLen = 0x0; +u32 bce_TPAT_b09FwText[(0x13a4/4) + 1] = { +0xa000122, +0x0, 0x0, 0xd, 0x74706134, +0x2e362e31, 0x36000000, 0x4061001, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x10000003, 0x0, +0xd, 0xd, 0x3c020800, 0x244217c0, +0x3c030800, 0x24632ab4, 0xac400000, 0x43202b, +0x1480fffd, 0x24420004, 0x3c1d0800, 0x37bd2ffc, +0x3a0f021, 0x3c100800, 0x26100488, 0x3c1c0800, +0x279c17c0, 0xe00025e, 0x0, 0xd, +0x2402ff80, 0x27bdffe0, 0x821024, 0xafb00010, +0xaf420020, 0xafbf0018, 0xafb10014, 0x93650004, +0x3084007f, 0x3441821, 0x3c020008, 0x621821, +0x30a50020, 0x3608021, 0x3c080111, 0x277b0008, +0x14a00002, 0x2466005c, 0x24660058, 0x92020004, +0x97430104, 0x92040004, 0x3047000f, 0x3063ffff, +0x30840040, 0x672823, 0x10800009, 0x4821, +0x92020005, 0x30420004, 0x10400005, 0x0, +0x10a00003, 0x0, 0x24a5fffc, 0x24090004, +0x92020005, 0x30420004, 0x10400012, 0x0, +0x10a00010, 0x0, 0x96020002, 0xa72021, +0x1044025, 0x2442fffe, 0xa7421016, 0x92030004, +0x2402ff80, 0x431024, 0x304200ff, 0x10400003, +0x3c020400, 0xa000172, 0x1024025, 0x8cc20000, +0xaf421018, 0x8f420178, 0x440fffe, 0x2402000a, +0xa7420140, 0x96020002, 0x24040009, 0x30420007, +0x21023, 0x30420007, 0xa7420142, 0x96020002, +0x2442fffe, 0xa7420144, 0xa7400146, 0x97420104, +0xa7420148, 0x8f420108, 0x30420020, 0x50400001, +0x24040001, 0x92020004, 0x30420010, 0x14400002, +0x34830010, 0x801821, 0xa743014a, 0x0, +0x0, 0x0, 0x0, 0xaf481000, +0x0, 0x0, 0x0, 0x0, +0x8f421000, 0x441fffe, 0x3102ffff, 0x10400007, +0x0, 0x92020004, 0x30420040, 0x14400003, +0x0, 0x8f421018, 0xacc20000, 0x96020006, +0x3042ffff, 0x24420002, 0x21043, 0x21040, +0x3628821, 0x96220000, 0x1120000d, 0x3044ffff, +0xa71021, 0x8f83003c, 0x8f45101c, 0x21082, +0x21080, 0x431021, 0xac450000, 0x30a6ffff, +0xe0005b7, 0x52c02, 0x402021, 0xa6220000, +0x92030004, 0x2402ff80, 0x431024, 0x304200ff, +0x1040001f, 0x0, 0x92020005, 0x30420002, +0x1040001b, 0x0, 0x9742100c, 0x2442fffe, +0xa7421016, 0x0, 0x3c020400, 0x34420030, +0xaf421000, 0x0, 0x0, 0x0, +0x0, 0x8f421000, 0x441fffe, 0x0, +0x9742100c, 0x8f45101c, 0x3042ffff, 0x24420030, +0x21082, 0x21080, 0x5b1021, 0xac450000, +0x30a6ffff, 0xe0005b7, 0x52c02, 0xa6220000, +0x96040002, 0x24840008, 0xe0001e7, 0x3084ffff, +0x97440104, 0xe0001f5, 0x3084ffff, 0x8fbf0018, +0x8fb10014, 0x8fb00010, 0x3c021000, 0x27bd0020, +0x3e00008, 0xaf420178, 0x3084ffff, 0x30820007, +0x8f850024, 0x10400002, 0x24830007, 0x3064fff8, +0xa41021, 0x30421fff, 0x3421821, 0x247b4000, +0xaf850028, 0xaf820024, 0x3e00008, 0xaf420084, +0x3084ffff, 0x3082000f, 0x8f85002c, 0x8f860034, +0x10400002, 0x2483000f, 0x3064fff0, 0xa41021, +0x46182b, 0xaf850030, 0x462023, 0x14600002, +0xaf82002c, 0xaf84002c, 0x8f82002c, 0x34048000, +0x3421821, 0x641821, 0xaf83003c, 0x3e00008, +0xaf420080, 0x8f820014, 0x10400008, 0x8f820004, +0x8f82ffe4, 0x14400005, 0x8f820004, 0x3c02ffbf, +0x3442ffff, 0x822024, 0x8f820004, 0x30430006, +0x24020002, 0x1062000f, 0x3c020101, 0x2c620003, +0x50400005, 0x24020004, 0x1060000f, 0x3c020001, +0xa00022e, 0x0, 0x10620005, 0x24020006, +0x1462000c, 0x3c020111, 0xa000227, 0x821025, +0x3c020011, 0x821025, 0xaf421000, 0x24020001, +0xa00022e, 0xaf82000c, 0x821025, 0xaf421000, +0xaf80000c, 0x0, 0x0, 0x0, +0x3e00008, 0x0, 0x8f82000c, 0x10400004, +0x0, 0x8f421000, 0x441fffe, 0x0, +0x3e00008, 0x0, 0x8f820010, 0x229c2, +0x24a3fff0, 0x31842, 0x2444f800, 0x31140, +0x431021, 0x21080, 0x431021, 0x21080, +0x3c030800, 0x24631800, 0x2c840301, 0x14800013, +0x433021, 0x8f840018, 0xa4102b, 0x1440000f, +0x3021, 0xa41023, 0x21940, 0x621821, +0x31880, 0x621821, 0x8f82001c, 0x821021, +0x2442ffff, 0x45102b, 0x14400004, 0x31880, +0x3c020800, 0x24421a14, 0x623021, 0x3e00008, +0xc01021, 0x27bdffe0, 0xafbf0018, 0xafb10014, +0xafb00010, 0x3c046008, 0x8c825000, 0x2403ff7f, +0x3c066000, 0x431024, 0x3442380c, 0xac825000, +0x8cc24c1c, 0x3c1a8000, 0x21602, 0x3042000f, +0x10400007, 0xaf82001c, 0x8cc34c1c, 0x3c02001f, +0x3442fc00, 0x621824, 0x319c2, 0xaf830018, +0x8f420008, 0x275b4000, 0x34420001, 0xaf420008, +0xaf800024, 0x3c02601c, 0xaf400080, 0xaf400084, +0x8c450008, 0x8cc30808, 0x34028000, 0x3422021, +0x2402fff0, 0x621824, 0x3c020080, 0x3c010800, +0xac220420, 0x3c025709, 0xaf84003c, 0x14620004, +0xaf850034, 0x24020001, 0xa00028e, 0xaf820014, +0xaf800014, 0x3c028000, 0x34440070, 0x8c830000, +0x8f420000, 0x38420001, 0x30420001, 0x10400018, +0xaf830038, 0x804021, 0x603021, 0x8d070000, +0x3c050800, 0x8ca5045c, 0x3c040800, 0x8c840458, +0xe63023, 0x1021, 0xa62821, 0xa6302b, +0x822021, 0x862021, 0x3c010800, 0xac25045c, +0x3c010800, 0xac240458, 0x8f420000, 0x38420001, +0x30420001, 0x1440ffed, 0xe03021, 0xaf870038, +0x3c028000, 0x34420070, 0x8c470000, 0x8f860038, +0x3c050800, 0x8ca5045c, 0x3c040800, 0x8c840458, +0xe63823, 0x1021, 0xa72821, 0x822021, +0x8f820014, 0xa7302b, 0x862021, 0x3c010800, +0xac25045c, 0x3c010800, 0xac240458, 0x10400016, +0x0, 0x97420104, 0x10400005, 0x8f830000, +0x14600007, 0x2462ffff, 0xa0002d0, 0x2c62000a, +0x2c620010, 0x50400004, 0x8f830000, 0x24620001, +0xaf820000, 0x8f830000, 0x2c62000a, 0x14400003, +0x2c620007, 0xa0002d7, 0xaf80ffe4, 0x10400002, +0x24020001, 0xaf82ffe4, 0x8f430108, 0x8f440100, +0x30622000, 0xaf830004, 0x10400008, 0xaf840010, +0x3c020800, 0x8c42042c, 0x24420001, 0x3c010800, +0xac22042c, 0xa0005b3, 0x3c024000, 0x30650200, +0x14a00003, 0x24020f00, 0x14820260, 0x24020d00, +0x97420104, 0x104002c8, 0x3c024000, 0x30624000, +0x144000ad, 0x8f82003c, 0x8c440008, 0x8f420178, +0x440fffe, 0x24020800, 0xaf420178, 0x24020008, +0xa7420140, 0xa7400142, 0x97420104, 0x8f840004, +0x3051ffff, 0x30820001, 0x10400007, 0x2208021, +0x2623fffe, 0x24020002, 0x3070ffff, 0xa7420146, +0xa000304, 0xa7430148, 0xa7400146, 0x3c020800, +0x8c42043c, 0x1440000d, 0x8f830010, 0x30820020, +0x14400002, 0x24030009, 0x24030001, 0x602021, +0x8f830010, 0x24020900, 0x50620001, 0x34840004, +0xa744014a, 0xa00031f, 0x0, 0x24020f00, +0x14620005, 0x30820020, 0x14400006, 0x2403000d, +0xa00031e, 0x24030005, 0x14400002, 0x24030009, +0x24030001, 0xa743014a, 0x3c020800, 0x8c420420, +0x3c040048, 0xe00020a, 0x442025, 0xe000233, +0x0, 0x8f82000c, 0x1040003e, 0x0, +0x8f421000, 0x3c030020, 0x431024, 0x10400039, +0x8f820004, 0x30420002, 0x10400036, 0x0, +0x97421014, 0x14400033, 0x0, 0x97421008, +0x8f88003c, 0x3042ffff, 0x24420006, 0x21882, +0x33880, 0xe83021, 0x30430001, 0x8cc40000, +0x10600004, 0x30420003, 0xd, 0xa000360, +0xe81021, 0x54400010, 0x3084ffff, 0x3c05ffff, +0x852024, 0x851826, 0x3182b, 0x4102b, +0x431024, 0x10400005, 0x0, 0x0, +0xd, 0x0, 0x240001cb, 0x8cc20000, +0xa00035f, 0x452025, 0x3883ffff, 0x3182b, +0x4102b, 0x431024, 0x10400005, 0x0, +0x0, 0xd, 0x0, 0x240001d4, +0x8cc20000, 0x3444ffff, 0xe81021, 0xac440000, +0x3c020800, 0x8c420430, 0x24420001, 0x3c010800, +0xac220430, 0x8f620000, 0x8f84003c, 0xaf820008, +0x8c830000, 0x3402ffff, 0x1462000f, 0x1021, +0x3c050800, 0x8ca50454, 0x3c040800, 0x8c840450, +0xb02821, 0xb0302b, 0x822021, 0x862021, +0x3c010800, 0xac250454, 0x3c010800, 0xac240450, +0xa0005a9, 0x24040008, 0x8c820000, 0x30420100, +0x1040000f, 0x1021, 0x3c050800, 0x8ca5044c, +0x3c040800, 0x8c840448, 0xb02821, 0xb0302b, +0x822021, 0x862021, 0x3c010800, 0xac25044c, +0x3c010800, 0xac240448, 0xa0005a9, 0x24040008, +0x3c050800, 0x8ca50444, 0x3c040800, 0x8c840440, +0xb02821, 0xb0302b, 0x822021, 0x862021, +0x3c010800, 0xac250444, 0x3c010800, 0xac240440, +0xa0005a9, 0x24040008, 0x8f620008, 0x8f620000, +0x21602, 0x304300f0, 0x24020030, 0x10620005, +0x24020040, 0x106200e0, 0x8f820020, 0xa0005b1, +0x24420001, 0x14a00005, 0x0, 0x0, +0xd, 0x0, 0x240001fe, 0x8f420178, +0x440fffe, 0x0, 0xe00023b, 0x0, +0x14400005, 0x408021, 0x0, 0xd, +0x0, 0x24000205, 0x8e020000, 0x10400005, +0x0, 0x0, 0xd, 0x0, +0x24000208, 0x8f62000c, 0x4430003, 0x24020001, +0xa000457, 0xae000000, 0xae020000, 0x8f82003c, +0x8c480008, 0xa2000007, 0x8f65000c, 0x8f640004, +0x30a3ffff, 0x42402, 0x852023, 0x308200ff, +0x431021, 0x24420005, 0x23083, 0x2cc20081, +0xa605000a, 0x14400005, 0xa2040004, 0x0, +0xd, 0x0, 0x24000220, 0x8f85003c, +0xe0005d5, 0x26040014, 0x8f620004, 0x8f430108, +0xa6020008, 0x3c021000, 0x621824, 0x10600008, +0x0, 0x97420104, 0x92030007, 0x2442ffec, +0x34630002, 0x3045ffff, 0xa0003ec, 0xa2030007, +0x97420104, 0x2442fff0, 0x3045ffff, 0x96060008, +0x2cc20013, 0x54400005, 0x92030007, 0x92020007, +0x34420001, 0xa2020007, 0x92030007, 0x24020001, +0x10620005, 0x24020003, 0x1062000b, 0x8f82003c, +0xa000409, 0x30c6ffff, 0x8f82003c, 0x3c04ffff, +0x8c43000c, 0x641824, 0x651825, 0xac43000c, +0xa000409, 0x30c6ffff, 0x3c04ffff, 0x8c430010, +0x641824, 0x651825, 0xac430010, 0x30c6ffff, +0x24c20002, 0x21083, 0xa2020005, 0x8f83003c, +0x304200ff, 0x21080, 0x432821, 0x8ca80000, +0x8ca20000, 0x24030004, 0x21702, 0x14430012, +0x0, 0x97420104, 0x3c03ffff, 0x1031824, +0x3042ffff, 0x461023, 0x2442fffe, 0x624025, +0xaca80000, 0x92030005, 0x306200ff, 0x21080, +0x501021, 0x90420014, 0x3042000f, 0x431021, +0xa00043e, 0xa2020006, 0x8ca40004, 0x97420104, +0x9603000a, 0x3088ffff, 0x3042ffff, 0x461023, +0x2442ffd6, 0x21400, 0x1024025, 0xaca80004, +0x92020007, 0x92040005, 0x24630028, 0x31883, +0x641821, 0x34420004, 0xa2030006, 0xa2020007, +0x8f820004, 0x2403fffb, 0x34420002, 0x431024, +0xaf820004, 0x92030006, 0x8f87003c, 0x31880, +0x701021, 0x8c440020, 0x3c02fff6, 0x3442ffff, +0x824024, 0x671821, 0xae04000c, 0xac68000c, +0x92050006, 0x3c03ff7f, 0x8e02000c, 0x52880, +0xb02021, 0x3463ffff, 0x1033024, 0x94880026, +0xa72821, 0x431024, 0xae02000c, 0xac860020, +0xac880024, 0xaca80010, 0x24020010, 0xa7420140, +0x24020002, 0xa7400142, 0xa7400144, 0xa7420146, +0x97420104, 0x3c040008, 0x2442fffe, 0xa7420148, +0x24020001, 0xe00020a, 0xa742014a, 0x9603000a, +0x92020004, 0x431021, 0x24420002, 0x30420007, +0x21023, 0x30420007, 0xe000233, 0xae020010, +0x8f620000, 0x3c030800, 0x8c630444, 0x24040010, +0xaf820008, 0x97420104, 0x3042ffff, 0x2442fffe, +0x403821, 0x237c3, 0x3c020800, 0x8c420440, +0x671821, 0x67282b, 0x461021, 0x451021, +0x3c010800, 0xac230444, 0x3c010800, 0xac220440, +0xa00053e, 0x0, 0x14a00005, 0x0, +0x0, 0xd, 0x0, 0x2400029e, +0x8f420178, 0x440fffe, 0x0, 0xe00023b, +0x0, 0x14400005, 0x408021, 0x0, +0xd, 0x0, 0x240002a5, 0x8e020000, +0x54400006, 0x92020007, 0x0, 0xd, +0x0, 0x240002a8, 0x92020007, 0x30420004, +0x10400005, 0x8f820004, 0x2403fffb, 0x34420002, +0x431024, 0xaf820004, 0x8f620004, 0x4430008, +0x92020007, 0x92020006, 0x8e03000c, 0xae000000, +0x21080, 0x501021, 0xac430020, 0x92020007, +0x30420004, 0x54400009, 0x9602000a, 0x92020005, +0x3c030001, 0x21080, 0x501021, 0x8c460018, +0xc33021, 0xac460018, 0x9602000a, 0x92060004, +0x27710008, 0x2202021, 0xc23021, 0x24c60005, +0x26050014, 0xe0005d5, 0x63082, 0x92040006, +0x8f650004, 0x3c027fff, 0x42080, 0x912021, +0x8c830004, 0x3442ffff, 0xa22824, 0x651821, +0xac830004, 0x92020007, 0x92040005, 0x92030004, +0x30420004, 0x10400014, 0x96070008, 0x308400ff, +0x42080, 0x912021, 0x8c860004, 0x97420104, +0x9605000a, 0x306300ff, 0x3042ffff, 0x431021, +0x451021, 0x30e3ffff, 0x431023, 0x2442ffd8, +0x30c6ffff, 0x21400, 0xc23025, 0xac860004, +0xa0004f2, 0x92030007, 0x308500ff, 0x52880, +0xb12821, 0x8ca40000, 0x97420104, 0x306300ff, +0x3042ffff, 0x431021, 0x471023, 0x3c03ffff, +0x832024, 0x3042ffff, 0x822025, 0xaca40000, +0x92030007, 0x24020001, 0x10620006, 0x0, +0x24020003, 0x10620011, 0x0, 0xa000515, +0x8e030010, 0x97420104, 0x92030004, 0x9605000a, +0x8e24000c, 0x431021, 0x451021, 0x2442fff2, +0x3c03ffff, 0x832024, 0x3042ffff, 0x822025, +0xae24000c, 0xa000515, 0x8e030010, 0x97420104, +0x92030004, 0x9605000a, 0x8e240010, 0x431021, +0x451021, 0x2442ffee, 0x3c03ffff, 0x832024, +0x3042ffff, 0x822025, 0xae240010, 0x8e030010, +0x2402000a, 0xa7420140, 0xa7430142, 0x9603000a, +0x92020004, 0x3c040040, 0x431021, 0xa7420144, +0xa7400146, 0x97420104, 0xa7420148, 0x24020001, +0xe00020a, 0xa742014a, 0xe000233, 0x0, +0x8f620000, 0x92030004, 0x2021, 0xaf820008, +0x97420104, 0x9606000a, 0x3042ffff, 0x621821, +0x602821, 0x3c030800, 0x8c630444, 0x3c020800, +0x8c420440, 0x651821, 0x441021, 0x65382b, +0x471021, 0x3c010800, 0xac230444, 0x3c010800, +0xac220440, 0x92040004, 0x862021, 0x2484000a, +0x3084ffff, 0xe0001e7, 0x0, 0x97440104, +0x3084ffff, 0xe0001f5, 0x0, 0x3c021000, +0xaf420178, 0xa0005b0, 0x8f820020, 0x14820027, +0x30620006, 0x97420104, 0x10400067, 0x3c024000, +0x30624000, 0x10400005, 0x0, 0x0, +0xd, 0x0, 0x24000396, 0x8f420178, +0x440fffe, 0x24020800, 0xaf420178, 0x24020008, +0xa7420140, 0xa7400142, 0x8f820004, 0x97430104, +0x30420001, 0x10400007, 0x3070ffff, 0x2603fffe, +0x24020002, 0xa7420146, 0xa7430148, 0xa000568, +0x2402000d, 0xa7400146, 0x2402000d, 0xa742014a, +0x8f620000, 0x24040008, 0xaf820008, 0xe0001e7, +0x0, 0xa000542, 0x2002021, 0x10400042, +0x3c024000, 0x93620000, 0x304300f0, 0x24020010, +0x10620005, 0x24020070, 0x10620035, 0x0, +0xa0005b0, 0x8f820020, 0x8f620000, 0x97430104, +0x3050ffff, 0x3071ffff, 0x8f420178, 0x440fffe, +0x32020007, 0x21023, 0x30420007, 0x2403000a, +0x2604fffe, 0xa7430140, 0xa7420142, 0xa7440144, +0xa7400146, 0xa7510148, 0x8f420108, 0x30420020, +0x14400002, 0x24030009, 0x24030001, 0xa743014a, +0xe00020a, 0x3c040040, 0xe000233, 0x0, +0x3c070800, 0x8ce70444, 0x2111021, 0x2442fffe, +0x3c060800, 0x8cc60440, 0x401821, 0xe33821, +0x1021, 0x8f650000, 0xe3402b, 0xc23021, +0x26040008, 0xc83021, 0x3084ffff, 0xaf850008, +0x3c010800, 0xac270444, 0x3c010800, 0xac260440, +0xe0001e7, 0x0, 0xa000542, 0x2202021, +0xe000139, 0x0, 0x8f820020, 0x24420001, +0xaf820020, 0x3c024000, 0xaf420138, 0x0, +0xa00028f, 0x3c028000, 0x3084ffff, 0x30c6ffff, +0x52c00, 0xa62825, 0x3882ffff, 0x451021, +0x45282b, 0x451021, 0x21c02, 0x3042ffff, +0x431021, 0x21c02, 0x3042ffff, 0x431021, +0x3842ffff, 0x3e00008, 0x3042ffff, 0x3084ffff, +0x30a5ffff, 0x1821, 0x10800007, 0x0, +0x30820001, 0x10400002, 0x42042, 0x651821, +0xa0005cb, 0x52840, 0x3e00008, 0x601021, +0x10c00006, 0x24c6ffff, 0x8ca20000, 0x24a50004, +0xac820000, 0xa0005d5, 0x24840004, 0x3e00008, +0x0, 0x10a00008, 0x24a3ffff, 0xac860000, +0x0, 0x0, 0x2402ffff, 0x2463ffff, +0x1462fffa, 0x24840004, 0x3e00008, 0x0, +0x0 }; +u32 bce_TPAT_b09FwData[(0x0/4) + 1] = { 0x0 }; +u32 bce_TPAT_b09FwRodata[(0x4/4) + 1] = { +0x1, +0x0 }; +u32 bce_TPAT_b09FwBss[(0x12b4/4) + 1] = { 0x0 }; +u32 bce_TPAT_b09FwSbss[(0x40/4) + 1] = { 0x0 }; +u32 bce_TPAT_b09FwSdata[(0x0/4) + 1] = { 0x0 }; + + +int bce_COM_b09FwReleaseMajor = 0x1; +int bce_COM_b09FwReleaseMinor = 0x0; +int bce_COM_b09FwReleaseFix = 0x0; +u32 bce_COM_b09FwStartAddr = 0x080000f8; +u32 bce_COM_b09FwTextAddr = 0x08000000; +int bce_COM_b09FwTextLen = 0x4ac8; +u32 bce_COM_b09FwDataAddr = 0x00000000; +int bce_COM_b09FwDataLen = 0x0; +u32 bce_COM_b09FwRodataAddr = 0x08004ac8; +int bce_COM_b09FwRodataLen = 0x30; +u32 bce_COM_b09FwBssAddr = 0x08004b58; +int bce_COM_b09FwBssLen = 0xc0; +u32 bce_COM_b09FwSbssAddr = 0x08004b20; +int bce_COM_b09FwSbssLen = 0x38; +u32 bce_COM_b09FwSDataAddr = 0x00000000; +int bce_COM_b09FwSDataLen = 0x0; +u32 bce_COM_b09FwText[(0x4ac8/4) + 1] = { +0xa00003e, +0x0, 0x0, 0xd, 0x636f6d34, +0x2e362e31, 0x36000000, 0x4061002, 0x0, +0x3, 0x14, 0x32, 0x3, +0x0, 0x0, 0x0, 0x0, +0x0, 0x10, 0x136, 0xea60, +0x1, 0x0, 0x0, 0x0, +0x8, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x2, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x10, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x10000003, 0x0, +0xd, 0xd, 0x3c020800, 0x24424b20, +0x3c030800, 0x24634c18, 0xac400000, 0x43202b, +0x1480fffd, 0x24420004, 0x3c1d0800, 0x37bd9ffc, +0x3a0f021, 0x3c100800, 0x261000f8, 0x3c1c0800, +0x279c4b20, 0xe000273, 0x0, 0xd, +0x27bdffe8, 0x3c028000, 0xafb00010, 0xafbf0014, +0x34500100, 0x92020009, 0x1040001a, 0x24030001, +0x3c020800, 0x8c420020, 0x10400016, 0x1821, +0xe000d71, 0x0, 0x96030008, 0x3c060800, +0x94c64bfe, 0x8e040018, 0x8f82002c, 0x9605000c, +0x31c00, 0x661825, 0xac440000, 0xac450004, +0x24040001, 0xac400008, 0xac40000c, 0xac400010, +0xac400014, 0xac400018, 0xe000d98, 0xac43001c, +0x1821, 0x8fbf0014, 0x8fb00010, 0x601021, +0x3e00008, 0x27bd0018, 0x27bdffe8, 0xafbf0010, +0x3c028000, 0x94420108, 0x30437000, 0x24022000, +0x1062000a, 0x28642001, 0x54800012, 0x8fbf0010, +0x24024000, 0x10620008, 0x24026000, 0x1062000a, +0x8fbf0010, 0xa000097, 0x1021, 0x8fbf0010, +0xa000055, 0x27bd0018, 0xe000433, 0x0, +0xa000096, 0x8fbf0010, 0xe000c81, 0x0, +0x8fbf0010, 0x1021, 0x3e00008, 0x27bd0018, +0x3c020800, 0x8c420020, 0x27bdffe8, 0x10400028, +0xafbf0010, 0xe000d71, 0x0, 0x3c058000, +0x94a20108, 0x94a3010c, 0x8f86002c, 0x3042003e, +0x3063ffff, 0x21400, 0x431025, 0xacc20000, +0x8ca20100, 0x3c070800, 0x94e74bfe, 0x8fbf0010, +0xacc20004, 0x94a30116, 0x94a4010e, 0x3c022000, +0x31c00, 0x3084ffff, 0x641825, 0xacc30008, +0xe23825, 0x94a20110, 0x94a30112, 0x24040001, +0x21400, 0x3063ffff, 0x431025, 0xacc2000c, +0x94a20114, 0x27bd0018, 0x3042ffff, 0xacc20010, +0xacc00014, 0xacc00018, 0xa000d98, 0xacc7001c, +0x8fbf0010, 0x3e00008, 0x27bd0018, 0x3c068000, +0x8cc202b8, 0x24030001, 0x4410008, 0x802821, +0x3c020800, 0x8c420060, 0x24420001, 0x3c010800, +0xac220060, 0x3e00008, 0x601021, 0x8c830020, +0x94820016, 0xacc30280, 0x2442fffc, 0xa4c20284, +0x3c020800, 0x8c42005c, 0x8c840004, 0x94a3000e, +0x24420001, 0x3c010800, 0xac22005c, 0x3c021000, +0xa4c30286, 0xacc40288, 0x1821, 0xacc202b8, +0x3e00008, 0x601021, 0x3c020800, 0x8c420020, +0x27bdffe8, 0x1040002b, 0xafbf0010, 0xe000d71, +0x0, 0x3c058000, 0x94a20108, 0x94a3010c, +0x8f86002c, 0x3042003e, 0x3063ffff, 0x21400, +0x431025, 0xacc20000, 0x8ca20100, 0x3c070800, +0x94e74bfe, 0x8fbf0010, 0xacc20004, 0x94a30116, +0x94a4010e, 0x3c022000, 0x31c00, 0x3084ffff, +0x641825, 0xacc30008, 0xe23825, 0x94a20110, +0x94a30112, 0x24040001, 0x21400, 0x3063ffff, +0x431025, 0xacc2000c, 0x94a20114, 0x27bd0018, +0x3042ffff, 0xacc20010, 0x8ca20118, 0xacc20014, +0x90a2010b, 0x304200ff, 0xacc20018, 0xa000d98, +0xacc7001c, 0x8fbf0010, 0x3e00008, 0x27bd0018, +0x27bdffe0, 0xafb00010, 0x3c108000, 0xafb20018, +0xafbf001c, 0xafb10014, 0x36120100, 0x9243000b, +0x2402001a, 0x96510008, 0x1462005b, 0x2821, +0x32220001, 0x10400018, 0x0, 0x8e420000, +0x22340, 0x3c02003f, 0x3442ffff, 0x44102b, +0x10400004, 0x3c030040, 0x96420014, 0xa00013b, +0x832021, 0x8e030100, 0x24020100, 0x54620006, +0x96420014, 0x3c028008, 0x94420004, 0x3042000f, +0x22500, 0x96420014, 0x821025, 0xae020080, +0xa00016f, 0x0, 0x3c020800, 0x8c420020, +0x10400028, 0x0, 0xe000d71, 0x0, +0x96020108, 0x9603010c, 0x8f85002c, 0x3042003e, +0x3063ffff, 0x21400, 0x431025, 0xaca20000, +0x8e020100, 0x3c060800, 0x94c64bfe, 0xaca20004, +0x96030116, 0x9604010e, 0x3c022000, 0x31c00, +0x3084ffff, 0x641825, 0xaca30008, 0xc23025, +0x96020110, 0x96030112, 0x24040001, 0x21400, +0x3063ffff, 0x431025, 0xaca2000c, 0x96020114, +0x3042ffff, 0xaca20010, 0x8e020118, 0xaca20014, +0x9202010b, 0x304200ff, 0xaca20018, 0xe000d98, +0xaca6001c, 0x3c020800, 0x8c420040, 0x24420001, +0x3c010800, 0xac220040, 0x3c030800, 0x8c630044, +0x32220002, 0x32240004, 0x24630001, 0x3c010800, +0xac230044, 0x10800008, 0x2282b, 0x2402021, +0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, +0xa0000c8, 0x27bd0020, 0x8fbf001c, 0x8fb20018, +0x8fb10014, 0x8fb00010, 0xa01021, 0x3e00008, +0x27bd0020, 0x27bdffe0, 0x3c058000, 0xafb10014, +0xafbf0018, 0xafb00010, 0x34b10100, 0x9223000b, +0x24020003, 0x14620043, 0x96300008, 0x32020001, +0x10400016, 0x3c02003f, 0x8e230000, 0x3442ffff, +0x32340, 0x44102b, 0x50400005, 0x24020100, +0x96220014, 0x3c030040, 0xa0001a4, 0x832021, +0x54620006, 0x96220014, 0x3c028008, 0x94420004, +0x3042000f, 0x22500, 0x96220014, 0x821025, +0xaca20080, 0xa0001af, 0x0, 0xe000099, +0x0, 0x3c020800, 0x8c420040, 0x24420001, +0x3c010800, 0xac220040, 0x3c020800, 0x8c420044, +0x32030004, 0x24420001, 0x3c010800, 0xac220044, +0x10600007, 0x32020002, 0x2202021, 0x8fbf0018, +0x8fb10014, 0x8fb00010, 0xa0000c8, 0x27bd0020, +0x10400015, 0x8fbf0018, 0x3c048000, 0x8c830104, +0x3c026020, 0xac430014, 0x8c420004, 0x240301fe, +0x304203ff, 0x1443000c, 0x8fbf0018, 0x8c820100, +0x219c2, 0x2462fffc, 0x2c420008, 0x10400003, +0x24040002, 0x2462fffd, 0x442004, 0x3c026000, +0xac446914, 0x8fbf0018, 0x8fb10014, 0x8fb00010, +0x1021, 0x3e00008, 0x27bd0020, 0x3c048000, +0x8c830100, 0x24020100, 0x50620003, 0x3c028008, +0xd, 0x3c028008, 0x94430004, 0x1021, +0x3063000f, 0x31d00, 0x3e00008, 0xac830080, +0x3c028008, 0x34420080, 0x90420000, 0x3e00008, +0xaf800000, 0x3e00008, 0x1021, 0x27bdffe8, +0x3c028000, 0xafbf0014, 0xafb00010, 0x8c430100, +0xac430020, 0x8c430104, 0xac4300a8, 0x9050010b, +0xe0001e5, 0x321000ff, 0x3c020800, 0x24424b58, +0x101880, 0x2e10001d, 0x16000005, 0x621021, +0xe0001ea, 0x401821, 0xa000205, 0x0, +0x8c420000, 0x40f809, 0x0, 0x401821, +0x3c020800, 0x8c420034, 0x10600005, 0x24440001, +0x3c028000, 0x8c430104, 0x3c026020, 0xac430014, +0x8fbf0014, 0x8fb00010, 0x3c034000, 0x3c028000, +0x27bd0018, 0xac430138, 0x3c010800, 0xac240034, +0x3e00008, 0x0, 0x27bdffe8, 0xafbf0014, +0xafb00010, 0x3c108000, 0x8e020140, 0xe0001e5, +0xae020020, 0xe000399, 0x0, 0x3c040800, +0x24840038, 0x8c820000, 0x3c034000, 0xae030178, +0x8fbf0014, 0x8fb00010, 0x24420001, 0x27bd0018, +0x3e00008, 0xac820000, 0x27bdffe8, 0xafb00010, +0xafbf0014, 0x3c108000, 0x8e020180, 0xe0001e5, +0xae020020, 0x8e030180, 0x24020f00, 0x54620008, +0x3c028008, 0x8e020188, 0x3c0300e0, 0x3042ffff, +0x431025, 0xae020080, 0xa00024a, 0x3c028000, +0x34420080, 0x90420000, 0x24030050, 0x304200ff, +0x14430008, 0x3c028000, 0xe000379, 0x0, +0x14400004, 0x3c028000, 0xe000967, 0x0, +0x3c028000, 0x3c034000, 0xac4301b8, 0x3c020800, +0x8c42003c, 0x8fbf0014, 0x8fb00010, 0x24420001, +0x3c010800, 0xac22003c, 0x3e00008, 0x27bd0018, +0x3e00008, 0x1021, 0x3c058000, 0x34a40100, +0x94820008, 0x30430002, 0x30420004, 0x10400003, +0x0, 0xa0000c8, 0x0, 0x10600005, +0x24040001, 0x3c020800, 0x8c420084, 0xa00026f, +0x24420001, 0x8ca30104, 0x8f82000c, 0x10430008, +0x2021, 0x8ca30104, 0x3c020800, 0x8c420084, +0xaf83000c, 0x24420001, 0x3c010800, 0xac220084, +0x3e00008, 0x801021, 0x27bdffe8, 0x3c036010, +0xafbf0014, 0xafb00010, 0x8c655000, 0x2402ff7f, +0x3c048000, 0xa22824, 0x34a5380c, 0x24020037, +0xac655000, 0xac820008, 0x24020c80, 0xac820024, +0x3c060800, 0x24c607a8, 0x3c020800, 0x24424b58, +0x2405001c, 0x24a5ffff, 0xac460000, 0x4a1fffd, +0x24420004, 0x3c020800, 0x244201ec, 0x3c010800, +0xac224b60, 0x3c020800, 0x24420618, 0x3c010800, +0xac224b64, 0x3c020800, 0x24420d10, 0x3c010800, +0xac224ba0, 0x3c020800, 0x24420464, 0x3c030800, +0x24630954, 0x3c040800, 0x2484095c, 0x3c050800, +0x24a52c94, 0x3c010800, 0xac224bc0, 0x3c020800, +0x24420760, 0x3c010800, 0xac264ba8, 0x3c010800, +0xac254bb4, 0x3c010800, 0xac234bbc, 0x3c010800, +0xac244bc4, 0x3c010800, 0xac224bc8, 0x3c010800, +0xac234b5c, 0x3c010800, 0xac204b68, 0x3c010800, +0xac204b6c, 0x3c010800, 0xac204b70, 0x3c010800, +0xac204b74, 0x3c010800, 0xac204b78, 0x3c010800, +0xac204b7c, 0x3c010800, 0xac204b80, 0x3c010800, +0xac244b84, 0x3c010800, 0xac204b88, 0x3c010800, +0xac204b8c, 0x3c010800, 0xac204b90, 0x3c010800, +0xac204b94, 0x3c010800, 0xac204b98, 0x3c010800, +0xac264b9c, 0x3c010800, 0xac264ba4, 0x3c010800, +0xac204bac, 0x3c010800, 0xac254bb0, 0x3c010800, +0xac234bb8, 0xe00055a, 0x0, 0x3c028000, +0x34420070, 0x8c420000, 0xaf820010, 0x3c030800, +0x8c630020, 0x8f820004, 0x10430004, 0x3c058000, +0xe000d37, 0xaf830004, 0x3c058000, 0x34a90070, +0x8d280000, 0x8f840010, 0x3c070800, 0x8ce700bc, +0x3c060800, 0x8cc600b8, 0x1042023, 0x1021, +0xe43821, 0xc23021, 0xe4202b, 0xc43021, +0x3c010800, 0xac2700bc, 0x3c010800, 0xac2600b8, +0x8cb00000, 0x32020007, 0x1040ffe4, 0xaf880010, +0x8d260000, 0x3c050800, 0x8ca500bc, 0x3c040800, +0x8c8400b8, 0xc83023, 0xa62821, 0x1021, +0xa6302b, 0x822021, 0x862021, 0x32070001, +0x3c010800, 0xac2500bc, 0x3c010800, 0xac2400b8, +0x10e00004, 0x32020002, 0xe0001ec, 0x0, +0x32020002, 0x10400004, 0x32020004, 0xe000217, +0x0, 0x32020004, 0x5040ffc5, 0x3c028000, +0xe00022b, 0x0, 0xa0002d5, 0x3c028000, +0x3c029000, 0x34420001, 0x822025, 0x3c028000, +0xac440020, 0x3c038000, 0x8c620020, 0x440fffe, +0x0, 0x3e00008, 0x0, 0x3c028000, +0x34430001, 0x832025, 0x3e00008, 0xac440020, +0x27bdffe0, 0xafb10014, 0xafb00010, 0x808821, +0xafbf0018, 0xe000315, 0x30b000ff, 0x8f83ffac, +0x2202021, 0x90620025, 0x2028025, 0xa0700025, +0x8c700018, 0x3c028000, 0xe000320, 0x2028024, +0x1600000a, 0x8fbf0018, 0x3c038000, 0x8c6201f8, +0x440fffe, 0x24020002, 0xac7101c0, 0xa06201c4, +0x3c021000, 0xac6201f8, 0x8fbf0018, 0x8fb10014, +0x8fb00010, 0x3e00008, 0x27bd0020, 0x27bdffb8, +0xafbf0044, 0xafb00040, 0x3c078000, 0x8ce60104, +0x8f82ffa8, 0xafa60028, 0x8c450020, 0xafa5002c, +0x8c44003c, 0xafa40030, 0x8c430040, 0xafa30034, +0x8c42004c, 0xafa60010, 0xafa50014, 0xafa20020, +0xafa20038, 0x3c020800, 0x8c420020, 0xafa40018, +0xafa3001c, 0x8cf00100, 0x10400019, 0x8fbf0044, +0xe000d71, 0x0, 0x8f83002c, 0x3c050800, +0x94a54bfe, 0x3c024018, 0xac700000, 0xa22825, +0x8fa20010, 0x24040001, 0xac620004, 0x8fa20014, +0xac620008, 0x8fa20018, 0xac62000c, 0x8fa2001c, +0xac620010, 0x8fa20020, 0xac620014, 0x8fa20024, +0xac620018, 0xe000d98, 0xac65001c, 0x8fbf0044, +0x8fb00040, 0x1021, 0x3e00008, 0x27bd0048, +0x27bdffe8, 0xafbf0010, 0x3c038000, 0x94620184, +0x30420200, 0x10400005, 0x2021, 0xe000fe3, +0x0, 0xa00038f, 0x24040001, 0x8c620188, +0x440000a, 0x8fbf0010, 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bce_RXP_b09FwRodataLen = 0x124; +u32 bce_RXP_b09FwBssAddr = 0x08007ab8; +int bce_RXP_b09FwBssLen = 0x20; +u32 bce_RXP_b09FwSbssAddr = 0x08007a60; +int bce_RXP_b09FwSbssLen = 0x58; +u32 bce_RXP_b09FwSDataAddr = 0x00000000; +int bce_RXP_b09FwSDataLen = 0x0; +u32 bce_RXP_b09FwText[(0x7908/4) + 1] = { +0xa000c76, +0x0, 0x0, 0xd, 0x72787034, +0x2e362e31, 0x36000000, 0x4061003, 0x0, +0x1, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 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0xa25823, +0xa001c5f, 0xaf8b0048, 0x2403ffff, 0x11830005, +0x0, 0xe001981, 0x2202021, 0xa001c5f, +0x409021, 0xe001908, 0x2202021, 0xa001c5f, +0x409021, 0xe0019e5, 0x2202021, 0xa001c5f, +0x409021, 0xe00185f, 0x2202021, 0xa001c5f, +0x409021, 0xe001a87, 0x2202021, 0xa001c5f, +0x409021, 0xe0015db, 0x0, 0x97830044, +0x8f850048, 0x306cffff, 0xac3823, 0x2cff0005, +0x53e0ffa8, 0x3062ffff, 0x8f860024, 0xa7800044, +0xacc200dc, 0x3062ffff, 0xa25823, 0xa001c5f, +0xaf8b0048, 0x27bdffd0, 0xafb20018, 0xafb00010, +0xafbf0028, 0xafb50024, 0xafb40020, 0xafb3001c, +0xafb10014, 0x3c0c8000, 0x8d880128, 0x240fff80, +0x3c07800a, 0x25100100, 0x250b0080, 0x20f6824, +0x3205007f, 0x16f7024, 0xad8e0090, 0xa72821, +0xad8d0024, 0x90a700ec, 0x3169007f, 0x3c0a8004, +0x12a1821, 0xa3870042, 0x9066007c, 0x809021, +0xaf83001c, 0x30c20002, 0xaf880054, 0xaf850024, +0xa01821, 0x14400002, 0x24040034, 0x24040030, +0xa3840030, 0x8c6600cc, 0x30f100ff, 0x24040004, +0xaf860048, 0x12240004, 0xa3800050, 0x8e530004, +0x1660001d, 0x3c088000, 0x93870041, 0x30f20001, +0x1240000f, 0x8fbf0028, 0x8cb80074, 0x8ca40074, +0x2419ff80, 0x3198824, 0x117140, 0x308f007f, +0x1cf6025, 0x3c0d2000, 0x18d5825, 0x30f500fe, +0x3c0a8000, 0xad4b0830, 0xa3950041, 0x8fbf0028, +0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018, +0x8fb10014, 0x8fb00010, 0x24020001, 0x27bd0030, +0x3e00008, 0xaca600cc, 0x8e590008, 0x951f0120, +0x8e460010, 0x33fc021, 0x3307ffff, 0x30f5000f, +0x32b40001, 0xaf860020, 0x1680003b, 0xa3950040, +0x35060c00, 0x2a61021, 0xf51823, 0xad030084, +0xaf82004c, 0x8e490004, 0x3128ffff, 0x1100002b, +0xa7890044, 0x2410ff80, 0x3c158000, 0x3c142000, +0xa001d4d, 0x2413fffe, 0x90ae00c4, 0x20e6824, +0x31ac00ff, 0x1580002a, 0x2402021, 0x93840041, +0x97860044, 0x308f0001, 0x11e0000b, 0x2642824, +0x8f890024, 0x8d230074, 0x8d280074, 0xa3850041, +0x701024, 0x2c940, 0x311f007f, 0x33fc025, +0x3148825, 0xaeb10830, 0x10c00010, 0x8f850024, +0x90a700c4, 0x2075824, 0x316a00ff, 0x1540ffe6, +0x2402021, 0xe001c01, 0x97910044, 0x1040ffe8, +0x93840041, 0x2405fffd, 0x54450005, 0x8e430020, +0x2202821, 0xe001586, 0x2402021, 0x8e430020, +0x30700004, 0x1600000a, 0x2414fffb, 0x8f850024, +0xa001d03, 0x8f860048, 0xa001d2e, 0xaf86004c, +0xe00182b, 0x0, 0xa001d3d, 0x93840041, +0x749824, 0xe0015a0, 0xae530020, 0x8f850024, +0xa001d03, 0x8f860048, 0x27bdffd8, 0xafb3001c, +0xafb10014, 0xafbf0020, 0xafb20018, 0xafb00010, +0x3c028000, 0x8c520140, 0x8c4b0148, 0x3c048000, +0xb8c02, 0x322300ff, 0x317300ff, 0x8c8501b8, +0x4a0fffe, 0x34900180, 0xae120000, 0x8c870144, +0x2464fff0, 0x24060002, 0x2c830013, 0xae070004, +0xa6110008, 0xa206000b, 0xae130024, 0x1060004f, +0x8fbf0020, 0x44880, 0x3c0a0800, 0x254a79e0, +0x12a4021, 0x8d040000, 0x800008, 0x0, +0x3c100800, 0x8e1031a8, 0x31733fff, 0x138980, +0x2122821, 0x240cff80, 0xb12021, 0x264d0100, +0x26470080, 0x3c0f8000, 0x3c038004, 0x31a8007f, +0x30e9007f, 0x308a007f, 0x3c0e800a, 0x3c02800c, +0x8cc024, 0x1ac3024, 0xecc824, 0x1239821, +0x1428021, 0xade60024, 0x10ef821, 0xadf90090, +0xadf80028, 0xaf90002c, 0xaf9f0024, 0xaf93001c, +0xe001675, 0x1608021, 0x3c038000, 0x8c6b01b8, +0x560fffe, 0x8f87002c, 0x8f860024, 0x34650180, +0x90f9000d, 0xacb20000, 0x24c20078, 0x19c600, +0x187e03, 0xf9027, 0x1227c2, 0xa4b00006, +0x10800070, 0x240e6082, 0xa4ae0008, 0xa0a00005, +0x240f0002, 0xa0af000b, 0x4c400, 0x8f8b001c, +0x3c192700, 0x3199025, 0xacb20010, 0xaca00014, +0xaca00024, 0xaca00028, 0xaca0002c, 0x8d730038, +0x2411ff80, 0xacb30018, 0x90f0000d, 0x2302824, +0x30a400ff, 0x10800005, 0x8fbf0020, 0x90ec000d, +0x319f007f, 0xa0ff000d, 0x8fbf0020, 0x8fb3001c, +0x8fb20018, 0x8fb10014, 0x8fb00010, 0x3c0a1000, +0x3c0d8000, 0x27bd0028, 0x3e00008, 0xadaa01b8, +0x265f0100, 0x2405ff80, 0x33f8007f, 0x3c068000, +0x3e57824, 0x3c19800a, 0x3192021, 0xaccf0024, +0x908e00c4, 0xae6824, 0x31ac00ff, 0x1180ffea, +0xaf840024, 0x248e0078, 0x95cd0012, 0x3c0c0800, +0x8d8c31a8, 0x3c03800c, 0x31ab3fff, 0x1924821, +0xb5180, 0x12a4021, 0x3104007f, 0x1051024, +0x833821, 0xacc20028, 0xe001675, 0xaf87002c, +0x3c038000, 0x8c6501b8, 0x4a0fffe, 0x0, +0xae120000, 0x8c720144, 0xae120004, 0xa6110008, +0x24110002, 0xa211000b, 0xae130024, 0xa001dd8, +0x8fbf0020, 0x3c126000, 0x8e452c08, 0x3c03f003, +0x3462ffff, 0xa2f824, 0xae5f2c08, 0x8e582c08, +0x3c1901b0, 0x3199825, 0xae532c08, 0xa001dd8, +0x8fbf0020, 0x264d0100, 0x31af007f, 0x3c10800a, +0x240eff80, 0x1f02821, 0x1ae6024, 0x3c0b8000, +0xad6c0024, 0x1660ffb8, 0xaf850024, 0x24110003, +0xa0b100ec, 0xa001dd8, 0x8fbf0020, 0x26480100, +0x310a007f, 0x3c0b800a, 0x2409ff80, 0x14b3021, +0x1092024, 0x3c078000, 0xace40024, 0xa001dd7, +0xaf860024, 0x944d0012, 0x321f3fff, 0x31ac3fff, +0x159fff8d, 0x240e6082, 0x90c300c4, 0x2409ff80, +0x1231024, 0x304a00ff, 0x1140ff87, 0x0, +0x24070004, 0xa0c700ec, 0x8f87002c, 0x24086084, +0x2406000d, 0xa4a80008, 0xa0a60005, 0xa001dc2, +0x240f0002, 0x0 }; +u32 bce_RXP_b09FwData[(0x0/4) + 1] = { 0x0 }; +u32 bce_RXP_b09FwRodata[(0x124/4) + 1] = { +0x5f865437, 0xe4ac62cc, 0x50103a45, +0x36621985, 0xbf14c0e8, 0x1bc27a1e, 0x84f4b556, +0x94ea6fe, 0x7dda01e7, 0xc04d7481, 0x80080100, +0x80080080, 0x80080000, 0x8004fbc, 0x8004fbc, +0x8005098, 0x800506c, 0x8005050, 0x8004f8c, +0x8004f8c, 0x8004f8c, 0x8004fc4, 0x80072bc, +0x8007308, 0x80072c8, 0x80071f0, 0x80072c8, +0x80072f8, 0x80072c8, 0x80071f0, 0x80071f0, +0x80071f0, 0x80071f0, 0x80071f0, 0x80071f0, +0x80071f0, 0x80071f0, 0x80071f0, 0x80071f0, +0x80072e8, 0x80072d8, 0x80071f0, 0x80071f0, +0x80071f0, 0x80071f0, 0x80071f0, 0x80071f0, +0x80071f0, 0x80071f0, 0x80071f0, 0x80071f0, +0x80071f0, 0x80071f0, 0x80072d8, 0x8007890, +0x800775c, 0x8007858, 0x800775c, 0x8007828, +0x8007644, 0x800775c, 0x800775c, 0x800775c, +0x800775c, 0x800775c, 0x800775c, 0x800775c, +0x800775c, 0x800775c, 0x800775c, 0x800775c, +0x800775c, 0x8007784, 0x0 }; +u32 bce_RXP_b09FwBss[(0x20/4) + 1] = { 0x0 }; +u32 bce_RXP_b09FwSbss[(0x58/4) + 1] = { 0x0 }; +u32 bce_RXP_b09FwSdata[(0x0/4) + 1] = { 0x0 }; + + +int bce_CP_b09FwReleaseMajor = 0x1; +int bce_CP_b09FwReleaseMinor = 0x0; +int bce_CP_b09FwReleaseFix = 0x0; +u32 bce_CP_b09FwStartAddr = 0x08000080; +u32 bce_CP_b09FwTextAddr = 0x08000000; +int bce_CP_b09FwTextLen = 0x5418; +u32 bce_CP_b09FwDataAddr = 0x080055a0; +int bce_CP_b09FwDataLen = 0x84; +u32 bce_CP_b09FwRodataAddr = 0x08005418; +int bce_CP_b09FwRodataLen = 0x16c; +u32 bce_CP_b09FwBssAddr = 0x080056b8; +int bce_CP_b09FwBssLen = 0x19c; +u32 bce_CP_b09FwSbssAddr = 0x08005624; +int bce_CP_b09FwSbssLen = 0x91; +u32 bce_CP_b09FwSDataAddr = 0x00000000; +int bce_CP_b09FwSDataLen = 0x0; +u32 bce_CP_b09FwText[(0x5418/4) + 1] = { +0xa000020, +0x0, 0x0, 0xd, 0x6370342e, +0x362e3136, 0x0, 0x4061004, 0x0, +0x0, 0x0, 0x0, 0x0, +0x38003c00, 0x0, 0x0, 0x0, +0x0, 0x20, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x21003800, 0x1, 0x2b, 0x0, +0x10000003, 0x0, 0xd, 0xd, +0x3c020800, 0x24425624, 0x3c030800, 0x24635854, +0xac400000, 0x43202b, 0x1480fffd, 0x24420004, +0x3c1d0800, 0x37bd9ffc, 0x3a0f021, 0x3c100800, +0x26100080, 0x3c1c0800, 0x279c5624, 0xe000286, +0x0, 0xd, 0xa01821, 0x801021, +0x802821, 0x3c046000, 0x3c076000, 0x24060008, +0x10600006, 0x34842078, 0x8c420000, 0xace22008, +0x8c630000, 0x3e00008, 0xace3200c, 0xa000e38, +0x0, 0x24030040, 0x3c026000, 0x3e00008, +0xac432000, 0x3c076000, 0x8f860000, 0x8ce52074, +0x861021, 0xa2182b, 0x14600007, 0x2821, +0x8f8afdfc, 0x24050001, 0xa1440013, 0x8f890000, +0x1244021, 0xaf880000, 0x3e00008, 0xa01021, +0x8f84fdfc, 0x8f850000, 0x90860013, 0x30c300ff, +0xa31023, 0xaf820000, 0x3e00008, 0xa0800013, +0x8f84fdfc, 0x27bdffe8, 0xafb00010, 0xafbf0014, +0x90890011, 0x90870011, 0x24020028, 0x312800ff, +0x39060028, 0x30e300ff, 0x2485002c, 0x2cd00001, +0x10620016, 0x2484001c, 0xe000037, 0x0, +0x8f8ffdfc, 0x3c056000, 0x24020204, 0x95ee003e, +0x95ed003c, 0xe5c00, 0x31acffff, 0x16c5025, +0xacaa2010, 0x52000001, 0x24020004, 0xaca22000, +0x0, 0x0, 0x0, 0x8fbf0014, +0x8fb00010, 0x3e00008, 0x27bd0018, 0xa00006f, +0x2821, 0x8f85fdfc, 0x27bdffd8, 0xafbf0020, +0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, +0x809821, 0x90a40011, 0x24b0001c, 0x24b1002c, +0x308300ff, 0x38620028, 0xe000059, 0x2c520001, +0xe000061, 0x0, 0x2002021, 0x12400002, +0x2202821, 0x2821, 0xe000037, 0x0, +0x8f8dfdfc, 0x3c088000, 0x3c056000, 0x95ac003e, +0x95ab003c, 0x2683025, 0xc4c00, 0x316affff, +0x12a3825, 0xaca72010, 0x24020202, 0xaca62014, +0x52400001, 0x24020002, 0x8fbf0020, 0x8fb3001c, +0x8fb20018, 0x8fb10014, 0x8fb00010, 0x27bd0028, +0x3e00008, 0xaca22000, 0x27bdffe0, 0xafb20018, +0xafb10014, 0xafb00010, 0xafbf001c, 0x3c116000, +0x8e232074, 0x8f820000, 0x30d0ffff, 0x30f2ffff, +0x1062000c, 0x2406008f, 0xe000037, 0x0, +0x3c06801f, 0x104400, 0x34c5ff00, 0x1123825, +0x24040002, 0xae272010, 0x3021, 0xae252014, +0xae242000, 0x8fbf001c, 0x8fb20018, 0x8fb10014, +0x8fb00010, 0xc01021, 0x3e00008, 0x27bd0020, +0x27bdffe0, 0xafb00010, 0x30d0ffff, 0xafbf0018, +0xafb10014, 0xe000037, 0x30f1ffff, 0x102400, +0x918025, 0x3c036000, 0xac702010, 0x8fbf0018, +0x8fb10014, 0x8fb00010, 0x24020004, 0xac622000, +0x27bd0020, 0x3e00008, 0x1021, 0x27bdffe8, +0x3c0c6018, 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0x3c0c8000, 0x27bd0020, 0x3e00008, +0xad8d0024, 0x96580078, 0x9651007a, 0x924e007d, +0x2387826, 0x31e8ffff, 0x31c400c0, 0x14800009, +0x2d110001, 0x16000037, 0x0, 0x5620ffe2, +0x8fbf001c, 0xe000edf, 0x0, 0xa0013d3, +0x8fbf001c, 0x1620ffda, 0x0, 0xe000edf, +0x0, 0x1440ffd8, 0x8fbf001c, 0x16000022, +0x0, 0x925f007d, 0x33e2003f, 0xa242007d, +0xa0013d3, 0x8fbf001c, 0x950900da, 0x8f860064, +0x802821, 0x24040005, 0xe000682, 0x3130ffff, +0x97830076, 0x3c048000, 0x2465ffff, 0xa7850076, +0x8c8a01b8, 0x540fffe, 0x0, 0xac800180, +0x8fbf001c, 0xac900184, 0x8fb20018, 0x8fb10014, +0x8fb00010, 0x3c076013, 0x3c0b1000, 0x240d0c00, +0x3c0c8000, 0x27bd0020, 0xac870188, 0xac8b01b8, +0x3e00008, 0xad8d0024, 0xe000fde, 0x2002021, +0x5040ffb1, 0x8fbf001c, 0x925f007d, 0xa001400, +0x33e2003f, 0xe000fde, 0x2002021, 0x1440ffaa, +0x8fbf001c, 0x12200007, 0x0, 0x9259007d, +0x3330003f, 0x36020040, 0xa242007d, 0xa0013d3, +0x8fbf001c, 0xe000edf, 0x0, 0x5040ff9e, +0x8fbf001c, 0x9259007d, 0x3330003f, 0xa00142f, +0x36020040, 0x411c0, 0x3e00008, 0x24420240, +0x3c050006, 0x851025, 0x3c038000, 0xac620030, +0x0, 0x0, 0x0, 0x3c058000, +0x8ca70000, 0x30e60010, 0x10c0fffd, 0x0, +0x8cab003c, 0x8caa003c, 0x1644821, 0x12a402b, +0x11000004, 0x3c068000, 0x8cad0038, 0x25ac0001, +0xacac0038, 0x8ccf003c, 0x1e47021, 0x3e00008, +0xacce003c, 0x27bdffd0, 0xafb20018, 0xafb00010, +0xafbf0028, 0xafb50024, 0xafb40020, 0xafb3001c, +0xafb10014, 0xa09021, 0x14a00012, 0x808021, +0x8f820024, 0x21880, 0x14600037, 0x24040010, +0xe00143d, 0x0, 0x8fbf0028, 0x8fb50024, +0x8fb40020, 0x8fb3001c, 0x8fb20018, 0x8fb10014, +0x8fb00010, 0x1021, 0x27bd0030, 0x3e00008, +0xaf800024, 0x10a0001e, 0x8821, 0x3c138000, +0x24140020, 0xa00147c, 0x3c150005, 0x26310004, +0x232502b, 0x11400017, 0x2401021, 0x8f880024, +0x8e070000, 0x24040080, 0x84880, 0x1331821, +0x25060001, 0xac670400, 0x26100004, 0x14d4fff3, +0xaf860024, 0xe00143d, 0x0, 0xae750030, +0x0, 0x0, 0x0, 0x0, +0x26310004, 0x232502b, 0x1540ffec, 0xaf800024, +0x2401021, 0x8fbf0028, 0x8fb50024, 0x8fb40020, +0x8fb3001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, +0x3e00008, 0x27bd0030, 0x32023, 0x3085000f, +0xa001465, 0x652021, 0x27bdffd8, 0x3c038000, +0xa03821, 0xac670038, 0xafb10014, 0xac66003c, +0x808821, 0x3c060022, 0xac660030, 0xafb00010, +0xac710028, 0x3c10800c, 0x3c04800c, 0x24050070, +0xafbf0024, 0xafb40020, 0xafb3001c, 0xe001456, +0xafb20018, 0x26040080, 0xe001456, 0x24050080, +0x26040100, 0xe001456, 0x240500f0, 0x3c020800, +0x8c420064, 0x10400013, 0x8021, 0x3c148000, +0x2413ff80, 0x3c12800c, 0xe00143a, 0x2002021, +0x514821, 0x312a007f, 0x1334024, 0x1522021, +0x24050050, 0xae880028, 0xe001456, 0x26100001, +0x3c050800, 0x8ca50064, 0x205202b, 0x1480fff2, +0x0, 0x3c060800, 0x8cc60060, 0x10c00015, +0x8021, 0x3c148000, 0x2413ff80, 0x3c12800c, +0x3c190800, 0x8f390058, 0x10c180, 0x24050040, +0x3317821, 0x1f86821, 0x31ae007f, 0x1b36024, +0x1d22021, 0xae8c0028, 0xe001456, 0x26100001, +0x3c060800, 0x8cc60060, 0x206582b, 0x1560fff0, +0x0, 0x3c100800, 0x8e10005c, 0x2414ff80, +0x3c1f800c, 0x2119821, 0x2749024, 0x3262007f, +0x3c118000, 0x5f2021, 0xae320028, 0xe001456, +0x62840, 0x8fbf0024, 0x8fb40020, 0x8fb3001c, +0x8fb20018, 0x8fb10014, 0x8fb00010, 0x2021, +0x2821, 0xa001456, 0x27bd0028, 0x8f83003c, +0x8c620004, 0x10400003, 0x0, 0x3e00008, +0x0, 0x8c640010, 0x8c650008, 0xa00149f, +0x8c66000c, 0x0 }; +u32 bce_CP_b09FwData[(0x84/4) + 1] = { +0x0, +0x1b, 0xf, 0xa, 0x8, +0x6, 0x5, 0x5, 0x4, +0x4, 0x3, 0x3, 0x3, +0x3, 0x3, 0x2, 0x2, +0x2, 0x2, 0x2, 0x2, +0x2, 0x2, 0x2, 0x2, +0x2, 0x2, 0x2, 0x2, +0x2, 0x1, 0x1, 0x1, +0x0 }; +u32 bce_CP_b09FwRodata[(0x16c/4) + 1] = { +0x80080100, +0x80080080, 0x80080000, 0x8001800, 0x8001800, +0x8001838, 0x8001838, 0x800184c, 0x800181c, +0x8001a74, 0x8001a40, 0x8001acc, 0x8001acc, +0x8001b54, 0x8001a84, 0x80080240, 0x80021c4, +0x8002010, 0x80021ec, 0x8002284, 0x80023d4, +0x8002420, 0x8002544, 0x800244c, 0x80024d0, +0x8002080, 0x80029f8, 0x800299c, 0x800202c, +0x800202c, 0x800202c, 0x80025b8, 0x80025b8, +0x800202c, 0x800202c, 0x8002874, 0x800202c, +0x800202c, 0x800202c, 0x800202c, 0x80028d4, +0x800202c, 0x800202c, 0x800202c, 0x800202c, +0x800202c, 0x800202c, 0x800202c, 0x800202c, +0x800202c, 0x800202c, 0x800202c, 0x800202c, +0x800202c, 0x800202c, 0x8002440, 0x800202c, +0x800202c, 0x8002944, 0x800202c, 0x800202c, +0x800202c, 0x800202c, 0x800202c, 0x800202c, +0x800202c, 0x800202c, 0x800202c, 0x800202c, +0x800202c, 0x800202c, 0x800202c, 0x800202c, +0x800202c, 0x800202c, 0x800202c, 0x8002798, +0x800202c, 0x800202c, 0x8002700, 0x800265c, +0x80037c0, 0x8003794, 0x8003760, 0x8003734, +0x8003714, 0x80036c8, 0x80080100, 0x80080080, +0x80080000, 0x80080080, 0x0 }; +u32 bce_CP_b09FwBss[(0x19c/4) + 1] = { 0x0 }; +u32 bce_CP_b09FwSbss[(0x91/4) + 1] = { 0x0 }; +u32 bce_CP_b09FwSdata[(0x0/4) + 1] = { 0x0 }; + + +u32 bce_xi_rv2p_proc1[] = { + 0x00000010, 0xb1800002, + 0x0000001f, 0x05030100, + 0x00000008, 0xac000001, + 0x00000000, 0x05000000, + 0x0000000c, 0x2f800001, + 0x00000000, 0x2b000000, + 0x00000000, 0x2b800000, + 0x00000010, 0x203f006c, + 0x00000010, 0x213f0003, + 0x00000010, 0x20bf003b, + 0x00000018, 0x8000fffd, + 0x00000010, 0xb1b8b015, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x03d80000, + 0x00000000, 0x2c380000, + 0x00000008, 0x2c800000, + 0x00000008, 0x2d000000, + 0x00000010, 0x91d40000, + 0x00000008, 0x06005555, + 0x00000018, 0x8000007c, + 0x00000008, 0x2d80011c, + 0x00000008, 0x02000001, + 0x00000010, 0x91de0000, + 0x0000000f, 0x42e0001c, + 0x00000010, 0x91840a17, + 0x00000010, 0x08660016, + 0x0000000c, 0x29800002, + 0x0000000c, 0x1f800002, + 0x00000000, 0x2adf0000, + 0x00000008, 0x2a00000f, + 0x00000008, 0x05005555, + 0x00000018, 0x8000ffe8, + 0x00000008, 0x02000001, + 0x0000000f, 0x42e0001c, + 0x00000010, 0x91840a19, + 0x00000008, 0x2c800006, + 0x00000008, 0x2d000006, + 0x00000010, 0x91d40000, + 0x00000008, 0x2d800106, + 0x00000018, 0x80000070, + 0x00000010, 0x08660013, + 0x00000018, 0x8000fff1, + 0x00000008, 0xb1000001, + 0x00000008, 0x2c80010c, + 0x00000008, 0x2d000008, + 0x00000008, 0x2d800001, + 0x00000018, 0x80000069, + 0x0000000b, 0x2fdf0002, + 0x0000000c, 0x1f800002, + 0x00000000, 0x2c070000, + 0x00000010, 0x91de0000, + 0x00000000, 0x05000000, + 0x00000018, 0x8000ffd3, + 0x0000000b, 0x2fdf0002, + 0x0000000c, 0x1f800000, + 0x00000000, 0x2c070000, + 0x00000010, 0x91de0000, + 0x00000000, 0x05000000, + 0x00000018, 0x8000ffcd, + 0x0000000c, 0x1f800002, + 0x00000000, 0x05000000, + 0x00000018, 0x8000ffca, + 0x0000000c, 0x29800002, + 0x0000000c, 0x1f800002, + 0x00000000, 0x2adf0000, + 0x00000008, 0x2a000005, + 0x00000008, 0x05005555, + 0x00000018, 0x8000ffc4, + 0x00000008, 0x02240045, + 0x00000018, 0x00040000, + 0x00000018, 0x8000001c, + 0x00000018, 0x8000001e, + 0x00000018, 0x80000052, + 0x00000018, 0x8000009e, + 0x00000018, 0x8000009d, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x800000e4, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000015, + 0x00000018, 0x8000001b, + 0x00000018, 0x80000000, + 0x00000018, 0x800000b4, + 0x00000018, 0x8000002e, + 0x00000018, 0x800000e4, + 0x00000018, 0x8000010f, + 0x00000018, 0x800000da, + 0x00000018, 0x80000133, + 0x00000018, 0x8000003b, + 0x00000018, 0x80000000, + 0x00000018, 0x80000071, + 0x0000000c, 0x1f800001, + 0x00000000, 0x05000000, + 0x00000018, 0x8000ffa3, + 0x00000010, 0x91d40000, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000008, 0x2a000002, + 0x00000000, 0x05000000, + 0x00000018, 0x8000ff9d, + 0x00000010, 0x91d40000, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000000, 0x29420000, + 0x00000008, 0x2a000002, + 0x00000000, 0x05000000, + 0x00000018, 0x8000ff96, + 0x00000018, 0x8000ff95, + 0x00000010, 0xb1bcb00a, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x03d80000, + 0x00000000, 0x2c3c0000, + 0x00000010, 0x91d40000, + 0x00000008, 0x06005555, + 0x00000018, 0x80000016, + 0x00000018, 0x800000ac, + 0x00000010, 0x2c6201ba, + 0x00000018, 0x80000005, + 0x00000008, 0x2c80010d, + 0x00000008, 0x2d000009, + 0x00000010, 0x91d40000, + 0x00000008, 0x2d800107, + 0x0000000c, 0x29800000, + 0x0000000c, 0x1f800000, + 0x00000010, 0x91de0000, + 0x00000000, 0x2adf0000, + 0x00000008, 0x2a000006, + 0x00000008, 0x05005555, + 0x00000018, 0x8000ff80, + 0x00000010, 0x91d40000, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000008, 0x2a00000b, + 0x00000000, 0x05000000, + 0x00000018, 0x8000ff7a, + 0x00000018, 0x00020000, + 0x00000000, 0x06820000, + 0x00000010, 0xb18a0006, + 0x00000000, 0x860c1400, + 0x00000010, 0xb18c0004, + 0x00000000, 0x05000000, + 0x00000008, 0x2a000001, + 0x00000010, 0x91d40000, + 0x00000018, 0x000d0000, + 0x00000000, 0x05020000, + 0x00000010, 0x91de0000, + 0x00000018, 0x000a0000, + 0x00000010, 0xb1a0b013, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c200000, + 0x00000008, 0x2c800000, + 0x00000008, 0x2d000000, + 0x00000010, 0x91d40000, + 0x00000008, 0x06005555, + 0x00000018, 0x8000ffee, + 0x00000008, 0x2d80011c, + 0x00000010, 0x001f0000, + 0x00000010, 0x91de0000, + 0x0000000f, 0x47600008, + 0x0000000f, 0x060e0001, + 0x00000000, 0x0f580000, + 0x00000000, 0x0a640000, + 0x00000000, 0x0ae50000, + 0x00000009, 0x0b66ffff, + 0x00000000, 0x0d610000, + 0x00000018, 0x80000013, + 0x0000000f, 0x47600008, + 0x0000000b, 0x2fdf0002, + 0x00000008, 0x2c800000, + 0x00000008, 0x2d000000, + 0x00000010, 0x91d40000, + 0x00000008, 0x2d80011c, + 0x0000000f, 0x060e0001, + 0x00000010, 0x001f0000, + 0x00000000, 0x0f580000, + 0x00000010, 0x91de0000, + 0x00000000, 0x0a640000, + 0x00000000, 0x0ae50000, + 0x00000009, 0x0b66ffff, + 0x00000000, 0x0d610000, + 0x00000000, 0x02620000, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x31040000, + 0x00000000, 0x309a0000, + 0x00000000, 0x0c961800, + 0x00000009, 0x0c99ffff, + 0x00000004, 0xcc993400, + 0x00000010, 0xb1963202, + 0x00000008, 0x0f800000, + 0x0000000c, 0x29800001, + 0x00000010, 0x00220002, + 0x0000000c, 0x29520001, + 0x0000000c, 0x29520000, + 0x00000008, 0x0200000e, + 0x00000008, 0x0280001a, + 0x00000010, 0xb1c40a02, + 0x00000008, 0x02000003, + 0x00000008, 0x22000001, + 0x0000000c, 0x1f800001, + 0x00000000, 0x2adf0000, + 0x00000000, 0x2a000800, + 0x00000008, 0x05005555, + 0x00000018, 0x8000ff36, + 0x0000000b, 0x2fdf0002, + 0x00000010, 0x91d40000, + 0x00000008, 0x2a000001, + 0x00000000, 0x2c200000, + 0x00000008, 0x2c800000, + 0x00000008, 0x2d000000, + 0x00000008, 0x2d80011c, + 0x00000010, 0x91d40000, + 0x00000010, 0x91de0000, + 0x00000008, 0x2c800006, + 0x00000008, 0x2d000006, + 0x00000000, 0x30800000, + 0x00000000, 0x31000000, + 0x00000008, 0x2d800006, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000010, 0x91de0000, + 0x00000000, 0x2adf0000, + 0x00000008, 0x2a000010, + 0x00000000, 0x05000000, + 0x00000018, 0x8000ff21, + 0x00000010, 0x91a0b009, + 0x00000008, 0x2c80010d, + 0x00000008, 0x2d000009, + 0x00000010, 0x91d40000, + 0x00000008, 0x2d800107, + 0x00000018, 0x8000ffab, + 0x00000018, 0x80000010, + 0x00000008, 0xac000001, + 0x00000018, 0x8000000b, + 0x00000000, 0x0380b000, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c004000, + 0x00000010, 0x91d40000, + 0x00000008, 0x06005555, + 0x00000018, 0x8000ff9a, + 0x00000018, 0x80000030, + 0x00000018, 0x80000006, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c000e00, + 0x00000008, 0x2a000007, + 0x00000008, 0x05005555, + 0x00000018, 0x8000ff0b, + 0x00000000, 0x06820000, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000010, 0x0ce70007, + 0x00000009, 0x0562ffff, + 0x00000010, 0xba6c1405, + 0x00000000, 0x2adf0000, + 0x00000000, 0x21000000, + 0x00000008, 0x2a000005, + 0x00000010, 0x91d40000, + 0x00000008, 0x2c80010c, + 0x00000008, 0x2d000008, + 0x0000000c, 0x31620018, + 0x00000008, 0x2d800001, + 0x00000018, 0x8000ff8c, + 0x00000018, 0x000d0000, + 0x00000010, 0xb1a0b00e, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x03d80000, + 0x00000000, 0x2c200000, + 0x00000010, 0x91d40000, + 0x00000018, 0x80000014, + 0x00000010, 0x2c620002, + 0x00000018, 0x8000000b, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c070000, + 0x0000000c, 0x1f800001, + 0x00000010, 0x91de0000, + 0x00000000, 0x05000000, + 0x00000018, 0x8000feed, + 0x00000008, 0x2c80010d, + 0x00000008, 0x2d000009, + 0x00000010, 0x91d40000, + 0x00000008, 0x2d800107, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000010, 0x91de0000, + 0x00000000, 0x2adf0000, + 0x00000008, 0x2a00000a, + 0x00000000, 0x05000000, + 0x00000018, 0x8000fee2, + 0x00000000, 0x05020000, + 0x00000008, 0x2c80010c, + 0x00000008, 0x2d000008, + 0x00000008, 0x2d800134, + 0x00000000, 0x00000000, + 0x00000010, 0x205f0000, + 0x00000008, 0x2c800140, + 0x00000008, 0x2d00003c, + 0x00000008, 0x2d80011c, + 0x00000000, 0x00000000, + 0x00000010, 0x205f0000, + 0x00000008, 0x2c800080, + 0x00000008, 0x2d000000, + 0x00000008, 0x2d800108, + 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, + 0x00000018, 0x000a0000, + 0x00000010, 0x91d40000, + 0x00000008, 0x0600aaaa, + 0x00000018, 0x8000ff56, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000008, 0x2a000009, + 0x00000008, 0x0500aaaa, + 0x00000018, 0x8000fec9, + 0x00000010, 0x91d40000, + 0x00000008, 0x06005555, + 0x00000018, 0x8000ff4e, + 0x00000010, 0x91a03c02, + 0x00000010, 0xb1e66207, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c310000, + 0x00000009, 0x2cb1007f, + 0x00000008, 0x2cd90000, + 0x00000008, 0x2d000000, + 0x00000008, 0x2d80010d, + 0x00000010, 0xb1a80006, + 0x00000010, 0x205f0000, + 0x00000000, 0x2c200000, + 0x00000000, 0x2ca70000, + 0x00000008, 0x2d000010, + 0x00000008, 0x2d800108, + 0x00000018, 0x8000ff47, + 0x00000010, 0xb1a60010, + 0x00000010, 0x001f0000, + 0x0000000f, 0x0f300007, + 0x00000000, 0x0a600000, + 0x00000000, 0x0ae10000, + 0x0000000f, 0x4b620008, + 0x00000009, 0x0b1600ff, + 0x00000000, 0x0d620000, + 0x00000009, 0x0d1a00ff, + 0x00000010, 0x07300003, + 0x0000000c, 0x0d1a0008, + 0x0000000c, 0x0b160008, + 0x0000000f, 0x4ce30018, + 0x00000000, 0x0c992c00, + 0x00000004, 0xcc993400, + 0x00000008, 0x0f800000, + 0x0000000c, 0x29800001, + 0x00000000, 0x33310000, + 0x00000008, 0x22000016, + 0x00000000, 0x2adf0000, + 0x00000008, 0x2a00000c, + 0x00000010, 0x009f0000, + 0x00000000, 0x0f200000, + 0x0000000c, 0x1f800001, + 0x00000008, 0x05005555, + 0x00000018, 0x8000fe9d, + 0x00000010, 0x91d40000, + 0x00000008, 0x0600aaaa, + 0x00000018, 0x8000ff22, + 0x0000000f, 0x47220008, + 0x00000009, 0x070e000f, + 0x00000008, 0x070e0008, + 0x00000008, 0x02800001, + 0x00000007, 0x02851c00, + 0x00000008, 0x82850001, + 0x00000000, 0x02854c00, + 0x00000007, 0x42851c00, + 0x00000003, 0xc3aa5200, + 0x00000000, 0x03b10e00, + 0x00000007, 0x4b071c00, + 0x0000000f, 0x0f300007, + 0x0000000f, 0x0a960003, + 0x00000000, 0x0a955c00, + 0x00000000, 0x4a005a00, + 0x00000000, 0x0c960a00, + 0x00000009, 0x0c99ffff, + 0x00000008, 0x0d00ffff, + 0x00000010, 0xb1963202, + 0x00000008, 0x0f800005, + 0x00000010, 0xb1a80008, + 0x00000010, 0x205f0000, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c200000, + 0x00000000, 0x2ca70000, + 0x00000008, 0x2d000010, + 0x00000008, 0x2d800108, + 0x00000018, 0x8000ff0e, + 0x0000000c, 0x29800001, + 0x00000010, 0x001f0000, + 0x0000000c, 0x1f800001, + 0x00000000, 0x2adf0000, + 0x00000008, 0x2a00000d, + 0x00000008, 0x0500aaaa, + 0x00000018, 0x8000fe77, + 0x00000010, 0x91d40000, + 0x00000008, 0x06005555, + 0x00000018, 0x8000fefc, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000008, 0x2a000007, + 0x00000008, 0x05005555, + 0x00000018, 0x8000fe6f, + 0x00000008, 0x03050004, + 0x00000006, 0x83040c00, + 0x00000008, 0x02850200, + 0x00000000, 0x86050c00, + 0x00000001, 0x860c0e00, + 0x00000008, 0x02040004, + 0x00000000, 0x02041800, + 0x00000000, 0x83871800, + 0x00000018, 0x00020000, +}; + + +u32 bce_xi_rv2p_proc2[] = { + 0x00000010, 0xb1800004, + 0x0000001f, 0x05030100, + 0x00000008, 0x050000ff, + 0x00000018, 0x00020000, + 0x00000000, 0x2a000000, + 0x00000010, 0xb1d40000, + 0x0000000c, 0x29800001, + 0x00000008, 0x02540009, + 0x00000009, 0x2952003f, + 0x00000018, 0x00040000, + 0x00000018, 0x80000010, + 0x00000018, 0x80000011, + 0x00000018, 0x8000003a, + 0x00000018, 0x8000010f, + 0x00000018, 0x8000010e, + 0x00000018, 0x8000010d, + 0x00000018, 0x8000010d, + 0x00000018, 0x80000000, + 0x00000018, 0x8000011f, + 0x00000018, 0x80000109, + 0x00000018, 0x8000000c, + 0x00000018, 0x80000123, + 0x00000018, 0x80000175, + 0x00000018, 0x80000067, + 0x00000018, 0x800000da, + 0x00000018, 0x800000e8, + 0x00000000, 0x2a000000, + 0x00000018, 0x8000ffea, + 0x00000000, 0x2a000000, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x00000018, 0x8000ffe6, + 0x00000000, 0x2a000000, + 0x00000018, 0x8000ffe4, + 0x00000018, 0x00020000, + 0x00000000, 0x05020000, + 0x00000010, 0x91963421, + 0x00000010, 0x205f0000, + 0x00000000, 0x2c1e0000, + 0x00000008, 0x2c800006, + 0x00000008, 0x2d000006, + 0x00000008, 0x2d800102, + 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, + 0x00000000, 0x0d610000, + 0x00000018, 0x000a0000, + 0x00000000, 0x05020000, + 0x00000010, 0x91963416, + 0x00000010, 0x205f0000, + 0x00000000, 0x09d80000, + 0x00000000, 0x2c1e0000, + 0x00000008, 0x2c80010e, + 0x00000008, 0x2d00000a, + 0x00000008, 0x2d800102, + 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, + 0x00000000, 0x0d620000, + 0x00000000, 0x2c130000, + 0x00000018, 0x000a0000, + 0x00000000, 0x05020000, + 0x00000010, 0x91963409, + 0x00000010, 0x205f0000, + 0x00000000, 0x2c1e0000, + 0x00000008, 0x2c800006, + 0x00000008, 0x2d00006a, + 0x00000008, 0x2d800102, + 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, + 0x00000000, 0x0d7a0000, + 0x00000018, 0x000a0000, + 0x00000010, 0x91de0000, + 0x00000010, 0x001f0000, + 0x00000000, 0x2f80aa00, + 0x00000000, 0x2a000000, + 0x00000000, 0x0d610000, + 0x00000000, 0x03620000, + 0x00000000, 0x2c400000, + 0x00000000, 0x02638c00, + 0x00000000, 0x26460000, + 0x00000008, 0x02040012, + 0x00000010, 0xb9060827, + 0x00000000, 0x0f580000, + 0x00000000, 0x0a640000, + 0x00000000, 0x0ae50000, + 0x00000009, 0x0b66ffff, + 0x00000000, 0x0c000000, + 0x00000000, 0x0b800000, + 0x00000008, 0x0cc60012, + 0x00000018, 0x8000ffcb, + 0x00000008, 0x0f800003, + 0x00000000, 0x00000000, + 0x00000010, 0x009f0000, + 0x00000008, 0x27110012, + 0x00000000, 0x66900000, + 0x00000008, 0xa31b0012, + 0x00000010, 0xb1980003, + 0x00000010, 0x001f0000, + 0x00000008, 0x0f800004, + 0x00000008, 0x22000003, + 0x00000008, 0x2c80000c, + 0x00000008, 0x2d00000c, + 0x00000010, 0x009f0000, + 0x00000000, 0x25960000, + 0x0000000c, 0x29800000, + 0x00000000, 0x06660000, + 0x00000000, 0x86611800, + 0x00000009, 0x0260000f, + 0x0000000f, 0x02040002, + 0x00000010, 0xb60c0803, + 0x0000000c, 0x1fbf0000, + 0x0000000c, 0x33660010, + 0x00000000, 0x32140000, + 0x00000000, 0x32950000, + 0x00000005, 0x73662c00, + 0x00000000, 0x31e32e00, + 0x00000008, 0x2d800010, + 0x00000010, 0x20530000, + 0x00000010, 0x91de0000, + 0x00000018, 0x8000ff8f, + 0x00000000, 0x23000000, + 0x00000009, 0x25e6ffff, + 0x00000008, 0x2200000b, + 0x0000000c, 0x69520000, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x00000018, 0x8000ff88, + 0x00000010, 0x91de0000, + 0x00000010, 0x001f0000, + 0x00000000, 0x2f80aa00, + 0x00000000, 0x2a000000, + 0x00000000, 0x2c400000, + 0x00000008, 0x2c800040, + 0x00000008, 0x2d000020, + 0x00000008, 0x2d80011c, + 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, + 0x0000000f, 0x42ea0010, + 0x00000010, 0x004f0004, + 0x00000010, 0xb7469200, + 0x00000008, 0x02490012, + 0x00000010, 0xb5840a00, + 0x00000000, 0x0d610000, + 0x00000010, 0xba66345a, + 0x00000000, 0x03620000, + 0x00000010, 0xb8630c58, + 0x00000008, 0x83050012, + 0x00000010, 0x004f0002, + 0x00000000, 0x03490000, + 0x00000001, 0x83068c00, + 0x00000000, 0x83c60c00, + 0x00000010, 0xb1870010, + 0x00000000, 0x0b6e0000, + 0x00000018, 0x8000ff6a, + 0x00000001, 0x06691400, + 0x00000010, 0x918c0002, + 0x00000008, 0xb4e90001, + 0x00000010, 0xb1e92c4c, + 0x00000000, 0x86692c00, + 0x00000000, 0x02000000, + 0x00000009, 0x02eaffff, + 0x00000010, 0x000c0002, + 0x00000000, 0x02040a00, + 0x0000000f, 0x460c0001, + 0x0000000f, 0x02850001, + 0x00000010, 0x918c01fc, + 0x00000010, 0xb7040e43, + 0x00000000, 0x2c400000, + 0x00000000, 0x0f400000, + 0x00000000, 0x0d610000, + 0x00000000, 0x0a640000, + 0x00000000, 0x0ae50000, + 0x00000009, 0x0b66ffff, + 0x00000000, 0x0c000000, + 0x00000000, 0x0b800000, + 0x00000008, 0x0c860012, + 0x00000008, 0x0f800003, + 0x0000000c, 0x29520000, + 0x00000010, 0x009f0000, + 0x00000008, 0x27110012, + 0x00000000, 0x66900000, + 0x00000000, 0x26460000, + 0x00000000, 0x23060000, + 0x00000010, 0xb1980005, + 0x00000010, 0x001f0000, + 0x00000008, 0x0f800004, + 0x00000000, 0x00000000, + 0x00000010, 0x001f0000, + 0x00000000, 0x32140000, + 0x00000000, 0x32950000, + 0x00000000, 0x31e32e00, + 0x00000005, 0x73662c00, + 0x00000000, 0x25960000, + 0x00000010, 0xb1870016, + 0x0000000c, 0x29800000, + 0x0000000f, 0x0f6b0007, + 0x00000000, 0x0d690000, + 0x00000000, 0x0a6c0000, + 0x00000000, 0x0aed0000, + 0x00000000, 0x0b6e0000, + 0x00000000, 0x0b800000, + 0x00000000, 0x0c870000, + 0x00000008, 0x0f800003, + 0x00000010, 0x20530000, + 0x0000000c, 0x69520001, + 0x00000010, 0x001f0000, + 0x00000000, 0x22c58c00, + 0x00000000, 0x231b0000, + 0x00000000, 0x27110000, + 0x00000000, 0x26900000, + 0x00000010, 0xb8170e03, + 0x0000000c, 0x29800000, + 0x00000018, 0x8000fff6, + 0x00000010, 0xb1980002, + 0x00000008, 0x0f800004, + 0x00000008, 0x2200001a, + 0x00000008, 0x2c80000c, + 0x00000008, 0x2d00000c, + 0x00000008, 0x2d800010, + 0x00000010, 0x001f0000, + 0x00000000, 0x0d6e0000, + 0x00000003, 0xe7cf3400, + 0x0000000c, 0x29800000, + 0x00000010, 0x91de0000, + 0x00000010, 0xb1870007, + 0x00000000, 0x36140000, + 0x00000000, 0x36950000, + 0x00000000, 0x37160000, + 0x00000008, 0x2c800050, + 0x00000008, 0x2d000030, + 0x00000008, 0x2d80000c, + 0x00000010, 0x20530000, + 0x00000018, 0x8000ff1e, + 0x00000000, 0x26460000, + 0x00000000, 0x23000000, + 0x00000009, 0x25e6ffff, + 0x00000000, 0x0b6e0000, + 0x00000003, 0xe7cf2c00, + 0x00000008, 0x2200001b, + 0x0000000c, 0x69520000, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x00000018, 0x8000ff14, + 0x00000000, 0x2fd50000, + 0x00000000, 0x2a000000, + 0x00000010, 0x003f000c, + 0x00000000, 0x06660000, + 0x00000000, 0x86611800, + 0x00000009, 0x026000f0, + 0x00000010, 0xb70c0808, + 0x00000000, 0x2c400000, + 0x0000000c, 0x73660010, + 0x00000008, 0x2c800018, + 0x00000008, 0x2d000018, + 0x00000008, 0x2d800002, + 0x0000000c, 0x5fbf0000, + 0x00000010, 0x91de0000, + 0x00000018, 0x8000ff05, + 0x00000000, 0x2fd50000, + 0x00000000, 0x2a000000, + 0x00000000, 0x2c400000, + 0x0000000c, 0x73660010, + 0x00000008, 0x2c800018, + 0x00000008, 0x2d000018, + 0x00000008, 0x2d800002, + 0x0000000c, 0x5fbf0000, + 0x00000010, 0x91de0000, + 0x00000008, 0x2c800003, + 0x00000008, 0x2d000003, + 0x00000009, 0x3060fff0, + 0x00000008, 0x2d800001, + 0x0000000c, 0x29800000, + 0x00000010, 0x91de0000, + 0x00000008, 0x2c80001a, + 0x00000008, 0x2d00001a, + 0x00000000, 0x33000000, + 0x00000008, 0x2d800002, + 0x00000000, 0x31800000, + 0x00000010, 0x91de0000, + 0x00000008, 0x2c80000c, + 0x00000008, 0x2d00000c, + 0x00000008, 0x2d800004, + 0x00000010, 0x20530000, + 0x00000010, 0x91de0000, + 0x00000018, 0x8000feea, + 0x00000018, 0x8000fee9, + 0x00000000, 0x2a000000, + 0x00000010, 0x001f0000, + 0x00000000, 0x0f008000, + 0x00000008, 0x0f800007, + 0x00000018, 0x80000014, + 0x00000000, 0x05020000, + 0x00000008, 0x22000009, + 0x00000000, 0x286d0000, + 0x00000000, 0x29000000, + 0x0000000f, 0x65680010, + 0x00000003, 0xf66c9400, + 0x00000010, 0xb972a004, + 0x0000000c, 0x73e70019, + 0x0000000c, 0x21420004, + 0x00000000, 0x3bf60000, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x00000008, 0x22000008, + 0x0000000c, 0x61420004, + 0x00000018, 0x000a0000, + 0x00000000, 0x2a000000, + 0x00000010, 0x001f0000, + 0x0000000f, 0x0f470007, + 0x00000008, 0x0f800008, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x00000018, 0x8000fece, + 0x00000010, 0x91de0000, + 0x00000000, 0x2fd50000, + 0x00000010, 0x001f0000, + 0x00000000, 0x33510000, + 0x00000000, 0x2a000000, + 0x00000010, 0xb1c60023, + 0x0000000f, 0x0f500007, + 0x00000000, 0x0a600000, + 0x00000000, 0x0ae10000, + 0x0000000f, 0x4b620008, + 0x00000009, 0x0b1600ff, + 0x0000000f, 0x4c620010, + 0x00000000, 0x0d620000, + 0x00000009, 0x0d1a00ff, + 0x00000010, 0x07500003, + 0x0000000c, 0x0d1a0008, + 0x0000000c, 0x0b160008, + 0x00000000, 0x0cc60000, + 0x00000000, 0x0b800000, + 0x00000000, 0x06980000, + 0x00000008, 0x0f800003, + 0x00000010, 0x06c20004, + 0x0000000c, 0x29000002, + 0x00000010, 0x26420002, + 0x0000000c, 0x29520003, + 0x00000008, 0x22000001, + 0x00000010, 0x009f0000, + 0x00000000, 0x231b0000, + 0x00000000, 0x27111a00, + 0x00000000, 0x66900000, + 0x0000000c, 0x29520000, + 0x00000010, 0xb1973209, + 0x0000000c, 0x29800000, + 0x00000000, 0x06980000, + 0x00000010, 0x20530000, + 0x0000000c, 0x29520003, + 0x00000000, 0x22c58c00, + 0x00000010, 0x001f0000, + 0x00000008, 0x0f800003, + 0x00000018, 0x8000fff3, + 0x00000010, 0xb1c80013, + 0x00000010, 0xb1c60003, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x0000000c, 0x29520000, + 0x0000000c, 0x29520003, + 0x00000010, 0x06c20002, + 0x0000000c, 0x29520002, + 0x00000000, 0x22c58c00, + 0x00000000, 0x27650000, + 0x00000000, 0x26e40000, + 0x00000008, 0x22000016, + 0x00000010, 0xb1c60003, + 0x00000000, 0x23480000, + 0x00000010, 0xb1800005, + 0x00000000, 0x23480000, + 0x0000000c, 0x29800000, + 0x0000000f, 0x0f500007, + 0x00000018, 0x80000012, + 0x00000008, 0x22000016, + 0x0000000c, 0x29800000, + 0x00000000, 0x30140000, + 0x00000000, 0x30950000, + 0x00000010, 0x07500003, + 0x00000009, 0x0b1600ff, + 0x00000009, 0x0d1a00ff, + 0x0000000f, 0x31160008, + 0x00000000, 0x31623400, + 0x00000003, 0xf1623000, + 0x00000010, 0x205f0000, + 0x00000000, 0x2c510000, + 0x00000009, 0x2cd1007f, + 0x00000008, 0x2cd90000, + 0x00000008, 0x2d000000, + 0x00000008, 0x2d80000c, + 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, + 0x00000010, 0x05c20003, + 0x00000000, 0x33000000, + 0x00000008, 0x0f800007, + 0x00000010, 0x20530000, + 0x00000010, 0x009f0000, + 0x00000018, 0x8000fe7b, + 0x00000000, 0x2fd50000, + 0x00000000, 0x2a000000, + 0x0000000f, 0x0f500007, + 0x00000010, 0xb1c6002d, + 0x0000000f, 0x47420008, + 0x00000009, 0x070e000f, + 0x00000008, 0x070e0008, + 0x00000010, 0x001f0000, + 0x00000008, 0x09000001, + 0x00000007, 0x09121c00, + 0x00000003, 0xcbca9200, + 0x00000000, 0x0b97a200, + 0x00000007, 0x42171c00, + 0x00000000, 0x0b040000, + 0x0000000f, 0x0a840003, + 0x00000000, 0x0a959c00, + 0x00000000, 0x4a009a00, + 0x00000008, 0x82120001, + 0x00000001, 0x0c170800, + 0x00000000, 0x0c978c00, + 0x00000000, 0x02180000, + 0x00000008, 0x0d00ffff, + 0x00000008, 0x0f800006, + 0x0000000c, 0x29000000, + 0x00000010, 0x06c20004, + 0x0000000c, 0x29520002, + 0x00000010, 0x26420002, + 0x0000000c, 0x29520003, + 0x00000008, 0x22000001, + 0x00000010, 0x009f0000, + 0x00000010, 0xb197320c, + 0x00000000, 0x231b0000, + 0x00000000, 0x27110800, + 0x00000000, 0x66900000, + 0x0000000c, 0x29800000, + 0x00000000, 0x02180000, + 0x00000010, 0x20530000, + 0x0000000c, 0x29520003, + 0x00000000, 0x22c53600, + 0x00000010, 0x001f0000, + 0x00000008, 0x0f800006, + 0x00000018, 0x8000fff4, + 0x00000000, 0x231b0000, + 0x00000000, 0x27110800, + 0x00000000, 0x66900000, + 0x00000010, 0xb1c8000b, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x0000000c, 0x29520000, + 0x0000000c, 0x29520003, + 0x00000010, 0x06c20002, + 0x0000000c, 0x29520002, + 0x00000000, 0x22c58c00, + 0x00000000, 0x27650000, + 0x00000000, 0x26e40000, + 0x00000000, 0x23480000, + 0x00000008, 0x22000017, + 0x0000000c, 0x29800000, + 0x00000010, 0x001f0000, + 0x00000010, 0x20530000, + 0x00000018, 0x8000fe3e, +}; + + +u32 bce_xi90_rv2p_proc1[] = { + 0x00000010, 0xb1800002, + 0x0000001f, 0x03030100, + 0x00000008, 0xac000001, + 0x00000000, 0x05000000, + 0x0000000c, 0x2f800001, + 0x00000000, 0x2b000000, + 0x00000000, 0x2b800000, + 0x00000010, 0x203f006c, + 0x00000010, 0x213f0003, + 0x00000010, 0x20bf003b, + 0x00000018, 0x8000fffd, + 0x00000010, 0xb1b8b015, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x03d80000, + 0x00000000, 0x2c380000, + 0x00000008, 0x2c800000, + 0x00000008, 0x2d000000, + 0x00000010, 0x91d40000, + 0x00000008, 0x06005555, + 0x00000018, 0x8000008f, + 0x00000008, 0x2d80011c, + 0x00000008, 0x02000001, + 0x00000010, 0x91de0000, + 0x0000000f, 0x42e0001c, + 0x00000010, 0x91840a17, + 0x00000010, 0x08660016, + 0x0000000c, 0x29800002, + 0x0000000c, 0x1f800002, + 0x00000000, 0x2adf0000, + 0x00000008, 0x2a00000f, + 0x00000008, 0x05005555, + 0x00000018, 0x8000ffe8, + 0x00000008, 0x02000001, + 0x0000000f, 0x42e0001c, + 0x00000010, 0x91840a19, + 0x00000008, 0x2c800006, + 0x00000008, 0x2d000006, + 0x00000010, 0x91d40000, + 0x00000008, 0x2d800106, + 0x00000018, 0x80000083, + 0x00000010, 0x08660013, + 0x00000018, 0x8000fff1, + 0x00000008, 0xb1000001, + 0x00000008, 0x2c80010c, + 0x00000008, 0x2d000008, + 0x00000008, 0x2d800001, + 0x00000018, 0x8000007c, + 0x0000000b, 0x2fdf0002, + 0x0000000c, 0x1f800002, + 0x00000000, 0x2c070000, + 0x00000010, 0x91de0000, + 0x00000000, 0x05000000, + 0x00000018, 0x8000ffd3, + 0x0000000b, 0x2fdf0002, + 0x0000000c, 0x1f800000, + 0x00000000, 0x2c070000, + 0x00000010, 0x91de0000, + 0x00000000, 0x05000000, + 0x00000018, 0x8000ffcd, + 0x0000000c, 0x1f800002, + 0x00000000, 0x05000000, + 0x00000018, 0x8000ffca, + 0x0000000c, 0x29800002, + 0x0000000c, 0x1f800002, + 0x00000000, 0x2adf0000, + 0x00000008, 0x2a000005, + 0x00000008, 0x05005555, + 0x00000018, 0x8000ffc4, + 0x00000008, 0x02240045, + 0x00000018, 0x00040000, + 0x00000018, 0x8000001c, + 0x00000018, 0x8000001e, + 0x00000018, 0x80000065, + 0x00000018, 0x800000ad, + 0x00000018, 0x800000ac, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x800000f3, + 0x00000018, 0x80000000, + 0x00000018, 0x80000000, + 0x00000018, 0x80000015, + 0x00000018, 0x8000001b, + 0x00000018, 0x80000000, + 0x00000018, 0x800000c3, + 0x00000018, 0x8000002e, + 0x00000018, 0x800000f3, + 0x00000018, 0x8000011e, + 0x00000018, 0x800000e9, + 0x00000018, 0x80000142, + 0x00000018, 0x8000004e, + 0x00000018, 0x80000000, + 0x00000018, 0x80000080, + 0x0000000c, 0x1f800001, + 0x00000000, 0x05000000, + 0x00000018, 0x8000ffa3, + 0x00000010, 0x91d40000, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000008, 0x2a000002, + 0x00000000, 0x05000000, + 0x00000018, 0x8000ff9d, + 0x00000010, 0x91d40000, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000000, 0x29420000, + 0x00000008, 0x2a000002, + 0x00000000, 0x05000000, + 0x00000018, 0x8000ff96, + 0x00000018, 0x8000ff95, + 0x00000010, 0xb1bcb00a, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x03d80000, + 0x00000000, 0x2c3c0000, + 0x00000010, 0x91d40000, + 0x00000008, 0x06005555, + 0x00000018, 0x80000029, + 0x00000018, 0x800000bb, + 0x00000010, 0x2c6201ba, + 0x00000018, 0x80000005, + 0x00000008, 0x2c80010d, + 0x00000008, 0x2d000009, + 0x00000010, 0x91d40000, + 0x00000008, 0x2d800107, + 0x0000000c, 0x29800000, + 0x0000000c, 0x1f800000, + 0x00000010, 0x91de0000, + 0x00000000, 0x2adf0000, + 0x00000008, 0x2a000006, + 0x00000008, 0x05005555, + 0x00000018, 0x8000ff80, + 0x00000010, 0x91d40000, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000008, 0x2a00000b, + 0x00000000, 0x05000000, + 0x00000018, 0x8000ff7a, + 0x00000000, 0x02020000, + 0x00000000, 0x029a0000, + 0x00000000, 0x060c2c00, + 0x00000004, 0xc60c3400, + 0x00000010, 0x001f0000, + 0x00000010, 0xb196180c, + 0x00000008, 0x06960004, + 0x00000009, 0x068dfffc, + 0x00000004, 0xcd051a00, + 0x00000004, 0xcc9a1800, + 0x00000010, 0x20d70000, + 0x0000000c, 0x2b560000, + 0x00000000, 0x00000000, + 0x00000000, 0x00000000, + 0x00000010, 0x20d70000, + 0x00000008, 0x0f800001, + 0x00000010, 0xb18001f4, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6b560000, + 0x00000018, 0x00040000, + 0x00000000, 0x06820000, + 0x00000010, 0xb18a0006, + 0x00000000, 0x860c1400, + 0x00000010, 0xb18c0004, + 0x00000000, 0x05000000, + 0x00000008, 0x2a000001, + 0x00000010, 0x91d40000, + 0x00000018, 0x000d0000, + 0x00000000, 0x05020000, + 0x00000010, 0x91de0000, + 0x00000018, 0x000a0000, + 0x00000010, 0xb1a0b013, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c200000, + 0x00000008, 0x2c800000, + 0x00000008, 0x2d000000, + 0x00000010, 0x91d40000, + 0x00000008, 0x06005555, + 0x00000018, 0x8000ffee, + 0x00000008, 0x2d80011c, + 0x00000010, 0x001f0000, + 0x00000010, 0x91de0000, + 0x0000000f, 0x47600008, + 0x0000000f, 0x060e0001, + 0x00000000, 0x0f580000, + 0x00000000, 0x0a640000, + 0x00000000, 0x0ae50000, + 0x00000009, 0x0b66ffff, + 0x00000000, 0x0d610000, + 0x00000018, 0x80000013, + 0x0000000f, 0x47600008, + 0x0000000b, 0x2fdf0002, + 0x00000008, 0x2c800000, + 0x00000008, 0x2d000000, + 0x00000010, 0x91d40000, + 0x00000008, 0x2d80011c, + 0x0000000f, 0x060e0001, + 0x00000010, 0x001f0000, + 0x00000000, 0x0f580000, + 0x00000010, 0x91de0000, + 0x00000000, 0x0a640000, + 0x00000000, 0x0ae50000, + 0x00000009, 0x0b66ffff, + 0x00000000, 0x0d610000, + 0x00000000, 0x02620000, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x31040000, + 0x00000000, 0x309a0000, + 0x00000018, 0x8000ffbc, + 0x0000000c, 0x29800001, + 0x00000010, 0x00220002, + 0x0000000c, 0x29520001, + 0x0000000c, 0x29520000, + 0x00000008, 0x0200000e, + 0x00000008, 0x0280001a, + 0x00000010, 0xb1c40a02, + 0x00000008, 0x02000003, + 0x00000008, 0x22000001, + 0x0000000c, 0x1f800001, + 0x00000000, 0x2adf0000, + 0x00000000, 0x2a000800, + 0x00000008, 0x05005555, + 0x00000018, 0x8000ff27, + 0x0000000b, 0x2fdf0002, + 0x00000010, 0x91d40000, + 0x00000008, 0x2a000001, + 0x00000000, 0x2c200000, + 0x00000008, 0x2c800000, + 0x00000008, 0x2d000000, + 0x00000008, 0x2d80011c, + 0x00000010, 0x91d40000, + 0x00000010, 0x91de0000, + 0x00000008, 0x2c800006, + 0x00000008, 0x2d000006, + 0x00000000, 0x30800000, + 0x00000000, 0x31000000, + 0x00000008, 0x2d800006, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000010, 0x91de0000, + 0x00000000, 0x2adf0000, + 0x00000008, 0x2a000010, + 0x00000000, 0x05000000, + 0x00000018, 0x8000ff12, + 0x00000010, 0x91a0b009, + 0x00000008, 0x2c80010d, + 0x00000008, 0x2d000009, + 0x00000010, 0x91d40000, + 0x00000008, 0x2d800107, + 0x00000018, 0x8000ffaf, + 0x00000018, 0x80000010, + 0x00000008, 0xac000001, + 0x00000018, 0x8000000b, + 0x00000000, 0x0380b000, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c004000, + 0x00000010, 0x91d40000, + 0x00000008, 0x06005555, + 0x00000018, 0x8000ff9e, + 0x00000018, 0x80000030, + 0x00000018, 0x80000006, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c000e00, + 0x00000008, 0x2a000007, + 0x00000008, 0x05005555, + 0x00000018, 0x8000fefc, + 0x00000000, 0x06820000, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000010, 0x0ce70007, + 0x00000009, 0x0562ffff, + 0x00000010, 0xba6c1405, + 0x00000000, 0x2adf0000, + 0x00000000, 0x21000000, + 0x00000008, 0x2a000005, + 0x00000010, 0x91d40000, + 0x00000008, 0x2c80010c, + 0x00000008, 0x2d000008, + 0x0000000c, 0x31620018, + 0x00000008, 0x2d800001, + 0x00000018, 0x8000ff90, + 0x00000018, 0x000d0000, + 0x00000010, 0xb1a0b00e, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x03d80000, + 0x00000000, 0x2c200000, + 0x00000010, 0x91d40000, + 0x00000018, 0x80000014, + 0x00000010, 0x2c620002, + 0x00000018, 0x8000000b, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c070000, + 0x0000000c, 0x1f800001, + 0x00000010, 0x91de0000, + 0x00000000, 0x05000000, + 0x00000018, 0x8000fede, + 0x00000008, 0x2c80010d, + 0x00000008, 0x2d000009, + 0x00000010, 0x91d40000, + 0x00000008, 0x2d800107, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000010, 0x91de0000, + 0x00000000, 0x2adf0000, + 0x00000008, 0x2a00000a, + 0x00000000, 0x05000000, + 0x00000018, 0x8000fed3, + 0x00000000, 0x05020000, + 0x00000008, 0x2c80010c, + 0x00000008, 0x2d000008, + 0x00000008, 0x2d800134, + 0x00000000, 0x00000000, + 0x00000010, 0x205f0000, + 0x00000008, 0x2c800140, + 0x00000008, 0x2d00003c, + 0x00000008, 0x2d80011c, + 0x00000000, 0x00000000, + 0x00000010, 0x205f0000, + 0x00000008, 0x2c800080, + 0x00000008, 0x2d000000, + 0x00000008, 0x2d800108, + 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, + 0x00000018, 0x000a0000, + 0x00000010, 0x91d40000, + 0x00000008, 0x0600aaaa, + 0x00000018, 0x8000ff5a, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000008, 0x2a000009, + 0x00000008, 0x0500aaaa, + 0x00000018, 0x8000feba, + 0x00000010, 0x91d40000, + 0x00000008, 0x06005555, + 0x00000018, 0x8000ff52, + 0x00000010, 0x91a03c02, + 0x00000010, 0xb1e66207, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c310000, + 0x00000009, 0x2cb1007f, + 0x00000008, 0x2cd90000, + 0x00000008, 0x2d000000, + 0x00000008, 0x2d80010d, + 0x00000010, 0xb1a80006, + 0x00000010, 0x205f0000, + 0x00000000, 0x2c200000, + 0x00000000, 0x2ca70000, + 0x00000008, 0x2d000010, + 0x00000008, 0x2d800108, + 0x00000018, 0x8000ff4b, + 0x00000010, 0xb1a60010, + 0x00000010, 0x001f0000, + 0x0000000f, 0x0f300007, + 0x00000000, 0x0a600000, + 0x00000000, 0x0ae10000, + 0x0000000f, 0x4b620008, + 0x00000009, 0x0b1600ff, + 0x00000000, 0x0d620000, + 0x00000009, 0x0d1a00ff, + 0x00000010, 0x07300003, + 0x0000000c, 0x0d1a0008, + 0x0000000c, 0x0b160008, + 0x0000000f, 0x4ce30018, + 0x00000000, 0x0c992c00, + 0x00000004, 0xcc993400, + 0x00000008, 0x0f800000, + 0x0000000c, 0x29800001, + 0x00000000, 0x33310000, + 0x00000008, 0x22000016, + 0x00000000, 0x2adf0000, + 0x00000008, 0x2a00000c, + 0x00000010, 0x009f0000, + 0x00000000, 0x0f200000, + 0x0000000c, 0x1f800001, + 0x00000008, 0x05005555, + 0x00000018, 0x8000fe8e, + 0x00000010, 0x91d40000, + 0x00000008, 0x0600aaaa, + 0x00000018, 0x8000ff26, + 0x0000000f, 0x47220008, + 0x00000009, 0x070e000f, + 0x00000008, 0x070e0008, + 0x00000008, 0x02800001, + 0x00000007, 0x02851c00, + 0x00000008, 0x82850001, + 0x00000000, 0x02854c00, + 0x00000007, 0x42851c00, + 0x00000003, 0xc3aa5200, + 0x00000000, 0x03b10e00, + 0x00000007, 0x4b071c00, + 0x0000000f, 0x0f300007, + 0x0000000f, 0x0a960003, + 0x00000000, 0x0a955c00, + 0x00000000, 0x4a005a00, + 0x00000000, 0x0c960a00, + 0x00000009, 0x0c99ffff, + 0x00000008, 0x0d00ffff, + 0x00000010, 0xb1963202, + 0x00000008, 0x0f800005, + 0x00000010, 0xb1a80008, + 0x00000010, 0x205f0000, + 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c200000, + 0x00000000, 0x2ca70000, + 0x00000008, 0x2d000010, + 0x00000008, 0x2d800108, + 0x00000018, 0x8000ff12, + 0x0000000c, 0x29800001, + 0x00000010, 0x001f0000, + 0x0000000c, 0x1f800001, + 0x00000000, 0x2adf0000, + 0x00000008, 0x2a00000d, + 0x00000008, 0x0500aaaa, + 0x00000018, 0x8000fe68, + 0x00000010, 0x91d40000, + 0x00000008, 0x06005555, + 0x00000018, 0x8000ff00, + 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, + 0x00000008, 0x2a000007, + 0x00000008, 0x05005555, + 0x00000018, 0x8000fe60, + 0x00000008, 0x03050004, + 0x00000006, 0x83040c00, + 0x00000008, 0x02850200, + 0x00000000, 0x86050c00, + 0x00000001, 0x860c0e00, + 0x00000008, 0x02040004, + 0x00000000, 0x02041800, + 0x00000000, 0x83871800, + 0x00000018, 0x00020000, +}; + + +u32 bce_xi90_rv2p_proc2[] = { + 0x00000010, 0xb1800004, + 0x0000001f, 0x03030100, + 0x00000008, 0x050000ff, + 0x00000018, 0x00020000, + 0x00000000, 0x2a000000, + 0x00000010, 0xb1d40000, + 0x0000000c, 0x29800001, + 0x00000008, 0x02540009, + 0x00000009, 0x2952003f, + 0x00000018, 0x00040000, + 0x00000018, 0x80000010, + 0x00000018, 0x80000011, + 0x00000018, 0x8000004b, + 0x00000018, 0x8000013c, + 0x00000018, 0x8000013b, + 0x00000018, 0x8000013a, + 0x00000018, 0x8000013a, + 0x00000018, 0x80000000, + 0x00000018, 0x8000014d, + 0x00000018, 0x80000136, + 0x00000018, 0x8000000c, + 0x00000018, 0x80000152, + 0x00000018, 0x800001ac, + 0x00000018, 0x80000080, + 0x00000018, 0x80000107, + 0x00000018, 0x80000115, + 0x00000000, 0x2a000000, + 0x00000018, 0x8000ffea, + 0x00000000, 0x2a000000, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x00000018, 0x8000ffe6, + 0x00000000, 0x2a000000, + 0x00000018, 0x8000ffe4, + 0x00000000, 0x03820000, + 0x00000018, 0x8000ffdf, + 0x00000001, 0x0c161400, + 0x00000000, 0x8c181400, + 0x00000010, 0x91980003, + 0x00000008, 0x0c960002, + 0x00000010, 0xb1800003, + 0x00000008, 0x0c960001, + 0x00000000, 0x0c000000, + 0x00000000, 0x0d190000, + 0x00000010, 0x20560000, + 0x0000000c, 0x2bd70001, + 0x00000008, 0x0f800001, + 0x00000000, 0x00000000, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000010, 0x011301f1, + 0x00000018, 0x00070000, + 0x00000000, 0x05020000, + 0x00000010, 0x91963421, + 0x00000010, 0x205f0000, + 0x00000000, 0x2c1e0000, + 0x00000008, 0x2c800006, + 0x00000008, 0x2d000006, + 0x00000008, 0x2d800102, + 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, + 0x00000000, 0x0d610000, + 0x00000018, 0x000a0000, + 0x00000000, 0x05020000, + 0x00000010, 0x91963416, + 0x00000010, 0x205f0000, + 0x00000000, 0x09d80000, + 0x00000000, 0x2c1e0000, + 0x00000008, 0x2c80010e, + 0x00000008, 0x2d00000a, + 0x00000008, 0x2d800102, + 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, + 0x00000000, 0x0d620000, + 0x00000000, 0x2c130000, + 0x00000018, 0x000a0000, + 0x00000000, 0x05020000, + 0x00000010, 0x91963409, + 0x00000010, 0x205f0000, + 0x00000000, 0x2c1e0000, + 0x00000008, 0x2c800006, + 0x00000008, 0x2d00006a, + 0x00000008, 0x2d800102, + 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, + 0x00000000, 0x0d7a0000, + 0x00000018, 0x000a0000, + 0x00000010, 0x91de0000, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000000, 0x2f80aa00, + 0x00000000, 0x2a000000, + 0x00000000, 0x0d610000, + 0x00000000, 0x03620000, + 0x00000000, 0x2c400000, + 0x00000000, 0x02638c00, + 0x00000000, 0x26460000, + 0x00000008, 0x02040012, + 0x00000010, 0xb906082e, + 0x00000000, 0x0f580000, + 0x00000000, 0x0a640000, + 0x00000000, 0x0ae50000, + 0x00000009, 0x0b66ffff, + 0x00000000, 0x0c000000, + 0x00000000, 0x0b800000, + 0x00000008, 0x0cc60012, + 0x00000018, 0x8000ffca, + 0x00000010, 0x20560000, + 0x0000000c, 0x2bd70001, + 0x00000008, 0x0f800003, + 0x00000000, 0x00000000, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000008, 0x27110012, + 0x00000000, 0x66900000, + 0x00000008, 0xa31b0012, + 0x00000010, 0xb1980006, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000010, 0x20560000, + 0x0000000c, 0x2bd70001, + 0x00000008, 0x0f800004, + 0x00000008, 0x22000003, + 0x00000008, 0x2c80000c, + 0x00000008, 0x2d00000c, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000000, 0x25960000, + 0x0000000c, 0x29800000, + 0x00000000, 0x06660000, + 0x00000000, 0x86611800, + 0x00000009, 0x0260000f, + 0x0000000f, 0x02040002, + 0x00000010, 0xb60c0803, + 0x0000000c, 0x1fbf0000, + 0x0000000c, 0x33660010, + 0x00000000, 0x32140000, + 0x00000000, 0x32950000, + 0x00000005, 0x73662c00, + 0x00000000, 0x31e32e00, + 0x00000008, 0x2d800010, + 0x00000010, 0x20530000, + 0x00000010, 0x91de0000, + 0x00000018, 0x8000ff76, + 0x00000000, 0x23000000, + 0x00000009, 0x25e6ffff, + 0x00000008, 0x2200000b, + 0x0000000c, 0x69520000, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x00000018, 0x8000ff6f, + 0x00000010, 0x91de0000, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000000, 0x2f80aa00, + 0x00000000, 0x2a000000, + 0x00000000, 0x2c400000, + 0x00000008, 0x2c800040, + 0x00000008, 0x2d000020, + 0x00000008, 0x2d80011c, + 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, + 0x0000000f, 0x42ea0010, + 0x00000010, 0x004f0004, + 0x00000010, 0xb7469200, + 0x00000008, 0x02490012, + 0x00000010, 0xb5840a00, + 0x00000000, 0x0d610000, + 0x00000010, 0xba66346d, + 0x00000000, 0x03620000, + 0x00000010, 0xb8630c6b, + 0x00000008, 0x83050012, + 0x00000010, 0x004f0002, + 0x00000000, 0x03490000, + 0x00000001, 0x83068c00, + 0x00000000, 0x83c60c00, + 0x00000010, 0xb1870010, + 0x00000000, 0x0b6e0000, + 0x00000018, 0x8000ff50, + 0x00000001, 0x06691400, + 0x00000010, 0x918c0002, + 0x00000008, 0xb4e90001, + 0x00000010, 0xb1e92c5f, + 0x00000000, 0x86692c00, + 0x00000000, 0x02000000, + 0x00000009, 0x02eaffff, + 0x00000010, 0x000c0002, + 0x00000000, 0x02040a00, + 0x0000000f, 0x460c0001, + 0x0000000f, 0x02850001, + 0x00000010, 0x918c01fc, + 0x00000010, 0xb7040e56, + 0x00000000, 0x2c400000, + 0x00000000, 0x0f400000, + 0x00000000, 0x0d610000, + 0x00000000, 0x0a640000, + 0x00000000, 0x0ae50000, + 0x00000009, 0x0b66ffff, + 0x00000000, 0x0c000000, + 0x00000000, 0x0b800000, + 0x00000008, 0x0c860012, + 0x00000010, 0x20560000, + 0x0000000c, 0x2bd70001, + 0x00000008, 0x0f800003, + 0x0000000c, 0x29520000, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000008, 0x27110012, + 0x00000000, 0x66900000, + 0x00000000, 0x26460000, + 0x00000000, 0x23060000, + 0x00000010, 0xb1980009, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000010, 0x20560000, + 0x0000000c, 0x2bd70001, + 0x00000008, 0x0f800004, + 0x00000000, 0x00000000, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000000, 0x32140000, + 0x00000000, 0x32950000, + 0x00000000, 0x31e32e00, + 0x00000005, 0x73662c00, + 0x00000000, 0x25960000, + 0x00000010, 0xb1870021, + 0x0000000c, 0x29800000, + 0x0000000f, 0x0f6b0007, + 0x00000000, 0x0d690000, + 0x00000000, 0x0a6c0000, + 0x00000000, 0x0aed0000, + 0x00000000, 0x0b6e0000, + 0x00000000, 0x0b800000, + 0x00000000, 0x0c870000, + 0x00000018, 0x8000ff18, + 0x00000001, 0x0c161400, + 0x00000000, 0x8c181400, + 0x00000008, 0x0c960001, + 0x00000010, 0x91980002, + 0x00000008, 0x0c990001, + 0x00000000, 0x0d190000, + 0x00000000, 0x0c000000, + 0x00000010, 0x20560000, + 0x0000000c, 0x2bd70001, + 0x00000008, 0x0f800001, + 0x00000010, 0x20530000, + 0x0000000c, 0x69520001, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000000, 0x22c58c00, + 0x00000000, 0x23120000, + 0x00000000, 0x27110000, + 0x00000000, 0x26900000, + 0x00000010, 0xb8170e03, + 0x0000000c, 0x29800000, + 0x00000018, 0x8000ffeb, + 0x00000000, 0x82970e00, + 0x00000000, 0xa3120a00, + 0x00000008, 0x2200001a, + 0x00000008, 0x2c80000c, + 0x00000008, 0x2d00000c, + 0x00000008, 0x2d800010, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000000, 0x0d6e0000, + 0x00000003, 0xe7cf3400, + 0x0000000c, 0x29800000, + 0x00000010, 0x91de0000, + 0x00000010, 0xb1870007, + 0x00000000, 0x36140000, + 0x00000000, 0x36950000, + 0x00000000, 0x37160000, + 0x00000008, 0x2c800050, + 0x00000008, 0x2d000030, + 0x00000008, 0x2d80000c, + 0x00000010, 0x20530000, + 0x00000018, 0x8000fef1, + 0x00000000, 0x26460000, + 0x00000000, 0x23000000, + 0x00000009, 0x25e6ffff, + 0x00000000, 0x0b6e0000, + 0x00000003, 0xe7cf2c00, + 0x00000008, 0x2200001b, + 0x0000000c, 0x69520000, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x00000018, 0x8000fee7, + 0x00000000, 0x2fd50000, + 0x00000000, 0x2a000000, + 0x00000010, 0x003f000c, + 0x00000000, 0x06660000, + 0x00000000, 0x86611800, + 0x00000009, 0x026000f0, + 0x00000010, 0xb70c0808, + 0x00000000, 0x2c400000, + 0x0000000c, 0x73660010, + 0x00000008, 0x2c800018, + 0x00000008, 0x2d000018, + 0x00000008, 0x2d800002, + 0x0000000c, 0x5fbf0000, + 0x00000010, 0x91de0000, + 0x00000018, 0x8000fed8, + 0x00000000, 0x2fd50000, + 0x00000000, 0x2a000000, + 0x00000000, 0x2c400000, + 0x0000000c, 0x73660010, + 0x00000008, 0x2c800018, + 0x00000008, 0x2d000018, + 0x00000008, 0x2d800002, + 0x0000000c, 0x5fbf0000, + 0x00000010, 0x91de0000, + 0x00000008, 0x2c800003, + 0x00000008, 0x2d000003, + 0x00000009, 0x3060fff0, + 0x00000008, 0x2d800001, + 0x0000000c, 0x29800000, + 0x00000010, 0x91de0000, + 0x00000008, 0x2c80001a, + 0x00000008, 0x2d00001a, + 0x00000000, 0x33000000, + 0x00000008, 0x2d800002, + 0x00000000, 0x31800000, + 0x00000010, 0x91de0000, + 0x00000008, 0x2c80000c, + 0x00000008, 0x2d00000c, + 0x00000008, 0x2d800004, + 0x00000010, 0x20530000, + 0x00000010, 0x91de0000, + 0x00000018, 0x8000febd, + 0x00000018, 0x8000febc, + 0x00000000, 0x2a000000, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000000, 0x0f008000, + 0x00000008, 0x0f800007, + 0x00000018, 0x80000015, + 0x00000000, 0x05020000, + 0x00000008, 0x22000009, + 0x00000000, 0x286d0000, + 0x00000000, 0x29000000, + 0x0000000f, 0x65680010, + 0x00000003, 0xf66c9400, + 0x00000010, 0xb972a004, + 0x0000000c, 0x73e70019, + 0x0000000c, 0x21420004, + 0x00000000, 0x3bf60000, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x00000008, 0x22000008, + 0x0000000c, 0x61420004, + 0x00000018, 0x000a0000, + 0x00000000, 0x2a000000, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x0000000f, 0x0f470007, + 0x00000008, 0x0f800008, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x00000018, 0x8000fe9f, + 0x00000010, 0x91de0000, + 0x00000000, 0x2fd50000, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000000, 0x33510000, + 0x00000000, 0x2a000000, + 0x00000010, 0xb1c60029, + 0x0000000f, 0x0f500007, + 0x00000000, 0x0a600000, + 0x00000000, 0x0ae10000, + 0x0000000f, 0x4b620008, + 0x00000009, 0x0b1600ff, + 0x0000000f, 0x4c620010, + 0x00000000, 0x0d620000, + 0x00000009, 0x0d1a00ff, + 0x00000010, 0x07500003, + 0x0000000c, 0x0d1a0008, + 0x0000000c, 0x0b160008, + 0x00000000, 0x0cc60000, + 0x00000000, 0x0b800000, + 0x00000000, 0x06980000, + 0x00000010, 0x20560000, + 0x0000000c, 0x2bd70001, + 0x00000008, 0x0f800003, + 0x00000010, 0x06c20004, + 0x0000000c, 0x29000002, + 0x00000010, 0x26420002, + 0x0000000c, 0x29520003, + 0x00000008, 0x22000001, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000000, 0x231b0000, + 0x00000000, 0x27111a00, + 0x00000000, 0x66900000, + 0x0000000c, 0x29520000, + 0x00000010, 0xb197320c, + 0x0000000c, 0x29800000, + 0x00000000, 0x06980000, + 0x00000010, 0x20530000, + 0x0000000c, 0x29520003, + 0x00000000, 0x22c58c00, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000010, 0x20560000, + 0x0000000c, 0x2bd70001, + 0x00000008, 0x0f800003, + 0x00000018, 0x8000ffef, + 0x00000010, 0xb1c80013, + 0x00000010, 0xb1c60003, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x0000000c, 0x29520000, + 0x0000000c, 0x29520003, + 0x00000010, 0x06c20002, + 0x0000000c, 0x29520002, + 0x00000000, 0x22c58c00, + 0x00000000, 0x27650000, + 0x00000000, 0x26e40000, + 0x00000008, 0x22000016, + 0x00000010, 0xb1c60003, + 0x00000000, 0x23480000, + 0x00000010, 0xb1800005, + 0x00000000, 0x23480000, + 0x0000000c, 0x29800000, + 0x0000000f, 0x0f500007, + 0x00000018, 0x80000012, + 0x00000008, 0x22000016, + 0x0000000c, 0x29800000, + 0x00000000, 0x30140000, + 0x00000000, 0x30950000, + 0x00000010, 0x07500003, + 0x00000009, 0x0b1600ff, + 0x00000009, 0x0d1a00ff, + 0x0000000f, 0x31160008, + 0x00000000, 0x31623400, + 0x00000003, 0xf1623000, + 0x00000010, 0x205f0000, + 0x00000000, 0x2c510000, + 0x00000009, 0x2cd1007f, + 0x00000008, 0x2cd90000, + 0x00000008, 0x2d000000, + 0x00000008, 0x2d80000c, + 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, + 0x00000010, 0x05c20003, + 0x00000000, 0x33000000, + 0x00000008, 0x0f800007, + 0x00000010, 0x20530000, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000018, 0x8000fe44, + 0x00000000, 0x2fd50000, + 0x00000000, 0x2a000000, + 0x0000000f, 0x0f500007, + 0x00000010, 0xb1c60030, + 0x0000000f, 0x47420008, + 0x00000009, 0x070e000f, + 0x00000008, 0x070e0008, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000008, 0x09000001, + 0x00000007, 0x09121c00, + 0x00000003, 0xcbca9200, + 0x00000000, 0x0b97a200, + 0x00000007, 0x42171c00, + 0x00000000, 0x0b040000, + 0x0000000f, 0x0a840003, + 0x00000000, 0x0a959c00, + 0x00000000, 0x4a009a00, + 0x00000008, 0x82120001, + 0x00000001, 0x0c170800, + 0x00000000, 0x0c978c00, + 0x00000000, 0x02180000, + 0x00000008, 0x0d00ffff, + 0x00000008, 0x0f800006, + 0x0000000c, 0x29000000, + 0x00000010, 0x06c20004, + 0x0000000c, 0x29520002, + 0x00000010, 0x26420002, + 0x0000000c, 0x29520003, + 0x00000008, 0x22000001, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000010, 0xb197320d, + 0x00000000, 0x231b0000, + 0x00000000, 0x27110800, + 0x00000000, 0x66900000, + 0x0000000c, 0x29800000, + 0x00000000, 0x02180000, + 0x00000010, 0x20530000, + 0x0000000c, 0x29520003, + 0x00000000, 0x22c53600, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000008, 0x0f800006, + 0x00000018, 0x8000fff2, + 0x00000000, 0x231b0000, + 0x00000000, 0x27110800, + 0x00000000, 0x66900000, + 0x00000010, 0xb1c8000b, + 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, + 0x0000000c, 0x29520000, + 0x0000000c, 0x29520003, + 0x00000010, 0x06c20002, + 0x0000000c, 0x29520002, + 0x00000000, 0x22c58c00, + 0x00000000, 0x27650000, + 0x00000000, 0x26e40000, + 0x00000000, 0x23480000, + 0x00000008, 0x22000017, + 0x0000000c, 0x29800000, + 0x00000010, 0x001f0000, + 0x0000000c, 0x6bd70001, + 0x00000010, 0x20530000, + 0x00000018, 0x8000fe03, +}; + + +/* + * The RV2P block must be configured for the system + * page size, or more specifically, the number of + * usable rx_bd's per page, and should be called + * as follows prior to loading the RV2P firmware: + * + * BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE) + * + * The default value is 0xFF. + */ +#define BCE_RV2P_PROC2_MAX_BD_PAGE_LOC 5 +#define BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(value) { \ + bce_rv2p_proc2[BCE_RV2P_PROC2_MAX_BD_PAGE_LOC] = \ + (bce_rv2p_proc2[BCE_RV2P_PROC2_MAX_BD_PAGE_LOC] & ~0xFFFF) | (value); \ +} + + + diff --git a/freebsd/dev/bce/if_bcereg.h b/freebsd/dev/bce/if_bcereg.h new file mode 100644 index 00000000..4ed5fdda --- /dev/null +++ b/freebsd/dev/bce/if_bcereg.h @@ -0,0 +1,6796 @@ +/*- + * Copyright (c) 2006-2010 Broadcom Corporation + * David Christensen . All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Broadcom Corporation nor the name of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written consent. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _BCEREG_HH_DEFINED +#define _BCEREG_HH_DEFINED + +#ifdef HAVE_KERNEL_OPTION_HEADERS +#include +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include + +/****************************************************************************/ +/* Conversion to FreeBSD type definitions. */ +/****************************************************************************/ +#define u64 uint64_t +#define u32 uint32_t +#define u16 uint16_t +#define u8 uint8_t + +#if BYTE_ORDER == BIG_ENDIAN +#define __BIG_ENDIAN 1 +#undef __LITTLE_ENDIAN +#else +#undef __BIG_ENDIAN +#define __LITTLE_ENDIAN 1 +#endif + +#define BCE_DWORD_PRINTFB \ + "\020" \ + "\40b31" \ + "\37b30" \ + "\36b29" \ + "\35b28" \ + "\34b27" \ + "\33b26" \ + "\32b25" \ + "\31b24" \ + "\30b23" \ + "\27b22" \ + "\26b21" \ + "\25b20" \ + "\24b19" \ + "\23b18" \ + "\22b17" \ + "\21b16" \ + "\20b15" \ + "\17b14" \ + "\16b13" \ + "\15b12" \ + "\14b11" \ + "\13b10" \ + "\12b9" \ + "\11b8" \ + "\10b7" \ + "\07b6" \ + "\06b5" \ + "\05b4" \ + "\04b3" \ + "\03b2" \ + "\02b1" \ + "\01b0" + +/* MII Control Register 0x0 */ +#define BCE_BMCR_PRINTFB \ + "\020" \ + "\20Reset" \ + "\17Loopback" \ + "\16Spd0" \ + "\15AnegEna" \ + "\14PwrDn" \ + "\13Isolate" \ + "\12RstrtAneg" \ + "\11FD" \ + "\10CollTst" \ + "\07Spd1" \ + "\06Rsrvd" \ + "\05Rsrvd" \ + "\04Rsrvd" \ + "\03Rsrvd" \ + "\02Rsrvd" \ + "\01Rsrvd" + +/* MII Status Register 0x1 */ +#define BCE_BMSR_PRINTFB \ + "\020" \ + "\20Cap100T4" \ + "\17Cap100XFD" \ + "\16Cap100XHD" \ + "\15Cap10FD" \ + "\14Cap10HD" \ + "\13Cap100T2FD" \ + "\12Cap100T2HD" \ + "\11ExtStsPrsnt" \ + "\10Rsrvd" \ + "\07PrmblSupp" \ + "\06AnegCmpl" \ + "\05RemFaultDet" \ + "\04AnegCap" \ + "\03LnkUp" \ + "\02JabberDet" \ + "\01ExtCapSupp" + +/* MII Autoneg Advertisement Register 0x4 */ +#define BCE_ANAR_PRINTFB \ + "\020" \ + "\20AdvNxtPg" \ + "\17Rsrvd" \ + "\16AdvRemFault" \ + "\15Rsrvd" \ + "\14AdvAsymPause" \ + "\13AdvPause" \ + "\12Adv100T4" \ + "\11Adv100FD" \ + "\10Adv100HD" \ + "\07Adv10FD" \ + "\06Adv10HD" \ + "\05Rsrvd" \ + "\04Rsrvd" \ + "\03Rsrvd" \ + "\02Rsrvd" \ + "\01Adv802.3" + +/* MII Autoneg Link Partner Ability Register 0x5 */ +#define BCE_ANLPAR_PRINTFB \ + "\020" \ + "\20CapNxtPg" \ + "\17Ack" \ + "\16CapRemFault" \ + "\15Rsrvd" \ + "\14CapAsymPause" \ + "\13CapPause" \ + "\12Cap100T4" \ + "\11Cap100FD" \ + "\10Cap100HD" \ + "\07Cap10FD" \ + "\06Cap10HD" \ + "\05Rsrvd" \ + "\04Rsrvd" \ + "\03Rsrvd" \ + "\02Rsrvd" \ + "\01Cap802.3" + +/* 1000Base-T Control Register 0x09 */ +#define BCE_1000CTL_PRINTFB \ + "\020" \ + "\20Test3" \ + "\17Test2" \ + "\16Test1" \ + "\15MasterSlave" \ + "\14ForceMaster" \ + "\13SwitchDev" \ + "\12Adv1000TFD" \ + "\11Adv1000THD" \ + "\10Rsrvd" \ + "\07Rsrvd" \ + "\06Rsrvd" \ + "\05Rsrvd" \ + "\04Rsrvd" \ + "\03Rsrvd" \ + "\02Rsrvd" \ + "\01Rsrvd" + +/* MII 1000Base-T Status Register 0x0a */ +#define BCE_1000STS_PRINTFB \ + "\020" \ + "\20MstrSlvFault" \ + "\17Master" \ + "\16LclRcvrOk" \ + "\15RemRcvrOk" \ + "\14Cap1000FD" \ + "\13Cpa1000HD" \ + "\12Rsrvd" \ + "\11Rsrvd" + +/* MII Extended Status Register 0x0f */ +#define BCE_EXTSTS_PRINTFB \ + "\020" \ + "\20b15" \ + "\17b14" \ + "\16b13" \ + "\15b12" \ + "\14Rsrvd" \ + "\13Rsrvd" \ + "\12Rsrvd" \ + "\11Rsrvd" \ + "\10Rsrvd" \ + "\07Rsrvd" \ + "\06Rsrvd" \ + "\05Rsrvd" \ + "\04Rsrvd" \ + "\03Rsrvd" \ + "\02Rsrvd" \ + "\01Rsrvd" + +/* MII Autoneg Link Partner Ability Register 0x19 */ +#define BCE_AUXSTS_PRINTFB \ + "\020" \ + "\20AnegCmpl" \ + "\17AnegCmplAck" \ + "\16AnegAckDet" \ + "\15AnegAblDet" \ + "\14AnegNextPgWait" \ + "\13HCD" \ + "\12HCD" \ + "\11HCD" \ + "\10PrlDetFault" \ + "\07RemFault" \ + "\06PgRcvd" \ + "\05LnkPrtnrAnegAbl" \ + "\04LnkPrtnrNPAbl" \ + "\03LnkUp" \ + "\02EnaPauseRcv" \ + "\01EnaPausXmit" + +/* + * Remove before release: + * + * #define BCE_DEBUG + * #define BCE_NVRAM_WRITE_SUPPORT + * #define BCE_JUMBO_HDRSPLIT + */ + +/****************************************************************************/ +/* Debugging macros and definitions. */ +/****************************************************************************/ + +#define BCE_CP_LOAD 0x00000001 +#define BCE_CP_SEND 0x00000002 +#define BCE_CP_RECV 0x00000004 +#define BCE_CP_INTR 0x00000008 +#define BCE_CP_UNLOAD 0x00000010 +#define BCE_CP_RESET 0x00000020 +#define BCE_CP_PHY 0x00000040 +#define BCE_CP_NVRAM 0x00000080 +#define BCE_CP_FIRMWARE 0x00000100 +#define BCE_CP_CTX 0x00000200 +#define BCE_CP_REG 0x00000400 +#define BCE_CP_MISC 0x00400000 +#define BCE_CP_SPECIAL 0x00800000 +#define BCE_CP_ALL 0x00FFFFFF + +#define BCE_CP_MASK 0x00FFFFFF + +#define BCE_LEVEL_FATAL 0x00000000 +#define BCE_LEVEL_WARN 0x01000000 +#define BCE_LEVEL_INFO 0x02000000 +#define BCE_LEVEL_VERBOSE 0x03000000 +#define BCE_LEVEL_EXTREME 0x04000000 +#define BCE_LEVEL_INSANE 0x05000000 + +#define BCE_LEVEL_MASK 0xFF000000 + +#define BCE_WARN_LOAD (BCE_CP_LOAD | BCE_LEVEL_WARN) +#define BCE_INFO_LOAD (BCE_CP_LOAD | BCE_LEVEL_INFO) +#define BCE_VERBOSE_LOAD (BCE_CP_LOAD | BCE_LEVEL_VERBOSE) +#define BCE_EXTREME_LOAD (BCE_CP_LOAD | BCE_LEVEL_EXTREME) +#define BCE_INSANE_LOAD (BCE_CP_LOAD | BCE_LEVEL_INSANE) + +#define BCE_WARN_SEND (BCE_CP_SEND | BCE_LEVEL_WARN) +#define BCE_INFO_SEND (BCE_CP_SEND | BCE_LEVEL_INFO) +#define BCE_VERBOSE_SEND (BCE_CP_SEND | BCE_LEVEL_VERBOSE) +#define BCE_EXTREME_SEND (BCE_CP_SEND | BCE_LEVEL_EXTREME) +#define BCE_INSANE_SEND (BCE_CP_SEND | BCE_LEVEL_INSANE) + +#define BCE_WARN_RECV (BCE_CP_RECV | BCE_LEVEL_WARN) +#define BCE_INFO_RECV (BCE_CP_RECV | BCE_LEVEL_INFO) +#define BCE_VERBOSE_RECV (BCE_CP_RECV | BCE_LEVEL_VERBOSE) +#define BCE_EXTREME_RECV (BCE_CP_RECV | BCE_LEVEL_EXTREME) +#define BCE_INSANE_RECV (BCE_CP_RECV | BCE_LEVEL_INSANE) + +#define BCE_WARN_INTR (BCE_CP_INTR | BCE_LEVEL_WARN) +#define BCE_INFO_INTR (BCE_CP_INTR | BCE_LEVEL_INFO) +#define BCE_VERBOSE_INTR (BCE_CP_INTR | BCE_LEVEL_VERBOSE) +#define BCE_EXTREME_INTR (BCE_CP_INTR | BCE_LEVEL_EXTREME) +#define BCE_INSANE_INTR (BCE_CP_INTR | BCE_LEVEL_INSANE) + +#define BCE_WARN_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_WARN) +#define BCE_INFO_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_INFO) +#define BCE_VERBOSE_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_VERBOSE) +#define BCE_EXTREME_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_EXTREME) +#define BCE_INSANE_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_INSANE) + +#define BCE_WARN_RESET (BCE_CP_RESET | BCE_LEVEL_WARN) +#define BCE_INFO_RESET (BCE_CP_RESET | BCE_LEVEL_INFO) +#define BCE_VERBOSE_RESET (BCE_CP_RESET | BCE_LEVEL_VERBOSE) +#define BCE_EXTREME_RESET (BCE_CP_RESET | BCE_LEVEL_EXTREME) +#define BCE_INSANE_RESET (BCE_CP_RESET | BCE_LEVEL_INSANE) + +#define BCE_WARN_PHY (BCE_CP_PHY | BCE_LEVEL_WARN) +#define BCE_INFO_PHY (BCE_CP_PHY | BCE_LEVEL_INFO) +#define BCE_VERBOSE_PHY (BCE_CP_PHY | BCE_LEVEL_VERBOSE) +#define BCE_EXTREME_PHY (BCE_CP_PHY | BCE_LEVEL_EXTREME) +#define BCE_INSANE_PHY (BCE_CP_PHY | BCE_LEVEL_INSANE) + +#define BCE_WARN_NVRAM (BCE_CP_NVRAM | BCE_LEVEL_WARN) +#define BCE_INFO_NVRAM (BCE_CP_NVRAM | BCE_LEVEL_INFO) +#define BCE_VERBOSE_NVRAM (BCE_CP_NVRAM | BCE_LEVEL_VERBOSE) +#define BCE_EXTREME_NVRAM (BCE_CP_NVRAM | BCE_LEVEL_EXTREME) +#define BCE_INSANE_NVRAM (BCE_CP_NVRAM | BCE_LEVEL_INSANE) + +#define BCE_WARN_FIRMWARE (BCE_CP_FIRMWARE | BCE_LEVEL_WARN) +#define BCE_INFO_FIRMWARE (BCE_CP_FIRMWARE | BCE_LEVEL_INFO) +#define BCE_VERBOSE_FIRMWARE (BCE_CP_FIRMWARE | BCE_LEVEL_VERBOSE) +#define BCE_EXTREME_FIRMWARE (BCE_CP_FIRMWARE | BCE_LEVEL_EXTREME) +#define BCE_INSANE_FIRMWARE (BCE_CP_FIRMWARE | BCE_LEVEL_INSANE) + +#define BCE_WARN_CTX (BCE_CP_CTX | BCE_LEVEL_WARN) +#define BCE_INFO_CTX (BCE_CP_CTX | BCE_LEVEL_INFO) +#define BCE_VERBOSE_CTX (BCE_CP_CTX | BCE_LEVEL_VERBOSE) +#define BCE_EXTREME_CTX (BCE_CP_CTX | BCE_LEVEL_EXTREME) +#define BCE_INSANE_CTX (BCE_CP_CTX | BCE_LEVEL_INSANE) + +#define BCE_WARN_REG (BCE_CP_REG | BCE_LEVEL_WARN) +#define BCE_INFO_REG (BCE_CP_REG | BCE_LEVEL_INFO) +#define BCE_VERBOSE_REG (BCE_CP_REG | BCE_LEVEL_VERBOSE) +#define BCE_EXTREME_REG (BCE_CP_REG | BCE_LEVEL_EXTREME) +#define BCE_INSANE_REG (BCE_CP_REG | BCE_LEVEL_INSANE) + +#define BCE_WARN_MISC (BCE_CP_MISC | BCE_LEVEL_WARN) +#define BCE_INFO_MISC (BCE_CP_MISC | BCE_LEVEL_INFO) +#define BCE_VERBOSE_MISC (BCE_CP_MISC | BCE_LEVEL_VERBOSE) +#define BCE_EXTREME_MISC (BCE_CP_MISC | BCE_LEVEL_EXTREME) +#define BCE_INSANE_MISC (BCE_CP_MISC | BCE_LEVEL_INSANE) + +#define BCE_WARN_SPECIAL (BCE_CP_SPECIAL | BCE_LEVEL_WARN) +#define BCE_INFO_SPECIAL (BCE_CP_SPECIAL | BCE_LEVEL_INFO) +#define BCE_VERBOSE_SPECIAL (BCE_CP_SPECIAL | BCE_LEVEL_VERBOSE) +#define BCE_EXTREME_SPECIAL (BCE_CP_SPECIAL | BCE_LEVEL_EXTREME) +#define BCE_INSANE_SPECIAL (BCE_CP_SPECIAL | BCE_LEVEL_INSANE) + +#define BCE_FATAL (BCE_CP_ALL | BCE_LEVEL_FATAL) +#define BCE_WARN (BCE_CP_ALL | BCE_LEVEL_WARN) +#define BCE_INFO (BCE_CP_ALL | BCE_LEVEL_INFO) +#define BCE_VERBOSE (BCE_CP_ALL | BCE_LEVEL_VERBOSE) +#define BCE_EXTREME (BCE_CP_ALL | BCE_LEVEL_EXTREME) +#define BCE_INSANE (BCE_CP_ALL | BCE_LEVEL_INSANE) + +#define BCE_CODE_PATH(cp) ((cp & BCE_CP_MASK) & bce_debug) +#define BCE_MSG_LEVEL(lv) \ + ((lv & BCE_LEVEL_MASK) <= (bce_debug & BCE_LEVEL_MASK)) +#define BCE_LOG_MSG(m) (BCE_CODE_PATH(m) && BCE_MSG_LEVEL(m)) + +#ifdef BCE_DEBUG + +/* Print a message based on the logging level and code path. */ +#define DBPRINT(sc, level, format, args...) \ + if (BCE_LOG_MSG(level)) { \ + device_printf(sc->bce_dev, format, ## args); \ + } + +/* Runs a particular command when debugging is enabled. */ +#define DBRUN(args...) \ + do { \ + args; \ + } while (0) + +/* Runs a particular command based on the logging level and code path. */ +#define DBRUNMSG(msg, args...) \ + if (BCE_LOG_MSG(msg)) { \ + args; \ + } + +/* Runs a particular command based on the logging level. */ +#define DBRUNLV(level, args...) \ + if (BCE_MSG_LEVEL(level)) { \ + args; \ + } + +/* Runs a particular command based on the code path. */ +#define DBRUNCP(cp, args...) \ + if (BCE_CODE_PATH(cp)) { \ + args; \ + } + +/* Runs a particular command based on a condition. */ +#define DBRUNIF(cond, args...) \ + if (cond) { \ + args; \ + } + +/* Announces function entry. */ +#define DBENTER(cond) \ + DBPRINT(sc, (cond), "%s(enter)\n", __FUNCTION__) + +/* Announces function exit. */ +#define DBEXIT(cond) \ + DBPRINT(sc, (cond), "%s(exit)\n", __FUNCTION__) + +/* Temporarily override the debug level. */ +#define DBPUSH(cond) \ + u32 bce_debug_temp = bce_debug; \ + bce_debug |= cond; + +/* Restore the previously overriden debug level. */ +#define DBPOP() \ + bce_debug = bce_debug_temp; + +/* Needed for random() function which is only used in debugging. */ +#include + +/* Returns FALSE in "defects" per 2^31 - 1 calls, otherwise returns TRUE. */ +#define DB_RANDOMFALSE(defects) (random() > defects) +#define DB_OR_RANDOMFALSE(defects) || (random() > defects) +#define DB_AND_RANDOMFALSE(defects) && (random() > ddfects) + +/* Returns TRUE in "defects" per 2^31 - 1 calls, otherwise returns FALSE. */ +#define DB_RANDOMTRUE(defects) (random() < defects) +#define DB_OR_RANDOMTRUE(defects) || (random() < defects) +#define DB_AND_RANDOMTRUE(defects) && (random() < defects) + +#define DB_PRINT_PHY_REG(reg, val) \ +switch(reg) { \ +case 0x00: DBPRINT(sc, BCE_INSANE_PHY, \ + "%s(): phy = %d, reg = 0x%04X (BMCR ), val = 0x%b\n", \ + __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \ + BCE_BMCR_PRINTFB); break; \ +case 0x01: DBPRINT(sc, BCE_INSANE_PHY, \ + "%s(): phy = %d, reg = 0x%04X (BMSR ), val = 0x%b\n", \ + __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \ + BCE_BMSR_PRINTFB); break; \ +case 0x04: DBPRINT(sc, BCE_INSANE_PHY, \ + "%s(): phy = %d, reg = 0x%04X (ANAR ), val = 0x%b\n", \ + __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \ + BCE_ANAR_PRINTFB); break; \ +case 0x05: DBPRINT(sc, BCE_INSANE_PHY, \ + "%s(): phy = %d, reg = 0x%04X (ANLPAR ), val = 0x%b\n", \ + __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \ + BCE_ANLPAR_PRINTFB); break; \ +case 0x09: DBPRINT(sc, BCE_INSANE_PHY, \ + "%s(): phy = %d, reg = 0x%04X (1000CTL), val = 0x%b\n", \ + __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \ + BCE_1000CTL_PRINTFB); break; \ +case 0x0a: DBPRINT(sc, BCE_INSANE_PHY, \ + "%s(): phy = %d, reg = 0x%04X (1000STS), val = 0x%b\n", \ + __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \ + BCE_1000STS_PRINTFB); break; \ +case 0x0f: DBPRINT(sc, BCE_INSANE_PHY, \ + "%s(): phy = %d, reg = 0x%04X (EXTSTS ), val = 0x%b\n", \ + __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \ + BCE_EXTSTS_PRINTFB); break; \ +case 0x19: DBPRINT(sc, BCE_INSANE_PHY, \ + "%s(): phy = %d, reg = 0x%04X (AUXSTS ), val = 0x%b\n", \ + __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \ + BCE_AUXSTS_PRINTFB); break; \ +default: DBPRINT(sc, BCE_INSANE_PHY, \ + "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n", \ + __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff); \ + } + +#else + +#define DBPRINT(level, format, args...) +#define DBRUN(args...) +#define DBRUNMSG(msg, args...) +#define DBRUNLV(level, args...) +#define DBRUNCP(cp, args...) +#define DBRUNIF(cond, args...) +#define DBENTER(cond) +#define DBEXIT(cond) +#define DBPUSH(cond) +#define DBPOP() +#define DB_RANDOMFALSE(defects) +#define DB_OR_RANDOMFALSE(percent) +#define DB_AND_RANDOMFALSE(percent) +#define DB_RANDOMTRUE(defects) +#define DB_OR_RANDOMTRUE(percent) +#define DB_AND_RANDOMTRUE(percent) +#define DB_PRINT_PHY_REG(reg, val) + +#endif /* BCE_DEBUG */ + + +#if __FreeBSD_version < 800054 +#if defined(__i386__) || defined(__amd64__) +#define mb() __asm volatile("mfence" ::: "memory") +#define wmb() __asm volatile("sfence" ::: "memory") +#define rmb() __asm volatile("lfence" ::: "memory") +#else +#define mb() +#define rmb() +#define wmb() +#endif +#endif + +/****************************************************************************/ +/* Device identification definitions. */ +/****************************************************************************/ +#define BRCM_VENDORID 0x14E4 +#define BRCM_DEVICEID_BCM5706 0x164A +#define BRCM_DEVICEID_BCM5706S 0x16AA +#define BRCM_DEVICEID_BCM5708 0x164C +#define BRCM_DEVICEID_BCM5708S 0x16AC +#define BRCM_DEVICEID_BCM5709 0x1639 +#define BRCM_DEVICEID_BCM5709S 0x163A +#define BRCM_DEVICEID_BCM5716 0x163B + +#define HP_VENDORID 0x103C + +#define PCI_ANY_ID (u_int16_t) (~0U) + +/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ + +#define BCE_CHIP_NUM(sc) (((sc)->bce_chipid) & 0xffff0000) +#define BCE_CHIP_NUM_5706 0x57060000 +#define BCE_CHIP_NUM_5708 0x57080000 +#define BCE_CHIP_NUM_5709 0x57090000 +#define BCE_CHIP_NUM_5716 0x57160000 + +#define BCE_CHIP_REV(sc) (((sc)->bce_chipid) & 0x0000f000) +#define BCE_CHIP_REV_Ax 0x00000000 +#define BCE_CHIP_REV_Bx 0x00001000 +#define BCE_CHIP_REV_Cx 0x00002000 + +#define BCE_CHIP_METAL(sc) (((sc)->bce_chipid) & 0x00000ff0) +#define BCE_CHIP_BOND(bp) (((sc)->bce_chipid) & 0x0000000f) + +#define BCE_CHIP_ID(sc) (((sc)->bce_chipid) & 0xfffffff0) +#define BCE_CHIP_ID_5706_A0 0x57060000 +#define BCE_CHIP_ID_5706_A1 0x57060010 +#define BCE_CHIP_ID_5706_A2 0x57060020 +#define BCE_CHIP_ID_5706_A3 0x57060030 +#define BCE_CHIP_ID_5708_A0 0x57080000 +#define BCE_CHIP_ID_5708_B0 0x57081000 +#define BCE_CHIP_ID_5708_B1 0x57081010 +#define BCE_CHIP_ID_5708_B2 0x57081020 +#define BCE_CHIP_ID_5709_A0 0x57090000 +#define BCE_CHIP_ID_5709_A1 0x57090010 +#define BCE_CHIP_ID_5709_B0 0x57091000 +#define BCE_CHIP_ID_5709_B1 0x57091010 +#define BCE_CHIP_ID_5709_B2 0x57091020 +#define BCE_CHIP_ID_5709_C0 0x57092000 +#define BCE_CHIP_ID_5716_C0 0x57162000 + +#define BCE_CHIP_BOND_ID(sc) (((sc)->bce_chipid) & 0xf) + +/* A serdes chip will have the first bit of the bond id set. */ +#define BCE_CHIP_BOND_ID_SERDES_BIT 0x01 + + +/* shorthand one */ +#define BCE_ASICREV(x) ((x) >> 28) +#define BCE_ASICREV_BCM5700 0x06 + +/* chip revisions */ +#define BCE_CHIPREV(x) ((x) >> 24) +#define BCE_CHIPREV_5700_AX 0x70 +#define BCE_CHIPREV_5700_BX 0x71 +#define BCE_CHIPREV_5700_CX 0x72 +#define BCE_CHIPREV_5701_AX 0x00 + +struct bce_type { + u_int16_t bce_vid; + u_int16_t bce_did; + u_int16_t bce_svid; + u_int16_t bce_sdid; + char *bce_name; +}; + +/****************************************************************************/ +/* Byte order conversions. */ +/****************************************************************************/ +#if __FreeBSD_version >= 500000 +#define bce_htobe16(x) htobe16(x) +#define bce_htobe32(x) htobe32(x) +#define bce_htobe64(x) htobe64(x) +#define bce_htole16(x) htole16(x) +#define bce_htole32(x) htole32(x) +#define bce_htole64(x) htole64(x) + +#define bce_be16toh(x) be16toh(x) +#define bce_be32toh(x) be32toh(x) +#define bce_be64toh(x) be64toh(x) +#define bce_le16toh(x) le16toh(x) +#define bce_le32toh(x) le32toh(x) +#define bce_le64toh(x) le64toh(x) +#else +#define bce_htobe16(x) (x) +#define bce_htobe32(x) (x) +#define bce_htobe64(x) (x) +#define bce_htole16(x) (x) +#define bce_htole32(x) (x) +#define bce_htole64(x) (x) + +#define bce_be16toh(x) (x) +#define bce_be32toh(x) (x) +#define bce_be64toh(x) (x) +#define bce_le16toh(x) (x) +#define bce_le32toh(x) (x) +#define bce_le64toh(x) (x) +#endif + + +/****************************************************************************/ +/* NVRAM Access */ +/****************************************************************************/ + +/* Buffered flash (Atmel: AT45DB011B) specific information */ +#define SEEPROM_PAGE_BITS 2 +#define SEEPROM_PHY_PAGE_SIZE (1 << SEEPROM_PAGE_BITS) +#define SEEPROM_BYTE_ADDR_MASK (SEEPROM_PHY_PAGE_SIZE-1) +#define SEEPROM_PAGE_SIZE 4 +#define SEEPROM_TOTAL_SIZE 65536 + +#define BUFFERED_FLASH_PAGE_BITS 9 +#define BUFFERED_FLASH_PHY_PAGE_SIZE (1 << BUFFERED_FLASH_PAGE_BITS) +#define BUFFERED_FLASH_BYTE_ADDR_MASK (BUFFERED_FLASH_PHY_PAGE_SIZE-1) +#define BUFFERED_FLASH_PAGE_SIZE 264 +#define BUFFERED_FLASH_TOTAL_SIZE 0x21000 + +#define SAIFUN_FLASH_PAGE_BITS 8 +#define SAIFUN_FLASH_PHY_PAGE_SIZE (1 << SAIFUN_FLASH_PAGE_BITS) +#define SAIFUN_FLASH_BYTE_ADDR_MASK (SAIFUN_FLASH_PHY_PAGE_SIZE-1) +#define SAIFUN_FLASH_PAGE_SIZE 256 +#define SAIFUN_FLASH_BASE_TOTAL_SIZE 65536 + +#define ST_MICRO_FLASH_PAGE_BITS 8 +#define ST_MICRO_FLASH_PHY_PAGE_SIZE (1 << ST_MICRO_FLASH_PAGE_BITS) +#define ST_MICRO_FLASH_BYTE_ADDR_MASK (ST_MICRO_FLASH_PHY_PAGE_SIZE-1) +#define ST_MICRO_FLASH_PAGE_SIZE 256 +#define ST_MICRO_FLASH_BASE_TOTAL_SIZE 65536 + +#define BCM5709_FLASH_PAGE_BITS 8 +#define BCM5709_FLASH_PHY_PAGE_SIZE (1 << BCM5709_FLASH_PAGE_BITS) +#define BCM5709_FLASH_BYTE_ADDR_MASK (BCM5709_FLASH_PHY_PAGE_SIZE-1) +#define BCM5709_FLASH_PAGE_SIZE 256 + +#define NVRAM_TIMEOUT_COUNT 30000 +#define BCE_FLASHDESC_MAX 64 + +#define FLASH_STRAP_MASK (BCE_NVM_CFG1_FLASH_MODE | \ + BCE_NVM_CFG1_BUFFER_MODE | BCE_NVM_CFG1_PROTECT_MODE | \ + BCE_NVM_CFG1_FLASH_SIZE) + +#define FLASH_BACKUP_STRAP_MASK (0xf << 26) + +struct flash_spec { + u32 strapping; + u32 config1; + u32 config2; + u32 config3; + u32 write1; +#define BCE_NV_BUFFERED 0x00000001 +#define BCE_NV_TRANSLATE 0x00000002 +#define BCE_NV_WREN 0x00000004 + u32 flags; + u32 page_bits; + u32 page_size; + u32 addr_mask; + u32 total_size; + u8 *name; +}; + + +/****************************************************************************/ +/* Shared Memory layout */ +/* The BCE bootcode will initialize this data area with port configurtion */ +/* information which can be accessed by the driver. */ +/****************************************************************************/ + +/* + * This value (in milliseconds) determines the frequency of the driver + * issuing the PULSE message code. The firmware monitors this periodic + * pulse to determine when to switch to an OS-absent mode. + */ +#define DRV_PULSE_PERIOD_MS 250 + +/* + * This value (in milliseconds) determines how long the driver should + * wait for an acknowledgement from the firmware before timing out. Once + * the firmware has timed out, the driver will assume there is no firmware + * running and there won't be any firmware-driver synchronization during a + * driver reset. + */ +#define FW_ACK_TIME_OUT_MS 1000 + + +#define BCE_DRV_RESET_SIGNATURE 0x00000000 +#define BCE_DRV_RESET_SIGNATURE_MAGIC 0x4841564b /* HAVK */ + +#define BCE_DRV_MB 0x00000004 +#define BCE_DRV_MSG_CODE 0xff000000 +#define BCE_DRV_MSG_CODE_RESET 0x01000000 +#define BCE_DRV_MSG_CODE_UNLOAD 0x02000000 +#define BCE_DRV_MSG_CODE_SHUTDOWN 0x03000000 +#define BCE_DRV_MSG_CODE_SUSPEND_WOL 0x04000000 +#define BCE_DRV_MSG_CODE_FW_TIMEOUT 0x05000000 +#define BCE_DRV_MSG_CODE_PULSE 0x06000000 +#define BCE_DRV_MSG_CODE_DIAG 0x07000000 +#define BCE_DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000 +#define BCE_DRV_MSG_CODE_UNLOAD_LNK_DN 0x0b000000 +#define BCE_DRV_MSG_CODE_CMD_SET_LINK 0x10000000 + +#define BCE_DRV_MSG_DATA 0x00ff0000 +#define BCE_DRV_MSG_DATA_WAIT0 0x00010000 +#define BCE_DRV_MSG_DATA_WAIT1 0x00020000 +#define BCE_DRV_MSG_DATA_WAIT2 0x00030000 +#define BCE_DRV_MSG_DATA_WAIT3 0x00040000 + +#define BCE_DRV_MSG_SEQ 0x0000ffff + +#define BCE_FW_MB 0x00000008 +#define BCE_FW_MSG_ACK 0x0000ffff +#define BCE_FW_MSG_STATUS_MASK 0x00ff0000 +#define BCE_FW_MSG_STATUS_OK 0x00000000 +#define BCE_FW_MSG_STATUS_INVALID_ARGS 0x00010000 +#define BCE_FW_MSG_STATUS_DRV_PRSNT 0x00020000 +#define BCE_FW_MSG_STATUS_FAILURE 0x00ff0000 + +#define BCE_LINK_STATUS 0x0000000c +#define BCE_LINK_STATUS_INIT_VALUE 0xffffffff +#define BCE_LINK_STATUS_LINK_UP 0x1 +#define BCE_LINK_STATUS_LINK_DOWN 0x0 +#define BCE_LINK_STATUS_SPEED_MASK 0x1e +#define BCE_LINK_STATUS_AN_INCOMPLETE (0<<1) +#define BCE_LINK_STATUS_10HALF (1<<1) +#define BCE_LINK_STATUS_10FULL (2<<1) +#define BCE_LINK_STATUS_100HALF (3<<1) +#define BCE_LINK_STATUS_100BASE_T4 (4<<1) +#define BCE_LINK_STATUS_100FULL (5<<1) +#define BCE_LINK_STATUS_1000HALF (6<<1) +#define BCE_LINK_STATUS_1000FULL (7<<1) +#define BCE_LINK_STATUS_2500HALF (8<<1) +#define BCE_LINK_STATUS_2500FULL (9<<1) +#define BCE_LINK_STATUS_AN_ENABLED (1<<5) +#define BCE_LINK_STATUS_AN_COMPLETE (1<<6) +#define BCE_LINK_STATUS_PARALLEL_DET (1<<7) +#define BCE_LINK_STATUS_RESERVED (1<<8) +#define BCE_LINK_STATUS_PARTNER_AD_1000FULL (1<<9) +#define BCE_LINK_STATUS_PARTNER_AD_1000HALF (1<<10) +#define BCE_LINK_STATUS_PARTNER_AD_100BT4 (1<<11) +#define BCE_LINK_STATUS_PARTNER_AD_100FULL (1<<12) +#define BCE_LINK_STATUS_PARTNER_AD_100HALF (1<<13) +#define BCE_LINK_STATUS_PARTNER_AD_10FULL (1<<14) +#define BCE_LINK_STATUS_PARTNER_AD_10HALF (1<<15) +#define BCE_LINK_STATUS_TX_FC_ENABLED (1<<16) +#define BCE_LINK_STATUS_RX_FC_ENABLED (1<<17) +#define BCE_LINK_STATUS_PARTNER_SYM_PAUSE_CAP (1<<18) +#define BCE_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP (1<<19) +#define BCE_LINK_STATUS_SERDES_LINK (1<<20) +#define BCE_LINK_STATUS_PARTNER_AD_2500FULL (1<<21) +#define BCE_LINK_STATUS_PARTNER_AD_2500HALF (1<<22) + +#define BCE_DRV_PULSE_MB 0x00000010 +#define BCE_DRV_PULSE_SEQ_MASK 0x00007fff + +#define BCE_MB_ARGS_0 0x00000014 +#define BCE_MB_ARGS_1 0x00000018 + +/* Indicate to the firmware not to go into the + * OS absent when it is not getting driver pulse. + * This is used for debugging. */ +#define BCE_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE 0x00080000 + +#define BCE_DEV_INFO_SIGNATURE 0x00000020 +#define BCE_DEV_INFO_SIGNATURE_MAGIC 0x44564900 +#define BCE_DEV_INFO_SIGNATURE_MAGIC_MASK 0xffffff00 +#define BCE_DEV_INFO_FEATURE_CFG_VALID 0x01 +#define BCE_DEV_INFO_SECONDARY_PORT 0x80 +#define BCE_DEV_INFO_DRV_ALWAYS_ALIVE 0x40 + +#define BCE_SHARED_HW_CFG_PART_NUM 0x00000024 + +#define BCE_SHARED_HW_CFG_POWER_DISSIPATED 0x00000034 +#define BCE_SHARED_HW_CFG_POWER_STATE_D3_MASK 0xff000000 +#define BCE_SHARED_HW_CFG_POWER_STATE_D2_MASK 0xff0000 +#define BCE_SHARED_HW_CFG_POWER_STATE_D1_MASK 0xff00 +#define BCE_SHARED_HW_CFG_POWER_STATE_D0_MASK 0xff + +#define BCE_SHARED_HW_CFG_POWER_CONSUMED 0x00000038 +#define BCE_SHARED_HW_CFG_CONFIG 0x0000003c +#define BCE_SHARED_HW_CFG_DESIGN_NIC 0 +#define BCE_SHARED_HW_CFG_DESIGN_LOM 0x1 +#define BCE_SHARED_HW_CFG_PHY_COPPER 0 +#define BCE_SHARED_HW_CFG_PHY_FIBER 0x2 +#define BCE_SHARED_HW_CFG_PHY_2_5G 0x20 +#define BCE_SHARED_HW_CFG_PHY_BACKPLANE 0x40 +#define BCE_SHARED_HW_CFG_LED_MODE_SHIFT_BITS 8 +#define BCE_SHARED_HW_CFG_LED_MODE_MASK 0x300 +#define BCE_SHARED_HW_CFG_LED_MODE_MAC 0 +#define BCE_SHARED_HW_CFG_LED_MODE_GPHY1 0x100 +#define BCE_SHARED_HW_CFG_LED_MODE_GPHY2 0x200 + +#define BCE_SHARED_HW_CFG_CONFIG2 0x00000040 +#define BCE_SHARED_HW_CFG2_NVM_SIZE_MASK 0x00fff000 + +#define BCE_DEV_INFO_BC_REV 0x0000004c + +#define BCE_PORT_HW_CFG_MAC_UPPER 0x00000050 +#define BCE_PORT_HW_CFG_UPPERMAC_MASK 0xffff + +#define BCE_PORT_HW_CFG_MAC_LOWER 0x00000054 +#define BCE_PORT_HW_CFG_CONFIG 0x00000058 +#define BCE_PORT_HW_CFG_CFG_TXCTL3_MASK 0x0000ffff +#define BCE_PORT_HW_CFG_CFG_DFLT_LINK_MASK 0x001f0000 +#define BCE_PORT_HW_CFG_CFG_DFLT_LINK_AN 0x00000000 +#define BCE_PORT_HW_CFG_CFG_DFLT_LINK_1G 0x00030000 +#define BCE_PORT_HW_CFG_CFG_DFLT_LINK_2_5G 0x00040000 + +#define BCE_PORT_HW_CFG_IMD_MAC_A_UPPER 0x00000068 +#define BCE_PORT_HW_CFG_IMD_MAC_A_LOWER 0x0000006c +#define BCE_PORT_HW_CFG_IMD_MAC_B_UPPER 0x00000070 +#define BCE_PORT_HW_CFG_IMD_MAC_B_LOWER 0x00000074 +#define BCE_PORT_HW_CFG_ISCSI_MAC_UPPER 0x00000078 +#define BCE_PORT_HW_CFG_ISCSI_MAC_LOWER 0x0000007c + +#define BCE_DEV_INFO_PER_PORT_HW_CONFIG2 0x000000b4 + +#define BCE_DEV_INFO_FORMAT_REV 0x000000c4 +#define BCE_DEV_INFO_FORMAT_REV_MASK 0xff000000 +#define BCE_DEV_INFO_FORMAT_REV_ID ('A' << 24) + +#define BCE_SHARED_FEATURE 0x000000c8 +#define BCE_SHARED_FEATURE_MASK 0xffffffff + +#define BCE_PORT_FEATURE 0x000000d8 +#define BCE_PORT2_FEATURE 0x00000014c +#define BCE_PORT_FEATURE_WOL_ENABLED 0x01000000 +#define BCE_PORT_FEATURE_MBA_ENABLED 0x02000000 +#define BCE_PORT_FEATURE_ASF_ENABLED 0x04000000 +#define BCE_PORT_FEATURE_IMD_ENABLED 0x08000000 +#define BCE_PORT_FEATURE_BAR1_SIZE_MASK 0xf +#define BCE_PORT_FEATURE_BAR1_SIZE_DISABLED 0x0 +#define BCE_PORT_FEATURE_BAR1_SIZE_64K 0x1 +#define BCE_PORT_FEATURE_BAR1_SIZE_128K 0x2 +#define BCE_PORT_FEATURE_BAR1_SIZE_256K 0x3 +#define BCE_PORT_FEATURE_BAR1_SIZE_512K 0x4 +#define BCE_PORT_FEATURE_BAR1_SIZE_1M 0x5 +#define BCE_PORT_FEATURE_BAR1_SIZE_2M 0x6 +#define BCE_PORT_FEATURE_BAR1_SIZE_4M 0x7 +#define BCE_PORT_FEATURE_BAR1_SIZE_8M 0x8 +#define BCE_PORT_FEATURE_BAR1_SIZE_16M 0x9 +#define BCE_PORT_FEATURE_BAR1_SIZE_32M 0xa +#define BCE_PORT_FEATURE_BAR1_SIZE_64M 0xb +#define BCE_PORT_FEATURE_BAR1_SIZE_128M 0xc +#define BCE_PORT_FEATURE_BAR1_SIZE_256M 0xd +#define BCE_PORT_FEATURE_BAR1_SIZE_512M 0xe +#define BCE_PORT_FEATURE_BAR1_SIZE_1G 0xf + +#define BCE_PORT_FEATURE_WOL 0xdc +#define BCE_PORT2_FEATURE_WOL 0x150 +#define BCE_PORT_FEATURE_WOL_DEFAULT_SHIFT_BITS 4 +#define BCE_PORT_FEATURE_WOL_DEFAULT_MASK 0x30 +#define BCE_PORT_FEATURE_WOL_DEFAULT_DISABLE 0 +#define BCE_PORT_FEATURE_WOL_DEFAULT_MAGIC 0x10 +#define BCE_PORT_FEATURE_WOL_DEFAULT_ACPI 0x20 +#define BCE_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x30 +#define BCE_PORT_FEATURE_WOL_LINK_SPEED_MASK 0xf +#define BCE_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG 0 +#define BCE_PORT_FEATURE_WOL_LINK_SPEED_10HALF 1 +#define BCE_PORT_FEATURE_WOL_LINK_SPEED_10FULL 2 +#define BCE_PORT_FEATURE_WOL_LINK_SPEED_100HALF 3 +#define BCE_PORT_FEATURE_WOL_LINK_SPEED_100FULL 4 +#define BCE_PORT_FEATURE_WOL_LINK_SPEED_1000HALF 5 +#define BCE_PORT_FEATURE_WOL_LINK_SPEED_1000FULL 6 +#define BCE_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000 0x40 +#define BCE_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP 0x400 +#define BCE_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP 0x800 + +#define BCE_PORT_FEATURE_MBA 0xe0 +#define BCE_PORT2_FEATURE_MBA 0x154 +#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS 0 +#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x3 +#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0 +#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 1 +#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 2 +#define BCE_PORT_FEATURE_MBA_LINK_SPEED_SHIFT_BITS 2 +#define BCE_PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c +#define BCE_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG 0 +#define BCE_PORT_FEATURE_MBA_LINK_SPEED_10HALF 0x4 +#define BCE_PORT_FEATURE_MBA_LINK_SPEED_10FULL 0x8 +#define BCE_PORT_FEATURE_MBA_LINK_SPEED_100HALF 0xc +#define BCE_PORT_FEATURE_MBA_LINK_SPEED_100FULL 0x10 +#define BCE_PORT_FEATURE_MBA_LINK_SPEED_1000HALF 0x14 +#define BCE_PORT_FEATURE_MBA_LINK_SPEED_1000FULL 0x18 +#define BCE_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x40 +#define BCE_PORT_FEATURE_MBA_HOTKEY_CTRL_S 0 +#define BCE_PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x80 +#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS 8 +#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0xff00 +#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0 +#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K 0x100 +#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x200 +#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x300 +#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x400 +#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x500 +#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x600 +#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x700 +#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x800 +#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x900 +#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0xa00 +#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0xb00 +#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0xc00 +#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0xd00 +#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0xe00 +#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0xf00 +#define BCE_PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS 16 +#define BCE_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0xf0000 +#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS 20 +#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x300000 +#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0 +#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x100000 +#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x200000 +#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x300000 + +#define BCE_PORT_FEATURE_IMD 0xe4 +#define BCE_PORT2_FEATURE_IMD 0x158 +#define BCE_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT 0 +#define BCE_PORT_FEATURE_IMD_LINK_OVERRIDE_ENABLE 1 + +#define BCE_PORT_FEATURE_VLAN 0xe8 +#define BCE_PORT2_FEATURE_VLAN 0x15c +#define BCE_PORT_FEATURE_MBA_VLAN_TAG_MASK 0xffff +#define BCE_PORT_FEATURE_MBA_VLAN_ENABLE 0x10000 + +#define BCE_MFW_VER_PTR 0x00000014c + +#define BCE_BC_STATE_RESET_TYPE 0x000001c0 +#define BCE_BC_STATE_RESET_TYPE_SIG 0x00005254 +#define BCE_BC_STATE_RESET_TYPE_SIG_MASK 0x0000ffff + +#define BCE_BC_STATE_RESET_TYPE_NONE \ + (BCE_BC_STATE_RESET_TYPE_SIG | 0x00010000) +#define BCE_BC_STATE_RESET_TYPE_PCI \ + (BCE_BC_STATE_RESET_TYPE_SIG | 0x00020000) +#define BCE_BC_STATE_RESET_TYPE_VAUX \ + (BCE_BC_STATE_RESET_TYPE_SIG | 0x00030000) +#define BCE_BC_STATE_RESET_TYPE_DRV_MASK DRV_MSG_CODE +#define BCE_BC_STATE_RESET_TYPE_DRV_RESET \ + (BCE_BC_STATE_RESET_TYPE_SIG | DRV_MSG_CODE_RESET) +#define BCE_BC_STATE_RESET_TYPE_DRV_UNLOAD \ + (BCE_BC_STATE_RESET_TYPE_SIG | DRV_MSG_CODE_UNLOAD) +#define BCE_BC_STATE_RESET_TYPE_DRV_SHUTDOWN \ + (BCE_BC_STATE_RESET_TYPE_SIG | DRV_MSG_CODE_SHUTDOWN) +#define BCE_BC_STATE_RESET_TYPE_DRV_WOL \ + (BCE_BC_STATE_RESET_TYPE_SIG | DRV_MSG_CODE_WOL) +#define BCE_BC_STATE_RESET_TYPE_DRV_DIAG \ + (BCE_BC_STATE_RESET_TYPE_SIG | DRV_MSG_CODE_DIAG) +#define BCE_BC_STATE_RESET_TYPE_VALUE(msg) \ + (BCE_BC_STATE_RESET_TYPE_SIG | (msg)) + +#define BCE_BC_RESET_TYPE 0x000001c0 + +#define BCE_BC_STATE 0x000001c4 +#define BCE_BC_STATE_ERR_MASK 0x0000ff00 +#define BCE_BC_STATE_SIGN 0x42530000 +#define BCE_BC_STATE_SIGN_MASK 0xffff0000 +#define BCE_BC_STATE_BC1_START (BCE_BC_STATE_SIGN | 0x1) +#define BCE_BC_STATE_GET_NVM_CFG1 (BCE_BC_STATE_SIGN | 0x2) +#define BCE_BC_STATE_PROG_BAR (BCE_BC_STATE_SIGN | 0x3) +#define BCE_BC_STATE_INIT_VID (BCE_BC_STATE_SIGN | 0x4) +#define BCE_BC_STATE_GET_NVM_CFG2 (BCE_BC_STATE_SIGN | 0x5) +#define BCE_BC_STATE_APPLY_WKARND (BCE_BC_STATE_SIGN | 0x6) +#define BCE_BC_STATE_LOAD_BC2 (BCE_BC_STATE_SIGN | 0x7) +#define BCE_BC_STATE_GOING_BC2 (BCE_BC_STATE_SIGN | 0x8) +#define BCE_BC_STATE_GOING_DIAG (BCE_BC_STATE_SIGN | 0x9) +#define BCE_BC_STATE_RT_FINAL_INIT (BCE_BC_STATE_SIGN | 0x81) +#define BCE_BC_STATE_RT_WKARND (BCE_BC_STATE_SIGN | 0x82) +#define BCE_BC_STATE_RT_DRV_PULSE (BCE_BC_STATE_SIGN | 0x83) +#define BCE_BC_STATE_RT_FIOEVTS (BCE_BC_STATE_SIGN | 0x84) +#define BCE_BC_STATE_RT_DRV_CMD (BCE_BC_STATE_SIGN | 0x85) +#define BCE_BC_STATE_RT_LOW_POWER (BCE_BC_STATE_SIGN | 0x86) +#define BCE_BC_STATE_RT_SET_WOL (BCE_BC_STATE_SIGN | 0x87) +#define BCE_BC_STATE_RT_OTHER_FW (BCE_BC_STATE_SIGN | 0x88) +#define BCE_BC_STATE_RT_GOING_D3 (BCE_BC_STATE_SIGN | 0x89) +#define BCE_BC_STATE_ERR_BAD_VERSION (BCE_BC_STATE_SIGN | 0x0100) +#define BCE_BC_STATE_ERR_BAD_BC2_CRC (BCE_BC_STATE_SIGN | 0x0200) +#define BCE_BC_STATE_ERR_BC1_LOOP (BCE_BC_STATE_SIGN | 0x0300) +#define BCE_BC_STATE_ERR_UNKNOWN_CMD (BCE_BC_STATE_SIGN | 0x0400) +#define BCE_BC_STATE_ERR_DRV_DEAD (BCE_BC_STATE_SIGN | 0x0500) +#define BCE_BC_STATE_ERR_NO_RXP (BCE_BC_STATE_SIGN | 0x0600) +#define BCE_BC_STATE_ERR_TOO_MANY_RBUF (BCE_BC_STATE_SIGN | 0x0700) + +#define BCE_BC_STATE_CONDITION 0x000001c8 +#define BCE_CONDITION_INIT_POR 0x00000001 +#define BCE_CONDITION_INIT_VAUX_AVAIL 0x00000002 +#define BCE_CONDITION_INIT_PCI_AVAIL 0x00000004 +#define BCE_CONDITION_INIT_PCI_RESET 0x00000008 +#define BCE_CONDITION_INIT_HD_RESET 0x00000010 /* 5709/16 only */ +#define BCE_CONDITION_DRV_PRESENT 0x00000100 +#define BCE_CONDITION_LOW_POWER_LINK 0x00000200 +#define BCE_CONDITION_CORE_RST_OCCURRED 0x00000400 /* 5709/16 only */ +#define BCE_CONDITION_UNUSED 0x00000800 +#define BCE_CONDITION_BUSY_EXPROM 0x00001000 /* 5706/08 only */ + +#define BCE_CONDITION_MFW_RUN_UNKNOWN 0x00000000 +#define BCE_CONDITION_MFW_RUN_IPMI 0x00002000 +#define BCE_CONDITION_MFW_RUN_UMP 0x00004000 +#define BCE_CONDITION_MFW_RUN_NCSI 0x00006000 +#define BCE_CONDITION_MFW_RUN_NONE 0x0000e000 +#define BCE_CONDITION_MFW_RUN_MASK 0x0000e000 + +/* 5709/16 only */ +#define BCE_CONDITION_PM_STATE_MASK 0x00030000 +#define BCE_CONDITION_PM_STATE_FULL 0x00030000 +#define BCE_CONDITION_PM_STATE_PREP 0x00020000 +#define BCE_CONDITION_PM_STATE_UNPREP 0x00010000 +#define BCE_CONDITION_PM_RESERVED 0x00000000 + +/* 5709/16 only */ +#define BCE_CONDITION_RXMODE_KEEP_VLAN 0x00040000 +#define BCE_CONDITION_DRV_WOL_ENABLED 0x00080000 +#define BCE_CONDITION_PORT_DISABLED 0x00100000 +#define BCE_CONDITION_DRV_MAYBE_OUT 0x00200000 +#define BCE_CONDITION_DPFW_DEAD 0x00400000 + +#define BCE_BC_STATE_DEBUG_CMD 0x000001dc +#define BCE_BC_STATE_BC_DBG_CMD_SIGNATURE 0x42440000 +#define BCE_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK 0xffff0000 +#define BCE_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK 0xffff +#define BCE_BC_STATE_BC_DBG_CMD_LOOP_INFINITE 0xffff + +#define HOST_VIEW_SHMEM_BASE 0x167c00 + +/* + * PCI registers defined in the PCI 2.2 spec. + */ +#define BCE_PCI_PCIX_CMD 0x42 + + +/****************************************************************************/ +/* Convenience definitions. */ +/****************************************************************************/ +#define BCE_PRINTF(fmt, args...) \ + device_printf(sc->bce_dev, fmt, ##args) + +#define BCE_LOCK_INIT(_sc, _name) \ + mtx_init(&(_sc)->bce_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) +#define BCE_LOCK(_sc) mtx_lock(&(_sc)->bce_mtx) +#define BCE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bce_mtx, MA_OWNED) +#define BCE_UNLOCK(_sc) mtx_unlock(&(_sc)->bce_mtx) +#define BCE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bce_mtx) + +#ifdef BCE_DEBUG +#define REG_WR(sc, offset, val) bce_reg_wr(sc, offset, val) +#define REG_WR16(sc, offset, val) bce_reg_wr16(sc, offset, val) +#define REG_RD(sc, offset) bce_reg_rd(sc, offset) +#else +#define REG_WR(sc, offset, val) \ + bus_space_write_4(sc->bce_btag, sc->bce_bhandle, offset, val) +#define REG_WR16(sc, offset, val) \ + bus_space_write_2(sc->bce_btag, sc->bce_bhandle, offset, val) +#define REG_RD(sc, offset) \ + bus_space_read_4(sc->bce_btag, sc->bce_bhandle, offset) +#endif + +#define REG_RD_IND(sc, offset) bce_reg_rd_ind(sc, offset) +#define REG_WR_IND(sc, offset, val) bce_reg_wr_ind(sc, offset, val) +#define CTX_WR(sc, cid_addr, offset, val)bce_ctx_wr(sc, cid_addr, offset, val) +#define CTX_RD(sc, cid_addr, offset) bce_ctx_rd(sc, cid_addr, offset) + +#define BCE_SETBIT(sc, reg, x) \ + REG_WR(sc, reg, (REG_RD(sc, reg) | (x))) +#define BCE_CLRBIT(sc, reg, x) \ + REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x))) +#define PCI_SETBIT(dev, reg, x, s) \ + pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) +#define PCI_CLRBIT(dev, reg, x, s) \ + pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) + +#define BCE_STATS(x) (u_long) stats->stat_ ## x ## _lo + +#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) +#define BCE_ADDR_LO(y) ((u64) (y) & 0xFFFFFFFF) +#define BCE_ADDR_HI(y) ((u64) (y) >> 32) +#else +#define BCE_ADDR_LO(y) ((u32)y) +#define BCE_ADDR_HI(y) (0) +#endif + + +/****************************************************************************/ +/* Do not modify any of the following data structures, they are generated */ +/* from RTL code. */ +/* */ +/* Begin machine generated definitions. */ +/****************************************************************************/ + +/* + * tx_bd definition + */ +struct tx_bd { + u32 tx_bd_haddr_hi; + u32 tx_bd_haddr_lo; + u32 tx_bd_mss_nbytes; + u16 tx_bd_flags; + u16 tx_bd_vlan_tag; + #define TX_BD_FLAGS_CONN_FAULT (1<<0) + #define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1) + #define TX_BD_FLAGS_IP_CKSUM (1<<2) + #define TX_BD_FLAGS_VLAN_TAG (1<<3) + #define TX_BD_FLAGS_COAL_NOW (1<<4) + #define TX_BD_FLAGS_DONT_GEN_CRC (1<<5) + #define TX_BD_FLAGS_END (1<<6) + #define TX_BD_FLAGS_START (1<<7) + #define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8) + #define TX_BD_FLAGS_SW_FLAGS (1<<13) + #define TX_BD_FLAGS_SW_SNAP (1<<14) + #define TX_BD_FLAGS_SW_LSO (1<<15) + +}; + + +/* + * rx_bd definition + */ +struct rx_bd { + u32 rx_bd_haddr_hi; + u32 rx_bd_haddr_lo; + u32 rx_bd_len; + u32 rx_bd_flags; + #define RX_BD_FLAGS_NOPUSH (1<<0) + #define RX_BD_FLAGS_DUMMY (1<<1) + #define RX_BD_FLAGS_END (1<<2) + #define RX_BD_FLAGS_START (1<<3) + +}; + + +/* + * status_block definition + */ +struct status_block { + u32 status_attn_bits; + #define STATUS_ATTN_BITS_LINK_STATE (1L<<0) + #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT (1L<<1) + #define STATUS_ATTN_BITS_TX_BD_READ_ABORT (1L<<2) + #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT (1L<<3) + #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT (1L<<4) + #define STATUS_ATTN_BITS_TX_DMA_ABORT (1L<<5) + #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT (1L<<6) + #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT (1L<<7) + #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT (1L<<8) + #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT (1L<<9) + #define STATUS_ATTN_BITS_RX_MBUF_ABORT (1L<<10) + #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT (1L<<11) + #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT (1L<<12) + #define STATUS_ATTN_BITS_RX_V2P_ABORT (1L<<13) + #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT (1L<<14) + #define STATUS_ATTN_BITS_RX_DMA_ABORT (1L<<15) + #define STATUS_ATTN_BITS_COMPLETION_ABORT (1L<<16) + #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT (1L<<17) + #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT (1L<<18) + #define STATUS_ATTN_BITS_CONTEXT_ABORT (1L<<19) + #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT (1L<<20) + #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT (1L<<21) + #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT (1L<<22) + #define STATUS_ATTN_BITS_MAC_ABORT (1L<<23) + #define STATUS_ATTN_BITS_TIMER_ABORT (1L<<24) + #define STATUS_ATTN_BITS_DMAE_ABORT (1L<<25) + #define STATUS_ATTN_BITS_FLSH_ABORT (1L<<26) + #define STATUS_ATTN_BITS_GRC_ABORT (1L<<27) + #define STATUS_ATTN_BITS_PARITY_ERROR (1L<<31) + + u32 status_attn_bits_ack; +#if defined(__BIG_ENDIAN) + u16 status_tx_quick_consumer_index0; + u16 status_tx_quick_consumer_index1; + u16 status_tx_quick_consumer_index2; + u16 status_tx_quick_consumer_index3; + u16 status_rx_quick_consumer_index0; + u16 status_rx_quick_consumer_index1; + u16 status_rx_quick_consumer_index2; + u16 status_rx_quick_consumer_index3; + u16 status_rx_quick_consumer_index4; + u16 status_rx_quick_consumer_index5; + u16 status_rx_quick_consumer_index6; + u16 status_rx_quick_consumer_index7; + u16 status_rx_quick_consumer_index8; + u16 status_rx_quick_consumer_index9; + u16 status_rx_quick_consumer_index10; + u16 status_rx_quick_consumer_index11; + u16 status_rx_quick_consumer_index12; + u16 status_rx_quick_consumer_index13; + u16 status_rx_quick_consumer_index14; + u16 status_rx_quick_consumer_index15; + u16 status_completion_producer_index; + u16 status_cmd_consumer_index; + u16 status_idx; + u16 status_unused; +#elif defined(__LITTLE_ENDIAN) + u16 status_tx_quick_consumer_index1; + u16 status_tx_quick_consumer_index0; + u16 status_tx_quick_consumer_index3; + u16 status_tx_quick_consumer_index2; + u16 status_rx_quick_consumer_index1; + u16 status_rx_quick_consumer_index0; + u16 status_rx_quick_consumer_index3; + u16 status_rx_quick_consumer_index2; + u16 status_rx_quick_consumer_index5; + u16 status_rx_quick_consumer_index4; + u16 status_rx_quick_consumer_index7; + u16 status_rx_quick_consumer_index6; + u16 status_rx_quick_consumer_index9; + u16 status_rx_quick_consumer_index8; + u16 status_rx_quick_consumer_index11; + u16 status_rx_quick_consumer_index10; + u16 status_rx_quick_consumer_index13; + u16 status_rx_quick_consumer_index12; + u16 status_rx_quick_consumer_index15; + u16 status_rx_quick_consumer_index14; + u16 status_cmd_consumer_index; + u16 status_completion_producer_index; + u16 status_unused; + u16 status_idx; +#endif +}; + + +/* + * statistics_block definition + */ +struct statistics_block { + u32 stat_IfHCInOctets_hi; + u32 stat_IfHCInOctets_lo; + u32 stat_IfHCInBadOctets_hi; + u32 stat_IfHCInBadOctets_lo; + u32 stat_IfHCOutOctets_hi; + u32 stat_IfHCOutOctets_lo; + u32 stat_IfHCOutBadOctets_hi; + u32 stat_IfHCOutBadOctets_lo; + u32 stat_IfHCInUcastPkts_hi; + u32 stat_IfHCInUcastPkts_lo; + u32 stat_IfHCInMulticastPkts_hi; + u32 stat_IfHCInMulticastPkts_lo; + u32 stat_IfHCInBroadcastPkts_hi; + u32 stat_IfHCInBroadcastPkts_lo; + u32 stat_IfHCOutUcastPkts_hi; + u32 stat_IfHCOutUcastPkts_lo; + u32 stat_IfHCOutMulticastPkts_hi; + u32 stat_IfHCOutMulticastPkts_lo; + u32 stat_IfHCOutBroadcastPkts_hi; + u32 stat_IfHCOutBroadcastPkts_lo; + u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors; + u32 stat_Dot3StatsCarrierSenseErrors; + u32 stat_Dot3StatsFCSErrors; + u32 stat_Dot3StatsAlignmentErrors; + u32 stat_Dot3StatsSingleCollisionFrames; + u32 stat_Dot3StatsMultipleCollisionFrames; + u32 stat_Dot3StatsDeferredTransmissions; + u32 stat_Dot3StatsExcessiveCollisions; + u32 stat_Dot3StatsLateCollisions; + u32 stat_EtherStatsCollisions; + u32 stat_EtherStatsFragments; + u32 stat_EtherStatsJabbers; + u32 stat_EtherStatsUndersizePkts; + u32 stat_EtherStatsOversizePkts; + u32 stat_EtherStatsPktsRx64Octets; + u32 stat_EtherStatsPktsRx65Octetsto127Octets; + u32 stat_EtherStatsPktsRx128Octetsto255Octets; + u32 stat_EtherStatsPktsRx256Octetsto511Octets; + u32 stat_EtherStatsPktsRx512Octetsto1023Octets; + u32 stat_EtherStatsPktsRx1024Octetsto1522Octets; + u32 stat_EtherStatsPktsRx1523Octetsto9022Octets; + u32 stat_EtherStatsPktsTx64Octets; + u32 stat_EtherStatsPktsTx65Octetsto127Octets; + u32 stat_EtherStatsPktsTx128Octetsto255Octets; + u32 stat_EtherStatsPktsTx256Octetsto511Octets; + u32 stat_EtherStatsPktsTx512Octetsto1023Octets; + u32 stat_EtherStatsPktsTx1024Octetsto1522Octets; + u32 stat_EtherStatsPktsTx1523Octetsto9022Octets; + u32 stat_XonPauseFramesReceived; + u32 stat_XoffPauseFramesReceived; + u32 stat_OutXonSent; + u32 stat_OutXoffSent; + u32 stat_FlowControlDone; + u32 stat_MacControlFramesReceived; + u32 stat_XoffStateEntered; + u32 stat_IfInFramesL2FilterDiscards; + u32 stat_IfInRuleCheckerDiscards; + u32 stat_IfInFTQDiscards; + u32 stat_IfInMBUFDiscards; + u32 stat_IfInRuleCheckerP4Hit; + u32 stat_CatchupInRuleCheckerDiscards; + u32 stat_CatchupInFTQDiscards; + u32 stat_CatchupInMBUFDiscards; + u32 stat_CatchupInRuleCheckerP4Hit; + u32 stat_GenStat00; + u32 stat_GenStat01; + u32 stat_GenStat02; + u32 stat_GenStat03; + u32 stat_GenStat04; + u32 stat_GenStat05; + u32 stat_GenStat06; + u32 stat_GenStat07; + u32 stat_GenStat08; + u32 stat_GenStat09; + u32 stat_GenStat10; + u32 stat_GenStat11; + u32 stat_GenStat12; + u32 stat_GenStat13; + u32 stat_GenStat14; + u32 stat_GenStat15; +}; + + +/* + * l2_fhdr definition + */ +struct l2_fhdr { + u32 l2_fhdr_status; + #define L2_FHDR_STATUS_RULE_CLASS (0x7<<0) + #define L2_FHDR_STATUS_RULE_P2 (1<<3) + #define L2_FHDR_STATUS_RULE_P3 (1<<4) + #define L2_FHDR_STATUS_RULE_P4 (1<<5) + #define L2_FHDR_STATUS_L2_VLAN_TAG (1<<6) + #define L2_FHDR_STATUS_L2_LLC_SNAP (1<<7) + #define L2_FHDR_STATUS_RSS_HASH (1<<8) + #define L2_FHDR_STATUS_IP_DATAGRAM (1<<13) + #define L2_FHDR_STATUS_TCP_SEGMENT (1<<14) + #define L2_FHDR_STATUS_UDP_DATAGRAM (1<<15) + + #define L2_FHDR_STATUS_SPLIT (1<<16) + #define L2_FHDR_ERRORS_BAD_CRC (1<<17) + #define L2_FHDR_ERRORS_PHY_DECODE (1<<18) + #define L2_FHDR_ERRORS_ALIGNMENT (1<<19) + #define L2_FHDR_ERRORS_TOO_SHORT (1<<20) + #define L2_FHDR_ERRORS_GIANT_FRAME (1<<21) + #define L2_FHDR_ERRORS_TCP_XSUM (1<<28) + #define L2_FHDR_ERRORS_UDP_XSUM (1<<31) + + u32 l2_fhdr_hash; +#if defined(__BIG_ENDIAN) + u16 l2_fhdr_pkt_len; + u16 l2_fhdr_vlan_tag; + u16 l2_fhdr_ip_xsum; + u16 l2_fhdr_tcp_udp_xsum; +#elif defined(__LITTLE_ENDIAN) + u16 l2_fhdr_vlan_tag; + u16 l2_fhdr_pkt_len; + u16 l2_fhdr_tcp_udp_xsum; + u16 l2_fhdr_ip_xsum; +#endif +}; + +#define BCE_L2FHDR_PRINTFB \ + "\20" \ + "\40UDP_XSUM_ERR" \ + "\37b30" \ + "\36b29" \ + "\35TCP_XSUM_ERR" \ + "\34b27" \ + "\33b26" \ + "\32b25" \ + "\31b24" \ + "\30b23" \ + "\27b22" \ + "\26GIANT_ERR" \ + "\25SHORT_ERR" \ + "\24ALIGN_ERR" \ + "\23PHY_ERR" \ + "\22CRC_ERR" \ + "\21SPLIT" \ + "\20UDP" \ + "\17TCP" \ + "\16IP" \ + "\15b12" \ + "\14b11" \ + "\13b10" \ + "\12b09" \ + "\11RSS" \ + "\10SNAP" \ + "\07VLAN" \ + "\06P4" \ + "\05P3" \ + "\04P2" + + +/* + * l2_tx_context definition (5706 and 5708) + */ +#define BCE_L2CTX_TX_TYPE 0x00000000 +#define BCE_L2CTX_TX_TYPE_SIZE_L2 ((0xc0/0x20)<<16) +#define BCE_L2CTX_TX_TYPE_TYPE (0xf<<28) +#define BCE_L2CTX_TX_TYPE_TYPE_EMPTY (0<<28) +#define BCE_L2CTX_TX_TYPE_TYPE_L2 (1<<28) + +#define BCE_L2CTX_TX_HOST_BIDX 0x00000088 +#define BCE_L2CTX_TX_EST_NBD 0x00000088 +#define BCE_L2CTX_TX_CMD_TYPE 0x00000088 +#define BCE_L2CTX_TX_CMD_TYPE_TYPE (0xf<<24) +#define BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 (0<<24) +#define BCE_L2CTX_TX_CMD_TYPE_TYPE_TCP (1<<24) + +#define BCE_L2CTX_TX_HOST_BSEQ 0x00000090 +#define BCE_L2CTX_TX_TSCH_BSEQ 0x00000094 +#define BCE_L2CTX_TX_TBDR_BSEQ 0x00000098 +#define BCE_L2CTX_TX_TBDR_BOFF 0x0000009c +#define BCE_L2CTX_TX_TBDR_BIDX 0x0000009c +#define BCE_L2CTX_TX_TBDR_BHADDR_HI 0x000000a0 +#define BCE_L2CTX_TX_TBDR_BHADDR_LO 0x000000a4 +#define BCE_L2CTX_TX_TXP_BOFF 0x000000a8 +#define BCE_L2CTX_TX_TXP_BIDX 0x000000a8 +#define BCE_L2CTX_TX_TXP_BSEQ 0x000000ac + +/* + * l2_tx_context definition (5709 and 5716) + */ +#define BCE_L2CTX_TX_TYPE_XI 0x00000080 +#define BCE_L2CTX_TX_TYPE_SIZE_L2_XI ((0xc0/0x20)<<16) +#define BCE_L2CTX_TX_TYPE_TYPE_XI (0xf<<28) +#define BCE_L2CTX_TX_TYPE_TYPE_EMPTY_XI (0<<28) +#define BCE_L2CTX_TX_TYPE_TYPE_L2_XI (1<<28) + +#define BCE_L2CTX_TX_CMD_TYPE_XI 0x00000240 +#define BCE_L2CTX_TX_CMD_TYPE_TYPE_XI (0xf<<24) +#define BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI (0<<24) +#define BCE_L2CTX_TX_CMD_TYPE_TYPE_TCP_XI (1<<24) + +#define BCE_L2CTX_TX_HOST_BIDX_XI 0x00000240 +#define BCE_L2CTX_TX_HOST_BSEQ_XI 0x00000248 +#define BCE_L2CTX_TX_TBDR_BHADDR_HI_XI 0x00000258 +#define BCE_L2CTX_TX_TBDR_BHADDR_LO_XI 0x0000025c + + +/* + * l2_rx_context definition (5706, 5708, 5709, and 5716) + */ +#define BCE_L2CTX_RX_WATER_MARK 0x00000000 +#define BCE_L2CTX_RX_LO_WATER_MARK_SHIFT 0 +#define BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT 32 +#define BCE_L2CTX_RX_LO_WATER_MARK_SCALE 4 +#define BCE_L2CTX_RX_LO_WATER_MARK_DIS 0 +#define BCE_L2CTX_RX_HI_WATER_MARK_SHIFT 4 +#define BCE_L2CTX_RX_HI_WATER_MARK_SCALE 16 +#define BCE_L2CTX_RX_WATER_MARKS_MSK 0x000000ff + +#define BCE_L2CTX_RX_BD_PRE_READ 0x00000000 +#define BCE_L2CTX_RX_BD_PRE_READ_SHIFT 8 + +#define BCE_L2CTX_RX_CTX_SIZE 0x00000000 +#define BCE_L2CTX_RX_CTX_SIZE_SHIFT 16 +#define BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 \ + ((0x20/20)<> BCM_PAGE_BITS) + +/* + * Page count must remain a power of 2 for all + * of the math to work correctly. + */ +#define TX_PAGES 2 +#define TOTAL_TX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct tx_bd)) +#define USABLE_TX_BD_PER_PAGE (TOTAL_TX_BD_PER_PAGE - 1) +#define TOTAL_TX_BD (TOTAL_TX_BD_PER_PAGE * TX_PAGES) +#define USABLE_TX_BD (USABLE_TX_BD_PER_PAGE * TX_PAGES) +#define MAX_TX_BD (TOTAL_TX_BD - 1) + +/* Advance to the next tx_bd, skipping any next page pointers. */ +#define NEXT_TX_BD(x) (((x) & USABLE_TX_BD_PER_PAGE) == \ + (USABLE_TX_BD_PER_PAGE - 1)) ? (x) + 2 : (x) + 1 + +#define TX_CHAIN_IDX(x) ((x) & MAX_TX_BD) + +#define TX_PAGE(x) (((x) & ~USABLE_TX_BD_PER_PAGE) >> (BCM_PAGE_BITS - 4)) +#define TX_IDX(x) ((x) & USABLE_TX_BD_PER_PAGE) + +/* + * Page count must remain a power of 2 for all + * of the math to work correctly. + */ +#define RX_PAGES 2 +#define TOTAL_RX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct rx_bd)) +#define USABLE_RX_BD_PER_PAGE (TOTAL_RX_BD_PER_PAGE - 1) +#define TOTAL_RX_BD (TOTAL_RX_BD_PER_PAGE * RX_PAGES) +#define USABLE_RX_BD (USABLE_RX_BD_PER_PAGE * RX_PAGES) +#define MAX_RX_BD (TOTAL_RX_BD - 1) + +/* Advance to the next rx_bd, skipping any next page pointers. */ +#define NEXT_RX_BD(x) (((x) & USABLE_RX_BD_PER_PAGE) == \ + (USABLE_RX_BD_PER_PAGE - 1)) ? (x) + 2 : (x) + 1 + +#define RX_CHAIN_IDX(x) ((x) & MAX_RX_BD) + +#define RX_PAGE(x) (((x) & ~USABLE_RX_BD_PER_PAGE) >> (BCM_PAGE_BITS - 4)) +#define RX_IDX(x) ((x) & USABLE_RX_BD_PER_PAGE) + +#ifdef BCE_JUMBO_HDRSPLIT +/* + * To accomodate jumbo frames, the page chain should + * be 4 times larger than the receive chain. + */ +#define PG_PAGES (RX_PAGES * 4) +#define TOTAL_PG_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct rx_bd)) +#define USABLE_PG_BD_PER_PAGE (TOTAL_PG_BD_PER_PAGE - 1) +#define TOTAL_PG_BD (TOTAL_PG_BD_PER_PAGE * PG_PAGES) +#define USABLE_PG_BD (USABLE_PG_BD_PER_PAGE * PG_PAGES) +#define MAX_PG_BD (TOTAL_PG_BD - 1) + +/* Advance to the next pg_bd, skipping any next page pointers. */ +#define NEXT_PG_BD(x) (((x) & USABLE_PG_BD_PER_PAGE) == \ + (USABLE_PG_BD_PER_PAGE - 1)) ? (x) + 2 : (x) + 1 + +#define PG_CHAIN_IDX(x) ((x) & MAX_PG_BD) + +#define PG_PAGE(x) (((x) & ~USABLE_PG_BD_PER_PAGE) >> (BCM_PAGE_BITS - 4)) +#define PG_IDX(x) ((x) & USABLE_PG_BD_PER_PAGE) + +#endif /* BCE_JUMBO_HDRSPLIT */ + +#define CTX_INIT_RETRY_COUNT 10 + +/* Context size. */ +#define CTX_SHIFT 7 +#define CTX_SIZE (1 << CTX_SHIFT) +#define CTX_MASK (CTX_SIZE - 1) +#define GET_CID_ADDR(_cid) ((_cid) << CTX_SHIFT) +#define GET_CID(_cid_addr) ((_cid_addr) >> CTX_SHIFT) + +#define PHY_CTX_SHIFT 6 +#define PHY_CTX_SIZE (1 << PHY_CTX_SHIFT) +#define PHY_CTX_MASK (PHY_CTX_SIZE - 1) +#define GET_PCID_ADDR(_pcid) ((_pcid) << PHY_CTX_SHIFT) +#define GET_PCID(_pcid_addr) ((_pcid_addr) >> PHY_CTX_SHIFT) + +#define MB_KERNEL_CTX_SHIFT 8 +#define MB_KERNEL_CTX_SIZE (1 << MB_KERNEL_CTX_SHIFT) +#define MB_KERNEL_CTX_MASK (MB_KERNEL_CTX_SIZE - 1) +#define MB_GET_CID_ADDR(_cid) (0x10000 + ((_cid) << MB_KERNEL_CTX_SHIFT)) + +#define MAX_CID_CNT 0x4000 +#define MAX_CID_ADDR (GET_CID_ADDR(MAX_CID_CNT)) +#define INVALID_CID_ADDR 0xffffffff + +#define TX_CID 16 +#define RX_CID 0 + +/****************************************************************************/ +/* BCE Processor Firmwware Load Definitions */ +/****************************************************************************/ + +struct cpu_reg { + u32 mode; + u32 mode_value_halt; + u32 mode_value_sstep; + + u32 state; + u32 state_value_clear; + + u32 gpr0; + u32 evmask; + u32 pc; + u32 inst; + u32 bp; + + u32 spad_base; + + u32 mips_view_base; +}; + +struct fw_info { + u32 ver_major; + u32 ver_minor; + u32 ver_fix; + + u32 start_addr; + + /* Text section. */ + u32 text_addr; + u32 text_len; + u32 text_index; + u32 *text; + + /* Data section. */ + u32 data_addr; + u32 data_len; + u32 data_index; + u32 *data; + + /* SBSS section. */ + u32 sbss_addr; + u32 sbss_len; + u32 sbss_index; + u32 *sbss; + + /* BSS section. */ + u32 bss_addr; + u32 bss_len; + u32 bss_index; + u32 *bss; + + /* Read-only section. */ + u32 rodata_addr; + u32 rodata_len; + u32 rodata_index; + u32 *rodata; +}; + +#define RV2P_PROC1 0 +#define RV2P_PROC2 1 + +#define BCE_MIREG(x) ((x & 0x1F) << 16) +#define BCE_MIPHY(x) ((x & 0x1F) << 21) +#define BCE_PHY_TIMEOUT 50 + +#define BCE_NVRAM_SIZE 0x200 +#define BCE_NVRAM_MAGIC 0x669955aa +#define BCE_CRC32_RESIDUAL 0xdebb20e3 + +#define BCE_TX_TIMEOUT 5 + +#define BCE_MAX_SEGMENTS 32 +#define BCE_TSO_MAX_SIZE 65536 +#define BCE_TSO_MAX_SEG_SIZE 4096 + +#define BCE_DMA_ALIGN 8 +#define BCE_DMA_BOUNDARY 0 +#define BCE_RX_BUF_ALIGN 16 + +#define BCE_MAX_CONTEXT 4 + +/* The BCM5708 has a problem with addresses greater that 40bits. */ +/* Handle the sizing issue in an architecture agnostic fashion. */ +#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) +#define BCE_BUS_SPACE_MAXADDR BUS_SPACE_MAXADDR +#else +#define BCE_BUS_SPACE_MAXADDR 0xFFFFFFFFFF +#endif + +/* + * XXX Checksum offload involving IP fragments seems to cause problems on + * transmit. Disable it for now, hopefully there will be a more elegant + * solution later. + */ +#ifdef BCE_IP_CSUM +#define BCE_IF_HWASSIST (CSUM_IP | CSUM_TCP | CSUM_UDP) +#else +#define BCE_IF_HWASSIST (CSUM_TCP | CSUM_UDP) +#endif + +#if __FreeBSD_version < 700000 +#define BCE_IF_CAPABILITIES (IFCAP_VLAN_MTU | \ + IFCAP_VLAN_HWTAGGING | IFCAP_HWCSUM | IFCAP_JUMBO_MTU) +#else +#define BCE_IF_CAPABILITIES (IFCAP_VLAN_MTU | \ + IFCAP_VLAN_HWTAGGING | IFCAP_HWCSUM | \ + IFCAP_JUMBO_MTU | IFCAP_VLAN_HWCSUM) +#endif + +#define BCE_MIN_MTU 60 +#define BCE_MIN_ETHER_MTU 64 + +#define BCE_MAX_STD_MTU 1500 +#define BCE_MAX_STD_ETHER_MTU 1518 +#define BCE_MAX_STD_ETHER_MTU_VLAN 1522 + +#define BCE_MAX_JUMBO_MTU 9000 +#define BCE_MAX_JUMBO_ETHER_MTU 9018 +#define BCE_MAX_JUMBO_ETHER_MTU_VLAN 9022 + +// #define BCE_MAX_MTU ETHER_MAX_LEN_JUMBO + ETHER_VLAN_ENCAP_LEN /* 9022 */ + +/****************************************************************************/ +/* BCE Device State Data Structure */ +/****************************************************************************/ + +#define BCE_STATUS_BLK_SZ sizeof(struct status_block) +#define BCE_STATS_BLK_SZ sizeof(struct statistics_block) +#define BCE_TX_CHAIN_PAGE_SZ BCM_PAGE_SIZE +#define BCE_RX_CHAIN_PAGE_SZ BCM_PAGE_SIZE +#define BCE_PG_CHAIN_PAGE_SZ BCM_PAGE_SIZE + +struct bce_softc +{ + /* Interface info. Must be first!! */ + struct ifnet *bce_ifp; + + /* Parent device handle */ + device_t bce_dev; + + /* Interface number */ + u_int8_t bce_unit; + + /* Device resource handle */ + struct resource *bce_res_mem; + + /* TBI media info */ + struct ifmedia bce_ifmedia; + + /* Device bus tag */ + bus_space_tag_t bce_btag; + + /* Device bus handle */ + bus_space_handle_t bce_bhandle; + + /* Device virtual memory handle */ + vm_offset_t bce_vhandle; + + /* IRQ Resource Handle */ + struct resource *bce_res_irq; + + struct mtx bce_mtx; + + /* Interrupt handler. */ + driver_intr_t *bce_intr; + void *bce_intrhand; + int bce_irq_rid; + int bce_msi_count; + + /* ASIC Chip ID. */ + u32 bce_chipid; + + /* General controller flags. */ + u32 bce_flags; +#define BCE_PCIX_FLAG 0x00000001 +#define BCE_PCI_32BIT_FLAG 0x00000002 +#define BCE_RESERVED_FLAG 0x00000004 +#define BCE_NO_WOL_FLAG 0x00000008 +#define BCE_USING_DAC_FLAG 0x00000010 +#define BCE_USING_MSI_FLAG 0x00000020 +#define BCE_MFW_ENABLE_FLAG 0x00000040 +#define BCE_ONE_SHOT_MSI_FLAG 0x00000080 +#define BCE_USING_MSIX_FLAG 0x00000100 +#define BCE_PCIE_FLAG 0x00000200 +#define BCE_USING_TX_FLOW_CONTROL 0x00000400 + + /* Controller capability flags. */ + u32 bce_cap_flags; +#define BCE_MSI_CAPABLE_FLAG 0x00000001 +#define BCE_MSIX_CAPABLE_FLAG 0x00000002 +#define BCE_PCIE_CAPABLE_FLAG 0x00000004 +#define BCE_PCIX_CAPABLE_FLAG 0x00000008 + + /* PHY specific flags. */ + u32 bce_phy_flags; +#define BCE_PHY_SERDES_FLAG 0x00000001 +#define BCE_PHY_CRC_FIX_FLAG 0x00000002 +#define BCE_PHY_PARALLEL_DETECT_FLAG 0x00000004 +#define BCE_PHY_2_5G_CAPABLE_FLAG 0x00000008 +#define BCE_PHY_INT_MODE_MASK_FLAG 0x00000300 +#define BCE_PHY_INT_MODE_AUTO_POLLING_FLAG 0x00000100 +#define BCE_PHY_INT_MODE_LINK_READY_FLAG 0x00000200 +#define BCE_PHY_IEEE_CLAUSE_45_FLAG 0x00000400 + + /* Values that need to be shared with the PHY driver. */ + u32 bce_shared_hw_cfg; + u32 bce_port_hw_cfg; + + bus_addr_t max_bus_addr; + + /* PCI bus speed */ + u16 bus_speed_mhz; + + /* PCIe link width */ + u16 link_width; + + /* PCIe link speed */ + u16 link_speed; + + /* Flash NVRAM settings */ + struct flash_spec *bce_flash_info; + + /* Flash NVRAM size */ + u32 bce_flash_size; + + /* Shared Memory base address */ + u32 bce_shmem_base; + + /* Name string */ + char *bce_name; + + /* Tracks the version of bootcode firmware. */ + char bce_bc_ver[32]; + + /* Tracks the version of management firmware. */ + char bce_mfw_ver[32]; + + /* + * Tracks the state of the firmware. 0 = Running while any + * other value indicates that the firmware is not responding. + */ + u16 bce_fw_timed_out; + + /* + * An incrementing sequence used to coordinate messages passed + * from the driver to the firmware. + */ + u16 bce_fw_wr_seq; + + /* + * An incrementing sequence used to let the firmware know that + * the driver is still operating. Without the pulse, management + * firmware such as IPMI or UMP will operate in OS absent state. + */ + u16 bce_fw_drv_pulse_wr_seq; + + /* Tracks whether firmware has lost the driver's pulse. */ + u16 bce_drv_cardiac_arrest; + + /* Ethernet MAC address. */ + u_char eaddr[6]; + + /* + * These setting are used by the host coalescing (HC) block to + * to control how often the status block, statistics block and + * interrupts are generated. + */ + u16 bce_tx_quick_cons_trip_int; + u16 bce_tx_quick_cons_trip; + u16 bce_rx_quick_cons_trip_int; + u16 bce_rx_quick_cons_trip; + u16 bce_tx_ticks_int; + u16 bce_tx_ticks; + u16 bce_rx_ticks_int; + u16 bce_rx_ticks; + u32 bce_stats_ticks; + + /* ToDo: Can these be removed? */ + u16 bce_comp_prod_trip_int; + u16 bce_comp_prod_trip; + u16 bce_com_ticks_int; + u16 bce_com_ticks; + u16 bce_cmd_ticks_int; + u16 bce_cmd_ticks; + + /* The address of the integrated PHY on the MII bus. */ + int bce_phy_addr; + + /* The device handle for the MII bus child device. */ + device_t bce_miibus; + + /* Driver maintained TX chain pointers and byte counter. */ + u16 rx_prod; + u16 rx_cons; + + /* Counts the bytes used in the RX chain. */ + u32 rx_prod_bseq; + u16 tx_prod; + u16 tx_cons; + + /* Counts the bytes used in the TX chain. */ + u32 tx_prod_bseq; + +#ifdef BCE_JUMBO_HDRSPLIT + u16 pg_prod; + u16 pg_cons; +#endif + + int bce_link_up; + struct callout bce_tick_callout; + struct callout bce_pulse_callout; + + /* Ticks until chip reset */ + int watchdog_timer; + + /* Frame size and mbuf allocation size for RX frames. */ + u32 max_frame_size; + int rx_bd_mbuf_alloc_size; + int rx_bd_mbuf_data_len; + int rx_bd_mbuf_align_pad; + +#ifdef BCE_JUMBO_HDRSPLIT + int pg_bd_mbuf_alloc_size; +#endif + + /* Receive mode settings (i.e promiscuous, multicast, etc.). */ + u32 rx_mode; + + /* Bus tag for the bce controller. */ + bus_dma_tag_t parent_tag; + + /* H/W maintained TX buffer descriptor chain structure. */ + bus_dma_tag_t tx_bd_chain_tag; + bus_dmamap_t tx_bd_chain_map[TX_PAGES]; + struct tx_bd *tx_bd_chain[TX_PAGES]; + bus_addr_t tx_bd_chain_paddr[TX_PAGES]; + + /* H/W maintained RX buffer descriptor chain structure. */ + bus_dma_tag_t rx_bd_chain_tag; + bus_dmamap_t rx_bd_chain_map[RX_PAGES]; + struct rx_bd *rx_bd_chain[RX_PAGES]; + bus_addr_t rx_bd_chain_paddr[RX_PAGES]; + +#ifdef BCE_JUMBO_HDRSPLIT + /* H/W maintained page buffer descriptor chain structure. */ + bus_dma_tag_t pg_bd_chain_tag; + bus_dmamap_t pg_bd_chain_map[PG_PAGES]; + struct rx_bd *pg_bd_chain[PG_PAGES]; + bus_addr_t pg_bd_chain_paddr[PG_PAGES]; +#endif + + /* H/W maintained status block. */ + bus_dma_tag_t status_tag; + bus_dmamap_t status_map; + struct status_block *status_block; + bus_addr_t status_block_paddr; + + /* Driver maintained status block values. */ + u16 last_status_idx; + u16 hw_rx_cons; + u16 hw_tx_cons; + + /* H/W maintained statistics block. */ + bus_dma_tag_t stats_tag; + bus_dmamap_t stats_map; + struct statistics_block *stats_block; + bus_addr_t stats_block_paddr; + + /* H/W maintained context block. */ + int ctx_pages; + bus_dma_tag_t ctx_tag; + + /* BCM5709/16 use host memory for context. */ + bus_dmamap_t ctx_map[BCE_MAX_CONTEXT]; + void *ctx_block[BCE_MAX_CONTEXT]; + bus_addr_t ctx_paddr[BCE_MAX_CONTEXT]; + + /* Bus tag for RX/TX mbufs. */ + bus_dma_tag_t rx_mbuf_tag; + bus_dma_tag_t tx_mbuf_tag; + +#ifdef BCE_JUMBO_HDRSPLIT + bus_dma_tag_t pg_mbuf_tag; +#endif + + /* S/W maintained mbuf TX chain structure. */ + bus_dmamap_t tx_mbuf_map[TOTAL_TX_BD]; + struct mbuf *tx_mbuf_ptr[TOTAL_TX_BD]; + + /* S/W maintained mbuf RX chain structure. */ + bus_dmamap_t rx_mbuf_map[TOTAL_RX_BD]; + struct mbuf *rx_mbuf_ptr[TOTAL_RX_BD]; + +#ifdef BCE_JUMBO_HDRSPLIT + /* S/W maintained mbuf page chain structure. */ + bus_dmamap_t pg_mbuf_map[TOTAL_PG_BD]; + struct mbuf *pg_mbuf_ptr[TOTAL_PG_BD]; +#endif + + /* Track the number of buffer descriptors in use. */ + u16 free_rx_bd; + u16 max_rx_bd; + u16 used_tx_bd; + u16 max_tx_bd; + +#ifdef BCE_JUMBO_HDRSPLIT + u16 free_pg_bd; + u16 max_pg_bd; +#endif + + /* Provides access to hardware statistics through sysctl. */ + u64 stat_IfHCInOctets; + u64 stat_IfHCInBadOctets; + u64 stat_IfHCOutOctets; + u64 stat_IfHCOutBadOctets; + u64 stat_IfHCInUcastPkts; + u64 stat_IfHCInMulticastPkts; + u64 stat_IfHCInBroadcastPkts; + u64 stat_IfHCOutUcastPkts; + u64 stat_IfHCOutMulticastPkts; + u64 stat_IfHCOutBroadcastPkts; + + u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors; + u32 stat_Dot3StatsCarrierSenseErrors; + u32 stat_Dot3StatsFCSErrors; + u32 stat_Dot3StatsAlignmentErrors; + u32 stat_Dot3StatsSingleCollisionFrames; + u32 stat_Dot3StatsMultipleCollisionFrames; + u32 stat_Dot3StatsDeferredTransmissions; + u32 stat_Dot3StatsExcessiveCollisions; + u32 stat_Dot3StatsLateCollisions; + u32 stat_EtherStatsCollisions; + u32 stat_EtherStatsFragments; + u32 stat_EtherStatsJabbers; + u32 stat_EtherStatsUndersizePkts; + u32 stat_EtherStatsOversizePkts; + u32 stat_EtherStatsPktsRx64Octets; + u32 stat_EtherStatsPktsRx65Octetsto127Octets; + u32 stat_EtherStatsPktsRx128Octetsto255Octets; + u32 stat_EtherStatsPktsRx256Octetsto511Octets; + u32 stat_EtherStatsPktsRx512Octetsto1023Octets; + u32 stat_EtherStatsPktsRx1024Octetsto1522Octets; + u32 stat_EtherStatsPktsRx1523Octetsto9022Octets; + u32 stat_EtherStatsPktsTx64Octets; + u32 stat_EtherStatsPktsTx65Octetsto127Octets; + u32 stat_EtherStatsPktsTx128Octetsto255Octets; + u32 stat_EtherStatsPktsTx256Octetsto511Octets; + u32 stat_EtherStatsPktsTx512Octetsto1023Octets; + u32 stat_EtherStatsPktsTx1024Octetsto1522Octets; + u32 stat_EtherStatsPktsTx1523Octetsto9022Octets; + u32 stat_XonPauseFramesReceived; + u32 stat_XoffPauseFramesReceived; + u32 stat_OutXonSent; + u32 stat_OutXoffSent; + u32 stat_FlowControlDone; + u32 stat_MacControlFramesReceived; + u32 stat_XoffStateEntered; + u32 stat_IfInFramesL2FilterDiscards; + u32 stat_IfInRuleCheckerDiscards; + u32 stat_IfInFTQDiscards; + u32 stat_IfInMBUFDiscards; + u32 stat_IfInRuleCheckerP4Hit; + u32 stat_CatchupInRuleCheckerDiscards; + u32 stat_CatchupInFTQDiscards; + u32 stat_CatchupInMBUFDiscards; + u32 stat_CatchupInRuleCheckerP4Hit; + + /* Provides access to certain firmware statistics. */ + u32 com_no_buffers; + + /* Recoverable failure counters. */ + u32 mbuf_alloc_failed_count; + u32 mbuf_frag_count; + u32 unexpected_attention_count; + u32 l2fhdr_error_count; + u32 dma_map_addr_tx_failed_count; + u32 dma_map_addr_rx_failed_count; + + /* Host coalescing block command register */ + u32 hc_command; + + /* Bootcode state */ + u32 bc_state; + +#ifdef BCE_DEBUG + /* Simulated recoverable failure counters. */ + u32 mbuf_alloc_failed_sim_count; + u32 unexpected_attention_sim_count; + u32 l2fhdr_error_sim_count; + u32 dma_map_addr_failed_sim_count; + + /* Track the number of enqueued mbufs. */ + int debug_tx_mbuf_alloc; + int debug_rx_mbuf_alloc; + +#ifdef BCE_JUMBO_HDRSPLIT + int debug_pg_mbuf_alloc; +#endif + + /* Track how many and what type of interrupts are generated. */ + u32 interrupts_generated; + u32 interrupts_handled; + u32 interrupts_rx; + u32 interrupts_tx; + u32 phy_interrupts; + + /* Track interrupt time (25MHz clock). */ + u64 rx_intr_time; + u64 tx_intr_time; + + /* Lowest number of rx_bd's free. */ + u32 rx_low_watermark; + + /* Number of times the RX chain was empty. */ + u32 rx_empty_count; + +#ifdef BCE_JUMBO_HDRSPLIT + /* Lowest number of pages free. */ + u32 pg_low_watermark; + + /* Number of times the page chain was empty. */ + u32 pg_empty_count; +#endif + + /* Greatest number of tx_bd's used. */ + u32 tx_hi_watermark; + + /* Number of times the TX chain was full. */ + u32 tx_full_count; + + /* Number of TSO frames requested. */ + u32 tso_frames_requested; + + /* Number of TSO frames completed. */ + u32 tso_frames_completed; + + /* Number of TSO frames failed. */ + u32 tso_frames_failed; + + /* Number of IP checksum offload frames.*/ + u32 csum_offload_ip; + + /* Number of TCP/UDP checksum offload frames.*/ + u32 csum_offload_tcp_udp; + + /* Number of VLAN tagged frames received. */ + u32 vlan_tagged_frames_rcvd; + + /* Number of VLAN tagged frames stripped. */ + u32 vlan_tagged_frames_stripped; +#endif +}; + +#endif /* __BCEREG_HH_DEFINED */ + diff --git a/freebsd/dev/bfe/if_bfe.c b/freebsd/dev/bfe/if_bfe.c new file mode 100644 index 00000000..7ce821b8 --- /dev/null +++ b/freebsd/dev/bfe/if_bfe.c @@ -0,0 +1,1973 @@ +#include + +/*- + * Copyright (c) 2003 Stuart Walsh + * and Duncan Barclay + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include + +#include + +MODULE_DEPEND(bfe, pci, 1, 1, 1); +MODULE_DEPEND(bfe, ether, 1, 1, 1); +MODULE_DEPEND(bfe, miibus, 1, 1, 1); + +/* "device miibus" required. See GENERIC if you get errors here. */ +#include + +#define BFE_DEVDESC_MAX 64 /* Maximum device description length */ + +static struct bfe_type bfe_devs[] = { + { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, + "Broadcom BCM4401 Fast Ethernet" }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0, + "Broadcom BCM4401-B0 Fast Ethernet" }, + { 0, 0, NULL } +}; + +static int bfe_probe (device_t); +static int bfe_attach (device_t); +static int bfe_detach (device_t); +static int bfe_suspend (device_t); +static int bfe_resume (device_t); +static void bfe_release_resources (struct bfe_softc *); +static void bfe_intr (void *); +static int bfe_encap (struct bfe_softc *, struct mbuf **); +static void bfe_start (struct ifnet *); +static void bfe_start_locked (struct ifnet *); +static int bfe_ioctl (struct ifnet *, u_long, caddr_t); +static void bfe_init (void *); +static void bfe_init_locked (void *); +static void bfe_stop (struct bfe_softc *); +static void bfe_watchdog (struct bfe_softc *); +static int bfe_shutdown (device_t); +static void bfe_tick (void *); +static void bfe_txeof (struct bfe_softc *); +static void bfe_rxeof (struct bfe_softc *); +static void bfe_set_rx_mode (struct bfe_softc *); +static int bfe_list_rx_init (struct bfe_softc *); +static void bfe_list_tx_init (struct bfe_softc *); +static void bfe_discard_buf (struct bfe_softc *, int); +static int bfe_list_newbuf (struct bfe_softc *, int); +static void bfe_rx_ring_free (struct bfe_softc *); + +static void bfe_pci_setup (struct bfe_softc *, u_int32_t); +static int bfe_ifmedia_upd (struct ifnet *); +static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); +static int bfe_miibus_readreg (device_t, int, int); +static int bfe_miibus_writereg (device_t, int, int, int); +static void bfe_miibus_statchg (device_t); +static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, + u_long, const int); +static void bfe_get_config (struct bfe_softc *sc); +static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); +static void bfe_stats_update (struct bfe_softc *); +static void bfe_clear_stats (struct bfe_softc *); +static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); +static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); +static int bfe_resetphy (struct bfe_softc *); +static int bfe_setupphy (struct bfe_softc *); +static void bfe_chip_reset (struct bfe_softc *); +static void bfe_chip_halt (struct bfe_softc *); +static void bfe_core_reset (struct bfe_softc *); +static void bfe_core_disable (struct bfe_softc *); +static int bfe_dma_alloc (struct bfe_softc *); +static void bfe_dma_free (struct bfe_softc *sc); +static void bfe_dma_map (void *, bus_dma_segment_t *, int, int); +static void bfe_cam_write (struct bfe_softc *, u_char *, int); +static int sysctl_bfe_stats (SYSCTL_HANDLER_ARGS); + +static device_method_t bfe_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, bfe_probe), + DEVMETHOD(device_attach, bfe_attach), + DEVMETHOD(device_detach, bfe_detach), + DEVMETHOD(device_shutdown, bfe_shutdown), + DEVMETHOD(device_suspend, bfe_suspend), + DEVMETHOD(device_resume, bfe_resume), + + /* bus interface */ + DEVMETHOD(bus_print_child, bus_generic_print_child), + DEVMETHOD(bus_driver_added, bus_generic_driver_added), + + /* MII interface */ + DEVMETHOD(miibus_readreg, bfe_miibus_readreg), + DEVMETHOD(miibus_writereg, bfe_miibus_writereg), + DEVMETHOD(miibus_statchg, bfe_miibus_statchg), + + { 0, 0 } +}; + +static driver_t bfe_driver = { + "bfe", + bfe_methods, + sizeof(struct bfe_softc) +}; + +static devclass_t bfe_devclass; + +DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); +DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); + +/* + * Probe for a Broadcom 4401 chip. + */ +static int +bfe_probe(device_t dev) +{ + struct bfe_type *t; + + t = bfe_devs; + + while (t->bfe_name != NULL) { + if (pci_get_vendor(dev) == t->bfe_vid && + pci_get_device(dev) == t->bfe_did) { + device_set_desc(dev, t->bfe_name); + return (BUS_PROBE_DEFAULT); + } + t++; + } + + return (ENXIO); +} + +struct bfe_dmamap_arg { + bus_addr_t bfe_busaddr; +}; + +static int +bfe_dma_alloc(struct bfe_softc *sc) +{ + struct bfe_dmamap_arg ctx; + struct bfe_rx_data *rd; + struct bfe_tx_data *td; + int error, i; + + /* + * parent tag. Apparently the chip cannot handle any DMA address + * greater than 1GB. + */ + error = bus_dma_tag_create(bus_get_dma_tag(sc->bfe_dev), /* parent */ + 1, 0, /* alignment, boundary */ + BFE_DMA_MAXADDR, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ + 0, /* nsegments */ + BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ + 0, /* flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->bfe_parent_tag); + if (error != 0) { + device_printf(sc->bfe_dev, "cannot create parent DMA tag.\n"); + goto fail; + } + + /* Create tag for Tx ring. */ + error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ + BFE_TX_RING_ALIGN, 0, /* alignment, boundary */ + BUS_SPACE_MAXADDR, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + BFE_TX_LIST_SIZE, /* maxsize */ + 1, /* nsegments */ + BFE_TX_LIST_SIZE, /* maxsegsize */ + 0, /* flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->bfe_tx_tag); + if (error != 0) { + device_printf(sc->bfe_dev, "cannot create Tx ring DMA tag.\n"); + goto fail; + } + + /* Create tag for Rx ring. */ + error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ + BFE_RX_RING_ALIGN, 0, /* alignment, boundary */ + BUS_SPACE_MAXADDR, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + BFE_RX_LIST_SIZE, /* maxsize */ + 1, /* nsegments */ + BFE_RX_LIST_SIZE, /* maxsegsize */ + 0, /* flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->bfe_rx_tag); + if (error != 0) { + device_printf(sc->bfe_dev, "cannot create Rx ring DMA tag.\n"); + goto fail; + } + + /* Create tag for Tx buffers. */ + error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ + 1, 0, /* alignment, boundary */ + BUS_SPACE_MAXADDR, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + MCLBYTES * BFE_MAXTXSEGS, /* maxsize */ + BFE_MAXTXSEGS, /* nsegments */ + MCLBYTES, /* maxsegsize */ + 0, /* flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->bfe_txmbuf_tag); + if (error != 0) { + device_printf(sc->bfe_dev, + "cannot create Tx buffer DMA tag.\n"); + goto fail; + } + + /* Create tag for Rx buffers. */ + error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ + 1, 0, /* alignment, boundary */ + BUS_SPACE_MAXADDR, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + MCLBYTES, /* maxsize */ + 1, /* nsegments */ + MCLBYTES, /* maxsegsize */ + 0, /* flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->bfe_rxmbuf_tag); + if (error != 0) { + device_printf(sc->bfe_dev, + "cannot create Rx buffer DMA tag.\n"); + goto fail; + } + + /* Allocate DMA'able memory and load DMA map. */ + error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, + BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_tx_map); + if (error != 0) { + device_printf(sc->bfe_dev, + "cannot allocate DMA'able memory for Tx ring.\n"); + goto fail; + } + ctx.bfe_busaddr = 0; + error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, + sc->bfe_tx_list, BFE_TX_LIST_SIZE, bfe_dma_map, &ctx, + BUS_DMA_NOWAIT); + if (error != 0 || ctx.bfe_busaddr == 0) { + device_printf(sc->bfe_dev, + "cannot load DMA'able memory for Tx ring.\n"); + goto fail; + } + sc->bfe_tx_dma = BFE_ADDR_LO(ctx.bfe_busaddr); + + error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, + BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_rx_map); + if (error != 0) { + device_printf(sc->bfe_dev, + "cannot allocate DMA'able memory for Rx ring.\n"); + goto fail; + } + ctx.bfe_busaddr = 0; + error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, + sc->bfe_rx_list, BFE_RX_LIST_SIZE, bfe_dma_map, &ctx, + BUS_DMA_NOWAIT); + if (error != 0 || ctx.bfe_busaddr == 0) { + device_printf(sc->bfe_dev, + "cannot load DMA'able memory for Rx ring.\n"); + goto fail; + } + sc->bfe_rx_dma = BFE_ADDR_LO(ctx.bfe_busaddr); + + /* Create DMA maps for Tx buffers. */ + for (i = 0; i < BFE_TX_LIST_CNT; i++) { + td = &sc->bfe_tx_ring[i]; + td->bfe_mbuf = NULL; + td->bfe_map = NULL; + error = bus_dmamap_create(sc->bfe_txmbuf_tag, 0, &td->bfe_map); + if (error != 0) { + device_printf(sc->bfe_dev, + "cannot create DMA map for Tx.\n"); + goto fail; + } + } + + /* Create spare DMA map for Rx buffers. */ + error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &sc->bfe_rx_sparemap); + if (error != 0) { + device_printf(sc->bfe_dev, "cannot create spare DMA map for Rx.\n"); + goto fail; + } + /* Create DMA maps for Rx buffers. */ + for (i = 0; i < BFE_RX_LIST_CNT; i++) { + rd = &sc->bfe_rx_ring[i]; + rd->bfe_mbuf = NULL; + rd->bfe_map = NULL; + rd->bfe_ctrl = 0; + error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &rd->bfe_map); + if (error != 0) { + device_printf(sc->bfe_dev, + "cannot create DMA map for Rx.\n"); + goto fail; + } + } + +fail: + return (error); +} + +static void +bfe_dma_free(struct bfe_softc *sc) +{ + struct bfe_tx_data *td; + struct bfe_rx_data *rd; + int i; + + /* Tx ring. */ + if (sc->bfe_tx_tag != NULL) { + if (sc->bfe_tx_map != NULL) + bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); + if (sc->bfe_tx_map != NULL && sc->bfe_tx_list != NULL) + bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, + sc->bfe_tx_map); + sc->bfe_tx_map = NULL; + sc->bfe_tx_list = NULL; + bus_dma_tag_destroy(sc->bfe_tx_tag); + sc->bfe_tx_tag = NULL; + } + + /* Rx ring. */ + if (sc->bfe_rx_tag != NULL) { + if (sc->bfe_rx_map != NULL) + bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); + if (sc->bfe_rx_map != NULL && sc->bfe_rx_list != NULL) + bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, + sc->bfe_rx_map); + sc->bfe_rx_map = NULL; + sc->bfe_rx_list = NULL; + bus_dma_tag_destroy(sc->bfe_rx_tag); + sc->bfe_rx_tag = NULL; + } + + /* Tx buffers. */ + if (sc->bfe_txmbuf_tag != NULL) { + for (i = 0; i < BFE_TX_LIST_CNT; i++) { + td = &sc->bfe_tx_ring[i]; + if (td->bfe_map != NULL) { + bus_dmamap_destroy(sc->bfe_txmbuf_tag, + td->bfe_map); + td->bfe_map = NULL; + } + } + bus_dma_tag_destroy(sc->bfe_txmbuf_tag); + sc->bfe_txmbuf_tag = NULL; + } + + /* Rx buffers. */ + if (sc->bfe_rxmbuf_tag != NULL) { + for (i = 0; i < BFE_RX_LIST_CNT; i++) { + rd = &sc->bfe_rx_ring[i]; + if (rd->bfe_map != NULL) { + bus_dmamap_destroy(sc->bfe_rxmbuf_tag, + rd->bfe_map); + rd->bfe_map = NULL; + } + } + if (sc->bfe_rx_sparemap != NULL) { + bus_dmamap_destroy(sc->bfe_rxmbuf_tag, + sc->bfe_rx_sparemap); + sc->bfe_rx_sparemap = NULL; + } + bus_dma_tag_destroy(sc->bfe_rxmbuf_tag); + sc->bfe_rxmbuf_tag = NULL; + } + + if (sc->bfe_parent_tag != NULL) { + bus_dma_tag_destroy(sc->bfe_parent_tag); + sc->bfe_parent_tag = NULL; + } +} + +static int +bfe_attach(device_t dev) +{ + struct ifnet *ifp = NULL; + struct bfe_softc *sc; + int error = 0, rid; + + sc = device_get_softc(dev); + mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, + MTX_DEF); + callout_init_mtx(&sc->bfe_stat_co, &sc->bfe_mtx, 0); + + sc->bfe_dev = dev; + + /* + * Map control/status registers. + */ + pci_enable_busmaster(dev); + + rid = PCIR_BAR(0); + sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, + RF_ACTIVE); + if (sc->bfe_res == NULL) { + device_printf(dev, "couldn't map memory\n"); + error = ENXIO; + goto fail; + } + + /* Allocate interrupt */ + rid = 0; + + sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, + RF_SHAREABLE | RF_ACTIVE); + if (sc->bfe_irq == NULL) { + device_printf(dev, "couldn't map interrupt\n"); + error = ENXIO; + goto fail; + } + + if (bfe_dma_alloc(sc) != 0) { + device_printf(dev, "failed to allocate DMA resources\n"); + error = ENXIO; + goto fail; + } + + SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), + SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, + "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_bfe_stats, + "I", "Statistics"); + + /* Set up ifnet structure */ + ifp = sc->bfe_ifp = if_alloc(IFT_ETHER); + if (ifp == NULL) { + device_printf(dev, "failed to if_alloc()\n"); + error = ENOSPC; + goto fail; + } + ifp->if_softc = sc; + if_initname(ifp, device_get_name(dev), device_get_unit(dev)); + ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; + ifp->if_ioctl = bfe_ioctl; + ifp->if_start = bfe_start; + ifp->if_init = bfe_init; + ifp->if_mtu = ETHERMTU; + IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN); + ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN; + IFQ_SET_READY(&ifp->if_snd); + + bfe_get_config(sc); + + /* Reset the chip and turn on the PHY */ + BFE_LOCK(sc); + bfe_chip_reset(sc); + BFE_UNLOCK(sc); + + error = mii_attach(dev, &sc->bfe_miibus, ifp, bfe_ifmedia_upd, + bfe_ifmedia_sts, BMSR_DEFCAPMASK, sc->bfe_phyaddr, MII_OFFSET_ANY, + 0); + if (error != 0) { + device_printf(dev, "attaching PHYs failed\n"); + goto fail; + } + + ether_ifattach(ifp, sc->bfe_enaddr); + + /* + * Tell the upper layer(s) we support long frames. + */ + ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); + ifp->if_capabilities |= IFCAP_VLAN_MTU; + ifp->if_capenable |= IFCAP_VLAN_MTU; + + /* + * Hook interrupt last to avoid having to lock softc + */ + error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE, + NULL, bfe_intr, sc, &sc->bfe_intrhand); + + if (error) { + device_printf(dev, "couldn't set up irq\n"); + goto fail; + } +fail: + if (error != 0) + bfe_detach(dev); + return (error); +} + +static int +bfe_detach(device_t dev) +{ + struct bfe_softc *sc; + struct ifnet *ifp; + + sc = device_get_softc(dev); + + ifp = sc->bfe_ifp; + + if (device_is_attached(dev)) { + BFE_LOCK(sc); + sc->bfe_flags |= BFE_FLAG_DETACH; + bfe_stop(sc); + BFE_UNLOCK(sc); + callout_drain(&sc->bfe_stat_co); + if (ifp != NULL) + ether_ifdetach(ifp); + } + + BFE_LOCK(sc); + bfe_chip_reset(sc); + BFE_UNLOCK(sc); + + bus_generic_detach(dev); + if (sc->bfe_miibus != NULL) + device_delete_child(dev, sc->bfe_miibus); + + bfe_release_resources(sc); + bfe_dma_free(sc); + mtx_destroy(&sc->bfe_mtx); + + return (0); +} + +/* + * Stop all chip I/O so that the kernel's probe routines don't + * get confused by errant DMAs when rebooting. + */ +static int +bfe_shutdown(device_t dev) +{ + struct bfe_softc *sc; + + sc = device_get_softc(dev); + BFE_LOCK(sc); + bfe_stop(sc); + + BFE_UNLOCK(sc); + + return (0); +} + +static int +bfe_suspend(device_t dev) +{ + struct bfe_softc *sc; + + sc = device_get_softc(dev); + BFE_LOCK(sc); + bfe_stop(sc); + BFE_UNLOCK(sc); + + return (0); +} + +static int +bfe_resume(device_t dev) +{ + struct bfe_softc *sc; + struct ifnet *ifp; + + sc = device_get_softc(dev); + ifp = sc->bfe_ifp; + BFE_LOCK(sc); + bfe_chip_reset(sc); + if (ifp->if_flags & IFF_UP) { + bfe_init_locked(sc); + if (ifp->if_drv_flags & IFF_DRV_RUNNING && + !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) + bfe_start_locked(ifp); + } + BFE_UNLOCK(sc); + + return (0); +} + +static int +bfe_miibus_readreg(device_t dev, int phy, int reg) +{ + struct bfe_softc *sc; + u_int32_t ret; + + sc = device_get_softc(dev); + bfe_readphy(sc, reg, &ret); + + return (ret); +} + +static int +bfe_miibus_writereg(device_t dev, int phy, int reg, int val) +{ + struct bfe_softc *sc; + + sc = device_get_softc(dev); + bfe_writephy(sc, reg, val); + + return (0); +} + +static void +bfe_miibus_statchg(device_t dev) +{ + struct bfe_softc *sc; + struct mii_data *mii; + u_int32_t val, flow; + + sc = device_get_softc(dev); + mii = device_get_softc(sc->bfe_miibus); + + sc->bfe_flags &= ~BFE_FLAG_LINK; + if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == + (IFM_ACTIVE | IFM_AVALID)) { + switch (IFM_SUBTYPE(mii->mii_media_active)) { + case IFM_10_T: + case IFM_100_TX: + sc->bfe_flags |= BFE_FLAG_LINK; + break; + default: + break; + } + } + + /* XXX Should stop Rx/Tx engine prior to touching MAC. */ + val = CSR_READ_4(sc, BFE_TX_CTRL); + val &= ~BFE_TX_DUPLEX; + if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { + val |= BFE_TX_DUPLEX; + flow = 0; +#ifdef notyet + flow = CSR_READ_4(sc, BFE_RXCONF); + flow &= ~BFE_RXCONF_FLOW; + if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & + IFM_ETH_RXPAUSE) != 0) + flow |= BFE_RXCONF_FLOW; + CSR_WRITE_4(sc, BFE_RXCONF, flow); + /* + * It seems that the hardware has Tx pause issues + * so enable only Rx pause. + */ + flow = CSR_READ_4(sc, BFE_MAC_FLOW); + flow &= ~BFE_FLOW_PAUSE_ENAB; + CSR_WRITE_4(sc, BFE_MAC_FLOW, flow); +#endif + } + CSR_WRITE_4(sc, BFE_TX_CTRL, val); +} + +static void +bfe_tx_ring_free(struct bfe_softc *sc) +{ + int i; + + for(i = 0; i < BFE_TX_LIST_CNT; i++) { + if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) { + bus_dmamap_sync(sc->bfe_txmbuf_tag, + sc->bfe_tx_ring[i].bfe_map, BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(sc->bfe_txmbuf_tag, + sc->bfe_tx_ring[i].bfe_map); + m_freem(sc->bfe_tx_ring[i].bfe_mbuf); + sc->bfe_tx_ring[i].bfe_mbuf = NULL; + } + } + bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); + bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); +} + +static void +bfe_rx_ring_free(struct bfe_softc *sc) +{ + int i; + + for (i = 0; i < BFE_RX_LIST_CNT; i++) { + if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { + bus_dmamap_sync(sc->bfe_rxmbuf_tag, + sc->bfe_rx_ring[i].bfe_map, BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(sc->bfe_rxmbuf_tag, + sc->bfe_rx_ring[i].bfe_map); + m_freem(sc->bfe_rx_ring[i].bfe_mbuf); + sc->bfe_rx_ring[i].bfe_mbuf = NULL; + } + } + bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); + bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); +} + +static int +bfe_list_rx_init(struct bfe_softc *sc) +{ + struct bfe_rx_data *rd; + int i; + + sc->bfe_rx_prod = sc->bfe_rx_cons = 0; + bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); + for (i = 0; i < BFE_RX_LIST_CNT; i++) { + rd = &sc->bfe_rx_ring[i]; + rd->bfe_mbuf = NULL; + rd->bfe_ctrl = 0; + if (bfe_list_newbuf(sc, i) != 0) + return (ENOBUFS); + } + + bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); + + return (0); +} + +static void +bfe_list_tx_init(struct bfe_softc *sc) +{ + int i; + + sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; + bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); + for (i = 0; i < BFE_TX_LIST_CNT; i++) + sc->bfe_tx_ring[i].bfe_mbuf = NULL; + + bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); +} + +static void +bfe_discard_buf(struct bfe_softc *sc, int c) +{ + struct bfe_rx_data *r; + struct bfe_desc *d; + + r = &sc->bfe_rx_ring[c]; + d = &sc->bfe_rx_list[c]; + d->bfe_ctrl = htole32(r->bfe_ctrl); +} + +static int +bfe_list_newbuf(struct bfe_softc *sc, int c) +{ + struct bfe_rxheader *rx_header; + struct bfe_desc *d; + struct bfe_rx_data *r; + struct mbuf *m; + bus_dma_segment_t segs[1]; + bus_dmamap_t map; + u_int32_t ctrl; + int nsegs; + + m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + m->m_len = m->m_pkthdr.len = MCLBYTES; + + if (bus_dmamap_load_mbuf_sg(sc->bfe_rxmbuf_tag, sc->bfe_rx_sparemap, + m, segs, &nsegs, 0) != 0) { + m_freem(m); + return (ENOBUFS); + } + + KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); + r = &sc->bfe_rx_ring[c]; + if (r->bfe_mbuf != NULL) { + bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map, + BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(sc->bfe_rxmbuf_tag, r->bfe_map); + } + map = r->bfe_map; + r->bfe_map = sc->bfe_rx_sparemap; + sc->bfe_rx_sparemap = map; + r->bfe_mbuf = m; + + rx_header = mtod(m, struct bfe_rxheader *); + rx_header->len = 0; + rx_header->flags = 0; + bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map, BUS_DMASYNC_PREREAD); + + ctrl = segs[0].ds_len & BFE_DESC_LEN; + KASSERT(ctrl > ETHER_MAX_LEN + 32, ("%s: buffer size too small(%d)!", + __func__, ctrl)); + if (c == BFE_RX_LIST_CNT - 1) + ctrl |= BFE_DESC_EOT; + r->bfe_ctrl = ctrl; + + d = &sc->bfe_rx_list[c]; + d->bfe_ctrl = htole32(ctrl); + /* The chip needs all addresses to be added to BFE_PCI_DMA. */ + d->bfe_addr = htole32(BFE_ADDR_LO(segs[0].ds_addr) + BFE_PCI_DMA); + + return (0); +} + +static void +bfe_get_config(struct bfe_softc *sc) +{ + u_int8_t eeprom[128]; + + bfe_read_eeprom(sc, eeprom); + + sc->bfe_enaddr[0] = eeprom[79]; + sc->bfe_enaddr[1] = eeprom[78]; + sc->bfe_enaddr[2] = eeprom[81]; + sc->bfe_enaddr[3] = eeprom[80]; + sc->bfe_enaddr[4] = eeprom[83]; + sc->bfe_enaddr[5] = eeprom[82]; + + sc->bfe_phyaddr = eeprom[90] & 0x1f; + sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; + + sc->bfe_core_unit = 0; + sc->bfe_dma_offset = BFE_PCI_DMA; +} + +static void +bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) +{ + u_int32_t bar_orig, pci_rev, val; + + bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); + pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); + pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; + + val = CSR_READ_4(sc, BFE_SBINTVEC); + val |= cores; + CSR_WRITE_4(sc, BFE_SBINTVEC, val); + + val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); + val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; + CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); + + pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); +} + +static void +bfe_clear_stats(struct bfe_softc *sc) +{ + uint32_t reg; + + BFE_LOCK_ASSERT(sc); + + CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); + for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) + CSR_READ_4(sc, reg); + for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) + CSR_READ_4(sc, reg); +} + +static int +bfe_resetphy(struct bfe_softc *sc) +{ + u_int32_t val; + + bfe_writephy(sc, 0, BMCR_RESET); + DELAY(100); + bfe_readphy(sc, 0, &val); + if (val & BMCR_RESET) { + device_printf(sc->bfe_dev, "PHY Reset would not complete.\n"); + return (ENXIO); + } + return (0); +} + +static void +bfe_chip_halt(struct bfe_softc *sc) +{ + BFE_LOCK_ASSERT(sc); + /* disable interrupts - not that it actually does..*/ + CSR_WRITE_4(sc, BFE_IMASK, 0); + CSR_READ_4(sc, BFE_IMASK); + + CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); + bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); + + CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); + CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); + DELAY(10); +} + +static void +bfe_chip_reset(struct bfe_softc *sc) +{ + u_int32_t val; + + BFE_LOCK_ASSERT(sc); + + /* Set the interrupt vector for the enet core */ + bfe_pci_setup(sc, BFE_INTVEC_ENET0); + + /* is core up? */ + val = CSR_READ_4(sc, BFE_SBTMSLOW) & + (BFE_RESET | BFE_REJECT | BFE_CLOCK); + if (val == BFE_CLOCK) { + /* It is, so shut it down */ + CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); + CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); + bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); + CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); + if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) + bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, + 100, 0); + CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); + } + + bfe_core_reset(sc); + bfe_clear_stats(sc); + + /* + * We want the phy registers to be accessible even when + * the driver is "downed" so initialize MDC preamble, frequency, + * and whether internal or external phy here. + */ + + /* 4402 has 62.5Mhz SB clock and internal phy */ + CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); + + /* Internal or external PHY? */ + val = CSR_READ_4(sc, BFE_DEVCTRL); + if (!(val & BFE_IPP)) + CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); + else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { + BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); + DELAY(100); + } + + /* Enable CRC32 generation and set proper LED modes */ + BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); + + /* Reset or clear powerdown control bit */ + BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); + + CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & + BFE_LAZY_FC_MASK)); + + /* + * We don't want lazy interrupts, so just send them at + * the end of a frame, please + */ + BFE_OR(sc, BFE_RCV_LAZY, 0); + + /* Set max lengths, accounting for VLAN tags */ + CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); + CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); + + /* Set watermark XXX - magic */ + CSR_WRITE_4(sc, BFE_TX_WMARK, 56); + + /* + * Initialise DMA channels + * - not forgetting dma addresses need to be added to BFE_PCI_DMA + */ + CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); + CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); + + CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | + BFE_RX_CTRL_ENABLE); + CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); + + bfe_resetphy(sc); + bfe_setupphy(sc); +} + +static void +bfe_core_disable(struct bfe_softc *sc) +{ + if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) + return; + + /* + * Set reject, wait for it set, then wait for the core to stop + * being busy, then set reset and reject and enable the clocks. + */ + CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); + bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); + bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); + CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | + BFE_RESET)); + CSR_READ_4(sc, BFE_SBTMSLOW); + DELAY(10); + /* Leave reset and reject set */ + CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); + DELAY(10); +} + +static void +bfe_core_reset(struct bfe_softc *sc) +{ + u_int32_t val; + + /* Disable the core */ + bfe_core_disable(sc); + + /* and bring it back up */ + CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); + CSR_READ_4(sc, BFE_SBTMSLOW); + DELAY(10); + + /* Chip bug, clear SERR, IB and TO if they are set. */ + if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) + CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); + val = CSR_READ_4(sc, BFE_SBIMSTATE); + if (val & (BFE_IBE | BFE_TO)) + CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); + + /* Clear reset and allow it to move through the core */ + CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); + CSR_READ_4(sc, BFE_SBTMSLOW); + DELAY(10); + + /* Leave the clock set */ + CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); + CSR_READ_4(sc, BFE_SBTMSLOW); + DELAY(10); +} + +static void +bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) +{ + u_int32_t val; + + val = ((u_int32_t) data[2]) << 24; + val |= ((u_int32_t) data[3]) << 16; + val |= ((u_int32_t) data[4]) << 8; + val |= ((u_int32_t) data[5]); + CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); + val = (BFE_CAM_HI_VALID | + (((u_int32_t) data[0]) << 8) | + (((u_int32_t) data[1]))); + CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); + CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | + ((u_int32_t) index << BFE_CAM_INDEX_SHIFT))); + bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); +} + +static void +bfe_set_rx_mode(struct bfe_softc *sc) +{ + struct ifnet *ifp = sc->bfe_ifp; + struct ifmultiaddr *ifma; + u_int32_t val; + int i = 0; + + BFE_LOCK_ASSERT(sc); + + val = CSR_READ_4(sc, BFE_RXCONF); + + if (ifp->if_flags & IFF_PROMISC) + val |= BFE_RXCONF_PROMISC; + else + val &= ~BFE_RXCONF_PROMISC; + + if (ifp->if_flags & IFF_BROADCAST) + val &= ~BFE_RXCONF_DBCAST; + else + val |= BFE_RXCONF_DBCAST; + + + CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); + bfe_cam_write(sc, IF_LLADDR(sc->bfe_ifp), i++); + + if (ifp->if_flags & IFF_ALLMULTI) + val |= BFE_RXCONF_ALLMULTI; + else { + val &= ~BFE_RXCONF_ALLMULTI; + if_maddr_rlock(ifp); + TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { + if (ifma->ifma_addr->sa_family != AF_LINK) + continue; + bfe_cam_write(sc, + LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); + } + if_maddr_runlock(ifp); + } + + CSR_WRITE_4(sc, BFE_RXCONF, val); + BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); +} + +static void +bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) +{ + struct bfe_dmamap_arg *ctx; + + if (error != 0) + return; + + KASSERT(nseg == 1, ("%s : %d segments returned!", __func__, nseg)); + + ctx = (struct bfe_dmamap_arg *)arg; + ctx->bfe_busaddr = segs[0].ds_addr; +} + +static void +bfe_release_resources(struct bfe_softc *sc) +{ + + if (sc->bfe_intrhand != NULL) + bus_teardown_intr(sc->bfe_dev, sc->bfe_irq, sc->bfe_intrhand); + + if (sc->bfe_irq != NULL) + bus_release_resource(sc->bfe_dev, SYS_RES_IRQ, 0, sc->bfe_irq); + + if (sc->bfe_res != NULL) + bus_release_resource(sc->bfe_dev, SYS_RES_MEMORY, PCIR_BAR(0), + sc->bfe_res); + + if (sc->bfe_ifp != NULL) + if_free(sc->bfe_ifp); +} + +static void +bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) +{ + long i; + u_int16_t *ptr = (u_int16_t *)data; + + for(i = 0; i < 128; i += 2) + ptr[i/2] = CSR_READ_4(sc, 4096 + i); +} + +static int +bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, + u_long timeout, const int clear) +{ + u_long i; + + for (i = 0; i < timeout; i++) { + u_int32_t val = CSR_READ_4(sc, reg); + + if (clear && !(val & bit)) + break; + if (!clear && (val & bit)) + break; + DELAY(10); + } + if (i == timeout) { + device_printf(sc->bfe_dev, + "BUG! Timeout waiting for bit %08x of register " + "%x to %s.\n", bit, reg, (clear ? "clear" : "set")); + return (-1); + } + return (0); +} + +static int +bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) +{ + int err; + + /* Clear MII ISR */ + CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); + CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | + (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | + (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | + (reg << BFE_MDIO_RA_SHIFT) | + (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); + err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); + *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; + + return (err); +} + +static int +bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) +{ + int status; + + CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); + CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | + (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | + (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | + (reg << BFE_MDIO_RA_SHIFT) | + (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | + (val & BFE_MDIO_DATA_DATA))); + status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); + + return (status); +} + +/* + * XXX - I think this is handled by the PHY driver, but it can't hurt to do it + * twice + */ +static int +bfe_setupphy(struct bfe_softc *sc) +{ + u_int32_t val; + + /* Enable activity LED */ + bfe_readphy(sc, 26, &val); + bfe_writephy(sc, 26, val & 0x7fff); + bfe_readphy(sc, 26, &val); + + /* Enable traffic meter LED mode */ + bfe_readphy(sc, 27, &val); + bfe_writephy(sc, 27, val | (1 << 6)); + + return (0); +} + +static void +bfe_stats_update(struct bfe_softc *sc) +{ + struct bfe_hw_stats *stats; + struct ifnet *ifp; + uint32_t mib[BFE_MIB_CNT]; + uint32_t reg, *val; + + BFE_LOCK_ASSERT(sc); + + val = mib; + CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); + for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) + *val++ = CSR_READ_4(sc, reg); + for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) + *val++ = CSR_READ_4(sc, reg); + + ifp = sc->bfe_ifp; + stats = &sc->bfe_stats; + /* Tx stat. */ + stats->tx_good_octets += mib[MIB_TX_GOOD_O]; + stats->tx_good_frames += mib[MIB_TX_GOOD_P]; + stats->tx_octets += mib[MIB_TX_O]; + stats->tx_frames += mib[MIB_TX_P]; + stats->tx_bcast_frames += mib[MIB_TX_BCAST]; + stats->tx_mcast_frames += mib[MIB_TX_MCAST]; + stats->tx_pkts_64 += mib[MIB_TX_64]; + stats->tx_pkts_65_127 += mib[MIB_TX_65_127]; + stats->tx_pkts_128_255 += mib[MIB_TX_128_255]; + stats->tx_pkts_256_511 += mib[MIB_TX_256_511]; + stats->tx_pkts_512_1023 += mib[MIB_TX_512_1023]; + stats->tx_pkts_1024_max += mib[MIB_TX_1024_MAX]; + stats->tx_jabbers += mib[MIB_TX_JABBER]; + stats->tx_oversize_frames += mib[MIB_TX_OSIZE]; + stats->tx_frag_frames += mib[MIB_TX_FRAG]; + stats->tx_underruns += mib[MIB_TX_URUNS]; + stats->tx_colls += mib[MIB_TX_TCOLS]; + stats->tx_single_colls += mib[MIB_TX_SCOLS]; + stats->tx_multi_colls += mib[MIB_TX_MCOLS]; + stats->tx_excess_colls += mib[MIB_TX_ECOLS]; + stats->tx_late_colls += mib[MIB_TX_LCOLS]; + stats->tx_deferrals += mib[MIB_TX_DEFERED]; + stats->tx_carrier_losts += mib[MIB_TX_CLOST]; + stats->tx_pause_frames += mib[MIB_TX_PAUSE]; + /* Rx stat. */ + stats->rx_good_octets += mib[MIB_RX_GOOD_O]; + stats->rx_good_frames += mib[MIB_RX_GOOD_P]; + stats->rx_octets += mib[MIB_RX_O]; + stats->rx_frames += mib[MIB_RX_P]; + stats->rx_bcast_frames += mib[MIB_RX_BCAST]; + stats->rx_mcast_frames += mib[MIB_RX_MCAST]; + stats->rx_pkts_64 += mib[MIB_RX_64]; + stats->rx_pkts_65_127 += mib[MIB_RX_65_127]; + stats->rx_pkts_128_255 += mib[MIB_RX_128_255]; + stats->rx_pkts_256_511 += mib[MIB_RX_256_511]; + stats->rx_pkts_512_1023 += mib[MIB_RX_512_1023]; + stats->rx_pkts_1024_max += mib[MIB_RX_1024_MAX]; + stats->rx_jabbers += mib[MIB_RX_JABBER]; + stats->rx_oversize_frames += mib[MIB_RX_OSIZE]; + stats->rx_frag_frames += mib[MIB_RX_FRAG]; + stats->rx_missed_frames += mib[MIB_RX_MISS]; + stats->rx_crc_align_errs += mib[MIB_RX_CRCA]; + stats->rx_runts += mib[MIB_RX_USIZE]; + stats->rx_crc_errs += mib[MIB_RX_CRC]; + stats->rx_align_errs += mib[MIB_RX_ALIGN]; + stats->rx_symbol_errs += mib[MIB_RX_SYM]; + stats->rx_pause_frames += mib[MIB_RX_PAUSE]; + stats->rx_control_frames += mib[MIB_RX_NPAUSE]; + + /* Update counters in ifnet. */ + ifp->if_opackets += (u_long)mib[MIB_TX_GOOD_P]; + ifp->if_collisions += (u_long)mib[MIB_TX_TCOLS]; + ifp->if_oerrors += (u_long)mib[MIB_TX_URUNS] + + (u_long)mib[MIB_TX_ECOLS] + + (u_long)mib[MIB_TX_DEFERED] + + (u_long)mib[MIB_TX_CLOST]; + + ifp->if_ipackets += (u_long)mib[MIB_RX_GOOD_P]; + + ifp->if_ierrors += mib[MIB_RX_JABBER] + + mib[MIB_RX_MISS] + + mib[MIB_RX_CRCA] + + mib[MIB_RX_USIZE] + + mib[MIB_RX_CRC] + + mib[MIB_RX_ALIGN] + + mib[MIB_RX_SYM]; +} + +static void +bfe_txeof(struct bfe_softc *sc) +{ + struct bfe_tx_data *r; + struct ifnet *ifp; + int i, chipidx; + + BFE_LOCK_ASSERT(sc); + + ifp = sc->bfe_ifp; + + chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; + chipidx /= sizeof(struct bfe_desc); + + i = sc->bfe_tx_cons; + if (i == chipidx) + return; + bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + /* Go through the mbufs and free those that have been transmitted */ + for (; i != chipidx; BFE_INC(i, BFE_TX_LIST_CNT)) { + r = &sc->bfe_tx_ring[i]; + sc->bfe_tx_cnt--; + if (r->bfe_mbuf == NULL) + continue; + bus_dmamap_sync(sc->bfe_txmbuf_tag, r->bfe_map, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map); + + m_freem(r->bfe_mbuf); + r->bfe_mbuf = NULL; + } + + if (i != sc->bfe_tx_cons) { + /* we freed up some mbufs */ + sc->bfe_tx_cons = i; + ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; + } + + if (sc->bfe_tx_cnt == 0) + sc->bfe_watchdog_timer = 0; +} + +/* Pass a received packet up the stack */ +static void +bfe_rxeof(struct bfe_softc *sc) +{ + struct mbuf *m; + struct ifnet *ifp; + struct bfe_rxheader *rxheader; + struct bfe_rx_data *r; + int cons, prog; + u_int32_t status, current, len, flags; + + BFE_LOCK_ASSERT(sc); + cons = sc->bfe_rx_cons; + status = CSR_READ_4(sc, BFE_DMARX_STAT); + current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); + + ifp = sc->bfe_ifp; + + bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + + for (prog = 0; current != cons; prog++, + BFE_INC(cons, BFE_RX_LIST_CNT)) { + r = &sc->bfe_rx_ring[cons]; + m = r->bfe_mbuf; + /* + * Rx status should be read from mbuf such that we can't + * delay bus_dmamap_sync(9). This hardware limiation + * results in inefficent mbuf usage as bfe(4) couldn't + * reuse mapped buffer from errored frame. + */ + if (bfe_list_newbuf(sc, cons) != 0) { + ifp->if_iqdrops++; + bfe_discard_buf(sc, cons); + continue; + } + rxheader = mtod(m, struct bfe_rxheader*); + len = le16toh(rxheader->len); + flags = le16toh(rxheader->flags); + + /* Remove CRC bytes. */ + len -= ETHER_CRC_LEN; + + /* flag an error and try again */ + if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { + m_freem(m); + continue; + } + + /* Make sure to skip header bytes written by hardware. */ + m_adj(m, BFE_RX_OFFSET); + m->m_len = m->m_pkthdr.len = len; + + m->m_pkthdr.rcvif = ifp; + BFE_UNLOCK(sc); + (*ifp->if_input)(ifp, m); + BFE_LOCK(sc); + } + + if (prog > 0) { + sc->bfe_rx_cons = cons; + bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + } +} + +static void +bfe_intr(void *xsc) +{ + struct bfe_softc *sc = xsc; + struct ifnet *ifp; + u_int32_t istat; + + ifp = sc->bfe_ifp; + + BFE_LOCK(sc); + + istat = CSR_READ_4(sc, BFE_ISTAT); + + /* + * Defer unsolicited interrupts - This is necessary because setting the + * chips interrupt mask register to 0 doesn't actually stop the + * interrupts + */ + istat &= BFE_IMASK_DEF; + CSR_WRITE_4(sc, BFE_ISTAT, istat); + CSR_READ_4(sc, BFE_ISTAT); + + /* not expecting this interrupt, disregard it */ + if (istat == 0 || (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { + BFE_UNLOCK(sc); + return; + } + + /* A packet was received */ + if (istat & BFE_ISTAT_RX) + bfe_rxeof(sc); + + /* A packet was sent */ + if (istat & BFE_ISTAT_TX) + bfe_txeof(sc); + + if (istat & BFE_ISTAT_ERRORS) { + + if (istat & BFE_ISTAT_DSCE) { + device_printf(sc->bfe_dev, "Descriptor Error\n"); + bfe_stop(sc); + BFE_UNLOCK(sc); + return; + } + + if (istat & BFE_ISTAT_DPE) { + device_printf(sc->bfe_dev, + "Descriptor Protocol Error\n"); + bfe_stop(sc); + BFE_UNLOCK(sc); + return; + } + ifp->if_drv_flags &= ~IFF_DRV_RUNNING; + bfe_init_locked(sc); + } + + /* We have packets pending, fire them out */ + if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) + bfe_start_locked(ifp); + + BFE_UNLOCK(sc); +} + +static int +bfe_encap(struct bfe_softc *sc, struct mbuf **m_head) +{ + struct bfe_desc *d; + struct bfe_tx_data *r, *r1; + struct mbuf *m; + bus_dmamap_t map; + bus_dma_segment_t txsegs[BFE_MAXTXSEGS]; + uint32_t cur, si; + int error, i, nsegs; + + BFE_LOCK_ASSERT(sc); + + M_ASSERTPKTHDR((*m_head)); + + si = cur = sc->bfe_tx_prod; + r = &sc->bfe_tx_ring[cur]; + error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map, *m_head, + txsegs, &nsegs, 0); + if (error == EFBIG) { + m = m_collapse(*m_head, M_DONTWAIT, BFE_MAXTXSEGS); + if (m == NULL) { + m_freem(*m_head); + *m_head = NULL; + return (ENOMEM); + } + *m_head = m; + error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map, + *m_head, txsegs, &nsegs, 0); + if (error != 0) { + m_freem(*m_head); + *m_head = NULL; + return (error); + } + } else if (error != 0) + return (error); + if (nsegs == 0) { + m_freem(*m_head); + *m_head = NULL; + return (EIO); + } + + if (sc->bfe_tx_cnt + nsegs > BFE_TX_LIST_CNT - 1) { + bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map); + return (ENOBUFS); + } + + for (i = 0; i < nsegs; i++) { + d = &sc->bfe_tx_list[cur]; + d->bfe_ctrl = htole32(txsegs[i].ds_len & BFE_DESC_LEN); + d->bfe_ctrl |= htole32(BFE_DESC_IOC); + if (cur == BFE_TX_LIST_CNT - 1) + /* + * Tell the chip to wrap to the start of + * the descriptor list. + */ + d->bfe_ctrl |= htole32(BFE_DESC_EOT); + /* The chip needs all addresses to be added to BFE_PCI_DMA. */ + d->bfe_addr = htole32(BFE_ADDR_LO(txsegs[i].ds_addr) + + BFE_PCI_DMA); + BFE_INC(cur, BFE_TX_LIST_CNT); + } + + /* Update producer index. */ + sc->bfe_tx_prod = cur; + + /* Set EOF on the last descriptor. */ + cur = (cur + BFE_TX_LIST_CNT - 1) % BFE_TX_LIST_CNT; + d = &sc->bfe_tx_list[cur]; + d->bfe_ctrl |= htole32(BFE_DESC_EOF); + + /* Lastly set SOF on the first descriptor to avoid races. */ + d = &sc->bfe_tx_list[si]; + d->bfe_ctrl |= htole32(BFE_DESC_SOF); + + r1 = &sc->bfe_tx_ring[cur]; + map = r->bfe_map; + r->bfe_map = r1->bfe_map; + r1->bfe_map = map; + r1->bfe_mbuf = *m_head; + sc->bfe_tx_cnt += nsegs; + + bus_dmamap_sync(sc->bfe_txmbuf_tag, map, BUS_DMASYNC_PREWRITE); + + return (0); +} + +/* + * Set up to transmit a packet. + */ +static void +bfe_start(struct ifnet *ifp) +{ + BFE_LOCK((struct bfe_softc *)ifp->if_softc); + bfe_start_locked(ifp); + BFE_UNLOCK((struct bfe_softc *)ifp->if_softc); +} + +/* + * Set up to transmit a packet. The softc is already locked. + */ +static void +bfe_start_locked(struct ifnet *ifp) +{ + struct bfe_softc *sc; + struct mbuf *m_head; + int queued; + + sc = ifp->if_softc; + + BFE_LOCK_ASSERT(sc); + + /* + * Not much point trying to send if the link is down + * or we have nothing to send. + */ + if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != + IFF_DRV_RUNNING || (sc->bfe_flags & BFE_FLAG_LINK) == 0) + return; + + for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && + sc->bfe_tx_cnt < BFE_TX_LIST_CNT - 1;) { + IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); + if (m_head == NULL) + break; + + /* + * Pack the data into the tx ring. If we dont have + * enough room, let the chip drain the ring. + */ + if (bfe_encap(sc, &m_head)) { + if (m_head == NULL) + break; + IFQ_DRV_PREPEND(&ifp->if_snd, m_head); + ifp->if_drv_flags |= IFF_DRV_OACTIVE; + break; + } + + queued++; + + /* + * If there's a BPF listener, bounce a copy of this frame + * to him. + */ + BPF_MTAP(ifp, m_head); + } + + if (queued) { + bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + /* Transmit - twice due to apparent hardware bug */ + CSR_WRITE_4(sc, BFE_DMATX_PTR, + sc->bfe_tx_prod * sizeof(struct bfe_desc)); + /* + * XXX It seems the following write is not necessary + * to kick Tx command. What might be required would be + * a way flushing PCI posted write. Reading the register + * back ensures the flush operation. In addition, + * hardware will execute PCI posted write in the long + * run and watchdog timer for the kick command was set + * to 5 seconds. Therefore I think the second write + * access is not necessary or could be replaced with + * read operation. + */ + CSR_WRITE_4(sc, BFE_DMATX_PTR, + sc->bfe_tx_prod * sizeof(struct bfe_desc)); + + /* + * Set a timeout in case the chip goes out to lunch. + */ + sc->bfe_watchdog_timer = 5; + } +} + +static void +bfe_init(void *xsc) +{ + BFE_LOCK((struct bfe_softc *)xsc); + bfe_init_locked(xsc); + BFE_UNLOCK((struct bfe_softc *)xsc); +} + +static void +bfe_init_locked(void *xsc) +{ + struct bfe_softc *sc = (struct bfe_softc*)xsc; + struct ifnet *ifp = sc->bfe_ifp; + struct mii_data *mii; + + BFE_LOCK_ASSERT(sc); + + mii = device_get_softc(sc->bfe_miibus); + + if (ifp->if_drv_flags & IFF_DRV_RUNNING) + return; + + bfe_stop(sc); + bfe_chip_reset(sc); + + if (bfe_list_rx_init(sc) == ENOBUFS) { + device_printf(sc->bfe_dev, + "%s: Not enough memory for list buffers\n", __func__); + bfe_stop(sc); + return; + } + bfe_list_tx_init(sc); + + bfe_set_rx_mode(sc); + + /* Enable the chip and core */ + BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); + /* Enable interrupts */ + CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); + + /* Clear link state and change media. */ + sc->bfe_flags &= ~BFE_FLAG_LINK; + mii_mediachg(mii); + + ifp->if_drv_flags |= IFF_DRV_RUNNING; + ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; + + callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc); +} + +/* + * Set media options. + */ +static int +bfe_ifmedia_upd(struct ifnet *ifp) +{ + struct bfe_softc *sc; + struct mii_data *mii; + int error; + + sc = ifp->if_softc; + BFE_LOCK(sc); + + mii = device_get_softc(sc->bfe_miibus); + if (mii->mii_instance) { + struct mii_softc *miisc; + for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; + miisc = LIST_NEXT(miisc, mii_list)) + mii_phy_reset(miisc); + } + error = mii_mediachg(mii); + BFE_UNLOCK(sc); + + return (error); +} + +/* + * Report current media status. + */ +static void +bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) +{ + struct bfe_softc *sc = ifp->if_softc; + struct mii_data *mii; + + BFE_LOCK(sc); + mii = device_get_softc(sc->bfe_miibus); + mii_pollstat(mii); + ifmr->ifm_active = mii->mii_media_active; + ifmr->ifm_status = mii->mii_media_status; + BFE_UNLOCK(sc); +} + +static int +bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) +{ + struct bfe_softc *sc = ifp->if_softc; + struct ifreq *ifr = (struct ifreq *) data; + struct mii_data *mii; + int error = 0; + + switch (command) { + case SIOCSIFFLAGS: + BFE_LOCK(sc); + if (ifp->if_flags & IFF_UP) { + if (ifp->if_drv_flags & IFF_DRV_RUNNING) + bfe_set_rx_mode(sc); + else if ((sc->bfe_flags & BFE_FLAG_DETACH) == 0) + bfe_init_locked(sc); + } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) + bfe_stop(sc); + BFE_UNLOCK(sc); + break; + case SIOCADDMULTI: + case SIOCDELMULTI: + BFE_LOCK(sc); + if (ifp->if_drv_flags & IFF_DRV_RUNNING) + bfe_set_rx_mode(sc); + BFE_UNLOCK(sc); + break; + case SIOCGIFMEDIA: + case SIOCSIFMEDIA: + mii = device_get_softc(sc->bfe_miibus); + error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); + break; + default: + error = ether_ioctl(ifp, command, data); + break; + } + + return (error); +} + +static void +bfe_watchdog(struct bfe_softc *sc) +{ + struct ifnet *ifp; + + BFE_LOCK_ASSERT(sc); + + if (sc->bfe_watchdog_timer == 0 || --sc->bfe_watchdog_timer) + return; + + ifp = sc->bfe_ifp; + + device_printf(sc->bfe_dev, "watchdog timeout -- resetting\n"); + + ifp->if_oerrors++; + ifp->if_drv_flags &= ~IFF_DRV_RUNNING; + bfe_init_locked(sc); + + if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) + bfe_start_locked(ifp); +} + +static void +bfe_tick(void *xsc) +{ + struct bfe_softc *sc = xsc; + struct mii_data *mii; + + BFE_LOCK_ASSERT(sc); + + mii = device_get_softc(sc->bfe_miibus); + mii_tick(mii); + bfe_stats_update(sc); + bfe_watchdog(sc); + callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc); +} + +/* + * Stop the adapter and free any mbufs allocated to the + * RX and TX lists. + */ +static void +bfe_stop(struct bfe_softc *sc) +{ + struct ifnet *ifp; + + BFE_LOCK_ASSERT(sc); + + ifp = sc->bfe_ifp; + ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); + sc->bfe_flags &= ~BFE_FLAG_LINK; + callout_stop(&sc->bfe_stat_co); + sc->bfe_watchdog_timer = 0; + + bfe_chip_halt(sc); + bfe_tx_ring_free(sc); + bfe_rx_ring_free(sc); +} + +static int +sysctl_bfe_stats(SYSCTL_HANDLER_ARGS) +{ + struct bfe_softc *sc; + struct bfe_hw_stats *stats; + int error, result; + + result = -1; + error = sysctl_handle_int(oidp, &result, 0, req); + + if (error != 0 || req->newptr == NULL) + return (error); + + if (result != 1) + return (error); + + sc = (struct bfe_softc *)arg1; + stats = &sc->bfe_stats; + + printf("%s statistics:\n", device_get_nameunit(sc->bfe_dev)); + printf("Transmit good octets : %ju\n", + (uintmax_t)stats->tx_good_octets); + printf("Transmit good frames : %ju\n", + (uintmax_t)stats->tx_good_frames); + printf("Transmit octets : %ju\n", + (uintmax_t)stats->tx_octets); + printf("Transmit frames : %ju\n", + (uintmax_t)stats->tx_frames); + printf("Transmit broadcast frames : %ju\n", + (uintmax_t)stats->tx_bcast_frames); + printf("Transmit multicast frames : %ju\n", + (uintmax_t)stats->tx_mcast_frames); + printf("Transmit frames 64 bytes : %ju\n", + (uint64_t)stats->tx_pkts_64); + printf("Transmit frames 65 to 127 bytes : %ju\n", + (uint64_t)stats->tx_pkts_65_127); + printf("Transmit frames 128 to 255 bytes : %ju\n", + (uint64_t)stats->tx_pkts_128_255); + printf("Transmit frames 256 to 511 bytes : %ju\n", + (uint64_t)stats->tx_pkts_256_511); + printf("Transmit frames 512 to 1023 bytes : %ju\n", + (uint64_t)stats->tx_pkts_512_1023); + printf("Transmit frames 1024 to max bytes : %ju\n", + (uint64_t)stats->tx_pkts_1024_max); + printf("Transmit jabber errors : %u\n", stats->tx_jabbers); + printf("Transmit oversized frames : %ju\n", + (uint64_t)stats->tx_oversize_frames); + printf("Transmit fragmented frames : %ju\n", + (uint64_t)stats->tx_frag_frames); + printf("Transmit underruns : %u\n", stats->tx_colls); + printf("Transmit total collisions : %u\n", stats->tx_single_colls); + printf("Transmit single collisions : %u\n", stats->tx_single_colls); + printf("Transmit multiple collisions : %u\n", stats->tx_multi_colls); + printf("Transmit excess collisions : %u\n", stats->tx_excess_colls); + printf("Transmit late collisions : %u\n", stats->tx_late_colls); + printf("Transmit deferrals : %u\n", stats->tx_deferrals); + printf("Transmit carrier losts : %u\n", stats->tx_carrier_losts); + printf("Transmit pause frames : %u\n", stats->tx_pause_frames); + + printf("Receive good octets : %ju\n", + (uintmax_t)stats->rx_good_octets); + printf("Receive good frames : %ju\n", + (uintmax_t)stats->rx_good_frames); + printf("Receive octets : %ju\n", + (uintmax_t)stats->rx_octets); + printf("Receive frames : %ju\n", + (uintmax_t)stats->rx_frames); + printf("Receive broadcast frames : %ju\n", + (uintmax_t)stats->rx_bcast_frames); + printf("Receive multicast frames : %ju\n", + (uintmax_t)stats->rx_mcast_frames); + printf("Receive frames 64 bytes : %ju\n", + (uint64_t)stats->rx_pkts_64); + printf("Receive frames 65 to 127 bytes : %ju\n", + (uint64_t)stats->rx_pkts_65_127); + printf("Receive frames 128 to 255 bytes : %ju\n", + (uint64_t)stats->rx_pkts_128_255); + printf("Receive frames 256 to 511 bytes : %ju\n", + (uint64_t)stats->rx_pkts_256_511); + printf("Receive frames 512 to 1023 bytes : %ju\n", + (uint64_t)stats->rx_pkts_512_1023); + printf("Receive frames 1024 to max bytes : %ju\n", + (uint64_t)stats->rx_pkts_1024_max); + printf("Receive jabber errors : %u\n", stats->rx_jabbers); + printf("Receive oversized frames : %ju\n", + (uint64_t)stats->rx_oversize_frames); + printf("Receive fragmented frames : %ju\n", + (uint64_t)stats->rx_frag_frames); + printf("Receive missed frames : %u\n", stats->rx_missed_frames); + printf("Receive CRC align errors : %u\n", stats->rx_crc_align_errs); + printf("Receive undersized frames : %u\n", stats->rx_runts); + printf("Receive CRC errors : %u\n", stats->rx_crc_errs); + printf("Receive align errors : %u\n", stats->rx_align_errs); + printf("Receive symbol errors : %u\n", stats->rx_symbol_errs); + printf("Receive pause frames : %u\n", stats->rx_pause_frames); + printf("Receive control frames : %u\n", stats->rx_control_frames); + + return (error); +} diff --git a/freebsd/dev/bfe/if_bfereg.h b/freebsd/dev/bfe/if_bfereg.h new file mode 100644 index 00000000..b50627ed --- /dev/null +++ b/freebsd/dev/bfe/if_bfereg.h @@ -0,0 +1,626 @@ +/*- + * Copyright (c) 2003 Stuart Walsh + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +/* $FreeBSD$ */ + +#ifndef _BFE_H +#define _BFE_H + +/* PCI registers */ +#define BFE_PCI_MEMLO 0x10 +#define BFE_PCI_MEMHIGH 0x14 +#define BFE_PCI_INTLINE 0x3C + +/* Register layout. */ +#define BFE_DEVCTRL 0x00000000 /* Device Control */ +#define BFE_PFE 0x00000080 /* Pattern Filtering Enable */ +#define BFE_IPP 0x00000400 /* Internal EPHY Present */ +#define BFE_EPR 0x00008000 /* EPHY Reset */ +#define BFE_PME 0x00001000 /* PHY Mode Enable */ +#define BFE_PMCE 0x00002000 /* PHY Mode Clocks Enable */ +#define BFE_PADDR 0x0007c000 /* PHY Address */ +#define BFE_PADDR_SHIFT 18 + +#define BFE_BIST_STAT 0x0000000C /* Built-In Self-Test Status */ +#define BFE_WKUP_LEN 0x00000010 /* Wakeup Length */ + +#define BFE_ISTAT 0x00000020 /* Interrupt Status */ +#define BFE_ISTAT_PME 0x00000040 /* Power Management Event */ +#define BFE_ISTAT_TO 0x00000080 /* General Purpose Timeout */ +#define BFE_ISTAT_DSCE 0x00000400 /* Descriptor Error */ +#define BFE_ISTAT_DATAE 0x00000800 /* Data Error */ +#define BFE_ISTAT_DPE 0x00001000 /* Descr. Protocol Error */ +#define BFE_ISTAT_RDU 0x00002000 /* Receive Descr. Underflow */ +#define BFE_ISTAT_RFO 0x00004000 /* Receive FIFO Overflow */ +#define BFE_ISTAT_TFU 0x00008000 /* Transmit FIFO Underflow */ +#define BFE_ISTAT_RX 0x00010000 /* RX Interrupt */ +#define BFE_ISTAT_TX 0x01000000 /* TX Interrupt */ +#define BFE_ISTAT_EMAC 0x04000000 /* EMAC Interrupt */ +#define BFE_ISTAT_MII_WRITE 0x08000000 /* MII Write Interrupt */ +#define BFE_ISTAT_MII_READ 0x10000000 /* MII Read Interrupt */ +#define BFE_ISTAT_ERRORS (BFE_ISTAT_DSCE | BFE_ISTAT_DATAE | BFE_ISTAT_DPE |\ + BFE_ISTAT_RDU | BFE_ISTAT_RFO | BFE_ISTAT_TFU) + +#define BFE_IMASK 0x00000024 /* Interrupt Mask */ +#define BFE_IMASK_DEF (BFE_ISTAT_ERRORS | BFE_ISTAT_TO | BFE_ISTAT_RX | \ + BFE_ISTAT_TX) + +#define BFE_MAC_CTRL 0x000000A8 /* MAC Control */ +#define BFE_CTRL_CRC32_ENAB 0x00000001 /* CRC32 Generation Enable */ +#define BFE_CTRL_PDOWN 0x00000004 /* Onchip EPHY Powerdown */ +#define BFE_CTRL_EDET 0x00000008 /* Onchip EPHY Energy Detected */ +#define BFE_CTRL_LED 0x000000e0 /* Onchip EPHY LED Control */ +#define BFE_CTRL_LED_SHIFT 5 + +#define BFE_MAC_FLOW 0x000000AC /* MAC Flow Control */ +#define BFE_FLOW_RX_HIWAT 0x000000ff /* Onchip FIFO HI Water Mark */ +#define BFE_FLOW_PAUSE_ENAB 0x00008000 /* Enable Pause Frame Generation */ + +#define BFE_RCV_LAZY 0x00000100 /* Lazy Interrupt Control */ +#define BFE_LAZY_TO_MASK 0x00ffffff /* Timeout */ +#define BFE_LAZY_FC_MASK 0xff000000 /* Frame Count */ +#define BFE_LAZY_FC_SHIFT 24 + +#define BFE_DMATX_CTRL 0x00000200 /* DMA TX Control */ +#define BFE_TX_CTRL_ENABLE 0x00000001 /* Enable */ +#define BFE_TX_CTRL_SUSPEND 0x00000002 /* Suepend Request */ +#define BFE_TX_CTRL_LPBACK 0x00000004 /* Loopback Enable */ +#define BFE_TX_CTRL_FAIRPRI 0x00000008 /* Fair Priority */ +#define BFE_TX_CTRL_FLUSH 0x00000010 /* Flush Request */ + +#define BFE_DMATX_ADDR 0x00000204 /* DMA TX Descriptor Ring Address */ +#define BFE_DMATX_PTR 0x00000208 /* DMA TX Last Posted Descriptor */ +#define BFE_DMATX_STAT 0x0000020C /* DMA TX Current Active Desc. + Status */ +#define BFE_STAT_CDMASK 0x00000fff /* Current Descriptor Mask */ +#define BFE_STAT_SMASK 0x0000f000 /* State Mask */ +#define BFE_STAT_DISABLE 0x00000000 /* State Disabled */ +#define BFE_STAT_SACTIVE 0x00001000 /* State Active */ +#define BFE_STAT_SIDLE 0x00002000 /* State Idle Wait */ +#define BFE_STAT_STOPPED 0x00003000 /* State Stopped */ +#define BFE_STAT_SSUSP 0x00004000 /* State Suspend Pending */ +#define BFE_STAT_EMASK 0x000f0000 /* Error Mask */ +#define BFE_STAT_ENONE 0x00000000 /* Error None */ +#define BFE_STAT_EDPE 0x00010000 /* Error Desc. Protocol Error */ +#define BFE_STAT_EDFU 0x00020000 /* Error Data FIFO Underrun */ +#define BFE_STAT_EBEBR 0x00030000 /* Error Bus Error on Buffer Read */ +#define BFE_STAT_EBEDA 0x00040000 /* Error Bus Error on Desc. Access */ +#define BFE_STAT_FLUSHED 0x00100000 /* Flushed */ + +#define BFE_DMARX_CTRL 0x00000210 /* DMA RX Control */ +#define BFE_RX_CTRL_ENABLE 0x00000001 /* Enable */ +#define BFE_RX_CTRL_ROMASK 0x000000fe /* Receive Offset Mask */ +#define BFE_RX_CTRL_ROSHIFT 1 /* Receive Offset Shift */ + +#define BFE_DMARX_ADDR 0x00000214 /* DMA RX Descriptor Ring Address */ +#define BFE_DMARX_PTR 0x00000218 /* DMA RX Last Posted Descriptor */ +#define BFE_DMARX_STAT 0x0000021C /* DMA RX Current Active Desc. + Status */ + +#define BFE_RXCONF 0x00000400 /* EMAC RX Config */ +#define BFE_RXCONF_DBCAST 0x00000001 /* Disable Broadcast */ +#define BFE_RXCONF_ALLMULTI 0x00000002 /* Accept All Multicast */ +#define BFE_RXCONF_NORXTX 0x00000004 /* Receive Disable While Transmitting */ +#define BFE_RXCONF_PROMISC 0x00000008 /* Promiscuous Enable */ +#define BFE_RXCONF_LPBACK 0x00000010 /* Loopback Enable */ +#define BFE_RXCONF_FLOW 0x00000020 /* Flow Control Enable */ +#define BFE_RXCONF_ACCEPT 0x00000040 /* Accept Unicast Flow Control Frame */ +#define BFE_RXCONF_RFILT 0x00000080 /* Reject Filter */ + +#define BFE_RXMAXLEN 0x00000404 /* EMAC RX Max Packet Length */ +#define BFE_TXMAXLEN 0x00000408 /* EMAC TX Max Packet Length */ + +#define BFE_MDIO_CTRL 0x00000410 /* EMAC MDIO Control */ +#define BFE_MDIO_MAXF_MASK 0x0000007f /* MDC Frequency */ +#define BFE_MDIO_PREAMBLE 0x00000080 /* MII Preamble Enable */ + +#define BFE_MDIO_DATA 0x00000414 /* EMAC MDIO Data */ +#define BFE_MDIO_DATA_DATA 0x0000ffff /* R/W Data */ +#define BFE_MDIO_TA_MASK 0x00030000 /* Turnaround Value */ +#define BFE_MDIO_TA_SHIFT 16 +#define BFE_MDIO_TA_VALID 2 + +#define BFE_MDIO_RA_MASK 0x007c0000 /* Register Address */ +#define BFE_MDIO_PMD_MASK 0x0f800000 /* Physical Media Device */ +#define BFE_MDIO_OP_MASK 0x30000000 /* Opcode */ +#define BFE_MDIO_SB_MASK 0xc0000000 /* Start Bits */ +#define BFE_MDIO_SB_START 0x40000000 /* Start Of Frame */ +#define BFE_MDIO_RA_SHIFT 18 +#define BFE_MDIO_PMD_SHIFT 23 +#define BFE_MDIO_OP_SHIFT 28 +#define BFE_MDIO_OP_WRITE 1 +#define BFE_MDIO_OP_READ 2 +#define BFE_MDIO_SB_SHIFT 30 + +#define BFE_EMAC_IMASK 0x00000418 /* EMAC Interrupt Mask */ +#define BFE_EMAC_ISTAT 0x0000041C /* EMAC Interrupt Status */ +#define BFE_EMAC_INT_MII 0x00000001 /* MII MDIO Interrupt */ +#define BFE_EMAC_INT_MIB 0x00000002 /* MIB Interrupt */ +#define BFE_EMAC_INT_FLOW 0x00000003 /* Flow Control Interrupt */ + +#define BFE_CAM_DATA_LO 0x00000420 /* EMAC CAM Data Low */ +#define BFE_CAM_DATA_HI 0x00000424 /* EMAC CAM Data High */ +#define BFE_CAM_HI_VALID 0x00010000 /* Valid Bit */ + +#define BFE_CAM_CTRL 0x00000428 /* EMAC CAM Control */ +#define BFE_CAM_ENABLE 0x00000001 /* CAM Enable */ +#define BFE_CAM_MSEL 0x00000002 /* Mask Select */ +#define BFE_CAM_READ 0x00000004 /* Read */ +#define BFE_CAM_WRITE 0x00000008 /* Read */ +#define BFE_CAM_INDEX_MASK 0x003f0000 /* Index Mask */ +#define BFE_CAM_BUSY 0x80000000 /* CAM Busy */ +#define BFE_CAM_INDEX_SHIFT 16 + +#define BFE_ENET_CTRL 0x0000042C /* EMAC ENET Control */ +#define BFE_ENET_ENABLE 0x00000001 /* EMAC Enable */ +#define BFE_ENET_DISABLE 0x00000002 /* EMAC Disable */ +#define BFE_ENET_SRST 0x00000004 /* EMAC Soft Reset */ +#define BFE_ENET_EPSEL 0x00000008 /* External PHY Select */ + +#define BFE_TX_CTRL 0x00000430 /* EMAC TX Control */ +#define BFE_TX_DUPLEX 0x00000001 /* Full Duplex */ +#define BFE_TX_FMODE 0x00000002 /* Flow Mode */ +#define BFE_TX_SBENAB 0x00000004 /* Single Backoff Enable */ +#define BFE_TX_SMALL_SLOT 0x00000008 /* Small Slottime */ + +#define BFE_TX_WMARK 0x00000434 /* EMAC TX Watermark */ + +#define BFE_MIB_CTRL 0x00000438 /* EMAC MIB Control */ +#define BFE_MIB_CLR_ON_READ 0x00000001 /* Autoclear on Read */ + +/* Status registers */ +#define BFE_TX_GOOD_O 0x00000500 /* MIB TX Good Octets */ +#define BFE_TX_GOOD_P 0x00000504 /* MIB TX Good Packets */ +#define BFE_TX_O 0x00000508 /* MIB TX Octets */ +#define BFE_TX_P 0x0000050C /* MIB TX Packets */ +#define BFE_TX_BCAST 0x00000510 /* MIB TX Broadcast Packets */ +#define BFE_TX_MCAST 0x00000514 /* MIB TX Multicast Packets */ +#define BFE_TX_64 0x00000518 /* MIB TX <= 64 byte Packets */ +#define BFE_TX_65_127 0x0000051C /* MIB TX 65 to 127 byte Packets */ +#define BFE_TX_128_255 0x00000520 /* MIB TX 128 to 255 byte Packets */ +#define BFE_TX_256_511 0x00000524 /* MIB TX 256 to 511 byte Packets */ +#define BFE_TX_512_1023 0x00000528 /* MIB TX 512 to 1023 byte Packets */ +#define BFE_TX_1024_MAX 0x0000052C /* MIB TX 1024 to max byte Packets */ +#define BFE_TX_JABBER 0x00000530 /* MIB TX Jabber Packets */ +#define BFE_TX_OSIZE 0x00000534 /* MIB TX Oversize Packets */ +#define BFE_TX_FRAG 0x00000538 /* MIB TX Fragment Packets */ +#define BFE_TX_URUNS 0x0000053C /* MIB TX Underruns */ +#define BFE_TX_TCOLS 0x00000540 /* MIB TX Total Collisions */ +#define BFE_TX_SCOLS 0x00000544 /* MIB TX Single Collisions */ +#define BFE_TX_MCOLS 0x00000548 /* MIB TX Multiple Collisions */ +#define BFE_TX_ECOLS 0x0000054C /* MIB TX Excessive Collisions */ +#define BFE_TX_LCOLS 0x00000550 /* MIB TX Late Collisions */ +#define BFE_TX_DEFERED 0x00000554 /* MIB TX Defered Packets */ +#define BFE_TX_CLOST 0x00000558 /* MIB TX Carrier Lost */ +#define BFE_TX_PAUSE 0x0000055C /* MIB TX Pause Packets */ +#define BFE_RX_GOOD_O 0x00000580 /* MIB RX Good Octets */ +#define BFE_RX_GOOD_P 0x00000584 /* MIB RX Good Packets */ +#define BFE_RX_O 0x00000588 /* MIB RX Octets */ +#define BFE_RX_P 0x0000058C /* MIB RX Packets */ +#define BFE_RX_BCAST 0x00000590 /* MIB RX Broadcast Packets */ +#define BFE_RX_MCAST 0x00000594 /* MIB RX Multicast Packets */ +#define BFE_RX_64 0x00000598 /* MIB RX <= 64 byte Packets */ +#define BFE_RX_65_127 0x0000059C /* MIB RX 65 to 127 byte Packets */ +#define BFE_RX_128_255 0x000005A0 /* MIB RX 128 to 255 byte Packets */ +#define BFE_RX_256_511 0x000005A4 /* MIB RX 256 to 511 byte Packets */ +#define BFE_RX_512_1023 0x000005A8 /* MIB RX 512 to 1023 byte Packets */ +#define BFE_RX_1024_MAX 0x000005AC /* MIB RX 1024 to max byte Packets */ +#define BFE_RX_JABBER 0x000005B0 /* MIB RX Jabber Packets */ +#define BFE_RX_OSIZE 0x000005B4 /* MIB RX Oversize Packets */ +#define BFE_RX_FRAG 0x000005B8 /* MIB RX Fragment Packets */ +#define BFE_RX_MISS 0x000005BC /* MIB RX Missed Packets */ +#define BFE_RX_CRCA 0x000005C0 /* MIB RX CRC Align Errors */ +#define BFE_RX_USIZE 0x000005C4 /* MIB RX Undersize Packets */ +#define BFE_RX_CRC 0x000005C8 /* MIB RX CRC Errors */ +#define BFE_RX_ALIGN 0x000005CC /* MIB RX Align Errors */ +#define BFE_RX_SYM 0x000005D0 /* MIB RX Symbol Errors */ +#define BFE_RX_PAUSE 0x000005D4 /* MIB RX Pause Packets */ +#define BFE_RX_NPAUSE 0x000005D8 /* MIB RX Non-Pause Packets */ + +#define BFE_SBIMSTATE 0x00000F90 /* BFE_SB Initiator Agent State */ +#define BFE_PC 0x0000000f /* Pipe Count */ +#define BFE_AP_MASK 0x00000030 /* Arbitration Priority */ +#define BFE_AP_BOTH 0x00000000 /* Use both timeslices and token */ +#define BFE_AP_TS 0x00000010 /* Use timeslices only */ +#define BFE_AP_TK 0x00000020 /* Use token only */ +#define BFE_AP_RSV 0x00000030 /* Reserved */ +#define BFE_IBE 0x00020000 /* In Band Error */ +#define BFE_TO 0x00040000 /* Timeout */ + + +/* Seems the bcm440x has a fairly generic core, we only need be concerned with + * a couple of these + */ +#define BFE_SBINTVEC 0x00000F94 /* BFE_SB Interrupt Mask */ +#define BFE_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */ +#define BFE_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */ +#define BFE_INTVEC_ILINE20 0x00000004 /* Enable interrupts for iline20 */ +#define BFE_INTVEC_CODEC 0x00000008 /* Enable interrupts for v90 codec */ +#define BFE_INTVEC_USB 0x00000010 /* Enable interrupts for usb */ +#define BFE_INTVEC_EXTIF 0x00000020 /* Enable interrupts for external i/f */ +#define BFE_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */ + +#define BFE_SBTMSLOW 0x00000F98 /* BFE_SB Target State Low */ +#define BFE_RESET 0x00000001 /* Reset */ +#define BFE_REJECT 0x00000002 /* Reject */ +#define BFE_CLOCK 0x00010000 /* Clock Enable */ +#define BFE_FGC 0x00020000 /* Force Gated Clocks On */ +#define BFE_PE 0x40000000 /* Power Management Enable */ +#define BFE_BE 0x80000000 /* BIST Enable */ + +#define BFE_SBTMSHIGH 0x00000F9C /* BFE_SB Target State High */ +#define BFE_SERR 0x00000001 /* S-error */ +#define BFE_INT 0x00000002 /* Interrupt */ +#define BFE_BUSY 0x00000004 /* Busy */ +#define BFE_GCR 0x20000000 /* Gated Clock Request */ +#define BFE_BISTF 0x40000000 /* BIST Failed */ +#define BFE_BISTD 0x80000000 /* BIST Done */ + +#define BFE_SBBWA0 0x00000FA0 /* BFE_SB Bandwidth Allocation Table 0 */ +#define BFE_TAB0_MASK 0x0000ffff /* Lookup Table 0 */ +#define BFE_TAB1_MASK 0xffff0000 /* Lookup Table 0 */ +#define BFE_TAB0_SHIFT 0 +#define BFE_TAB1_SHIFT 16 + +#define BFE_SBIMCFGLOW 0x00000FA8 /* BFE_SB Initiator Configuration Low */ +#define BFE_STO_MASK 0x00000003 /* Service Timeout */ +#define BFE_RTO_MASK 0x00000030 /* Request Timeout */ +#define BFE_CID_MASK 0x00ff0000 /* Connection ID */ +#define BFE_RTO_SHIFT 4 +#define BFE_CID_SHIFT 16 + +#define BFE_SBIMCFGHIGH 0x00000FAC /* BFE_SB Initiator Configuration High */ +#define BFE_IEM_MASK 0x0000000c /* Inband Error Mode */ +#define BFE_TEM_MASK 0x00000030 /* Timeout Error Mode */ +#define BFE_BEM_MASK 0x000000c0 /* Bus Error Mode */ +#define BFE_TEM_SHIFT 4 +#define BFE_BEM_SHIFT 6 + +#define BFE_SBTMCFGLOW 0x00000FB8 /* BFE_SB Target Configuration Low */ +#define BFE_LOW_CD_MASK 0x000000ff /* Clock Divide Mask */ +#define BFE_LOW_CO_MASK 0x0000f800 /* Clock Offset Mask */ +#define BFE_LOW_IF_MASK 0x00fc0000 /* Interrupt Flags Mask */ +#define BFE_LOW_IM_MASK 0x03000000 /* Interrupt Mode Mask */ +#define BFE_LOW_CO_SHIFT 11 +#define BFE_LOW_IF_SHIFT 18 +#define BFE_LOW_IM_SHIFT 24 + +#define BFE_SBTMCFGHIGH 0x00000FBC /* BFE_SB Target Configuration High */ +#define BFE_HIGH_BM_MASK 0x00000003 /* Busy Mode */ +#define BFE_HIGH_RM_MASK 0x0000000C /* Retry Mode */ +#define BFE_HIGH_SM_MASK 0x00000030 /* Stop Mode */ +#define BFE_HIGH_EM_MASK 0x00000300 /* Error Mode */ +#define BFE_HIGH_IM_MASK 0x00000c00 /* Interrupt Mode */ +#define BFE_HIGH_RM_SHIFT 2 +#define BFE_HIGH_SM_SHIFT 4 +#define BFE_HIGH_EM_SHIFT 8 +#define BFE_HIGH_IM_SHIFT 10 + +#define BFE_SBBCFG 0x00000FC0 /* BFE_SB Broadcast Configuration */ +#define BFE_LAT_MASK 0x00000003 /* BFE_SB Latency */ +#define BFE_MAX0_MASK 0x000f0000 /* MAX Counter 0 */ +#define BFE_MAX1_MASK 0x00f00000 /* MAX Counter 1 */ +#define BFE_MAX0_SHIFT 16 +#define BFE_MAX1_SHIFT 20 + +#define BFE_SBBSTATE 0x00000FC8 /* BFE_SB Broadcast State */ +#define BFE_SBBSTATE_SRD 0x00000001 /* ST Reg Disable */ +#define BFE_SBBSTATE_HRD 0x00000002 /* Hold Reg Disable */ + +#define BFE_SBACTCNFG 0x00000FD8 /* BFE_SB Activate Configuration */ +#define BFE_SBFLAGST 0x00000FE8 /* BFE_SB Current BFE_SBFLAGS */ + +#define BFE_SBIDLOW 0x00000FF8 /* BFE_SB Identification Low */ +#define BFE_CS_MASK 0x00000003 /* Config Space Mask */ +#define BFE_AR_MASK 0x00000038 /* Num Address Ranges Supported */ +#define BFE_SYNCH 0x00000040 /* Sync */ +#define BFE_INIT 0x00000080 /* Initiator */ +#define BFE_MINLAT_MASK 0x00000f00 /* Minimum Backplane Latency */ +#define BFE_MAXLAT_MASK 0x0000f000 /* Maximum Backplane Latency */ +#define BFE_FIRST 0x00010000 /* This Initiator is First */ +#define BFE_CW_MASK 0x000c0000 /* Cycle Counter Width */ +#define BFE_TP_MASK 0x00f00000 /* Target Ports */ +#define BFE_IP_MASK 0x0f000000 /* Initiator Ports */ +#define BFE_AR_SHIFT 3 +#define BFE_MINLAT_SHIFT 8 +#define BFE_MAXLAT_SHIFT 12 +#define BFE_CW_SHIFT 18 +#define BFE_TP_SHIFT 20 +#define BFE_IP_SHIFT 24 + +#define BFE_SBIDHIGH 0x00000FFC /* BFE_SB Identification High */ +#define BFE_RC_MASK 0x0000000f /* Revision Code */ +#define BFE_CC_MASK 0x0000fff0 /* Core Code */ +#define BFE_VC_MASK 0xffff0000 /* Vendor Code */ +#define BFE_CC_SHIFT 4 +#define BFE_VC_SHIFT 16 + +#define BFE_CORE_ILINE20 0x801 +#define BFE_CORE_SDRAM 0x803 +#define BFE_CORE_PCI 0x804 +#define BFE_CORE_MIPS 0x805 +#define BFE_CORE_ENET 0x806 +#define BFE_CORE_CODEC 0x807 +#define BFE_CORE_USB 0x808 +#define BFE_CORE_ILINE100 0x80a +#define BFE_CORE_EXTIF 0x811 + +/* SSB PCI config space registers. */ +#define BFE_BAR0_WIN 0x80 +#define BFE_BAR1_WIN 0x84 +#define BFE_SPROM_CONTROL 0x88 +#define BFE_BAR1_CONTROL 0x8c + +/* SSB core and hsot control registers. */ +#define BFE_SSB_CONTROL 0x00000000 +#define BFE_SSB_ARBCONTROL 0x00000010 +#define BFE_SSB_ISTAT 0x00000020 +#define BFE_SSB_IMASK 0x00000024 +#define BFE_SSB_MBOX 0x00000028 +#define BFE_SSB_BCAST_ADDR 0x00000050 +#define BFE_SSB_BCAST_DATA 0x00000054 +#define BFE_SSB_PCI_TRANS_0 0x00000100 +#define BFE_SSB_PCI_TRANS_1 0x00000104 +#define BFE_SSB_PCI_TRANS_2 0x00000108 +#define BFE_SSB_SPROM 0x00000800 + +#define BFE_SSB_PCI_MEM 0x00000000 +#define BFE_SSB_PCI_IO 0x00000001 +#define BFE_SSB_PCI_CFG0 0x00000002 +#define BFE_SSB_PCI_CFG1 0x00000003 +#define BFE_SSB_PCI_PREF 0x00000004 +#define BFE_SSB_PCI_BURST 0x00000008 +#define BFE_SSB_PCI_MASK0 0xfc000000 +#define BFE_SSB_PCI_MASK1 0xfc000000 +#define BFE_SSB_PCI_MASK2 0xc0000000 + +#define BFE_DESC_LEN 0x00001fff +#define BFE_DESC_CMASK 0x0ff00000 /* Core specific bits */ +#define BFE_DESC_EOT 0x10000000 /* End of Table */ +#define BFE_DESC_IOC 0x20000000 /* Interrupt On Completion */ +#define BFE_DESC_EOF 0x40000000 /* End of Frame */ +#define BFE_DESC_SOF 0x80000000 /* Start of Frame */ + +#define BFE_RX_CP_THRESHOLD 256 +#define BFE_RX_HEADER_LEN 28 + +#define BFE_RX_FLAG_OFIFO 0x00000001 /* FIFO Overflow */ +#define BFE_RX_FLAG_CRCERR 0x00000002 /* CRC Error */ +#define BFE_RX_FLAG_SERR 0x00000004 /* Receive Symbol Error */ +#define BFE_RX_FLAG_ODD 0x00000008 /* Frame has odd number of nibbles */ +#define BFE_RX_FLAG_LARGE 0x00000010 /* Frame is > RX MAX Length */ +#define BFE_RX_FLAG_MCAST 0x00000020 /* Dest is Multicast Address */ +#define BFE_RX_FLAG_BCAST 0x00000040 /* Dest is Broadcast Address */ +#define BFE_RX_FLAG_MISS 0x00000080 /* Received due to promisc mode */ +#define BFE_RX_FLAG_LAST 0x00000800 /* Last buffer in frame */ +#define BFE_RX_FLAG_ERRORS (BFE_RX_FLAG_ODD | BFE_RX_FLAG_SERR | \ + BFE_RX_FLAG_CRCERR | BFE_RX_FLAG_OFIFO) + +#define BFE_MCAST_TBL_SIZE 32 +#define BFE_PCI_DMA 0x40000000 +#define BFE_REG_PCI 0x18002000 + +#define BCOM_VENDORID 0x14E4 +#define BCOM_DEVICEID_BCM4401 0x4401 +#define BCOM_DEVICEID_BCM4401B0 0x170c + +#define PCI_SETBIT(dev, reg, x, s) \ + pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) +#define PCI_CLRBIT(dev, reg, x, s) \ + pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) + +#define BFE_TX_LIST_CNT 128 +#define BFE_RX_LIST_CNT 128 +#define BFE_TX_LIST_SIZE BFE_TX_LIST_CNT * sizeof(struct bfe_desc) +#define BFE_RX_LIST_SIZE BFE_RX_LIST_CNT * sizeof(struct bfe_desc) +#define BFE_RX_OFFSET 30 +#define BFE_TX_QLEN 256 + +#define BFE_RX_RING_ALIGN 4096 +#define BFE_TX_RING_ALIGN 4096 +#define BFE_MAXTXSEGS 16 +#define BFE_DMA_MAXADDR 0x3FFFFFFF /* 1GB DMA address limit. */ +#define BFE_ADDR_LO(x) ((uint64_t)(x) & 0xFFFFFFFF) + +#define CSR_READ_4(sc, reg) bus_read_4(sc->bfe_res, reg) + +#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->bfe_res, reg, val) + +#define BFE_OR(sc, name, val) \ + CSR_WRITE_4(sc, name, CSR_READ_4(sc, name) | val) + +#define BFE_AND(sc, name, val) \ + CSR_WRITE_4(sc, name, CSR_READ_4(sc, name) & val) + +#define BFE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bfe_mtx, MA_OWNED) +#define BFE_LOCK(_sc) mtx_lock(&(_sc)->bfe_mtx) +#define BFE_UNLOCK(_sc) mtx_unlock(&(_sc)->bfe_mtx) + +#define BFE_INC(x, y) (x) = ((x) == ((y)-1)) ? 0 : (x)+1 + +struct bfe_tx_data { + struct mbuf *bfe_mbuf; + bus_dmamap_t bfe_map; +}; + +struct bfe_rx_data { + struct mbuf *bfe_mbuf; + bus_dmamap_t bfe_map; + u_int32_t bfe_ctrl; +}; + +struct bfe_desc { + u_int32_t bfe_ctrl; + u_int32_t bfe_addr; +}; + +struct bfe_rxheader { + u_int16_t len; + u_int16_t flags; + u_int16_t pad[12]; +}; + +#define MIB_TX_GOOD_O 0 +#define MIB_TX_GOOD_P 1 +#define MIB_TX_O 2 +#define MIB_TX_P 3 +#define MIB_TX_BCAST 4 +#define MIB_TX_MCAST 5 +#define MIB_TX_64 6 +#define MIB_TX_65_127 7 +#define MIB_TX_128_255 8 +#define MIB_TX_256_511 9 +#define MIB_TX_512_1023 10 +#define MIB_TX_1024_MAX 11 +#define MIB_TX_JABBER 12 +#define MIB_TX_OSIZE 13 +#define MIB_TX_FRAG 14 +#define MIB_TX_URUNS 15 +#define MIB_TX_TCOLS 16 +#define MIB_TX_SCOLS 17 +#define MIB_TX_MCOLS 18 +#define MIB_TX_ECOLS 19 +#define MIB_TX_LCOLS 20 +#define MIB_TX_DEFERED 21 +#define MIB_TX_CLOST 22 +#define MIB_TX_PAUSE 23 +#define MIB_RX_GOOD_O 24 +#define MIB_RX_GOOD_P 25 +#define MIB_RX_O 26 +#define MIB_RX_P 27 +#define MIB_RX_BCAST 28 +#define MIB_RX_MCAST 29 +#define MIB_RX_64 30 +#define MIB_RX_65_127 31 +#define MIB_RX_128_255 32 +#define MIB_RX_256_511 33 +#define MIB_RX_512_1023 34 +#define MIB_RX_1024_MAX 35 +#define MIB_RX_JABBER 36 +#define MIB_RX_OSIZE 37 +#define MIB_RX_FRAG 38 +#define MIB_RX_MISS 39 +#define MIB_RX_CRCA 40 +#define MIB_RX_USIZE 41 +#define MIB_RX_CRC 42 +#define MIB_RX_ALIGN 43 +#define MIB_RX_SYM 44 +#define MIB_RX_PAUSE 45 +#define MIB_RX_NPAUSE 46 + +#define BFE_MIB_CNT (MIB_RX_NPAUSE - MIB_TX_GOOD_O + 1) + +struct bfe_hw_stats { + uint64_t tx_good_octets; + uint64_t tx_good_frames; + uint64_t tx_octets; + uint64_t tx_frames; + uint64_t tx_bcast_frames; + uint64_t tx_mcast_frames; + uint64_t tx_pkts_64; + uint64_t tx_pkts_65_127; + uint64_t tx_pkts_128_255; + uint64_t tx_pkts_256_511; + uint64_t tx_pkts_512_1023; + uint64_t tx_pkts_1024_max; + uint32_t tx_jabbers; + uint64_t tx_oversize_frames; + uint64_t tx_frag_frames; + uint32_t tx_underruns; + uint32_t tx_colls; + uint32_t tx_single_colls; + uint32_t tx_multi_colls; + uint32_t tx_excess_colls; + uint32_t tx_late_colls; + uint32_t tx_deferrals; + uint32_t tx_carrier_losts; + uint32_t tx_pause_frames; + + uint64_t rx_good_octets; + uint64_t rx_good_frames; + uint64_t rx_octets; + uint64_t rx_frames; + uint64_t rx_bcast_frames; + uint64_t rx_mcast_frames; + uint64_t rx_pkts_64; + uint64_t rx_pkts_65_127; + uint64_t rx_pkts_128_255; + uint64_t rx_pkts_256_511; + uint64_t rx_pkts_512_1023; + uint64_t rx_pkts_1024_max; + uint32_t rx_jabbers; + uint64_t rx_oversize_frames; + uint64_t rx_frag_frames; + uint32_t rx_missed_frames; + uint32_t rx_crc_align_errs; + uint32_t rx_runts; + uint32_t rx_crc_errs; + uint32_t rx_align_errs; + uint32_t rx_symbol_errs; + uint32_t rx_pause_frames; + uint32_t rx_control_frames; +}; + +struct bfe_softc +{ + struct ifnet *bfe_ifp; /* interface info */ + device_t bfe_dev; + device_t bfe_miibus; + bus_dma_tag_t bfe_tag; + bus_dma_tag_t bfe_parent_tag; + bus_dma_tag_t bfe_tx_tag, bfe_rx_tag; + bus_dmamap_t bfe_tx_map, bfe_rx_map; + bus_dma_tag_t bfe_txmbuf_tag, bfe_rxmbuf_tag; + bus_dmamap_t bfe_rx_sparemap; + void *bfe_intrhand; + struct resource *bfe_irq; + struct resource *bfe_res; + struct callout bfe_stat_co; + struct bfe_hw_stats bfe_stats; + struct bfe_desc *bfe_tx_list, *bfe_rx_list; + struct bfe_tx_data bfe_tx_ring[BFE_TX_LIST_CNT]; /* XXX */ + struct bfe_rx_data bfe_rx_ring[BFE_RX_LIST_CNT]; /* XXX */ + struct mtx bfe_mtx; + u_int32_t bfe_flags; +#define BFE_FLAG_DETACH 0x4000 +#define BFE_FLAG_LINK 0x8000 + u_int32_t bfe_imask; + u_int32_t bfe_dma_offset; + u_int32_t bfe_tx_cnt, bfe_tx_cons, bfe_tx_prod; + u_int32_t bfe_rx_prod, bfe_rx_cons; + u_int32_t bfe_tx_dma, bfe_rx_dma; + int bfe_watchdog_timer; + u_int8_t bfe_phyaddr; /* Address of the card's PHY */ + u_int8_t bfe_mdc_port; + u_int8_t bfe_core_unit; + u_char bfe_enaddr[6]; + int bfe_if_flags; +}; + +struct bfe_type +{ + u_int16_t bfe_vid; + u_int16_t bfe_did; + char *bfe_name; +}; + +#endif /* _BFE_H */ diff --git a/freebsd/dev/bge/if_bge.c b/freebsd/dev/bge/if_bge.c new file mode 100644 index 00000000..4ae441bd --- /dev/null +++ b/freebsd/dev/bge/if_bge.c @@ -0,0 +1,5874 @@ +#include + +/*- + * Copyright (c) 2001 Wind River Systems + * Copyright (c) 1997, 1998, 1999, 2001 + * Bill Paul . All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Bill Paul. + * 4. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +/* + * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. + * + * The Broadcom BCM5700 is based on technology originally developed by + * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet + * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has + * two on-board MIPS R4000 CPUs and can have as much as 16MB of external + * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo + * frames, highly configurable RX filtering, and 16 RX and TX queues + * (which, along with RX filter rules, can be used for QOS applications). + * Other features, such as TCP segmentation, may be available as part + * of value-added firmware updates. Unlike the Tigon I and Tigon II, + * firmware images can be stored in hardware and need not be compiled + * into the driver. + * + * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will + * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. + * + * The BCM5701 is a single-chip solution incorporating both the BCM5700 + * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 + * does not support external SSRAM. + * + * Broadcom also produces a variation of the BCM5700 under the "Altima" + * brand name, which is functionally similar but lacks PCI-X support. + * + * Without external SSRAM, you can only have at most 4 TX rings, + * and the use of the mini RX ring is disabled. This seems to imply + * that these features are simply not available on the BCM5701. As a + * result, this driver does not implement any support for the mini RX + * ring. + */ + +#ifdef HAVE_KERNEL_OPTION_HEADERS +#include +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#ifdef __sparc64__ +#include +#include +#include +#include +#endif + +#include +#include + +#include + +#define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP) +#define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ + +MODULE_DEPEND(bge, pci, 1, 1, 1); +MODULE_DEPEND(bge, ether, 1, 1, 1); +MODULE_DEPEND(bge, miibus, 1, 1, 1); + +/* "device miibus" required. See GENERIC if you get errors here. */ +#include + +/* + * Various supported device vendors/types and their names. Note: the + * spec seems to indicate that the hardware still has Alteon's vendor + * ID burned into it, though it will always be overriden by the vendor + * ID in the EEPROM. Just to be safe, we cover all possibilities. + */ +static const struct bge_type { + uint16_t bge_vid; + uint16_t bge_did; +} bge_devs[] = { + { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 }, + { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 }, + + { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 }, + { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 }, + { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 }, + + { APPLE_VENDORID, APPLE_DEVICE_BCM5701 }, + + { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5717 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5718 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5723 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5756 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5761 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5761E }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5761S }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5761SE }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5764 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5784 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5785F }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5785G }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5787F }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM57760 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM57780 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM57788 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM57790 }, + + { SK_VENDORID, SK_DEVICEID_ALTIMA }, + + { TC_VENDORID, TC_DEVICEID_3C996 }, + + { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE4 }, + { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE5 }, + { FJTSU_VENDORID, FJTSU_DEVICEID_PP250450 }, + + { 0, 0 } +}; + +static const struct bge_vendor { + uint16_t v_id; + const char *v_name; +} bge_vendors[] = { + { ALTEON_VENDORID, "Alteon" }, + { ALTIMA_VENDORID, "Altima" }, + { APPLE_VENDORID, "Apple" }, + { BCOM_VENDORID, "Broadcom" }, + { SK_VENDORID, "SysKonnect" }, + { TC_VENDORID, "3Com" }, + { FJTSU_VENDORID, "Fujitsu" }, + + { 0, NULL } +}; + +static const struct bge_revision { + uint32_t br_chipid; + const char *br_name; +} bge_revisions[] = { + { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, + { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, + { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, + { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, + { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, + { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, + { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, + { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, + { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, + { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, + { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, + { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, + { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, + { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, + { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, + { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, + { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" }, + { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, + { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, + { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, + { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, + { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, + { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, + { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, + { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, + { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, + { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, + { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, + { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, + { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, + { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, + { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, + { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, + { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, + { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, + { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, + { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, + { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, + { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, + { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, + { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, + { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, + { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, + { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, + { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, + { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, + { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, + { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, + { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" }, + { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, + { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, + { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, + { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, + /* 5754 and 5787 share the same ASIC ID */ + { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, + { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, + { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, + { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, + { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, + { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, + { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, + + { 0, NULL } +}; + +/* + * Some defaults for major revisions, so that newer steppings + * that we don't know about have a shot at working. + */ +static const struct bge_revision bge_majorrevs[] = { + { BGE_ASICREV_BCM5700, "unknown BCM5700" }, + { BGE_ASICREV_BCM5701, "unknown BCM5701" }, + { BGE_ASICREV_BCM5703, "unknown BCM5703" }, + { BGE_ASICREV_BCM5704, "unknown BCM5704" }, + { BGE_ASICREV_BCM5705, "unknown BCM5705" }, + { BGE_ASICREV_BCM5750, "unknown BCM5750" }, + { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, + { BGE_ASICREV_BCM5752, "unknown BCM5752" }, + { BGE_ASICREV_BCM5780, "unknown BCM5780" }, + { BGE_ASICREV_BCM5714, "unknown BCM5714" }, + { BGE_ASICREV_BCM5755, "unknown BCM5755" }, + { BGE_ASICREV_BCM5761, "unknown BCM5761" }, + { BGE_ASICREV_BCM5784, "unknown BCM5784" }, + { BGE_ASICREV_BCM5785, "unknown BCM5785" }, + /* 5754 and 5787 share the same ASIC ID */ + { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, + { BGE_ASICREV_BCM5906, "unknown BCM5906" }, + { BGE_ASICREV_BCM57780, "unknown BCM57780" }, + { BGE_ASICREV_BCM5717, "unknown BCM5717" }, + + { 0, NULL } +}; + +#define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO) +#define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY) +#define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS) +#define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY) +#define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS) +#define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS) +#define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5717_PLUS) + +const struct bge_revision * bge_lookup_rev(uint32_t); +const struct bge_vendor * bge_lookup_vendor(uint16_t); + +typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); + +static int bge_probe(device_t); +static int bge_attach(device_t); +static int bge_detach(device_t); +static int bge_suspend(device_t); +static int bge_resume(device_t); +static void bge_release_resources(struct bge_softc *); +static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int); +static int bge_dma_alloc(struct bge_softc *); +static void bge_dma_free(struct bge_softc *); +static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t, + bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *); + +static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]); +static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); +static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); +static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); +static int bge_get_eaddr(struct bge_softc *, uint8_t[]); + +static void bge_txeof(struct bge_softc *, uint16_t); +static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); +static int bge_rxeof(struct bge_softc *, uint16_t, int); + +static void bge_asf_driver_up (struct bge_softc *); +static void bge_tick(void *); +static void bge_stats_clear_regs(struct bge_softc *); +static void bge_stats_update(struct bge_softc *); +static void bge_stats_update_regs(struct bge_softc *); +static struct mbuf *bge_check_short_dma(struct mbuf *); +static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *, + uint16_t *, uint16_t *); +static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *); + +static void bge_intr(void *); +static int bge_msi_intr(void *); +static void bge_intr_task(void *, int); +static void bge_start_locked(struct ifnet *); +static void bge_start(struct ifnet *); +static int bge_ioctl(struct ifnet *, u_long, caddr_t); +static void bge_init_locked(struct bge_softc *); +static void bge_init(void *); +static void bge_stop(struct bge_softc *); +static void bge_watchdog(struct bge_softc *); +static int bge_shutdown(device_t); +static int bge_ifmedia_upd_locked(struct ifnet *); +static int bge_ifmedia_upd(struct ifnet *); +static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); + +static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); +static int bge_read_nvram(struct bge_softc *, caddr_t, int, int); + +static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); +static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); + +static void bge_setpromisc(struct bge_softc *); +static void bge_setmulti(struct bge_softc *); +static void bge_setvlan(struct bge_softc *); + +static __inline void bge_rxreuse_std(struct bge_softc *, int); +static __inline void bge_rxreuse_jumbo(struct bge_softc *, int); +static int bge_newbuf_std(struct bge_softc *, int); +static int bge_newbuf_jumbo(struct bge_softc *, int); +static int bge_init_rx_ring_std(struct bge_softc *); +static void bge_free_rx_ring_std(struct bge_softc *); +static int bge_init_rx_ring_jumbo(struct bge_softc *); +static void bge_free_rx_ring_jumbo(struct bge_softc *); +static void bge_free_tx_ring(struct bge_softc *); +static int bge_init_tx_ring(struct bge_softc *); + +static int bge_chipinit(struct bge_softc *); +static int bge_blockinit(struct bge_softc *); + +static int bge_has_eaddr(struct bge_softc *); +static uint32_t bge_readmem_ind(struct bge_softc *, int); +static void bge_writemem_ind(struct bge_softc *, int, int); +static void bge_writembx(struct bge_softc *, int, int); +#ifdef notdef +static uint32_t bge_readreg_ind(struct bge_softc *, int); +#endif +static void bge_writemem_direct(struct bge_softc *, int, int); +static void bge_writereg_ind(struct bge_softc *, int, int); + +static int bge_miibus_readreg(device_t, int, int); +static int bge_miibus_writereg(device_t, int, int, int); +static void bge_miibus_statchg(device_t); +#ifdef DEVICE_POLLING +static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); +#endif + +#define BGE_RESET_START 1 +#define BGE_RESET_STOP 2 +static void bge_sig_post_reset(struct bge_softc *, int); +static void bge_sig_legacy(struct bge_softc *, int); +static void bge_sig_pre_reset(struct bge_softc *, int); +static void bge_stop_fw(struct bge_softc *); +static int bge_reset(struct bge_softc *); +static void bge_link_upd(struct bge_softc *); + +/* + * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may + * leak information to untrusted users. It is also known to cause alignment + * traps on certain architectures. + */ +#ifdef BGE_REGISTER_DEBUG +static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS); +static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS); +static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS); +#endif +static void bge_add_sysctls(struct bge_softc *); +static void bge_add_sysctl_stats_regs(struct bge_softc *, + struct sysctl_ctx_list *, struct sysctl_oid_list *); +static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *, + struct sysctl_oid_list *); +static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS); + +static device_method_t bge_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, bge_probe), + DEVMETHOD(device_attach, bge_attach), + DEVMETHOD(device_detach, bge_detach), + DEVMETHOD(device_shutdown, bge_shutdown), + DEVMETHOD(device_suspend, bge_suspend), + DEVMETHOD(device_resume, bge_resume), + + /* bus interface */ + DEVMETHOD(bus_print_child, bus_generic_print_child), + DEVMETHOD(bus_driver_added, bus_generic_driver_added), + + /* MII interface */ + DEVMETHOD(miibus_readreg, bge_miibus_readreg), + DEVMETHOD(miibus_writereg, bge_miibus_writereg), + DEVMETHOD(miibus_statchg, bge_miibus_statchg), + + { 0, 0 } +}; + +static driver_t bge_driver = { + "bge", + bge_methods, + sizeof(struct bge_softc) +}; + +static devclass_t bge_devclass; + +DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); +DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); + +static int bge_allow_asf = 0; + +TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf); + +SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters"); +SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0, + "Allow ASF mode if available"); + +#define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500" +#define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2" +#define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500" +#define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3" +#define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id" + +static int +bge_has_eaddr(struct bge_softc *sc) +{ +#ifdef __sparc64__ + char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)]; + device_t dev; + uint32_t subvendor; + + dev = sc->bge_dev; + + /* + * The on-board BGEs found in sun4u machines aren't fitted with + * an EEPROM which means that we have to obtain the MAC address + * via OFW and that some tests will always fail. We distinguish + * such BGEs by the subvendor ID, which also has to be obtained + * from OFW instead of the PCI configuration space as the latter + * indicates Broadcom as the subvendor of the netboot interface. + * For early Blade 1500 and 2500 we even have to check the OFW + * device path as the subvendor ID always defaults to Broadcom + * there. + */ + if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR, + &subvendor, sizeof(subvendor)) == sizeof(subvendor) && + (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID)) + return (0); + memset(buf, 0, sizeof(buf)); + if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) { + if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 && + strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0) + return (0); + if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 && + strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0) + return (0); + } +#endif + return (1); +} + +static uint32_t +bge_readmem_ind(struct bge_softc *sc, int off) +{ + device_t dev; + uint32_t val; + + if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && + off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) + return (0); + + dev = sc->bge_dev; + + pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); + val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4); + pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); + return (val); +} + +static void +bge_writemem_ind(struct bge_softc *sc, int off, int val) +{ + device_t dev; + + if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && + off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) + return; + + dev = sc->bge_dev; + + pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); + pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); + pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); +} + +#ifdef notdef +static uint32_t +bge_readreg_ind(struct bge_softc *sc, int off) +{ + device_t dev; + + dev = sc->bge_dev; + + pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); + return (pci_read_config(dev, BGE_PCI_REG_DATA, 4)); +} +#endif + +static void +bge_writereg_ind(struct bge_softc *sc, int off, int val) +{ + device_t dev; + + dev = sc->bge_dev; + + pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); + pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); +} + +static void +bge_writemem_direct(struct bge_softc *sc, int off, int val) +{ + CSR_WRITE_4(sc, off, val); +} + +static void +bge_writembx(struct bge_softc *sc, int off, int val) +{ + if (sc->bge_asicrev == BGE_ASICREV_BCM5906) + off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; + + CSR_WRITE_4(sc, off, val); +} + +/* + * Map a single buffer address. + */ + +static void +bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) +{ + struct bge_dmamap_arg *ctx; + + if (error) + return; + + KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg)); + + ctx = arg; + ctx->bge_busaddr = segs->ds_addr; +} + +static uint8_t +bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) +{ + uint32_t access, byte = 0; + int i; + + /* Lock. */ + CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); + for (i = 0; i < 8000; i++) { + if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) + break; + DELAY(20); + } + if (i == 8000) + return (1); + + /* Enable access. */ + access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); + CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); + + CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); + CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); + for (i = 0; i < BGE_TIMEOUT * 10; i++) { + DELAY(10); + if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { + DELAY(10); + break; + } + } + + if (i == BGE_TIMEOUT * 10) { + if_printf(sc->bge_ifp, "nvram read timed out\n"); + return (1); + } + + /* Get result. */ + byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); + + *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; + + /* Disable access. */ + CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); + + /* Unlock. */ + CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); + CSR_READ_4(sc, BGE_NVRAM_SWARB); + + return (0); +} + +/* + * Read a sequence of bytes from NVRAM. + */ +static int +bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt) +{ + int err = 0, i; + uint8_t byte = 0; + + if (sc->bge_asicrev != BGE_ASICREV_BCM5906) + return (1); + + for (i = 0; i < cnt; i++) { + err = bge_nvram_getbyte(sc, off + i, &byte); + if (err) + break; + *(dest + i) = byte; + } + + return (err ? 1 : 0); +} + +/* + * Read a byte of data stored in the EEPROM at address 'addr.' The + * BCM570x supports both the traditional bitbang interface and an + * auto access interface for reading the EEPROM. We use the auto + * access method. + */ +static uint8_t +bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) +{ + int i; + uint32_t byte = 0; + + /* + * Enable use of auto EEPROM access so we can avoid + * having to use the bitbang method. + */ + BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); + + /* Reset the EEPROM, load the clock period. */ + CSR_WRITE_4(sc, BGE_EE_ADDR, + BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); + DELAY(20); + + /* Issue the read EEPROM command. */ + CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); + + /* Wait for completion */ + for(i = 0; i < BGE_TIMEOUT * 10; i++) { + DELAY(10); + if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) + break; + } + + if (i == BGE_TIMEOUT * 10) { + device_printf(sc->bge_dev, "EEPROM read timed out\n"); + return (1); + } + + /* Get result. */ + byte = CSR_READ_4(sc, BGE_EE_DATA); + + *dest = (byte >> ((addr % 4) * 8)) & 0xFF; + + return (0); +} + +/* + * Read a sequence of bytes from the EEPROM. + */ +static int +bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt) +{ + int i, error = 0; + uint8_t byte = 0; + + for (i = 0; i < cnt; i++) { + error = bge_eeprom_getbyte(sc, off + i, &byte); + if (error) + break; + *(dest + i) = byte; + } + + return (error ? 1 : 0); +} + +static int +bge_miibus_readreg(device_t dev, int phy, int reg) +{ + struct bge_softc *sc; + uint32_t val; + int i; + + sc = device_get_softc(dev); + + /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ + if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { + CSR_WRITE_4(sc, BGE_MI_MODE, + sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); + DELAY(80); + } + + CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | + BGE_MIPHY(phy) | BGE_MIREG(reg)); + + /* Poll for the PHY register access to complete. */ + for (i = 0; i < BGE_TIMEOUT; i++) { + DELAY(10); + val = CSR_READ_4(sc, BGE_MI_COMM); + if ((val & BGE_MICOMM_BUSY) == 0) { + DELAY(5); + val = CSR_READ_4(sc, BGE_MI_COMM); + break; + } + } + + if (i == BGE_TIMEOUT) { + device_printf(sc->bge_dev, + "PHY read timed out (phy %d, reg %d, val 0x%08x)\n", + phy, reg, val); + val = 0; + } + + /* Restore the autopoll bit if necessary. */ + if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { + CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); + DELAY(80); + } + + if (val & BGE_MICOMM_READFAIL) + return (0); + + return (val & 0xFFFF); +} + +static int +bge_miibus_writereg(device_t dev, int phy, int reg, int val) +{ + struct bge_softc *sc; + int i; + + sc = device_get_softc(dev); + + if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && + (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) + return (0); + + /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ + if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { + CSR_WRITE_4(sc, BGE_MI_MODE, + sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); + DELAY(80); + } + + CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | + BGE_MIPHY(phy) | BGE_MIREG(reg) | val); + + for (i = 0; i < BGE_TIMEOUT; i++) { + DELAY(10); + if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { + DELAY(5); + CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */ + break; + } + } + + /* Restore the autopoll bit if necessary. */ + if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { + CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); + DELAY(80); + } + + if (i == BGE_TIMEOUT) + device_printf(sc->bge_dev, + "PHY write timed out (phy %d, reg %d, val %d)\n", + phy, reg, val); + + return (0); +} + +static void +bge_miibus_statchg(device_t dev) +{ + struct bge_softc *sc; + struct mii_data *mii; + sc = device_get_softc(dev); + mii = device_get_softc(sc->bge_miibus); + + if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == + (IFM_ACTIVE | IFM_AVALID)) { + switch (IFM_SUBTYPE(mii->mii_media_active)) { + case IFM_10_T: + case IFM_100_TX: + sc->bge_link = 1; + break; + case IFM_1000_T: + case IFM_1000_SX: + case IFM_2500_SX: + if (sc->bge_asicrev != BGE_ASICREV_BCM5906) + sc->bge_link = 1; + else + sc->bge_link = 0; + break; + default: + sc->bge_link = 0; + break; + } + } else + sc->bge_link = 0; + if (sc->bge_link == 0) + return; + BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); + if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || + IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) + BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); + else + BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); + + if (IFM_OPTIONS(mii->mii_media_active & IFM_FDX) != 0) { + BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); + if ((IFM_OPTIONS(mii->mii_media_active) & + IFM_ETH_TXPAUSE) != 0) + BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); + else + BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); + if ((IFM_OPTIONS(mii->mii_media_active) & + IFM_ETH_RXPAUSE) != 0) + BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); + else + BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); + } else { + BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); + BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); + BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); + } +} + +/* + * Intialize a standard receive ring descriptor. + */ +static int +bge_newbuf_std(struct bge_softc *sc, int i) +{ + struct mbuf *m; + struct bge_rx_bd *r; + bus_dma_segment_t segs[1]; + bus_dmamap_t map; + int error, nsegs; + + m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + if (m == NULL) + return (ENOBUFS); + m->m_len = m->m_pkthdr.len = MCLBYTES; + if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) + m_adj(m, ETHER_ALIGN); + + error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag, + sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0); + if (error != 0) { + m_freem(m); + return (error); + } + if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { + bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, + sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, + sc->bge_cdata.bge_rx_std_dmamap[i]); + } + map = sc->bge_cdata.bge_rx_std_dmamap[i]; + sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap; + sc->bge_cdata.bge_rx_std_sparemap = map; + sc->bge_cdata.bge_rx_std_chain[i] = m; + sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len; + r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; + r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); + r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); + r->bge_flags = BGE_RXBDFLAG_END; + r->bge_len = segs[0].ds_len; + r->bge_idx = i; + + bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, + sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD); + + return (0); +} + +/* + * Initialize a jumbo receive ring descriptor. This allocates + * a jumbo buffer from the pool managed internally by the driver. + */ +static int +bge_newbuf_jumbo(struct bge_softc *sc, int i) +{ + bus_dma_segment_t segs[BGE_NSEG_JUMBO]; + bus_dmamap_t map; + struct bge_extrx_bd *r; + struct mbuf *m; + int error, nsegs; + + MGETHDR(m, M_DONTWAIT, MT_DATA); + if (m == NULL) + return (ENOBUFS); + + m_cljget(m, M_DONTWAIT, MJUM9BYTES); + if (!(m->m_flags & M_EXT)) { + m_freem(m); + return (ENOBUFS); + } + m->m_len = m->m_pkthdr.len = MJUM9BYTES; + if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) + m_adj(m, ETHER_ALIGN); + + error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo, + sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0); + if (error != 0) { + m_freem(m); + return (error); + } + + if (sc->bge_cdata.bge_rx_jumbo_chain[i] == NULL) { + bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, + sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, + sc->bge_cdata.bge_rx_jumbo_dmamap[i]); + } + map = sc->bge_cdata.bge_rx_jumbo_dmamap[i]; + sc->bge_cdata.bge_rx_jumbo_dmamap[i] = + sc->bge_cdata.bge_rx_jumbo_sparemap; + sc->bge_cdata.bge_rx_jumbo_sparemap = map; + sc->bge_cdata.bge_rx_jumbo_chain[i] = m; + sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0; + sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0; + sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0; + sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0; + + /* + * Fill in the extended RX buffer descriptor. + */ + r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; + r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; + r->bge_idx = i; + r->bge_len3 = r->bge_len2 = r->bge_len1 = 0; + switch (nsegs) { + case 4: + r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr); + r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr); + r->bge_len3 = segs[3].ds_len; + sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len; + case 3: + r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr); + r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr); + r->bge_len2 = segs[2].ds_len; + sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len; + case 2: + r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr); + r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr); + r->bge_len1 = segs[1].ds_len; + sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len; + case 1: + r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); + r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); + r->bge_len0 = segs[0].ds_len; + sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len; + break; + default: + panic("%s: %d segments\n", __func__, nsegs); + } + + bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, + sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD); + + return (0); +} + +static int +bge_init_rx_ring_std(struct bge_softc *sc) +{ + int error, i; + + bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); + sc->bge_std = 0; + for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { + if ((error = bge_newbuf_std(sc, i)) != 0) + return (error); + BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); + } + + bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, + sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); + + sc->bge_std = 0; + bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1); + + return (0); +} + +static void +bge_free_rx_ring_std(struct bge_softc *sc) +{ + int i; + + for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { + if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { + bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, + sc->bge_cdata.bge_rx_std_dmamap[i], + BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, + sc->bge_cdata.bge_rx_std_dmamap[i]); + m_freem(sc->bge_cdata.bge_rx_std_chain[i]); + sc->bge_cdata.bge_rx_std_chain[i] = NULL; + } + bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], + sizeof(struct bge_rx_bd)); + } +} + +static int +bge_init_rx_ring_jumbo(struct bge_softc *sc) +{ + struct bge_rcb *rcb; + int error, i; + + bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ); + sc->bge_jumbo = 0; + for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { + if ((error = bge_newbuf_jumbo(sc, i)) != 0) + return (error); + BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); + } + + bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, + sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); + + sc->bge_jumbo = 0; + + /* Enable the jumbo receive producer ring. */ + rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; + rcb->bge_maxlen_flags = + BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD); + CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); + + bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1); + + return (0); +} + +static void +bge_free_rx_ring_jumbo(struct bge_softc *sc) +{ + int i; + + for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { + if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { + bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, + sc->bge_cdata.bge_rx_jumbo_dmamap[i], + BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, + sc->bge_cdata.bge_rx_jumbo_dmamap[i]); + m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); + sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; + } + bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], + sizeof(struct bge_extrx_bd)); + } +} + +static void +bge_free_tx_ring(struct bge_softc *sc) +{ + int i; + + if (sc->bge_ldata.bge_tx_ring == NULL) + return; + + for (i = 0; i < BGE_TX_RING_CNT; i++) { + if (sc->bge_cdata.bge_tx_chain[i] != NULL) { + bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, + sc->bge_cdata.bge_tx_dmamap[i], + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, + sc->bge_cdata.bge_tx_dmamap[i]); + m_freem(sc->bge_cdata.bge_tx_chain[i]); + sc->bge_cdata.bge_tx_chain[i] = NULL; + } + bzero((char *)&sc->bge_ldata.bge_tx_ring[i], + sizeof(struct bge_tx_bd)); + } +} + +static int +bge_init_tx_ring(struct bge_softc *sc) +{ + sc->bge_txcnt = 0; + sc->bge_tx_saved_considx = 0; + + bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); + bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, + sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); + + /* Initialize transmit producer index for host-memory send ring. */ + sc->bge_tx_prodidx = 0; + bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); + + /* 5700 b2 errata */ + if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) + bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); + + /* NIC-memory send ring not used; initialize to zero. */ + bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); + /* 5700 b2 errata */ + if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) + bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); + + return (0); +} + +static void +bge_setpromisc(struct bge_softc *sc) +{ + struct ifnet *ifp; + + BGE_LOCK_ASSERT(sc); + + ifp = sc->bge_ifp; + + /* Enable or disable promiscuous mode as needed. */ + if (ifp->if_flags & IFF_PROMISC) + BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); + else + BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); +} + +static void +bge_setmulti(struct bge_softc *sc) +{ + struct ifnet *ifp; + struct ifmultiaddr *ifma; + uint32_t hashes[4] = { 0, 0, 0, 0 }; + int h, i; + + BGE_LOCK_ASSERT(sc); + + ifp = sc->bge_ifp; + + if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { + for (i = 0; i < 4; i++) + CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); + return; + } + + /* First, zot all the existing filters. */ + for (i = 0; i < 4; i++) + CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); + + /* Now program new ones. */ + if_maddr_rlock(ifp); + TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { + if (ifma->ifma_addr->sa_family != AF_LINK) + continue; + h = ether_crc32_le(LLADDR((struct sockaddr_dl *) + ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F; + hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); + } + if_maddr_runlock(ifp); + + for (i = 0; i < 4; i++) + CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); +} + +static void +bge_setvlan(struct bge_softc *sc) +{ + struct ifnet *ifp; + + BGE_LOCK_ASSERT(sc); + + ifp = sc->bge_ifp; + + /* Enable or disable VLAN tag stripping as needed. */ + if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) + BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); + else + BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); +} + +static void +bge_sig_pre_reset(struct bge_softc *sc, int type) +{ + + /* + * Some chips don't like this so only do this if ASF is enabled + */ + if (sc->bge_asf_mode) + bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); + + if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { + switch (type) { + case BGE_RESET_START: + bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ + break; + case BGE_RESET_STOP: + bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ + break; + } + } +} + +static void +bge_sig_post_reset(struct bge_softc *sc, int type) +{ + + if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { + switch (type) { + case BGE_RESET_START: + bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001); + /* START DONE */ + break; + case BGE_RESET_STOP: + bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002); + break; + } + } +} + +static void +bge_sig_legacy(struct bge_softc *sc, int type) +{ + + if (sc->bge_asf_mode) { + switch (type) { + case BGE_RESET_START: + bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ + break; + case BGE_RESET_STOP: + bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ + break; + } + } +} + +static void +bge_stop_fw(struct bge_softc *sc) +{ + int i; + + if (sc->bge_asf_mode) { + bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE); + CSR_WRITE_4(sc, BGE_CPU_EVENT, + CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); + + for (i = 0; i < 100; i++ ) { + if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14))) + break; + DELAY(10); + } + } +} + +/* + * Do endian, PCI and DMA initialization. + */ +static int +bge_chipinit(struct bge_softc *sc) +{ + uint32_t dma_rw_ctl, misc_ctl; + uint16_t val; + int i; + + /* Set endianness before we access any non-PCI registers. */ + misc_ctl = BGE_INIT; + if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS) + misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; + pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4); + + /* Clear the MAC control register */ + CSR_WRITE_4(sc, BGE_MAC_MODE, 0); + + /* + * Clear the MAC statistics block in the NIC's + * internal memory. + */ + for (i = BGE_STATS_BLOCK; + i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) + BGE_MEMWIN_WRITE(sc, i, 0); + + for (i = BGE_STATUS_BLOCK; + i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) + BGE_MEMWIN_WRITE(sc, i, 0); + + if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) { + /* + * Fix data corruption caused by non-qword write with WB. + * Fix master abort in PCI mode. + * Fix PCI latency timer. + */ + val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2); + val |= (1 << 10) | (1 << 12) | (1 << 13); + pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2); + } + + /* + * Set up the PCI DMA control register. + */ + dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) | + BGE_PCIDMARWCTL_WR_CMD_SHIFT(7); + if (sc->bge_flags & BGE_FLAG_PCIE) { + /* Read watermark not used, 128 bytes for write. */ + dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); + } else if (sc->bge_flags & BGE_FLAG_PCIX) { + if (BGE_IS_5714_FAMILY(sc)) { + /* 256 bytes for read and write. */ + dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | + BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); + dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ? + BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL : + BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; + } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { + /* + * In the BCM5703, the DMA read watermark should + * be set to less than or equal to the maximum + * memory read byte count of the PCI-X command + * register. + */ + dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | + BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); + } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { + /* 1536 bytes for read, 384 bytes for write. */ + dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | + BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); + } else { + /* 384 bytes for read and write. */ + dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | + BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | + 0x0F; + } + if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || + sc->bge_asicrev == BGE_ASICREV_BCM5704) { + uint32_t tmp; + + /* Set ONE_DMA_AT_ONCE for hardware workaround. */ + tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; + if (tmp == 6 || tmp == 7) + dma_rw_ctl |= + BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; + + /* Set PCI-X DMA write workaround. */ + dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; + } + } else { + /* Conventional PCI bus: 256 bytes for read and write. */ + dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | + BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); + + if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && + sc->bge_asicrev != BGE_ASICREV_BCM5750) + dma_rw_ctl |= 0x0F; + } + if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || + sc->bge_asicrev == BGE_ASICREV_BCM5701) + dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | + BGE_PCIDMARWCTL_ASRT_ALL_BE; + if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || + sc->bge_asicrev == BGE_ASICREV_BCM5704) + dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; + if (BGE_IS_5717_PLUS(sc)) + dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; + pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); + + /* + * Set up general mode register. + */ + CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | + BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | + BGE_MODECTL_TX_NO_PHDR_CSUM); + + /* + * BCM5701 B5 have a bug causing data corruption when using + * 64-bit DMA reads, which can be terminated early and then + * completed later as 32-bit accesses, in combination with + * certain bridges. + */ + if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && + sc->bge_chipid == BGE_CHIPID_BCM5701_B5) + BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32); + + /* + * Tell the firmware the driver is running + */ + if (sc->bge_asf_mode & ASF_STACKUP) + BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); + + /* + * Disable memory write invalidate. Apparently it is not supported + * properly by these devices. Also ensure that INTx isn't disabled, + * as these chips need it even when using MSI. + */ + PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, + PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4); + + /* Set the timer prescaler (always 66Mhz) */ + CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); + + /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */ + if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { + DELAY(40); /* XXX */ + + /* Put PHY into ready state */ + BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); + CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ + DELAY(40); + } + + return (0); +} + +static int +bge_blockinit(struct bge_softc *sc) +{ + struct bge_rcb *rcb; + bus_size_t vrcb; + bge_hostaddr taddr; + uint32_t val; + int i, limit; + + /* + * Initialize the memory window pointer register so that + * we can access the first 32K of internal NIC RAM. This will + * allow us to set up the TX send ring RCBs and the RX return + * ring RCBs, plus other things which live in NIC memory. + */ + CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); + + /* Note: the BCM5704 has a smaller mbuf space than other chips. */ + + if (!(BGE_IS_5705_PLUS(sc))) { + /* Configure mbuf memory pool */ + CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); + if (sc->bge_asicrev == BGE_ASICREV_BCM5704) + CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); + else + CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); + + /* Configure DMA resource pool */ + CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, + BGE_DMA_DESCRIPTORS); + CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); + } + + /* Configure mbuf pool watermarks */ + if (sc->bge_asicrev == BGE_ASICREV_BCM5717) { + CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); + if (sc->bge_ifp->if_mtu > ETHERMTU) { + CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e); + CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea); + } else { + CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); + CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); + } + } else if (!BGE_IS_5705_PLUS(sc)) { + CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); + CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); + CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); + } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { + CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); + CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); + CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); + } else { + CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); + CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); + CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); + } + + /* Configure DMA resource watermarks */ + CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); + CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); + + /* Enable buffer manager */ + if (!(BGE_IS_5705_PLUS(sc))) { + CSR_WRITE_4(sc, BGE_BMAN_MODE, + BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN); + + /* Poll for buffer manager start indication */ + for (i = 0; i < BGE_TIMEOUT; i++) { + DELAY(10); + if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) + break; + } + + if (i == BGE_TIMEOUT) { + device_printf(sc->bge_dev, + "buffer manager failed to start\n"); + return (ENXIO); + } + } + + /* Enable flow-through queues */ + CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); + CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); + + /* Wait until queue initialization is complete */ + for (i = 0; i < BGE_TIMEOUT; i++) { + DELAY(10); + if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) + break; + } + + if (i == BGE_TIMEOUT) { + device_printf(sc->bge_dev, "flow-through queue init failed\n"); + return (ENXIO); + } + + /* + * Summary of rings supported by the controller: + * + * Standard Receive Producer Ring + * - This ring is used to feed receive buffers for "standard" + * sized frames (typically 1536 bytes) to the controller. + * + * Jumbo Receive Producer Ring + * - This ring is used to feed receive buffers for jumbo sized + * frames (i.e. anything bigger than the "standard" frames) + * to the controller. + * + * Mini Receive Producer Ring + * - This ring is used to feed receive buffers for "mini" + * sized frames to the controller. + * - This feature required external memory for the controller + * but was never used in a production system. Should always + * be disabled. + * + * Receive Return Ring + * - After the controller has placed an incoming frame into a + * receive buffer that buffer is moved into a receive return + * ring. The driver is then responsible to passing the + * buffer up to the stack. Many versions of the controller + * support multiple RR rings. + * + * Send Ring + * - This ring is used for outgoing frames. Many versions of + * the controller support multiple send rings. + */ + + /* Initialize the standard receive producer ring control block. */ + rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; + rcb->bge_hostaddr.bge_addr_lo = + BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); + rcb->bge_hostaddr.bge_addr_hi = + BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); + bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, + sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); + if (BGE_IS_5717_PLUS(sc)) { + /* + * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) + * Bits 15-2 : Maximum RX frame size + * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled + * Bit 0 : Reserved + */ + rcb->bge_maxlen_flags = + BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); + } else if (BGE_IS_5705_PLUS(sc)) { + /* + * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) + * Bits 15-2 : Reserved (should be 0) + * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled + * Bit 0 : Reserved + */ + rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); + } else { + /* + * Ring size is always XXX entries + * Bits 31-16: Maximum RX frame size + * Bits 15-2 : Reserved (should be 0) + * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled + * Bit 0 : Reserved + */ + rcb->bge_maxlen_flags = + BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); + } + if (sc->bge_asicrev == BGE_ASICREV_BCM5717) + rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; + else + rcb->bge_nicaddr = BGE_STD_RX_RINGS; + /* Write the standard receive producer ring control block. */ + CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); + CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); + CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); + CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); + + /* Reset the standard receive producer ring producer index. */ + bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); + + /* + * Initialize the jumbo RX producer ring control + * block. We set the 'ring disabled' bit in the + * flags field until we're actually ready to start + * using this ring (i.e. once we set the MTU + * high enough to require it). + */ + if (BGE_IS_JUMBO_CAPABLE(sc)) { + rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; + /* Get the jumbo receive producer ring RCB parameters. */ + rcb->bge_hostaddr.bge_addr_lo = + BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); + rcb->bge_hostaddr.bge_addr_hi = + BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); + bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, + sc->bge_cdata.bge_rx_jumbo_ring_map, + BUS_DMASYNC_PREREAD); + rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, + BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); + if (sc->bge_asicrev == BGE_ASICREV_BCM5717) + rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; + else + rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; + CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, + rcb->bge_hostaddr.bge_addr_hi); + CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, + rcb->bge_hostaddr.bge_addr_lo); + /* Program the jumbo receive producer ring RCB parameters. */ + CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, + rcb->bge_maxlen_flags); + CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); + /* Reset the jumbo receive producer ring producer index. */ + bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); + } + + /* Disable the mini receive producer ring RCB. */ + if (BGE_IS_5700_FAMILY(sc)) { + rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; + rcb->bge_maxlen_flags = + BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); + CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, + rcb->bge_maxlen_flags); + /* Reset the mini receive producer ring producer index. */ + bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); + } + + /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ + if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { + if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || + sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || + sc->bge_chipid == BGE_CHIPID_BCM5906_A2) + CSR_WRITE_4(sc, BGE_ISO_PKT_TX, + (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); + } + /* + * The BD ring replenish thresholds control how often the + * hardware fetches new BD's from the producer rings in host + * memory. Setting the value too low on a busy system can + * starve the hardware and recue the throughpout. + * + * Set the BD ring replentish thresholds. The recommended + * values are 1/8th the number of descriptors allocated to + * each ring. + * XXX The 5754 requires a lower threshold, so it might be a + * requirement of all 575x family chips. The Linux driver sets + * the lower threshold for all 5705 family chips as well, but there + * are reports that it might not need to be so strict. + * + * XXX Linux does some extra fiddling here for the 5906 parts as + * well. + */ + if (BGE_IS_5705_PLUS(sc)) + val = 8; + else + val = BGE_STD_RX_RING_CNT / 8; + CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val); + if (BGE_IS_JUMBO_CAPABLE(sc)) + CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, + BGE_JUMBO_RX_RING_CNT/8); + if (BGE_IS_5717_PLUS(sc)) { + CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32); + CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16); + } + + /* + * Disable all send rings by setting the 'ring disabled' bit + * in the flags field of all the TX send ring control blocks, + * located in NIC memory. + */ + if (!BGE_IS_5705_PLUS(sc)) + /* 5700 to 5704 had 16 send rings. */ + limit = BGE_TX_RINGS_EXTSSRAM_MAX; + else + limit = 1; + vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; + for (i = 0; i < limit; i++) { + RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, + BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); + RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); + vrcb += sizeof(struct bge_rcb); + } + + /* Configure send ring RCB 0 (we use only the first ring) */ + vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; + BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr); + RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); + RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); + if (sc->bge_asicrev == BGE_ASICREV_BCM5717) + RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717); + else + RCB_WRITE_4(sc, vrcb, bge_nicaddr, + BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); + RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, + BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); + + /* + * Disable all receive return rings by setting the + * 'ring diabled' bit in the flags field of all the receive + * return ring control blocks, located in NIC memory. + */ + if (sc->bge_asicrev == BGE_ASICREV_BCM5717) { + /* Should be 17, use 16 until we get an SRAM map. */ + limit = 16; + } else if (!BGE_IS_5705_PLUS(sc)) + limit = BGE_RX_RINGS_MAX; + else if (sc->bge_asicrev == BGE_ASICREV_BCM5755) + limit = 4; + else + limit = 1; + /* Disable all receive return rings. */ + vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; + for (i = 0; i < limit; i++) { + RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); + RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); + RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, + BGE_RCB_FLAG_RING_DISABLED); + RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); + bge_writembx(sc, BGE_MBX_RX_CONS0_LO + + (i * (sizeof(uint64_t))), 0); + vrcb += sizeof(struct bge_rcb); + } + + /* + * Set up receive return ring 0. Note that the NIC address + * for RX return rings is 0x0. The return rings live entirely + * within the host, so the nicaddr field in the RCB isn't used. + */ + vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; + BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr); + RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); + RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); + RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); + RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, + BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); + + /* Set random backoff seed for TX */ + CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, + IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] + + IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] + + IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] + + BGE_TX_BACKOFF_SEED_MASK); + + /* Set inter-packet gap */ + CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); + + /* + * Specify which ring to use for packets that don't match + * any RX rules. + */ + CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); + + /* + * Configure number of RX lists. One interrupt distribution + * list, sixteen active lists, one bad frames class. + */ + CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); + + /* Inialize RX list placement stats mask. */ + CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); + CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); + + /* Disable host coalescing until we get it set up */ + CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); + + /* Poll to make sure it's shut down. */ + for (i = 0; i < BGE_TIMEOUT; i++) { + DELAY(10); + if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) + break; + } + + if (i == BGE_TIMEOUT) { + device_printf(sc->bge_dev, + "host coalescing engine failed to idle\n"); + return (ENXIO); + } + + /* Set up host coalescing defaults */ + CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); + CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); + CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); + CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); + if (!(BGE_IS_5705_PLUS(sc))) { + CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); + CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); + } + CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1); + CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1); + + /* Set up address of statistics block */ + if (!(BGE_IS_5705_PLUS(sc))) { + CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, + BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); + CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, + BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); + CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); + CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); + CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); + } + + /* Set up address of status block */ + CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, + BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); + CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, + BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); + + /* Set up status block size. */ + if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && + sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { + val = BGE_STATBLKSZ_FULL; + bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); + } else { + val = BGE_STATBLKSZ_32BYTE; + bzero(sc->bge_ldata.bge_status_block, 32); + } + bus_dmamap_sync(sc->bge_cdata.bge_status_tag, + sc->bge_cdata.bge_status_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + + /* Turn on host coalescing state machine */ + CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); + + /* Turn on RX BD completion state machine and enable attentions */ + CSR_WRITE_4(sc, BGE_RBDC_MODE, + BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); + + /* Turn on RX list placement state machine */ + CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); + + /* Turn on RX list selector state machine. */ + if (!(BGE_IS_5705_PLUS(sc))) + CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); + + val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | + BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | + BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | + BGE_MACMODE_FRMHDR_DMA_ENB; + + if (sc->bge_flags & BGE_FLAG_TBI) + val |= BGE_PORTMODE_TBI; + else if (sc->bge_flags & BGE_FLAG_MII_SERDES) + val |= BGE_PORTMODE_GMII; + else + val |= BGE_PORTMODE_MII; + + /* Turn on DMA, clear stats */ + CSR_WRITE_4(sc, BGE_MAC_MODE, val); + + /* Set misc. local control, enable interrupts on attentions */ + CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); + +#ifdef notdef + /* Assert GPIO pins for PHY reset */ + BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 | + BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2); + BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 | + BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2); +#endif + + /* Turn on DMA completion state machine */ + if (!(BGE_IS_5705_PLUS(sc))) + CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); + + val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; + + /* Enable host coalescing bug fix. */ + if (BGE_IS_5755_PLUS(sc)) + val |= BGE_WDMAMODE_STATUS_TAG_FIX; + + /* Request larger DMA burst size to get better performance. */ + if (sc->bge_asicrev == BGE_ASICREV_BCM5785) + val |= BGE_WDMAMODE_BURST_ALL_DATA; + + /* Turn on write DMA state machine */ + CSR_WRITE_4(sc, BGE_WDMA_MODE, val); + DELAY(40); + + /* Turn on read DMA state machine */ + val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; + + if (sc->bge_asicrev == BGE_ASICREV_BCM5717) + val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; + + if (sc->bge_asicrev == BGE_ASICREV_BCM5784 || + sc->bge_asicrev == BGE_ASICREV_BCM5785 || + sc->bge_asicrev == BGE_ASICREV_BCM57780) + val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | + BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | + BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; + if (sc->bge_flags & BGE_FLAG_PCIE) + val |= BGE_RDMAMODE_FIFO_LONG_BURST; + if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) { + val |= BGE_RDMAMODE_TSO4_ENABLE; + if (sc->bge_flags & BGE_FLAG_TSO3 || + sc->bge_asicrev == BGE_ASICREV_BCM5785 || + sc->bge_asicrev == BGE_ASICREV_BCM57780) + val |= BGE_RDMAMODE_TSO6_ENABLE; + } + if (sc->bge_asicrev == BGE_ASICREV_BCM5761 || + sc->bge_asicrev == BGE_ASICREV_BCM5784 || + sc->bge_asicrev == BGE_ASICREV_BCM5785 || + sc->bge_asicrev == BGE_ASICREV_BCM57780 || + BGE_IS_5717_PLUS(sc)) { + /* + * Enable fix for read DMA FIFO overruns. + * The fix is to limit the number of RX BDs + * the hardware would fetch at a fime. + */ + CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, + CSR_READ_4(sc, BGE_RDMA_RSRVCTRL) | + BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); + } + CSR_WRITE_4(sc, BGE_RDMA_MODE, val); + DELAY(40); + + /* Turn on RX data completion state machine */ + CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); + + /* Turn on RX BD initiator state machine */ + CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); + + /* Turn on RX data and RX BD initiator state machine */ + CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); + + /* Turn on Mbuf cluster free state machine */ + if (!(BGE_IS_5705_PLUS(sc))) + CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); + + /* Turn on send BD completion state machine */ + CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); + + /* Turn on send data completion state machine */ + val = BGE_SDCMODE_ENABLE; + if (sc->bge_asicrev == BGE_ASICREV_BCM5761) + val |= BGE_SDCMODE_CDELAY; + CSR_WRITE_4(sc, BGE_SDC_MODE, val); + + /* Turn on send data initiator state machine */ + if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) + CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | + BGE_SDIMODE_HW_LSO_PRE_DMA); + else + CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); + + /* Turn on send BD initiator state machine */ + CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); + + /* Turn on send BD selector state machine */ + CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); + + CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); + CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, + BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); + + /* ack/clear link change events */ + CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | + BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | + BGE_MACSTAT_LINK_CHANGED); + CSR_WRITE_4(sc, BGE_MI_STS, 0); + + /* + * Enable attention when the link has changed state for + * devices that use auto polling. + */ + if (sc->bge_flags & BGE_FLAG_TBI) { + CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); + } else { + if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { + CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); + DELAY(80); + } + if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && + sc->bge_chipid != BGE_CHIPID_BCM5700_B2) + CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, + BGE_EVTENB_MI_INTERRUPT); + } + + /* + * Clear any pending link state attention. + * Otherwise some link state change events may be lost until attention + * is cleared by bge_intr() -> bge_link_upd() sequence. + * It's not necessary on newer BCM chips - perhaps enabling link + * state change attentions implies clearing pending attention. + */ + CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | + BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | + BGE_MACSTAT_LINK_CHANGED); + + /* Enable link state change attentions. */ + BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); + + return (0); +} + +const struct bge_revision * +bge_lookup_rev(uint32_t chipid) +{ + const struct bge_revision *br; + + for (br = bge_revisions; br->br_name != NULL; br++) { + if (br->br_chipid == chipid) + return (br); + } + + for (br = bge_majorrevs; br->br_name != NULL; br++) { + if (br->br_chipid == BGE_ASICREV(chipid)) + return (br); + } + + return (NULL); +} + +const struct bge_vendor * +bge_lookup_vendor(uint16_t vid) +{ + const struct bge_vendor *v; + + for (v = bge_vendors; v->v_name != NULL; v++) + if (v->v_id == vid) + return (v); + + panic("%s: unknown vendor %d", __func__, vid); + return (NULL); +} + +/* + * Probe for a Broadcom chip. Check the PCI vendor and device IDs + * against our list and return its name if we find a match. + * + * Note that since the Broadcom controller contains VPD support, we + * try to get the device name string from the controller itself instead + * of the compiled-in string. It guarantees we'll always announce the + * right product name. We fall back to the compiled-in string when + * VPD is unavailable or corrupt. + */ +static int +bge_probe(device_t dev) +{ + const struct bge_type *t = bge_devs; + struct bge_softc *sc = device_get_softc(dev); + uint16_t vid, did; + + sc->bge_dev = dev; + vid = pci_get_vendor(dev); + did = pci_get_device(dev); + while(t->bge_vid != 0) { + if ((vid == t->bge_vid) && (did == t->bge_did)) { + char model[64], buf[96]; + const struct bge_revision *br; + const struct bge_vendor *v; + uint32_t id; + + id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> + BGE_PCIMISCCTL_ASICREV_SHIFT; + if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { + /* + * Find the ASCI revision. Different chips + * use different registers. + */ + switch (pci_get_device(dev)) { + case BCOM_DEVICEID_BCM5717: + case BCOM_DEVICEID_BCM5718: + id = pci_read_config(dev, + BGE_PCI_GEN2_PRODID_ASICREV, 4); + break; + default: + id = pci_read_config(dev, + BGE_PCI_PRODID_ASICREV, 4); + } + } + br = bge_lookup_rev(id); + v = bge_lookup_vendor(vid); + { +#if __FreeBSD_version > 700024 + const char *pname; + + if (bge_has_eaddr(sc) && + pci_get_vpd_ident(dev, &pname) == 0) + snprintf(model, 64, "%s", pname); + else +#endif + snprintf(model, 64, "%s %s", + v->v_name, + br != NULL ? br->br_name : + "NetXtreme Ethernet Controller"); + } + snprintf(buf, 96, "%s, %sASIC rev. %#08x", model, + br != NULL ? "" : "unknown ", id); + device_set_desc_copy(dev, buf); + return (0); + } + t++; + } + + return (ENXIO); +} + +static void +bge_dma_free(struct bge_softc *sc) +{ + int i; + + /* Destroy DMA maps for RX buffers. */ + for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { + if (sc->bge_cdata.bge_rx_std_dmamap[i]) + bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, + sc->bge_cdata.bge_rx_std_dmamap[i]); + } + if (sc->bge_cdata.bge_rx_std_sparemap) + bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, + sc->bge_cdata.bge_rx_std_sparemap); + + /* Destroy DMA maps for jumbo RX buffers. */ + for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { + if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) + bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, + sc->bge_cdata.bge_rx_jumbo_dmamap[i]); + } + if (sc->bge_cdata.bge_rx_jumbo_sparemap) + bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, + sc->bge_cdata.bge_rx_jumbo_sparemap); + + /* Destroy DMA maps for TX buffers. */ + for (i = 0; i < BGE_TX_RING_CNT; i++) { + if (sc->bge_cdata.bge_tx_dmamap[i]) + bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag, + sc->bge_cdata.bge_tx_dmamap[i]); + } + + if (sc->bge_cdata.bge_rx_mtag) + bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag); + if (sc->bge_cdata.bge_tx_mtag) + bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag); + + + /* Destroy standard RX ring. */ + if (sc->bge_cdata.bge_rx_std_ring_map) + bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, + sc->bge_cdata.bge_rx_std_ring_map); + if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring) + bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, + sc->bge_ldata.bge_rx_std_ring, + sc->bge_cdata.bge_rx_std_ring_map); + + if (sc->bge_cdata.bge_rx_std_ring_tag) + bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); + + /* Destroy jumbo RX ring. */ + if (sc->bge_cdata.bge_rx_jumbo_ring_map) + bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, + sc->bge_cdata.bge_rx_jumbo_ring_map); + + if (sc->bge_cdata.bge_rx_jumbo_ring_map && + sc->bge_ldata.bge_rx_jumbo_ring) + bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, + sc->bge_ldata.bge_rx_jumbo_ring, + sc->bge_cdata.bge_rx_jumbo_ring_map); + + if (sc->bge_cdata.bge_rx_jumbo_ring_tag) + bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); + + /* Destroy RX return ring. */ + if (sc->bge_cdata.bge_rx_return_ring_map) + bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, + sc->bge_cdata.bge_rx_return_ring_map); + + if (sc->bge_cdata.bge_rx_return_ring_map && + sc->bge_ldata.bge_rx_return_ring) + bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, + sc->bge_ldata.bge_rx_return_ring, + sc->bge_cdata.bge_rx_return_ring_map); + + if (sc->bge_cdata.bge_rx_return_ring_tag) + bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); + + /* Destroy TX ring. */ + if (sc->bge_cdata.bge_tx_ring_map) + bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, + sc->bge_cdata.bge_tx_ring_map); + + if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring) + bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, + sc->bge_ldata.bge_tx_ring, + sc->bge_cdata.bge_tx_ring_map); + + if (sc->bge_cdata.bge_tx_ring_tag) + bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); + + /* Destroy status block. */ + if (sc->bge_cdata.bge_status_map) + bus_dmamap_unload(sc->bge_cdata.bge_status_tag, + sc->bge_cdata.bge_status_map); + + if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block) + bus_dmamem_free(sc->bge_cdata.bge_status_tag, + sc->bge_ldata.bge_status_block, + sc->bge_cdata.bge_status_map); + + if (sc->bge_cdata.bge_status_tag) + bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); + + /* Destroy statistics block. */ + if (sc->bge_cdata.bge_stats_map) + bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, + sc->bge_cdata.bge_stats_map); + + if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats) + bus_dmamem_free(sc->bge_cdata.bge_stats_tag, + sc->bge_ldata.bge_stats, + sc->bge_cdata.bge_stats_map); + + if (sc->bge_cdata.bge_stats_tag) + bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); + + if (sc->bge_cdata.bge_buffer_tag) + bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag); + + /* Destroy the parent tag. */ + if (sc->bge_cdata.bge_parent_tag) + bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); +} + +static int +bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment, + bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, + bus_addr_t *paddr, const char *msg) +{ + struct bge_dmamap_arg ctx; + bus_addr_t lowaddr; + bus_size_t ring_end; + int error; + + lowaddr = BUS_SPACE_MAXADDR; +again: + error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, + alignment, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, + NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag); + if (error != 0) { + device_printf(sc->bge_dev, + "could not create %s dma tag\n", msg); + return (ENOMEM); + } + /* Allocate DMA'able memory for ring. */ + error = bus_dmamem_alloc(*tag, (void **)ring, + BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); + if (error != 0) { + device_printf(sc->bge_dev, + "could not allocate DMA'able memory for %s\n", msg); + return (ENOMEM); + } + /* Load the address of the ring. */ + ctx.bge_busaddr = 0; + error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr, + &ctx, BUS_DMA_NOWAIT); + if (error != 0) { + device_printf(sc->bge_dev, + "could not load DMA'able memory for %s\n", msg); + return (ENOMEM); + } + *paddr = ctx.bge_busaddr; + ring_end = *paddr + maxsize; + if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0 && + BGE_ADDR_HI(*paddr) != BGE_ADDR_HI(ring_end)) { + /* + * 4GB boundary crossed. Limit maximum allowable DMA + * address space to 32bit and try again. + */ + bus_dmamap_unload(*tag, *map); + bus_dmamem_free(*tag, *ring, *map); + bus_dma_tag_destroy(*tag); + if (bootverbose) + device_printf(sc->bge_dev, "4GB boundary crossed, " + "limit DMA address space to 32bit for %s\n", msg); + *ring = NULL; + *tag = NULL; + *map = NULL; + lowaddr = BUS_SPACE_MAXADDR_32BIT; + goto again; + } + return (0); +} + +static int +bge_dma_alloc(struct bge_softc *sc) +{ + bus_addr_t lowaddr; + bus_size_t boundary, sbsz, txsegsz, txmaxsegsz; + int i, error; + + lowaddr = BUS_SPACE_MAXADDR; + if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0) + lowaddr = BGE_DMA_MAXADDR; + /* + * Allocate the parent bus DMA tag appropriate for PCI. + */ + error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), + 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, + NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, + 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag); + if (error != 0) { + device_printf(sc->bge_dev, + "could not allocate parent dma tag\n"); + return (ENOMEM); + } + + /* Create tag for standard RX ring. */ + error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ, + &sc->bge_cdata.bge_rx_std_ring_tag, + (uint8_t **)&sc->bge_ldata.bge_rx_std_ring, + &sc->bge_cdata.bge_rx_std_ring_map, + &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring"); + if (error) + return (error); + + /* Create tag for RX return ring. */ + error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc), + &sc->bge_cdata.bge_rx_return_ring_tag, + (uint8_t **)&sc->bge_ldata.bge_rx_return_ring, + &sc->bge_cdata.bge_rx_return_ring_map, + &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring"); + if (error) + return (error); + + /* Create tag for TX ring. */ + error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ, + &sc->bge_cdata.bge_tx_ring_tag, + (uint8_t **)&sc->bge_ldata.bge_tx_ring, + &sc->bge_cdata.bge_tx_ring_map, + &sc->bge_ldata.bge_tx_ring_paddr, "TX ring"); + if (error) + return (error); + + /* + * Create tag for status block. + * Because we only use single Tx/Rx/Rx return ring, use + * minimum status block size except BCM5700 AX/BX which + * seems to want to see full status block size regardless + * of configured number of ring. + */ + if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && + sc->bge_chipid != BGE_CHIPID_BCM5700_C0) + sbsz = BGE_STATUS_BLK_SZ; + else + sbsz = 32; + error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz, + &sc->bge_cdata.bge_status_tag, + (uint8_t **)&sc->bge_ldata.bge_status_block, + &sc->bge_cdata.bge_status_map, + &sc->bge_ldata.bge_status_block_paddr, "status block"); + if (error) + return (error); + + /* Create tag for statistics block. */ + error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ, + &sc->bge_cdata.bge_stats_tag, + (uint8_t **)&sc->bge_ldata.bge_stats, + &sc->bge_cdata.bge_stats_map, + &sc->bge_ldata.bge_stats_paddr, "statistics block"); + if (error) + return (error); + + /* Create tag for jumbo RX ring. */ + if (BGE_IS_JUMBO_CAPABLE(sc)) { + error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ, + &sc->bge_cdata.bge_rx_jumbo_ring_tag, + (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring, + &sc->bge_cdata.bge_rx_jumbo_ring_map, + &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring"); + if (error) + return (error); + } + + /* Create parent tag for buffers. */ + boundary = 0; + if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) { + boundary = BGE_DMA_BNDRY; + /* + * XXX + * watchdog timeout issue was observed on BCM5704 which + * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge). + * Limiting DMA address space to 32bits seems to address + * it. + */ + if (sc->bge_flags & BGE_FLAG_PCIX) + lowaddr = BUS_SPACE_MAXADDR_32BIT; + } + error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), + 1, boundary, lowaddr, BUS_SPACE_MAXADDR, NULL, + NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, + 0, NULL, NULL, &sc->bge_cdata.bge_buffer_tag); + if (error != 0) { + device_printf(sc->bge_dev, + "could not allocate buffer dma tag\n"); + return (ENOMEM); + } + /* Create tag for Tx mbufs. */ + if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) { + txsegsz = BGE_TSOSEG_SZ; + txmaxsegsz = 65535 + sizeof(struct ether_vlan_header); + } else { + txsegsz = MCLBYTES; + txmaxsegsz = MCLBYTES * BGE_NSEG_NEW; + } + error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, + 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, + txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL, + &sc->bge_cdata.bge_tx_mtag); + + if (error) { + device_printf(sc->bge_dev, "could not allocate TX dma tag\n"); + return (ENOMEM); + } + + /* Create tag for Rx mbufs. */ + error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0, + BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, + MCLBYTES, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag); + + if (error) { + device_printf(sc->bge_dev, "could not allocate RX dma tag\n"); + return (ENOMEM); + } + + /* Create DMA maps for RX buffers. */ + error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, + &sc->bge_cdata.bge_rx_std_sparemap); + if (error) { + device_printf(sc->bge_dev, + "can't create spare DMA map for RX\n"); + return (ENOMEM); + } + for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { + error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, + &sc->bge_cdata.bge_rx_std_dmamap[i]); + if (error) { + device_printf(sc->bge_dev, + "can't create DMA map for RX\n"); + return (ENOMEM); + } + } + + /* Create DMA maps for TX buffers. */ + for (i = 0; i < BGE_TX_RING_CNT; i++) { + error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0, + &sc->bge_cdata.bge_tx_dmamap[i]); + if (error) { + device_printf(sc->bge_dev, + "can't create DMA map for TX\n"); + return (ENOMEM); + } + } + + /* Create tags for jumbo RX buffers. */ + if (BGE_IS_JUMBO_CAPABLE(sc)) { + error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, + 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, + NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE, + 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo); + if (error) { + device_printf(sc->bge_dev, + "could not allocate jumbo dma tag\n"); + return (ENOMEM); + } + /* Create DMA maps for jumbo RX buffers. */ + error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, + 0, &sc->bge_cdata.bge_rx_jumbo_sparemap); + if (error) { + device_printf(sc->bge_dev, + "can't create spare DMA map for jumbo RX\n"); + return (ENOMEM); + } + for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { + error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, + 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); + if (error) { + device_printf(sc->bge_dev, + "can't create DMA map for jumbo RX\n"); + return (ENOMEM); + } + } + } + + return (0); +} + +/* + * Return true if this device has more than one port. + */ +static int +bge_has_multiple_ports(struct bge_softc *sc) +{ + device_t dev = sc->bge_dev; + u_int b, d, f, fscan, s; + + d = pci_get_domain(dev); + b = pci_get_bus(dev); + s = pci_get_slot(dev); + f = pci_get_function(dev); + for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++) + if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL) + return (1); + return (0); +} + +/* + * Return true if MSI can be used with this device. + */ +static int +bge_can_use_msi(struct bge_softc *sc) +{ + int can_use_msi = 0; + + /* Disable MSI for polling(4). */ +#ifdef DEVICE_POLLING + return (0); +#endif + switch (sc->bge_asicrev) { + case BGE_ASICREV_BCM5714_A0: + case BGE_ASICREV_BCM5714: + /* + * Apparently, MSI doesn't work when these chips are + * configured in single-port mode. + */ + if (bge_has_multiple_ports(sc)) + can_use_msi = 1; + break; + case BGE_ASICREV_BCM5750: + if (sc->bge_chiprev != BGE_CHIPREV_5750_AX && + sc->bge_chiprev != BGE_CHIPREV_5750_BX) + can_use_msi = 1; + break; + default: + if (BGE_IS_575X_PLUS(sc)) + can_use_msi = 1; + } + return (can_use_msi); +} + +static int +bge_attach(device_t dev) +{ + struct ifnet *ifp; + struct bge_softc *sc; + uint32_t hwcfg = 0, misccfg; + u_char eaddr[ETHER_ADDR_LEN]; + int capmask, error, f, msicount, phy_addr, reg, rid, trys; + + sc = device_get_softc(dev); + sc->bge_dev = dev; + + TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc); + + /* + * Map control/status registers. + */ + pci_enable_busmaster(dev); + + rid = PCIR_BAR(0); + sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, + RF_ACTIVE); + + if (sc->bge_res == NULL) { + device_printf (sc->bge_dev, "couldn't map memory\n"); + error = ENXIO; + goto fail; + } + + /* Save various chip information. */ + sc->bge_chipid = + pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> + BGE_PCIMISCCTL_ASICREV_SHIFT; + if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) { + /* + * Find the ASCI revision. Different chips use different + * registers. + */ + switch (pci_get_device(dev)) { + case BCOM_DEVICEID_BCM5717: + case BCOM_DEVICEID_BCM5718: + sc->bge_chipid = pci_read_config(dev, + BGE_PCI_GEN2_PRODID_ASICREV, 4); + break; + default: + sc->bge_chipid = pci_read_config(dev, + BGE_PCI_PRODID_ASICREV, 4); + } + } + sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); + sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); + + /* Set default PHY address. */ + phy_addr = 1; + /* + * PHY address mapping for various devices. + * + * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | + * ---------+-------+-------+-------+-------+ + * BCM57XX | 1 | X | X | X | + * BCM5704 | 1 | X | 1 | X | + * BCM5717 | 1 | 8 | 2 | 9 | + * + * Other addresses may respond but they are not + * IEEE compliant PHYs and should be ignored. + */ + if (sc->bge_asicrev == BGE_ASICREV_BCM5717) { + f = pci_get_function(dev); + if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { + if (CSR_READ_4(sc, BGE_SGDIG_STS) & + BGE_SGDIGSTS_IS_SERDES) + phy_addr = f + 8; + else + phy_addr = f + 1; + } else if (sc->bge_chipid == BGE_CHIPID_BCM5717_B0) { + if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & + BGE_CPMU_PHY_STRAP_IS_SERDES) + phy_addr = f + 8; + else + phy_addr = f + 1; + } + } + + /* + * Don't enable Ethernet@WireSpeed for the 5700, 5906, or the + * 5705 A0 and A1 chips. + */ + if (sc->bge_asicrev != BGE_ASICREV_BCM5700 && + sc->bge_asicrev != BGE_ASICREV_BCM5906 && + sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && + sc->bge_chipid != BGE_CHIPID_BCM5705_A1 && + !BGE_IS_5717_PLUS(sc)) + sc->bge_phy_flags |= BGE_PHY_WIRESPEED; + + if (bge_has_eaddr(sc)) + sc->bge_flags |= BGE_FLAG_EADDR; + + /* Save chipset family. */ + switch (sc->bge_asicrev) { + case BGE_ASICREV_BCM5717: + sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS | + BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO | + BGE_FLAG_SHORT_DMA_BUG | BGE_FLAG_JUMBO_FRAME; + break; + case BGE_ASICREV_BCM5755: + case BGE_ASICREV_BCM5761: + case BGE_ASICREV_BCM5784: + case BGE_ASICREV_BCM5785: + case BGE_ASICREV_BCM5787: + case BGE_ASICREV_BCM57780: + sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS | + BGE_FLAG_5705_PLUS; + break; + case BGE_ASICREV_BCM5700: + case BGE_ASICREV_BCM5701: + case BGE_ASICREV_BCM5703: + case BGE_ASICREV_BCM5704: + sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO; + break; + case BGE_ASICREV_BCM5714_A0: + case BGE_ASICREV_BCM5780: + case BGE_ASICREV_BCM5714: + sc->bge_flags |= BGE_FLAG_5714_FAMILY /* | BGE_FLAG_JUMBO */; + /* FALLTHROUGH */ + case BGE_ASICREV_BCM5750: + case BGE_ASICREV_BCM5752: + case BGE_ASICREV_BCM5906: + sc->bge_flags |= BGE_FLAG_575X_PLUS; + if (sc->bge_asicrev == BGE_ASICREV_BCM5906) + sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG; + /* FALLTHROUGH */ + case BGE_ASICREV_BCM5705: + sc->bge_flags |= BGE_FLAG_5705_PLUS; + break; + } + + /* Set various PHY bug flags. */ + if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || + sc->bge_chipid == BGE_CHIPID_BCM5701_B0) + sc->bge_phy_flags |= BGE_PHY_CRC_BUG; + if (sc->bge_chiprev == BGE_CHIPREV_5703_AX || + sc->bge_chiprev == BGE_CHIPREV_5704_AX) + sc->bge_phy_flags |= BGE_PHY_ADC_BUG; + if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) + sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG; + if (pci_get_subvendor(dev) == DELL_VENDORID) + sc->bge_phy_flags |= BGE_PHY_NO_3LED; + if ((BGE_IS_5705_PLUS(sc)) && + sc->bge_asicrev != BGE_ASICREV_BCM5906 && + sc->bge_asicrev != BGE_ASICREV_BCM5717 && + sc->bge_asicrev != BGE_ASICREV_BCM5785 && + sc->bge_asicrev != BGE_ASICREV_BCM57780) { + if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || + sc->bge_asicrev == BGE_ASICREV_BCM5761 || + sc->bge_asicrev == BGE_ASICREV_BCM5784 || + sc->bge_asicrev == BGE_ASICREV_BCM5787) { + if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 && + pci_get_device(dev) != BCOM_DEVICEID_BCM5756) + sc->bge_phy_flags |= BGE_PHY_JITTER_BUG; + if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M) + sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM; + } else + sc->bge_phy_flags |= BGE_PHY_BER_BUG; + } + + /* Identify the chips that use an CPMU. */ + if (BGE_IS_5717_PLUS(sc) || + sc->bge_asicrev == BGE_ASICREV_BCM5784 || + sc->bge_asicrev == BGE_ASICREV_BCM5761 || + sc->bge_asicrev == BGE_ASICREV_BCM5785 || + sc->bge_asicrev == BGE_ASICREV_BCM57780) + sc->bge_flags |= BGE_FLAG_CPMU_PRESENT; + if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0) + sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST; + else + sc->bge_mi_mode = BGE_MIMODE_BASE; + /* Enable auto polling for BCM570[0-5]. */ + if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705) + sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL; + + /* + * All controllers that are not 5755 or higher have 4GB + * boundary DMA bug. + * Whenever an address crosses a multiple of the 4GB boundary + * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition + * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA + * state machine will lockup and cause the device to hang. + */ + if (BGE_IS_5755_PLUS(sc) == 0) + sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG; + + misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID; + if (sc->bge_asicrev == BGE_ASICREV_BCM5705) { + if (misccfg == BGE_MISCCFG_BOARD_ID_5788 || + misccfg == BGE_MISCCFG_BOARD_ID_5788M) + sc->bge_flags |= BGE_FLAG_5788; + } + + capmask = BMSR_DEFCAPMASK; + if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 && + (misccfg == 0x4000 || misccfg == 0x8000)) || + (sc->bge_asicrev == BGE_ASICREV_BCM5705 && + pci_get_vendor(dev) == BCOM_VENDORID && + (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 || + pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 || + pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) || + (pci_get_vendor(dev) == BCOM_VENDORID && + (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F || + pci_get_device(dev) == BCOM_DEVICEID_BCM5753F || + pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) || + pci_get_device(dev) == BCOM_DEVICEID_BCM57790 || + sc->bge_asicrev == BGE_ASICREV_BCM5906) { + /* These chips are 10/100 only. */ + capmask &= ~BMSR_EXTSTAT; + } + + /* + * Some controllers seem to require a special firmware to use + * TSO. But the firmware is not available to FreeBSD and Linux + * claims that the TSO performed by the firmware is slower than + * hardware based TSO. Moreover the firmware based TSO has one + * known bug which can't handle TSO if ethernet header + IP/TCP + * header is greater than 80 bytes. The workaround for the TSO + * bug exist but it seems it's too expensive than not using + * TSO at all. Some hardwares also have the TSO bug so limit + * the TSO to the controllers that are not affected TSO issues + * (e.g. 5755 or higher). + */ + if (BGE_IS_5717_PLUS(sc)) { + /* BCM5717 requires different TSO configuration. */ + sc->bge_flags |= BGE_FLAG_TSO3; + } else if (BGE_IS_5755_PLUS(sc)) { + /* + * BCM5754 and BCM5787 shares the same ASIC id so + * explicit device id check is required. + * Due to unknown reason TSO does not work on BCM5755M. + */ + if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 && + pci_get_device(dev) != BCOM_DEVICEID_BCM5754M && + pci_get_device(dev) != BCOM_DEVICEID_BCM5755M) + sc->bge_flags |= BGE_FLAG_TSO; + } + + /* + * Check if this is a PCI-X or PCI Express device. + */ + if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { + /* + * Found a PCI Express capabilities register, this + * must be a PCI Express device. + */ + sc->bge_flags |= BGE_FLAG_PCIE; + sc->bge_expcap = reg; + if (pci_get_max_read_req(dev) != 4096) + pci_set_max_read_req(dev, 4096); + } else { + /* + * Check if the device is in PCI-X Mode. + * (This bit is not valid on PCI Express controllers.) + */ + if (pci_find_extcap(dev, PCIY_PCIX, ®) == 0) + sc->bge_pcixcap = reg; + if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & + BGE_PCISTATE_PCI_BUSMODE) == 0) + sc->bge_flags |= BGE_FLAG_PCIX; + } + + /* + * The 40bit DMA bug applies to the 5714/5715 controllers and is + * not actually a MAC controller bug but an issue with the embedded + * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. + */ + if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX)) + sc->bge_flags |= BGE_FLAG_40BIT_BUG; + /* + * Allocate the interrupt, using MSI if possible. These devices + * support 8 MSI messages, but only the first one is used in + * normal operation. + */ + rid = 0; + if (pci_find_extcap(sc->bge_dev, PCIY_MSI, ®) == 0) { + sc->bge_msicap = reg; + if (bge_can_use_msi(sc)) { + msicount = pci_msi_count(dev); + if (msicount > 1) + msicount = 1; + } else + msicount = 0; + if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) { + rid = 1; + sc->bge_flags |= BGE_FLAG_MSI; + } + } + + /* + * All controllers except BCM5700 supports tagged status but + * we use tagged status only for MSI case on BCM5717. Otherwise + * MSI on BCM5717 does not work. + */ +#ifndef DEVICE_POLLING + if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc)) + sc->bge_flags |= BGE_FLAG_TAGGED_STATUS; +#endif + + sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, + RF_SHAREABLE | RF_ACTIVE); + + if (sc->bge_irq == NULL) { + device_printf(sc->bge_dev, "couldn't map interrupt\n"); + error = ENXIO; + goto fail; + } + + device_printf(dev, + "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n", + sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev, + (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X" : + ((sc->bge_flags & BGE_FLAG_PCIE) ? "PCI-E" : "PCI")); + + BGE_LOCK_INIT(sc, device_get_nameunit(dev)); + + /* Try to reset the chip. */ + if (bge_reset(sc)) { + device_printf(sc->bge_dev, "chip reset failed\n"); + error = ENXIO; + goto fail; + } + + sc->bge_asf_mode = 0; + if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) + == BGE_MAGIC_NUMBER)) { + if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG) + & BGE_HWCFG_ASF) { + sc->bge_asf_mode |= ASF_ENABLE; + sc->bge_asf_mode |= ASF_STACKUP; + if (BGE_IS_575X_PLUS(sc)) + sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; + } + } + + /* Try to reset the chip again the nice way. */ + bge_stop_fw(sc); + bge_sig_pre_reset(sc, BGE_RESET_STOP); + if (bge_reset(sc)) { + device_printf(sc->bge_dev, "chip reset failed\n"); + error = ENXIO; + goto fail; + } + + bge_sig_legacy(sc, BGE_RESET_STOP); + bge_sig_post_reset(sc, BGE_RESET_STOP); + + if (bge_chipinit(sc)) { + device_printf(sc->bge_dev, "chip initialization failed\n"); + error = ENXIO; + goto fail; + } + + error = bge_get_eaddr(sc, eaddr); + if (error) { + device_printf(sc->bge_dev, + "failed to read station address\n"); + error = ENXIO; + goto fail; + } + + /* 5705 limits RX return ring to 512 entries. */ + if (BGE_IS_5717_PLUS(sc)) + sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; + else if (BGE_IS_5705_PLUS(sc)) + sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; + else + sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; + + if (bge_dma_alloc(sc)) { + device_printf(sc->bge_dev, + "failed to allocate DMA resources\n"); + error = ENXIO; + goto fail; + } + + bge_add_sysctls(sc); + + /* Set default tuneable values. */ + sc->bge_stat_ticks = BGE_TICKS_PER_SEC; + sc->bge_rx_coal_ticks = 150; + sc->bge_tx_coal_ticks = 150; + sc->bge_rx_max_coal_bds = 10; + sc->bge_tx_max_coal_bds = 10; + + /* Initialize checksum features to use. */ + sc->bge_csum_features = BGE_CSUM_FEATURES; + if (sc->bge_forced_udpcsum != 0) + sc->bge_csum_features |= CSUM_UDP; + + /* Set up ifnet structure */ + ifp = sc->bge_ifp = if_alloc(IFT_ETHER); + if (ifp == NULL) { + device_printf(sc->bge_dev, "failed to if_alloc()\n"); + error = ENXIO; + goto fail; + } + ifp->if_softc = sc; + if_initname(ifp, device_get_name(dev), device_get_unit(dev)); + ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; + ifp->if_ioctl = bge_ioctl; + ifp->if_start = bge_start; + ifp->if_init = bge_init; + ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1; + IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); + IFQ_SET_READY(&ifp->if_snd); + ifp->if_hwassist = sc->bge_csum_features; + ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | + IFCAP_VLAN_MTU; + if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) { + ifp->if_hwassist |= CSUM_TSO; + ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_VLAN_HWTSO; + } +#ifdef IFCAP_VLAN_HWCSUM + ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; +#endif + ifp->if_capenable = ifp->if_capabilities; +#ifdef DEVICE_POLLING + ifp->if_capabilities |= IFCAP_POLLING; +#endif + + /* + * 5700 B0 chips do not support checksumming correctly due + * to hardware bugs. + */ + if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) { + ifp->if_capabilities &= ~IFCAP_HWCSUM; + ifp->if_capenable &= ~IFCAP_HWCSUM; + ifp->if_hwassist = 0; + } + + /* + * Figure out what sort of media we have by checking the + * hardware config word in the first 32k of NIC internal memory, + * or fall back to examining the EEPROM if necessary. + * Note: on some BCM5700 cards, this value appears to be unset. + * If that's the case, we have to rely on identifying the NIC + * by its PCI subsystem ID, as we do below for the SysKonnect + * SK-9D41. + */ + if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) + hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); + else if ((sc->bge_flags & BGE_FLAG_EADDR) && + (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { + if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, + sizeof(hwcfg))) { + device_printf(sc->bge_dev, "failed to read EEPROM\n"); + error = ENXIO; + goto fail; + } + hwcfg = ntohl(hwcfg); + } + + /* The SysKonnect SK-9D41 is a 1000baseSX card. */ + if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == + SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { + if (BGE_IS_5714_FAMILY(sc)) + sc->bge_flags |= BGE_FLAG_MII_SERDES; + else + sc->bge_flags |= BGE_FLAG_TBI; + } + + if (sc->bge_flags & BGE_FLAG_TBI) { + ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, + bge_ifmedia_sts); + ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL); + ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX, + 0, NULL); + ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); + ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); + sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; + } else { + /* + * Do transceiver setup and tell the firmware the + * driver is down so we can try to get access the + * probe if ASF is running. Retry a couple of times + * if we get a conflict with the ASF firmware accessing + * the PHY. + */ + trys = 0; + BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); +again: + bge_asf_driver_up(sc); + + error = mii_attach(dev, &sc->bge_miibus, ifp, bge_ifmedia_upd, + bge_ifmedia_sts, capmask, phy_addr, MII_OFFSET_ANY, + MIIF_DOPAUSE | MIIF_FORCEPAUSE); + if (error != 0) { + if (trys++ < 4) { + device_printf(sc->bge_dev, "Try again\n"); + bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR, + BMCR_RESET); + goto again; + } + device_printf(sc->bge_dev, "attaching PHYs failed\n"); + goto fail; + } + + /* + * Now tell the firmware we are going up after probing the PHY + */ + if (sc->bge_asf_mode & ASF_STACKUP) + BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); + } + + /* + * When using the BCM5701 in PCI-X mode, data corruption has + * been observed in the first few bytes of some received packets. + * Aligning the packet buffer in memory eliminates the corruption. + * Unfortunately, this misaligns the packet payloads. On platforms + * which do not support unaligned accesses, we will realign the + * payloads by copying the received packets. + */ + if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && + sc->bge_flags & BGE_FLAG_PCIX) + sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG; + + /* + * Call MI attach routine. + */ + ether_ifattach(ifp, eaddr); + callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0); + + /* Tell upper layer we support long frames. */ + ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); + + /* + * Hookup IRQ last. + */ +#if __FreeBSD_version > 700030 + if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) { + /* Take advantage of single-shot MSI. */ + CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) & + ~BGE_MSIMODE_ONE_SHOT_DISABLE); + sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK, + taskqueue_thread_enqueue, &sc->bge_tq); + if (sc->bge_tq == NULL) { + device_printf(dev, "could not create taskqueue.\n"); + ether_ifdetach(ifp); + error = ENXIO; + goto fail; + } + taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, "%s taskq", + device_get_nameunit(sc->bge_dev)); + error = bus_setup_intr(dev, sc->bge_irq, + INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc, + &sc->bge_intrhand); + if (error) + ether_ifdetach(ifp); + } else + error = bus_setup_intr(dev, sc->bge_irq, + INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc, + &sc->bge_intrhand); +#else + error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE, + bge_intr, sc, &sc->bge_intrhand); +#endif + + if (error) { + bge_detach(dev); + device_printf(sc->bge_dev, "couldn't set up irq\n"); + } + + return (0); + +fail: + bge_release_resources(sc); + + return (error); +} + +static int +bge_detach(device_t dev) +{ + struct bge_softc *sc; + struct ifnet *ifp; + + sc = device_get_softc(dev); + ifp = sc->bge_ifp; + +#ifdef DEVICE_POLLING + if (ifp->if_capenable & IFCAP_POLLING) + ether_poll_deregister(ifp); +#endif + + BGE_LOCK(sc); + bge_stop(sc); + bge_reset(sc); + BGE_UNLOCK(sc); + + callout_drain(&sc->bge_stat_ch); + + if (sc->bge_tq) + taskqueue_drain(sc->bge_tq, &sc->bge_intr_task); + ether_ifdetach(ifp); + + if (sc->bge_flags & BGE_FLAG_TBI) { + ifmedia_removeall(&sc->bge_ifmedia); + } else { + bus_generic_detach(dev); + device_delete_child(dev, sc->bge_miibus); + } + + bge_release_resources(sc); + + return (0); +} + +static void +bge_release_resources(struct bge_softc *sc) +{ + device_t dev; + + dev = sc->bge_dev; + + if (sc->bge_tq != NULL) + taskqueue_free(sc->bge_tq); + + if (sc->bge_intrhand != NULL) + bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); + + if (sc->bge_irq != NULL) + bus_release_resource(dev, SYS_RES_IRQ, + sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq); + + if (sc->bge_flags & BGE_FLAG_MSI) + pci_release_msi(dev); + + if (sc->bge_res != NULL) + bus_release_resource(dev, SYS_RES_MEMORY, + PCIR_BAR(0), sc->bge_res); + + if (sc->bge_ifp != NULL) + if_free(sc->bge_ifp); + + bge_dma_free(sc); + + if (mtx_initialized(&sc->bge_mtx)) /* XXX */ + BGE_LOCK_DESTROY(sc); +} + +static int +bge_reset(struct bge_softc *sc) +{ + device_t dev; + uint32_t cachesize, command, pcistate, reset, val; + void (*write_op)(struct bge_softc *, int, int); + uint16_t devctl; + int i; + + dev = sc->bge_dev; + + if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && + (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { + if (sc->bge_flags & BGE_FLAG_PCIE) + write_op = bge_writemem_direct; + else + write_op = bge_writemem_ind; + } else + write_op = bge_writereg_ind; + + /* Save some important PCI state. */ + cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); + command = pci_read_config(dev, BGE_PCI_CMD, 4); + pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); + + pci_write_config(dev, BGE_PCI_MISC_CTL, + BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | + BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); + + /* Disable fastboot on controllers that support it. */ + if (sc->bge_asicrev == BGE_ASICREV_BCM5752 || + BGE_IS_5755_PLUS(sc)) { + if (bootverbose) + device_printf(dev, "Disabling fastboot\n"); + CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0); + } + + /* + * Write the magic number to SRAM at offset 0xB50. + * When firmware finishes its initialization it will + * write ~BGE_MAGIC_NUMBER to the same location. + */ + bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); + + reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; + + /* XXX: Broadcom Linux driver. */ + if (sc->bge_flags & BGE_FLAG_PCIE) { + if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */ + CSR_WRITE_4(sc, 0x7E2C, 0x20); + if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { + /* Prevent PCIE link training during global reset */ + CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); + reset |= 1 << 29; + } + } + + /* + * Set GPHY Power Down Override to leave GPHY + * powered up in D0 uninitialized. + */ + if (BGE_IS_5705_PLUS(sc)) + reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; + + /* Issue global reset */ + write_op(sc, BGE_MISC_CFG, reset); + + if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { + val = CSR_READ_4(sc, BGE_VCPU_STATUS); + CSR_WRITE_4(sc, BGE_VCPU_STATUS, + val | BGE_VCPU_STATUS_DRV_RESET); + val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); + CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, + val & ~BGE_VCPU_EXT_CTRL_HALT_CPU); + } + + DELAY(1000); + + /* XXX: Broadcom Linux driver. */ + if (sc->bge_flags & BGE_FLAG_PCIE) { + if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { + DELAY(500000); /* wait for link training to complete */ + val = pci_read_config(dev, 0xC4, 4); + pci_write_config(dev, 0xC4, val | (1 << 15), 4); + } + devctl = pci_read_config(dev, + sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2); + /* Clear enable no snoop and disable relaxed ordering. */ + devctl &= ~(PCIM_EXP_CTL_RELAXED_ORD_ENABLE | + PCIM_EXP_CTL_NOSNOOP_ENABLE); + /* Set PCIE max payload size to 128. */ + devctl &= ~PCIM_EXP_CTL_MAX_PAYLOAD; + pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, + devctl, 2); + /* Clear error status. */ + pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_STA, + PCIM_EXP_STA_CORRECTABLE_ERROR | + PCIM_EXP_STA_NON_FATAL_ERROR | PCIM_EXP_STA_FATAL_ERROR | + PCIM_EXP_STA_UNSUPPORTED_REQ, 2); + } + + /* Reset some of the PCI state that got zapped by reset. */ + pci_write_config(dev, BGE_PCI_MISC_CTL, + BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | + BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); + pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); + pci_write_config(dev, BGE_PCI_CMD, command, 4); + write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); + /* + * Disable PCI-X relaxed ordering to ensure status block update + * comes first then packet buffer DMA. Otherwise driver may + * read stale status block. + */ + if (sc->bge_flags & BGE_FLAG_PCIX) { + devctl = pci_read_config(dev, + sc->bge_pcixcap + PCIXR_COMMAND, 2); + devctl &= ~PCIXM_COMMAND_ERO; + if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { + devctl &= ~PCIXM_COMMAND_MAX_READ; + devctl |= PCIXM_COMMAND_MAX_READ_2048; + } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { + devctl &= ~(PCIXM_COMMAND_MAX_SPLITS | + PCIXM_COMMAND_MAX_READ); + devctl |= PCIXM_COMMAND_MAX_READ_2048; + } + pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND, + devctl, 2); + } + /* Re-enable MSI, if neccesary, and enable the memory arbiter. */ + if (BGE_IS_5714_FAMILY(sc)) { + /* This chip disables MSI on reset. */ + if (sc->bge_flags & BGE_FLAG_MSI) { + val = pci_read_config(dev, + sc->bge_msicap + PCIR_MSI_CTRL, 2); + pci_write_config(dev, + sc->bge_msicap + PCIR_MSI_CTRL, + val | PCIM_MSICTRL_MSI_ENABLE, 2); + val = CSR_READ_4(sc, BGE_MSI_MODE); + CSR_WRITE_4(sc, BGE_MSI_MODE, + val | BGE_MSIMODE_ENABLE); + } + val = CSR_READ_4(sc, BGE_MARB_MODE); + CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); + } else + CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); + + if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { + for (i = 0; i < BGE_TIMEOUT; i++) { + val = CSR_READ_4(sc, BGE_VCPU_STATUS); + if (val & BGE_VCPU_STATUS_INIT_DONE) + break; + DELAY(100); + } + if (i == BGE_TIMEOUT) { + device_printf(dev, "reset timed out\n"); + return (1); + } + } else { + /* + * Poll until we see the 1's complement of the magic number. + * This indicates that the firmware initialization is complete. + * We expect this to fail if no chip containing the Ethernet + * address is fitted though. + */ + for (i = 0; i < BGE_TIMEOUT; i++) { + DELAY(10); + val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); + if (val == ~BGE_MAGIC_NUMBER) + break; + } + + if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT) + device_printf(dev, + "firmware handshake timed out, found 0x%08x\n", + val); + } + + /* + * XXX Wait for the value of the PCISTATE register to + * return to its original pre-reset state. This is a + * fairly good indicator of reset completion. If we don't + * wait for the reset to fully complete, trying to read + * from the device's non-PCI registers may yield garbage + * results. + */ + for (i = 0; i < BGE_TIMEOUT; i++) { + if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) + break; + DELAY(10); + } + + /* Fix up byte swapping. */ + CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | + BGE_MODECTL_BYTESWAP_DATA); + + /* Tell the ASF firmware we are up */ + if (sc->bge_asf_mode & ASF_STACKUP) + BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); + + CSR_WRITE_4(sc, BGE_MAC_MODE, 0); + + /* + * The 5704 in TBI mode apparently needs some special + * adjustment to insure the SERDES drive level is set + * to 1.2V. + */ + if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && + sc->bge_flags & BGE_FLAG_TBI) { + val = CSR_READ_4(sc, BGE_SERDES_CFG); + val = (val & ~0xFFF) | 0x880; + CSR_WRITE_4(sc, BGE_SERDES_CFG, val); + } + + /* XXX: Broadcom Linux driver. */ + if (sc->bge_flags & BGE_FLAG_PCIE && + sc->bge_asicrev != BGE_ASICREV_BCM5717 && + sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && + sc->bge_asicrev != BGE_ASICREV_BCM5785) { + /* Enable Data FIFO protection. */ + val = CSR_READ_4(sc, 0x7C00); + CSR_WRITE_4(sc, 0x7C00, val | (1 << 25)); + } + DELAY(10000); + + return (0); +} + +static __inline void +bge_rxreuse_std(struct bge_softc *sc, int i) +{ + struct bge_rx_bd *r; + + r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; + r->bge_flags = BGE_RXBDFLAG_END; + r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i]; + r->bge_idx = i; + BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); +} + +static __inline void +bge_rxreuse_jumbo(struct bge_softc *sc, int i) +{ + struct bge_extrx_bd *r; + + r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; + r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; + r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0]; + r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1]; + r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2]; + r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3]; + r->bge_idx = i; + BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); +} + +/* + * Frame reception handling. This is called if there's a frame + * on the receive return list. + * + * Note: we have to be able to handle two possibilities here: + * 1) the frame is from the jumbo receive ring + * 2) the frame is from the standard receive ring + */ + +static int +bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck) +{ + struct ifnet *ifp; + int rx_npkts = 0, stdcnt = 0, jumbocnt = 0; + uint16_t rx_cons; + + rx_cons = sc->bge_rx_saved_considx; + + /* Nothing to do. */ + if (rx_cons == rx_prod) + return (rx_npkts); + + ifp = sc->bge_ifp; + + bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, + sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD); + bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, + sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE); + if (ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN > + (MCLBYTES - ETHER_ALIGN)) + bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, + sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE); + + while (rx_cons != rx_prod) { + struct bge_rx_bd *cur_rx; + uint32_t rxidx; + struct mbuf *m = NULL; + uint16_t vlan_tag = 0; + int have_tag = 0; + +#ifdef DEVICE_POLLING + if (ifp->if_capenable & IFCAP_POLLING) { + if (sc->rxcycles <= 0) + break; + sc->rxcycles--; + } +#endif + + cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons]; + + rxidx = cur_rx->bge_idx; + BGE_INC(rx_cons, sc->bge_return_ring_cnt); + + if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING && + cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { + have_tag = 1; + vlan_tag = cur_rx->bge_vlan_tag; + } + + if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { + jumbocnt++; + m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; + if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { + bge_rxreuse_jumbo(sc, rxidx); + continue; + } + if (bge_newbuf_jumbo(sc, rxidx) != 0) { + bge_rxreuse_jumbo(sc, rxidx); + ifp->if_iqdrops++; + continue; + } + BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); + } else { + stdcnt++; + m = sc->bge_cdata.bge_rx_std_chain[rxidx]; + if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { + bge_rxreuse_std(sc, rxidx); + continue; + } + if (bge_newbuf_std(sc, rxidx) != 0) { + bge_rxreuse_std(sc, rxidx); + ifp->if_iqdrops++; + continue; + } + BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); + } + + ifp->if_ipackets++; +#ifndef __NO_STRICT_ALIGNMENT + /* + * For architectures with strict alignment we must make sure + * the payload is aligned. + */ + if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) { + bcopy(m->m_data, m->m_data + ETHER_ALIGN, + cur_rx->bge_len); + m->m_data += ETHER_ALIGN; + } +#endif + m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; + m->m_pkthdr.rcvif = ifp; + + if (ifp->if_capenable & IFCAP_RXCSUM) + bge_rxcsum(sc, cur_rx, m); + + /* + * If we received a packet with a vlan tag, + * attach that information to the packet. + */ + if (have_tag) { +#if __FreeBSD_version > 700022 + m->m_pkthdr.ether_vtag = vlan_tag; + m->m_flags |= M_VLANTAG; +#else + VLAN_INPUT_TAG_NEW(ifp, m, vlan_tag); + if (m == NULL) + continue; +#endif + } + + if (holdlck != 0) { + BGE_UNLOCK(sc); + (*ifp->if_input)(ifp, m); + BGE_LOCK(sc); + } else + (*ifp->if_input)(ifp, m); + rx_npkts++; + + if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) + return (rx_npkts); + } + + bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, + sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD); + if (stdcnt > 0) + bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, + sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); + + if (jumbocnt > 0) + bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, + sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); + + sc->bge_rx_saved_considx = rx_cons; + bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); + if (stdcnt) + bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std + + BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT); + if (jumbocnt) + bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo + + BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT); +#ifdef notyet + /* + * This register wraps very quickly under heavy packet drops. + * If you need correct statistics, you can enable this check. + */ + if (BGE_IS_5705_PLUS(sc)) + ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); +#endif + return (rx_npkts); +} + +static void +bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) +{ + + if (BGE_IS_5717_PLUS(sc)) { + if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { + if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { + m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; + if ((cur_rx->bge_error_flag & + BGE_RXERRFLAG_IP_CSUM_NOK) == 0) + m->m_pkthdr.csum_flags |= CSUM_IP_VALID; + } + if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { + m->m_pkthdr.csum_data = + cur_rx->bge_tcp_udp_csum; + m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | + CSUM_PSEUDO_HDR; + } + } + } else { + if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { + m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; + if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0) + m->m_pkthdr.csum_flags |= CSUM_IP_VALID; + } + if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && + m->m_pkthdr.len >= ETHER_MIN_NOPAD) { + m->m_pkthdr.csum_data = + cur_rx->bge_tcp_udp_csum; + m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | + CSUM_PSEUDO_HDR; + } + } +} + +static void +bge_txeof(struct bge_softc *sc, uint16_t tx_cons) +{ + struct bge_tx_bd *cur_tx; + struct ifnet *ifp; + + BGE_LOCK_ASSERT(sc); + + /* Nothing to do. */ + if (sc->bge_tx_saved_considx == tx_cons) + return; + + ifp = sc->bge_ifp; + + bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, + sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE); + /* + * Go through our tx ring and free mbufs for those + * frames that have been sent. + */ + while (sc->bge_tx_saved_considx != tx_cons) { + uint32_t idx; + + idx = sc->bge_tx_saved_considx; + cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; + if (cur_tx->bge_flags & BGE_TXBDFLAG_END) + ifp->if_opackets++; + if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { + bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, + sc->bge_cdata.bge_tx_dmamap[idx], + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, + sc->bge_cdata.bge_tx_dmamap[idx]); + m_freem(sc->bge_cdata.bge_tx_chain[idx]); + sc->bge_cdata.bge_tx_chain[idx] = NULL; + } + sc->bge_txcnt--; + BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); + } + + ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; + if (sc->bge_txcnt == 0) + sc->bge_timer = 0; +} + +#ifdef DEVICE_POLLING +static int +bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) +{ + struct bge_softc *sc = ifp->if_softc; + uint16_t rx_prod, tx_cons; + uint32_t statusword; + int rx_npkts = 0; + + BGE_LOCK(sc); + if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { + BGE_UNLOCK(sc); + return (rx_npkts); + } + + bus_dmamap_sync(sc->bge_cdata.bge_status_tag, + sc->bge_cdata.bge_status_map, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; + tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; + + statusword = sc->bge_ldata.bge_status_block->bge_status; + sc->bge_ldata.bge_status_block->bge_status = 0; + + bus_dmamap_sync(sc->bge_cdata.bge_status_tag, + sc->bge_cdata.bge_status_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + + /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */ + if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) + sc->bge_link_evt++; + + if (cmd == POLL_AND_CHECK_STATUS) + if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && + sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || + sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI)) + bge_link_upd(sc); + + sc->rxcycles = count; + rx_npkts = bge_rxeof(sc, rx_prod, 1); + if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { + BGE_UNLOCK(sc); + return (rx_npkts); + } + bge_txeof(sc, tx_cons); + if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) + bge_start_locked(ifp); + + BGE_UNLOCK(sc); + return (rx_npkts); +} +#endif /* DEVICE_POLLING */ + +static int +bge_msi_intr(void *arg) +{ + struct bge_softc *sc; + + sc = (struct bge_softc *)arg; + /* + * This interrupt is not shared and controller already + * disabled further interrupt. + */ + taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task); + return (FILTER_HANDLED); +} + +static void +bge_intr_task(void *arg, int pending) +{ + struct bge_softc *sc; + struct ifnet *ifp; + uint32_t status, status_tag; + uint16_t rx_prod, tx_cons; + + sc = (struct bge_softc *)arg; + ifp = sc->bge_ifp; + + BGE_LOCK(sc); + if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { + BGE_UNLOCK(sc); + return; + } + + /* Get updated status block. */ + bus_dmamap_sync(sc->bge_cdata.bge_status_tag, + sc->bge_cdata.bge_status_map, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + + /* Save producer/consumer indexess. */ + rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; + tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; + status = sc->bge_ldata.bge_status_block->bge_status; + status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24; + sc->bge_ldata.bge_status_block->bge_status = 0; + bus_dmamap_sync(sc->bge_cdata.bge_status_tag, + sc->bge_cdata.bge_status_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0) + status_tag = 0; + + if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0) + bge_link_upd(sc); + + /* Let controller work. */ + bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag); + + if (ifp->if_drv_flags & IFF_DRV_RUNNING && + sc->bge_rx_saved_considx != rx_prod) { + /* Check RX return ring producer/consumer. */ + BGE_UNLOCK(sc); + bge_rxeof(sc, rx_prod, 0); + BGE_LOCK(sc); + } + if (ifp->if_drv_flags & IFF_DRV_RUNNING) { + /* Check TX ring producer/consumer. */ + bge_txeof(sc, tx_cons); + if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) + bge_start_locked(ifp); + } + BGE_UNLOCK(sc); +} + +static void +bge_intr(void *xsc) +{ + struct bge_softc *sc; + struct ifnet *ifp; + uint32_t statusword; + uint16_t rx_prod, tx_cons; + + sc = xsc; + + BGE_LOCK(sc); + + ifp = sc->bge_ifp; + +#ifdef DEVICE_POLLING + if (ifp->if_capenable & IFCAP_POLLING) { + BGE_UNLOCK(sc); + return; + } +#endif + + /* + * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't + * disable interrupts by writing nonzero like we used to, since with + * our current organization this just gives complications and + * pessimizations for re-enabling interrupts. We used to have races + * instead of the necessary complications. Disabling interrupts + * would just reduce the chance of a status update while we are + * running (by switching to the interrupt-mode coalescence + * parameters), but this chance is already very low so it is more + * efficient to get another interrupt than prevent it. + * + * We do the ack first to ensure another interrupt if there is a + * status update after the ack. We don't check for the status + * changing later because it is more efficient to get another + * interrupt than prevent it, not quite as above (not checking is + * a smaller optimization than not toggling the interrupt enable, + * since checking doesn't involve PCI accesses and toggling require + * the status check). So toggling would probably be a pessimization + * even with MSI. It would only be needed for using a task queue. + */ + bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); + + /* + * Do the mandatory PCI flush as well as get the link status. + */ + statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED; + + /* Make sure the descriptor ring indexes are coherent. */ + bus_dmamap_sync(sc->bge_cdata.bge_status_tag, + sc->bge_cdata.bge_status_map, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; + tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; + sc->bge_ldata.bge_status_block->bge_status = 0; + bus_dmamap_sync(sc->bge_cdata.bge_status_tag, + sc->bge_cdata.bge_status_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + + if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && + sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || + statusword || sc->bge_link_evt) + bge_link_upd(sc); + + if (ifp->if_drv_flags & IFF_DRV_RUNNING) { + /* Check RX return ring producer/consumer. */ + bge_rxeof(sc, rx_prod, 1); + } + + if (ifp->if_drv_flags & IFF_DRV_RUNNING) { + /* Check TX ring producer/consumer. */ + bge_txeof(sc, tx_cons); + } + + if (ifp->if_drv_flags & IFF_DRV_RUNNING && + !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) + bge_start_locked(ifp); + + BGE_UNLOCK(sc); +} + +static void +bge_asf_driver_up(struct bge_softc *sc) +{ + if (sc->bge_asf_mode & ASF_STACKUP) { + /* Send ASF heartbeat aprox. every 2s */ + if (sc->bge_asf_count) + sc->bge_asf_count --; + else { + sc->bge_asf_count = 2; + bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, + BGE_FW_DRV_ALIVE); + bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4); + bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3); + CSR_WRITE_4(sc, BGE_CPU_EVENT, + CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); + } + } +} + +static void +bge_tick(void *xsc) +{ + struct bge_softc *sc = xsc; + struct mii_data *mii = NULL; + + BGE_LOCK_ASSERT(sc); + + /* Synchronize with possible callout reset/stop. */ + if (callout_pending(&sc->bge_stat_ch) || + !callout_active(&sc->bge_stat_ch)) + return; + + if (BGE_IS_5705_PLUS(sc)) + bge_stats_update_regs(sc); + else + bge_stats_update(sc); + + if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { + mii = device_get_softc(sc->bge_miibus); + /* + * Do not touch PHY if we have link up. This could break + * IPMI/ASF mode or produce extra input errors + * (extra errors was reported for bcm5701 & bcm5704). + */ + if (!sc->bge_link) + mii_tick(mii); + } else { + /* + * Since in TBI mode auto-polling can't be used we should poll + * link status manually. Here we register pending link event + * and trigger interrupt. + */ +#ifdef DEVICE_POLLING + /* In polling mode we poll link state in bge_poll(). */ + if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING)) +#endif + { + sc->bge_link_evt++; + if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || + sc->bge_flags & BGE_FLAG_5788) + BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); + else + BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); + } + } + + bge_asf_driver_up(sc); + bge_watchdog(sc); + + callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); +} + +static void +bge_stats_update_regs(struct bge_softc *sc) +{ + struct ifnet *ifp; + struct bge_mac_stats *stats; + + ifp = sc->bge_ifp; + stats = &sc->bge_mac_stats; + + stats->ifHCOutOctets += + CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS); + stats->etherStatsCollisions += + CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS); + stats->outXonSent += + CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT); + stats->outXoffSent += + CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT); + stats->dot3StatsInternalMacTransmitErrors += + CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS); + stats->dot3StatsSingleCollisionFrames += + CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL); + stats->dot3StatsMultipleCollisionFrames += + CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL); + stats->dot3StatsDeferredTransmissions += + CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED); + stats->dot3StatsExcessiveCollisions += + CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL); + stats->dot3StatsLateCollisions += + CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL); + stats->ifHCOutUcastPkts += + CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST); + stats->ifHCOutMulticastPkts += + CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST); + stats->ifHCOutBroadcastPkts += + CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST); + + stats->ifHCInOctets += + CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS); + stats->etherStatsFragments += + CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS); + stats->ifHCInUcastPkts += + CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST); + stats->ifHCInMulticastPkts += + CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST); + stats->ifHCInBroadcastPkts += + CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST); + stats->dot3StatsFCSErrors += + CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS); + stats->dot3StatsAlignmentErrors += + CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS); + stats->xonPauseFramesReceived += + CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD); + stats->xoffPauseFramesReceived += + CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD); + stats->macControlFramesReceived += + CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD); + stats->xoffStateEntered += + CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED); + stats->dot3StatsFramesTooLong += + CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG); + stats->etherStatsJabbers += + CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS); + stats->etherStatsUndersizePkts += + CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE); + + stats->FramesDroppedDueToFilters += + CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP); + stats->DmaWriteQueueFull += + CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL); + stats->DmaWriteHighPriQueueFull += + CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL); + stats->NoMoreRxBDs += + CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); + stats->InputDiscards += + CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); + stats->InputErrors += + CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); + stats->RecvThresholdHit += + CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT); + + ifp->if_collisions = (u_long)stats->etherStatsCollisions; + ifp->if_ierrors = (u_long)(stats->NoMoreRxBDs + stats->InputDiscards + + stats->InputErrors); +} + +static void +bge_stats_clear_regs(struct bge_softc *sc) +{ + + CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS); + CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS); + CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT); + CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT); + CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS); + CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL); + CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL); + CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED); + CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL); + CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL); + CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST); + CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST); + CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST); + + CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS); + CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS); + CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST); + CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST); + CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST); + CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS); + CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS); + CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD); + CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD); + CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD); + CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED); + CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG); + CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS); + CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE); + + CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP); + CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL); + CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL); + CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); + CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); + CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); + CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT); +} + +static void +bge_stats_update(struct bge_softc *sc) +{ + struct ifnet *ifp; + bus_size_t stats; + uint32_t cnt; /* current register value */ + + ifp = sc->bge_ifp; + + stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; + +#define READ_STAT(sc, stats, stat) \ + CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) + + cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo); + ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions); + sc->bge_tx_collisions = cnt; + + cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo); + ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards); + sc->bge_rx_discards = cnt; + + cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo); + ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards); + sc->bge_tx_discards = cnt; + +#undef READ_STAT +} + +/* + * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. + * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, + * but when such padded frames employ the bge IP/TCP checksum offload, + * the hardware checksum assist gives incorrect results (possibly + * from incorporating its own padding into the UDP/TCP checksum; who knows). + * If we pad such runts with zeros, the onboard checksum comes out correct. + */ +static __inline int +bge_cksum_pad(struct mbuf *m) +{ + int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len; + struct mbuf *last; + + /* If there's only the packet-header and we can pad there, use it. */ + if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) && + M_TRAILINGSPACE(m) >= padlen) { + last = m; + } else { + /* + * Walk packet chain to find last mbuf. We will either + * pad there, or append a new mbuf and pad it. + */ + for (last = m; last->m_next != NULL; last = last->m_next); + if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) { + /* Allocate new empty mbuf, pad it. Compact later. */ + struct mbuf *n; + + MGET(n, M_DONTWAIT, MT_DATA); + if (n == NULL) + return (ENOBUFS); + n->m_len = 0; + last->m_next = n; + last = n; + } + } + + /* Now zero the pad area, to avoid the bge cksum-assist bug. */ + memset(mtod(last, caddr_t) + last->m_len, 0, padlen); + last->m_len += padlen; + m->m_pkthdr.len += padlen; + + return (0); +} + +static struct mbuf * +bge_check_short_dma(struct mbuf *m) +{ + struct mbuf *n; + int found; + + /* + * If device receive two back-to-back send BDs with less than + * or equal to 8 total bytes then the device may hang. The two + * back-to-back send BDs must in the same frame for this failure + * to occur. Scan mbuf chains and see whether two back-to-back + * send BDs are there. If this is the case, allocate new mbuf + * and copy the frame to workaround the silicon bug. + */ + for (n = m, found = 0; n != NULL; n = n->m_next) { + if (n->m_len < 8) { + found++; + if (found > 1) + break; + continue; + } + found = 0; + } + + if (found > 1) { + n = m_defrag(m, M_DONTWAIT); + if (n == NULL) + m_freem(m); + } else + n = m; + return (n); +} + +static struct mbuf * +bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss, + uint16_t *flags) +{ + struct ip *ip; + struct tcphdr *tcp; + struct mbuf *n; + uint16_t hlen; + uint32_t poff; + + if (M_WRITABLE(m) == 0) { + /* Get a writable copy. */ + n = m_dup(m, M_DONTWAIT); + m_freem(m); + if (n == NULL) + return (NULL); + m = n; + } + m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip)); + if (m == NULL) + return (NULL); + ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); + poff = sizeof(struct ether_header) + (ip->ip_hl << 2); + m = m_pullup(m, poff + sizeof(struct tcphdr)); + if (m == NULL) + return (NULL); + tcp = (struct tcphdr *)(mtod(m, char *) + poff); + m = m_pullup(m, poff + (tcp->th_off << 2)); + if (m == NULL) + return (NULL); + /* + * It seems controller doesn't modify IP length and TCP pseudo + * checksum. These checksum computed by upper stack should be 0. + */ + *mss = m->m_pkthdr.tso_segsz; + ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); + ip->ip_sum = 0; + ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2)); + /* Clear pseudo checksum computed by TCP stack. */ + tcp = (struct tcphdr *)(mtod(m, char *) + poff); + tcp->th_sum = 0; + /* + * Broadcom controllers uses different descriptor format for + * TSO depending on ASIC revision. Due to TSO-capable firmware + * license issue and lower performance of firmware based TSO + * we only support hardware based TSO. + */ + /* Calculate header length, incl. TCP/IP options, in 32 bit units. */ + hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2; + if (sc->bge_flags & BGE_FLAG_TSO3) { + /* + * For BCM5717 and newer controllers, hardware based TSO + * uses the 14 lower bits of the bge_mss field to store the + * MSS and the upper 2 bits to store the lowest 2 bits of + * the IP/TCP header length. The upper 6 bits of the header + * length are stored in the bge_flags[14:10,4] field. Jumbo + * frames are supported. + */ + *mss |= ((hlen & 0x3) << 14); + *flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2); + } else { + /* + * For BCM5755 and newer controllers, hardware based TSO uses + * the lower 11 bits to store the MSS and the upper 5 bits to + * store the IP/TCP header length. Jumbo frames are not + * supported. + */ + *mss |= (hlen << 11); + } + return (m); +} + +/* + * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data + * pointers to descriptors. + */ +static int +bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx) +{ + bus_dma_segment_t segs[BGE_NSEG_NEW]; + bus_dmamap_t map; + struct bge_tx_bd *d; + struct mbuf *m = *m_head; + uint32_t idx = *txidx; + uint16_t csum_flags, mss, vlan_tag; + int nsegs, i, error; + + csum_flags = 0; + mss = 0; + vlan_tag = 0; + if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 && + m->m_next != NULL) { + *m_head = bge_check_short_dma(m); + if (*m_head == NULL) + return (ENOBUFS); + m = *m_head; + } + if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { + *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags); + if (*m_head == NULL) + return (ENOBUFS); + csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA | + BGE_TXBDFLAG_CPU_POST_DMA; + } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) { + if (m->m_pkthdr.csum_flags & CSUM_IP) + csum_flags |= BGE_TXBDFLAG_IP_CSUM; + if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) { + csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; + if (m->m_pkthdr.len < ETHER_MIN_NOPAD && + (error = bge_cksum_pad(m)) != 0) { + m_freem(m); + *m_head = NULL; + return (error); + } + } + if (m->m_flags & M_LASTFRAG) + csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; + else if (m->m_flags & M_FRAG) + csum_flags |= BGE_TXBDFLAG_IP_FRAG; + } + + if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) { + if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME && + m->m_pkthdr.len > ETHER_MAX_LEN) + csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME; + if (sc->bge_forced_collapse > 0 && + (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) { + /* + * Forcedly collapse mbuf chains to overcome hardware + * limitation which only support a single outstanding + * DMA read operation. + */ + if (sc->bge_forced_collapse == 1) + m = m_defrag(m, M_DONTWAIT); + else + m = m_collapse(m, M_DONTWAIT, + sc->bge_forced_collapse); + if (m == NULL) + m = *m_head; + *m_head = m; + } + } + + map = sc->bge_cdata.bge_tx_dmamap[idx]; + error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs, + &nsegs, BUS_DMA_NOWAIT); + if (error == EFBIG) { + m = m_collapse(m, M_DONTWAIT, BGE_NSEG_NEW); + if (m == NULL) { + m_freem(*m_head); + *m_head = NULL; + return (ENOBUFS); + } + *m_head = m; + error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, + m, segs, &nsegs, BUS_DMA_NOWAIT); + if (error) { + m_freem(m); + *m_head = NULL; + return (error); + } + } else if (error != 0) + return (error); + + /* Check if we have enough free send BDs. */ + if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) { + bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map); + return (ENOBUFS); + } + + bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE); + +#if __FreeBSD_version > 700022 + if (m->m_flags & M_VLANTAG) { + csum_flags |= BGE_TXBDFLAG_VLAN_TAG; + vlan_tag = m->m_pkthdr.ether_vtag; + } +#else + { + struct m_tag *mtag; + + if ((mtag = VLAN_OUTPUT_TAG(sc->bge_ifp, m)) != NULL) { + csum_flags |= BGE_TXBDFLAG_VLAN_TAG; + vlan_tag = VLAN_TAG_VALUE(mtag); + } + } +#endif + for (i = 0; ; i++) { + d = &sc->bge_ldata.bge_tx_ring[idx]; + d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); + d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); + d->bge_len = segs[i].ds_len; + d->bge_flags = csum_flags; + d->bge_vlan_tag = vlan_tag; + d->bge_mss = mss; + if (i == nsegs - 1) + break; + BGE_INC(idx, BGE_TX_RING_CNT); + } + + /* Mark the last segment as end of packet... */ + d->bge_flags |= BGE_TXBDFLAG_END; + + /* + * Insure that the map for this transmission + * is placed at the array index of the last descriptor + * in this chain. + */ + sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx]; + sc->bge_cdata.bge_tx_dmamap[idx] = map; + sc->bge_cdata.bge_tx_chain[idx] = m; + sc->bge_txcnt += nsegs; + + BGE_INC(idx, BGE_TX_RING_CNT); + *txidx = idx; + + return (0); +} + +/* + * Main transmit routine. To avoid having to do mbuf copies, we put pointers + * to the mbuf data regions directly in the transmit descriptors. + */ +static void +bge_start_locked(struct ifnet *ifp) +{ + struct bge_softc *sc; + struct mbuf *m_head; + uint32_t prodidx; + int count; + + sc = ifp->if_softc; + BGE_LOCK_ASSERT(sc); + + if (!sc->bge_link || + (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != + IFF_DRV_RUNNING) + return; + + prodidx = sc->bge_tx_prodidx; + + for (count = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) { + if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) { + ifp->if_drv_flags |= IFF_DRV_OACTIVE; + break; + } + IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); + if (m_head == NULL) + break; + + /* + * XXX + * The code inside the if() block is never reached since we + * must mark CSUM_IP_FRAGS in our if_hwassist to start getting + * requests to checksum TCP/UDP in a fragmented packet. + * + * XXX + * safety overkill. If this is a fragmented packet chain + * with delayed TCP/UDP checksums, then only encapsulate + * it if we have enough descriptors to handle the entire + * chain at once. + * (paranoia -- may not actually be needed) + */ + if (m_head->m_flags & M_FIRSTFRAG && + m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { + if ((BGE_TX_RING_CNT - sc->bge_txcnt) < + m_head->m_pkthdr.csum_data + 16) { + IFQ_DRV_PREPEND(&ifp->if_snd, m_head); + ifp->if_drv_flags |= IFF_DRV_OACTIVE; + break; + } + } + + /* + * Pack the data into the transmit ring. If we + * don't have room, set the OACTIVE flag and wait + * for the NIC to drain the ring. + */ + if (bge_encap(sc, &m_head, &prodidx)) { + if (m_head == NULL) + break; + IFQ_DRV_PREPEND(&ifp->if_snd, m_head); + ifp->if_drv_flags |= IFF_DRV_OACTIVE; + break; + } + ++count; + + /* + * If there's a BPF listener, bounce a copy of this frame + * to him. + */ +#ifdef ETHER_BPF_MTAP + ETHER_BPF_MTAP(ifp, m_head); +#else + BPF_MTAP(ifp, m_head); +#endif + } + + if (count > 0) { + bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, + sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); + /* Transmit. */ + bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); + /* 5700 b2 errata */ + if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) + bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); + + sc->bge_tx_prodidx = prodidx; + + /* + * Set a timeout in case the chip goes out to lunch. + */ + sc->bge_timer = 5; + } +} + +/* + * Main transmit routine. To avoid having to do mbuf copies, we put pointers + * to the mbuf data regions directly in the transmit descriptors. + */ +static void +bge_start(struct ifnet *ifp) +{ + struct bge_softc *sc; + + sc = ifp->if_softc; + BGE_LOCK(sc); + bge_start_locked(ifp); + BGE_UNLOCK(sc); +} + +static void +bge_init_locked(struct bge_softc *sc) +{ + struct ifnet *ifp; + uint16_t *m; + uint32_t mode; + + BGE_LOCK_ASSERT(sc); + + ifp = sc->bge_ifp; + + if (ifp->if_drv_flags & IFF_DRV_RUNNING) + return; + + /* Cancel pending I/O and flush buffers. */ + bge_stop(sc); + + bge_stop_fw(sc); + bge_sig_pre_reset(sc, BGE_RESET_START); + bge_reset(sc); + bge_sig_legacy(sc, BGE_RESET_START); + bge_sig_post_reset(sc, BGE_RESET_START); + + bge_chipinit(sc); + + /* + * Init the various state machines, ring + * control blocks and firmware. + */ + if (bge_blockinit(sc)) { + device_printf(sc->bge_dev, "initialization failure\n"); + return; + } + + ifp = sc->bge_ifp; + + /* Specify MTU. */ + CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + + ETHER_HDR_LEN + ETHER_CRC_LEN + + (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0)); + + /* Load our MAC address. */ + m = (uint16_t *)IF_LLADDR(sc->bge_ifp); + CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); + CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); + + /* Program promiscuous mode. */ + bge_setpromisc(sc); + + /* Program multicast filter. */ + bge_setmulti(sc); + + /* Program VLAN tag stripping. */ + bge_setvlan(sc); + + /* Override UDP checksum offloading. */ + if (sc->bge_forced_udpcsum == 0) + sc->bge_csum_features &= ~CSUM_UDP; + else + sc->bge_csum_features |= CSUM_UDP; + if (ifp->if_capabilities & IFCAP_TXCSUM && + ifp->if_capenable & IFCAP_TXCSUM) { + ifp->if_hwassist &= ~(BGE_CSUM_FEATURES | CSUM_UDP); + ifp->if_hwassist |= sc->bge_csum_features; + } + + /* Init RX ring. */ + if (bge_init_rx_ring_std(sc) != 0) { + device_printf(sc->bge_dev, "no memory for std Rx buffers.\n"); + bge_stop(sc); + return; + } + + /* + * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's + * memory to insure that the chip has in fact read the first + * entry of the ring. + */ + if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { + uint32_t v, i; + for (i = 0; i < 10; i++) { + DELAY(20); + v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); + if (v == (MCLBYTES - ETHER_ALIGN)) + break; + } + if (i == 10) + device_printf (sc->bge_dev, + "5705 A0 chip failed to load RX ring\n"); + } + + /* Init jumbo RX ring. */ + if (ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN > + (MCLBYTES - ETHER_ALIGN)) { + if (bge_init_rx_ring_jumbo(sc) != 0) { + device_printf(sc->bge_dev, + "no memory for jumbo Rx buffers.\n"); + bge_stop(sc); + return; + } + } + + /* Init our RX return ring index. */ + sc->bge_rx_saved_considx = 0; + + /* Init our RX/TX stat counters. */ + sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0; + + /* Init TX ring. */ + bge_init_tx_ring(sc); + + /* Enable TX MAC state machine lockup fix. */ + mode = CSR_READ_4(sc, BGE_TX_MODE); + if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) + mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; + /* Turn on transmitter. */ + CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); + + /* Turn on receiver. */ + BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); + + /* + * Set the number of good frames to receive after RX MBUF + * Low Watermark has been reached. After the RX MAC receives + * this number of frames, it will drop subsequent incoming + * frames until the MBUF High Watermark is reached. + */ + CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); + + /* Clear MAC statistics. */ + if (BGE_IS_5705_PLUS(sc)) + bge_stats_clear_regs(sc); + + /* Tell firmware we're alive. */ + BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); + +#ifdef DEVICE_POLLING + /* Disable interrupts if we are polling. */ + if (ifp->if_capenable & IFCAP_POLLING) { + BGE_SETBIT(sc, BGE_PCI_MISC_CTL, + BGE_PCIMISCCTL_MASK_PCI_INTR); + bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); + } else +#endif + + /* Enable host interrupts. */ + { + BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); + BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); + bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); + } + + bge_ifmedia_upd_locked(ifp); + + ifp->if_drv_flags |= IFF_DRV_RUNNING; + ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; + + callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); +} + +static void +bge_init(void *xsc) +{ + struct bge_softc *sc = xsc; + + BGE_LOCK(sc); + bge_init_locked(sc); + BGE_UNLOCK(sc); +} + +/* + * Set media options. + */ +static int +bge_ifmedia_upd(struct ifnet *ifp) +{ + struct bge_softc *sc = ifp->if_softc; + int res; + + BGE_LOCK(sc); + res = bge_ifmedia_upd_locked(ifp); + BGE_UNLOCK(sc); + + return (res); +} + +static int +bge_ifmedia_upd_locked(struct ifnet *ifp) +{ + struct bge_softc *sc = ifp->if_softc; + struct mii_data *mii; + struct mii_softc *miisc; + struct ifmedia *ifm; + + BGE_LOCK_ASSERT(sc); + + ifm = &sc->bge_ifmedia; + + /* If this is a 1000baseX NIC, enable the TBI port. */ + if (sc->bge_flags & BGE_FLAG_TBI) { + if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) + return (EINVAL); + switch(IFM_SUBTYPE(ifm->ifm_media)) { + case IFM_AUTO: + /* + * The BCM5704 ASIC appears to have a special + * mechanism for programming the autoneg + * advertisement registers in TBI mode. + */ + if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { + uint32_t sgdig; + sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); + if (sgdig & BGE_SGDIGSTS_DONE) { + CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); + sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); + sgdig |= BGE_SGDIGCFG_AUTO | + BGE_SGDIGCFG_PAUSE_CAP | + BGE_SGDIGCFG_ASYM_PAUSE; + CSR_WRITE_4(sc, BGE_SGDIG_CFG, + sgdig | BGE_SGDIGCFG_SEND); + DELAY(5); + CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); + } + } + break; + case IFM_1000_SX: + if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { + BGE_CLRBIT(sc, BGE_MAC_MODE, + BGE_MACMODE_HALF_DUPLEX); + } else { + BGE_SETBIT(sc, BGE_MAC_MODE, + BGE_MACMODE_HALF_DUPLEX); + } + break; + default: + return (EINVAL); + } + return (0); + } + + sc->bge_link_evt++; + mii = device_get_softc(sc->bge_miibus); + if (mii->mii_instance) + LIST_FOREACH(miisc, &mii->mii_phys, mii_list) + mii_phy_reset(miisc); + mii_mediachg(mii); + + /* + * Force an interrupt so that we will call bge_link_upd + * if needed and clear any pending link state attention. + * Without this we are not getting any further interrupts + * for link state changes and thus will not UP the link and + * not be able to send in bge_start_locked. The only + * way to get things working was to receive a packet and + * get an RX intr. + * bge_tick should help for fiber cards and we might not + * need to do this here if BGE_FLAG_TBI is set but as + * we poll for fiber anyway it should not harm. + */ + if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || + sc->bge_flags & BGE_FLAG_5788) + BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); + else + BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); + + return (0); +} + +/* + * Report current media status. + */ +static void +bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) +{ + struct bge_softc *sc = ifp->if_softc; + struct mii_data *mii; + + BGE_LOCK(sc); + + if (sc->bge_flags & BGE_FLAG_TBI) { + ifmr->ifm_status = IFM_AVALID; + ifmr->ifm_active = IFM_ETHER; + if (CSR_READ_4(sc, BGE_MAC_STS) & + BGE_MACSTAT_TBI_PCS_SYNCHED) + ifmr->ifm_status |= IFM_ACTIVE; + else { + ifmr->ifm_active |= IFM_NONE; + BGE_UNLOCK(sc); + return; + } + ifmr->ifm_active |= IFM_1000_SX; + if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) + ifmr->ifm_active |= IFM_HDX; + else + ifmr->ifm_active |= IFM_FDX; + BGE_UNLOCK(sc); + return; + } + + mii = device_get_softc(sc->bge_miibus); + mii_pollstat(mii); + ifmr->ifm_active = mii->mii_media_active; + ifmr->ifm_status = mii->mii_media_status; + + BGE_UNLOCK(sc); +} + +static int +bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) +{ + struct bge_softc *sc = ifp->if_softc; + struct ifreq *ifr = (struct ifreq *) data; + struct mii_data *mii; + int flags, mask, error = 0; + + switch (command) { + case SIOCSIFMTU: + BGE_LOCK(sc); + if (ifr->ifr_mtu < ETHERMIN || + ((BGE_IS_JUMBO_CAPABLE(sc)) && + ifr->ifr_mtu > BGE_JUMBO_MTU) || + ((!BGE_IS_JUMBO_CAPABLE(sc)) && + ifr->ifr_mtu > ETHERMTU)) + error = EINVAL; + else if (ifp->if_mtu != ifr->ifr_mtu) { + ifp->if_mtu = ifr->ifr_mtu; + if (ifp->if_drv_flags & IFF_DRV_RUNNING) { + ifp->if_drv_flags &= ~IFF_DRV_RUNNING; + bge_init_locked(sc); + } + } + BGE_UNLOCK(sc); + break; + case SIOCSIFFLAGS: + BGE_LOCK(sc); + if (ifp->if_flags & IFF_UP) { + /* + * If only the state of the PROMISC flag changed, + * then just use the 'set promisc mode' command + * instead of reinitializing the entire NIC. Doing + * a full re-init means reloading the firmware and + * waiting for it to start up, which may take a + * second or two. Similarly for ALLMULTI. + */ + if (ifp->if_drv_flags & IFF_DRV_RUNNING) { + flags = ifp->if_flags ^ sc->bge_if_flags; + if (flags & IFF_PROMISC) + bge_setpromisc(sc); + if (flags & IFF_ALLMULTI) + bge_setmulti(sc); + } else + bge_init_locked(sc); + } else { + if (ifp->if_drv_flags & IFF_DRV_RUNNING) { + bge_stop(sc); + } + } + sc->bge_if_flags = ifp->if_flags; + BGE_UNLOCK(sc); + error = 0; + break; + case SIOCADDMULTI: + case SIOCDELMULTI: + if (ifp->if_drv_flags & IFF_DRV_RUNNING) { + BGE_LOCK(sc); + bge_setmulti(sc); + BGE_UNLOCK(sc); + error = 0; + } + break; + case SIOCSIFMEDIA: + case SIOCGIFMEDIA: + if (sc->bge_flags & BGE_FLAG_TBI) { + error = ifmedia_ioctl(ifp, ifr, + &sc->bge_ifmedia, command); + } else { + mii = device_get_softc(sc->bge_miibus); + error = ifmedia_ioctl(ifp, ifr, + &mii->mii_media, command); + } + break; + case SIOCSIFCAP: + mask = ifr->ifr_reqcap ^ ifp->if_capenable; +#ifdef DEVICE_POLLING + if (mask & IFCAP_POLLING) { + if (ifr->ifr_reqcap & IFCAP_POLLING) { + error = ether_poll_register(bge_poll, ifp); + if (error) + return (error); + BGE_LOCK(sc); + BGE_SETBIT(sc, BGE_PCI_MISC_CTL, + BGE_PCIMISCCTL_MASK_PCI_INTR); + bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); + ifp->if_capenable |= IFCAP_POLLING; + BGE_UNLOCK(sc); + } else { + error = ether_poll_deregister(ifp); + /* Enable interrupt even in error case */ + BGE_LOCK(sc); + BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, + BGE_PCIMISCCTL_MASK_PCI_INTR); + bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); + ifp->if_capenable &= ~IFCAP_POLLING; + BGE_UNLOCK(sc); + } + } +#endif + if ((mask & IFCAP_TXCSUM) != 0 && + (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { + ifp->if_capenable ^= IFCAP_TXCSUM; + if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) + ifp->if_hwassist |= sc->bge_csum_features; + else + ifp->if_hwassist &= ~sc->bge_csum_features; + } + + if ((mask & IFCAP_RXCSUM) != 0 && + (ifp->if_capabilities & IFCAP_RXCSUM) != 0) + ifp->if_capenable ^= IFCAP_RXCSUM; + + if ((mask & IFCAP_TSO4) != 0 && + (ifp->if_capabilities & IFCAP_TSO4) != 0) { + ifp->if_capenable ^= IFCAP_TSO4; + if ((ifp->if_capenable & IFCAP_TSO4) != 0) + ifp->if_hwassist |= CSUM_TSO; + else + ifp->if_hwassist &= ~CSUM_TSO; + } + + if (mask & IFCAP_VLAN_MTU) { + ifp->if_capenable ^= IFCAP_VLAN_MTU; + ifp->if_drv_flags &= ~IFF_DRV_RUNNING; + bge_init(sc); + } + + if ((mask & IFCAP_VLAN_HWTSO) != 0 && + (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) + ifp->if_capenable ^= IFCAP_VLAN_HWTSO; + if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && + (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { + ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; + if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) + ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; + BGE_LOCK(sc); + bge_setvlan(sc); + BGE_UNLOCK(sc); + } +#ifdef VLAN_CAPABILITIES + VLAN_CAPABILITIES(ifp); +#endif + break; + default: + error = ether_ioctl(ifp, command, data); + break; + } + + return (error); +} + +static void +bge_watchdog(struct bge_softc *sc) +{ + struct ifnet *ifp; + + BGE_LOCK_ASSERT(sc); + + if (sc->bge_timer == 0 || --sc->bge_timer) + return; + + ifp = sc->bge_ifp; + + if_printf(ifp, "watchdog timeout -- resetting\n"); + + ifp->if_drv_flags &= ~IFF_DRV_RUNNING; + bge_init_locked(sc); + + ifp->if_oerrors++; +} + +/* + * Stop the adapter and free any mbufs allocated to the + * RX and TX lists. + */ +static void +bge_stop(struct bge_softc *sc) +{ + struct ifnet *ifp; + + BGE_LOCK_ASSERT(sc); + + ifp = sc->bge_ifp; + + callout_stop(&sc->bge_stat_ch); + + /* Disable host interrupts. */ + BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); + bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); + + /* + * Tell firmware we're shutting down. + */ + bge_stop_fw(sc); + bge_sig_pre_reset(sc, BGE_RESET_STOP); + + /* + * Disable all of the receiver blocks. + */ + BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); + BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); + BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); + if (!(BGE_IS_5705_PLUS(sc))) + BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); + BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); + BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); + BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); + + /* + * Disable all of the transmit blocks. + */ + BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); + BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); + BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); + BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); + BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); + if (!(BGE_IS_5705_PLUS(sc))) + BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); + BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); + + /* + * Shut down all of the memory managers and related + * state machines. + */ + BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); + BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); + if (!(BGE_IS_5705_PLUS(sc))) + BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); + CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); + CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); + if (!(BGE_IS_5705_PLUS(sc))) { + BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); + BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); + } + /* Update MAC statistics. */ + if (BGE_IS_5705_PLUS(sc)) + bge_stats_update_regs(sc); + + bge_reset(sc); + bge_sig_legacy(sc, BGE_RESET_STOP); + bge_sig_post_reset(sc, BGE_RESET_STOP); + + /* + * Keep the ASF firmware running if up. + */ + if (sc->bge_asf_mode & ASF_STACKUP) + BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); + else + BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); + + /* Free the RX lists. */ + bge_free_rx_ring_std(sc); + + /* Free jumbo RX list. */ + if (BGE_IS_JUMBO_CAPABLE(sc)) + bge_free_rx_ring_jumbo(sc); + + /* Free TX buffers. */ + bge_free_tx_ring(sc); + + sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; + + /* Clear MAC's link state (PHY may still have link UP). */ + if (bootverbose && sc->bge_link) + if_printf(sc->bge_ifp, "link DOWN\n"); + sc->bge_link = 0; + + ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); +} + +/* + * Stop all chip I/O so that the kernel's probe routines don't + * get confused by errant DMAs when rebooting. + */ +static int +bge_shutdown(device_t dev) +{ + struct bge_softc *sc; + + sc = device_get_softc(dev); + BGE_LOCK(sc); + bge_stop(sc); + bge_reset(sc); + BGE_UNLOCK(sc); + + return (0); +} + +static int +bge_suspend(device_t dev) +{ + struct bge_softc *sc; + + sc = device_get_softc(dev); + BGE_LOCK(sc); + bge_stop(sc); + BGE_UNLOCK(sc); + + return (0); +} + +static int +bge_resume(device_t dev) +{ + struct bge_softc *sc; + struct ifnet *ifp; + + sc = device_get_softc(dev); + BGE_LOCK(sc); + ifp = sc->bge_ifp; + if (ifp->if_flags & IFF_UP) { + bge_init_locked(sc); + if (ifp->if_drv_flags & IFF_DRV_RUNNING) + bge_start_locked(ifp); + } + BGE_UNLOCK(sc); + + return (0); +} + +static void +bge_link_upd(struct bge_softc *sc) +{ + struct mii_data *mii; + uint32_t link, status; + + BGE_LOCK_ASSERT(sc); + + /* Clear 'pending link event' flag. */ + sc->bge_link_evt = 0; + + /* + * Process link state changes. + * Grrr. The link status word in the status block does + * not work correctly on the BCM5700 rev AX and BX chips, + * according to all available information. Hence, we have + * to enable MII interrupts in order to properly obtain + * async link changes. Unfortunately, this also means that + * we have to read the MAC status register to detect link + * changes, thereby adding an additional register access to + * the interrupt handler. + * + * XXX: perhaps link state detection procedure used for + * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions. + */ + + if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && + sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { + status = CSR_READ_4(sc, BGE_MAC_STS); + if (status & BGE_MACSTAT_MI_INTERRUPT) { + mii = device_get_softc(sc->bge_miibus); + mii_pollstat(mii); + if (!sc->bge_link && + mii->mii_media_status & IFM_ACTIVE && + IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { + sc->bge_link++; + if (bootverbose) + if_printf(sc->bge_ifp, "link UP\n"); + } else if (sc->bge_link && + (!(mii->mii_media_status & IFM_ACTIVE) || + IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { + sc->bge_link = 0; + if (bootverbose) + if_printf(sc->bge_ifp, "link DOWN\n"); + } + + /* Clear the interrupt. */ + CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, + BGE_EVTENB_MI_INTERRUPT); + bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); + bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, + BRGPHY_INTRS); + } + return; + } + + if (sc->bge_flags & BGE_FLAG_TBI) { + status = CSR_READ_4(sc, BGE_MAC_STS); + if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { + if (!sc->bge_link) { + sc->bge_link++; + if (sc->bge_asicrev == BGE_ASICREV_BCM5704) + BGE_CLRBIT(sc, BGE_MAC_MODE, + BGE_MACMODE_TBI_SEND_CFGS); + CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); + if (bootverbose) + if_printf(sc->bge_ifp, "link UP\n"); + if_link_state_change(sc->bge_ifp, + LINK_STATE_UP); + } + } else if (sc->bge_link) { + sc->bge_link = 0; + if (bootverbose) + if_printf(sc->bge_ifp, "link DOWN\n"); + if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN); + } + } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { + /* + * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit + * in status word always set. Workaround this bug by reading + * PHY link status directly. + */ + link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0; + + if (link != sc->bge_link || + sc->bge_asicrev == BGE_ASICREV_BCM5700) { + mii = device_get_softc(sc->bge_miibus); + mii_pollstat(mii); + if (!sc->bge_link && + mii->mii_media_status & IFM_ACTIVE && + IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { + sc->bge_link++; + if (bootverbose) + if_printf(sc->bge_ifp, "link UP\n"); + } else if (sc->bge_link && + (!(mii->mii_media_status & IFM_ACTIVE) || + IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { + sc->bge_link = 0; + if (bootverbose) + if_printf(sc->bge_ifp, "link DOWN\n"); + } + } + } else { + /* + * For controllers that call mii_tick, we have to poll + * link status. + */ + mii = device_get_softc(sc->bge_miibus); + mii_pollstat(mii); + bge_miibus_statchg(sc->bge_dev); + } + + /* Clear the attention. */ + CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | + BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | + BGE_MACSTAT_LINK_CHANGED); +} + +static void +bge_add_sysctls(struct bge_softc *sc) +{ + struct sysctl_ctx_list *ctx; + struct sysctl_oid_list *children; + char tn[32]; + int unit; + + ctx = device_get_sysctl_ctx(sc->bge_dev); + children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev)); + +#ifdef BGE_REGISTER_DEBUG + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info", + CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I", + "Debug Information"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read", + CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I", + "Register Read"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read", + CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I", + "Memory Read"); + +#endif + + unit = device_get_unit(sc->bge_dev); + /* + * A common design characteristic for many Broadcom client controllers + * is that they only support a single outstanding DMA read operation + * on the PCIe bus. This means that it will take twice as long to fetch + * a TX frame that is split into header and payload buffers as it does + * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For + * these controllers, coalescing buffers to reduce the number of memory + * reads is effective way to get maximum performance(about 940Mbps). + * Without collapsing TX buffers the maximum TCP bulk transfer + * performance is about 850Mbps. However forcing coalescing mbufs + * consumes a lot of CPU cycles, so leave it off by default. + */ + sc->bge_forced_collapse = 0; + snprintf(tn, sizeof(tn), "dev.bge.%d.forced_collapse", unit); + TUNABLE_INT_FETCH(tn, &sc->bge_forced_collapse); + SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse", + CTLFLAG_RW, &sc->bge_forced_collapse, 0, + "Number of fragmented TX buffers of a frame allowed before " + "forced collapsing"); + + /* + * It seems all Broadcom controllers have a bug that can generate UDP + * datagrams with checksum value 0 when TX UDP checksum offloading is + * enabled. Generating UDP checksum value 0 is RFC 768 violation. + * Even though the probability of generating such UDP datagrams is + * low, I don't want to see FreeBSD boxes to inject such datagrams + * into network so disable UDP checksum offloading by default. Users + * still override this behavior by setting a sysctl variable, + * dev.bge.0.forced_udpcsum. + */ + sc->bge_forced_udpcsum = 0; + snprintf(tn, sizeof(tn), "dev.bge.%d.bge_forced_udpcsum", unit); + TUNABLE_INT_FETCH(tn, &sc->bge_forced_udpcsum); + SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum", + CTLFLAG_RW, &sc->bge_forced_udpcsum, 0, + "Enable UDP checksum offloading even if controller can " + "generate UDP checksum value 0"); + + if (BGE_IS_5705_PLUS(sc)) + bge_add_sysctl_stats_regs(sc, ctx, children); + else + bge_add_sysctl_stats(sc, ctx, children); +} + +#define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \ + SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \ + sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \ + desc) + +static void +bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx, + struct sysctl_oid_list *parent) +{ + struct sysctl_oid *tree; + struct sysctl_oid_list *children, *schildren; + + tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD, + NULL, "BGE Statistics"); + schildren = children = SYSCTL_CHILDREN(tree); + BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters", + children, COSFramesDroppedDueToFilters, + "FramesDroppedDueToFilters"); + BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full", + children, nicDmaWriteQueueFull, "DmaWriteQueueFull"); + BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full", + children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull"); + BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors", + children, nicNoMoreRxBDs, "NoMoreRxBDs"); + BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames", + children, ifInDiscards, "InputDiscards"); + BGE_SYSCTL_STAT(sc, ctx, "Input Errors", + children, ifInErrors, "InputErrors"); + BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit", + children, nicRecvThresholdHit, "RecvThresholdHit"); + BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full", + children, nicDmaReadQueueFull, "DmaReadQueueFull"); + BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full", + children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull"); + BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full", + children, nicSendDataCompQueueFull, "SendDataCompQueueFull"); + BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index", + children, nicRingSetSendProdIndex, "RingSetSendProdIndex"); + BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update", + children, nicRingStatusUpdate, "RingStatusUpdate"); + BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts", + children, nicInterrupts, "Interrupts"); + BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts", + children, nicAvoidedInterrupts, "AvoidedInterrupts"); + BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit", + children, nicSendThresholdHit, "SendThresholdHit"); + + tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD, + NULL, "BGE RX Statistics"); + children = SYSCTL_CHILDREN(tree); + BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets", + children, rxstats.ifHCInOctets, "ifHCInOctets"); + BGE_SYSCTL_STAT(sc, ctx, "Fragments", + children, rxstats.etherStatsFragments, "Fragments"); + BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets", + children, rxstats.ifHCInUcastPkts, "UnicastPkts"); + BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets", + children, rxstats.ifHCInMulticastPkts, "MulticastPkts"); + BGE_SYSCTL_STAT(sc, ctx, "FCS Errors", + children, rxstats.dot3StatsFCSErrors, "FCSErrors"); + BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors", + children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors"); + BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received", + children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived"); + BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received", + children, rxstats.xoffPauseFramesReceived, + "xoffPauseFramesReceived"); + BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received", + children, rxstats.macControlFramesReceived, + "ControlFramesReceived"); + BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered", + children, rxstats.xoffStateEntered, "xoffStateEntered"); + BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long", + children, rxstats.dot3StatsFramesTooLong, "FramesTooLong"); + BGE_SYSCTL_STAT(sc, ctx, "Jabbers", + children, rxstats.etherStatsJabbers, "Jabbers"); + BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets", + children, rxstats.etherStatsUndersizePkts, "UndersizePkts"); + BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors", + children, rxstats.inRangeLengthError, "inRangeLengthError"); + BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors", + children, rxstats.outRangeLengthError, "outRangeLengthError"); + + tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD, + NULL, "BGE TX Statistics"); + children = SYSCTL_CHILDREN(tree); + BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets", + children, txstats.ifHCOutOctets, "ifHCOutOctets"); + BGE_SYSCTL_STAT(sc, ctx, "TX Collisions", + children, txstats.etherStatsCollisions, "Collisions"); + BGE_SYSCTL_STAT(sc, ctx, "XON Sent", + children, txstats.outXonSent, "XonSent"); + BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent", + children, txstats.outXoffSent, "XoffSent"); + BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done", + children, txstats.flowControlDone, "flowControlDone"); + BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors", + children, txstats.dot3StatsInternalMacTransmitErrors, + "InternalMacTransmitErrors"); + BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames", + children, txstats.dot3StatsSingleCollisionFrames, + "SingleCollisionFrames"); + BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames", + children, txstats.dot3StatsMultipleCollisionFrames, + "MultipleCollisionFrames"); + BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions", + children, txstats.dot3StatsDeferredTransmissions, + "DeferredTransmissions"); + BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions", + children, txstats.dot3StatsExcessiveCollisions, + "ExcessiveCollisions"); + BGE_SYSCTL_STAT(sc, ctx, "Late Collisions", + children, txstats.dot3StatsLateCollisions, + "LateCollisions"); + BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets", + children, txstats.ifHCOutUcastPkts, "UnicastPkts"); + BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets", + children, txstats.ifHCOutMulticastPkts, "MulticastPkts"); + BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets", + children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts"); + BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors", + children, txstats.dot3StatsCarrierSenseErrors, + "CarrierSenseErrors"); + BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards", + children, txstats.ifOutDiscards, "Discards"); + BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors", + children, txstats.ifOutErrors, "Errors"); +} + +#undef BGE_SYSCTL_STAT + +#define BGE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ + SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) + +static void +bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx, + struct sysctl_oid_list *parent) +{ + struct sysctl_oid *tree; + struct sysctl_oid_list *child, *schild; + struct bge_mac_stats *stats; + + stats = &sc->bge_mac_stats; + tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD, + NULL, "BGE Statistics"); + schild = child = SYSCTL_CHILDREN(tree); + BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters", + &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters"); + BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull", + &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full"); + BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull", + &stats->DmaWriteHighPriQueueFull, + "NIC DMA Write High Priority Queue Full"); + BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs", + &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors"); + BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards", + &stats->InputDiscards, "Discarded Input Frames"); + BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors", + &stats->InputErrors, "Input Errors"); + BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit", + &stats->RecvThresholdHit, "NIC Recv Threshold Hit"); + + tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD, + NULL, "BGE RX Statistics"); + child = SYSCTL_CHILDREN(tree); + BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets", + &stats->ifHCInOctets, "Inbound Octets"); + BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments", + &stats->etherStatsFragments, "Fragments"); + BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts", + &stats->ifHCInUcastPkts, "Inbound Unicast Packets"); + BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts", + &stats->ifHCInMulticastPkts, "Inbound Multicast Packets"); + BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts", + &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets"); + BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors", + &stats->dot3StatsFCSErrors, "FCS Errors"); + BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors", + &stats->dot3StatsAlignmentErrors, "Alignment Errors"); + BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived", + &stats->xonPauseFramesReceived, "XON Pause Frames Received"); + BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived", + &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received"); + BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived", + &stats->macControlFramesReceived, "MAC Control Frames Received"); + BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered", + &stats->xoffStateEntered, "XOFF State Entered"); + BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong", + &stats->dot3StatsFramesTooLong, "Frames Too Long"); + BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers", + &stats->etherStatsJabbers, "Jabbers"); + BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts", + &stats->etherStatsUndersizePkts, "Undersized Packets"); + + tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD, + NULL, "BGE TX Statistics"); + child = SYSCTL_CHILDREN(tree); + BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets", + &stats->ifHCOutOctets, "Outbound Octets"); + BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions", + &stats->etherStatsCollisions, "TX Collisions"); + BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent", + &stats->outXonSent, "XON Sent"); + BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent", + &stats->outXoffSent, "XOFF Sent"); + BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors", + &stats->dot3StatsInternalMacTransmitErrors, + "Internal MAC TX Errors"); + BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames", + &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames"); + BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames", + &stats->dot3StatsMultipleCollisionFrames, + "Multiple Collision Frames"); + BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions", + &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions"); + BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions", + &stats->dot3StatsExcessiveCollisions, "Excessive Collisions"); + BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions", + &stats->dot3StatsLateCollisions, "Late Collisions"); + BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts", + &stats->ifHCOutUcastPkts, "Outbound Unicast Packets"); + BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts", + &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets"); + BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts", + &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets"); +} + +#undef BGE_SYSCTL_STAT_ADD64 + +static int +bge_sysctl_stats(SYSCTL_HANDLER_ARGS) +{ + struct bge_softc *sc; + uint32_t result; + int offset; + + sc = (struct bge_softc *)arg1; + offset = arg2; + result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset + + offsetof(bge_hostaddr, bge_addr_lo)); + return (sysctl_handle_int(oidp, &result, 0, req)); +} + +#ifdef BGE_REGISTER_DEBUG +static int +bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS) +{ + struct bge_softc *sc; + uint16_t *sbdata; + int error; + int result; + int i, j; + + result = -1; + error = sysctl_handle_int(oidp, &result, 0, req); + if (error || (req->newptr == NULL)) + return (error); + + if (result == 1) { + sc = (struct bge_softc *)arg1; + + sbdata = (uint16_t *)sc->bge_ldata.bge_status_block; + printf("Status Block:\n"); + for (i = 0x0; i < (BGE_STATUS_BLK_SZ / 4); ) { + printf("%06x:", i); + for (j = 0; j < 8; j++) { + printf(" %04x", sbdata[i]); + i += 4; + } + printf("\n"); + } + + printf("Registers:\n"); + for (i = 0x800; i < 0xA00; ) { + printf("%06x:", i); + for (j = 0; j < 8; j++) { + printf(" %08x", CSR_READ_4(sc, i)); + i += 4; + } + printf("\n"); + } + + printf("Hardware Flags:\n"); + if (BGE_IS_5755_PLUS(sc)) + printf(" - 5755 Plus\n"); + if (BGE_IS_575X_PLUS(sc)) + printf(" - 575X Plus\n"); + if (BGE_IS_5705_PLUS(sc)) + printf(" - 5705 Plus\n"); + if (BGE_IS_5714_FAMILY(sc)) + printf(" - 5714 Family\n"); + if (BGE_IS_5700_FAMILY(sc)) + printf(" - 5700 Family\n"); + if (sc->bge_flags & BGE_FLAG_JUMBO) + printf(" - Supports Jumbo Frames\n"); + if (sc->bge_flags & BGE_FLAG_PCIX) + printf(" - PCI-X Bus\n"); + if (sc->bge_flags & BGE_FLAG_PCIE) + printf(" - PCI Express Bus\n"); + if (sc->bge_phy_flags & BGE_PHY_NO_3LED) + printf(" - No 3 LEDs\n"); + if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) + printf(" - RX Alignment Bug\n"); + } + + return (error); +} + +static int +bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS) +{ + struct bge_softc *sc; + int error; + uint16_t result; + uint32_t val; + + result = -1; + error = sysctl_handle_int(oidp, &result, 0, req); + if (error || (req->newptr == NULL)) + return (error); + + if (result < 0x8000) { + sc = (struct bge_softc *)arg1; + val = CSR_READ_4(sc, result); + printf("reg 0x%06X = 0x%08X\n", result, val); + } + + return (error); +} + +static int +bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS) +{ + struct bge_softc *sc; + int error; + uint16_t result; + uint32_t val; + + result = -1; + error = sysctl_handle_int(oidp, &result, 0, req); + if (error || (req->newptr == NULL)) + return (error); + + if (result < 0x8000) { + sc = (struct bge_softc *)arg1; + val = bge_readmem_ind(sc, result); + printf("mem 0x%06X = 0x%08X\n", result, val); + } + + return (error); +} +#endif + +static int +bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) +{ + + if (sc->bge_flags & BGE_FLAG_EADDR) + return (1); + +#ifdef __sparc64__ + OF_getetheraddr(sc->bge_dev, ether_addr); + return (0); +#endif + return (1); +} + +static int +bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) +{ + uint32_t mac_addr; + + mac_addr = bge_readmem_ind(sc, 0x0c14); + if ((mac_addr >> 16) == 0x484b) { + ether_addr[0] = (uint8_t)(mac_addr >> 8); + ether_addr[1] = (uint8_t)mac_addr; + mac_addr = bge_readmem_ind(sc, 0x0c18); + ether_addr[2] = (uint8_t)(mac_addr >> 24); + ether_addr[3] = (uint8_t)(mac_addr >> 16); + ether_addr[4] = (uint8_t)(mac_addr >> 8); + ether_addr[5] = (uint8_t)mac_addr; + return (0); + } + return (1); +} + +static int +bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) +{ + int mac_offset = BGE_EE_MAC_OFFSET; + + if (sc->bge_asicrev == BGE_ASICREV_BCM5906) + mac_offset = BGE_EE_MAC_OFFSET_5906; + + return (bge_read_nvram(sc, ether_addr, mac_offset + 2, + ETHER_ADDR_LEN)); +} + +static int +bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) +{ + + if (sc->bge_asicrev == BGE_ASICREV_BCM5906) + return (1); + + return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, + ETHER_ADDR_LEN)); +} + +static int +bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) +{ + static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { + /* NOTE: Order is critical */ + bge_get_eaddr_fw, + bge_get_eaddr_mem, + bge_get_eaddr_nvram, + bge_get_eaddr_eeprom, + NULL + }; + const bge_eaddr_fcn_t *func; + + for (func = bge_eaddr_funcs; *func != NULL; ++func) { + if ((*func)(sc, eaddr) == 0) + break; + } + return (*func == NULL ? ENXIO : 0); +} diff --git a/freebsd/dev/bge/if_bgereg.h b/freebsd/dev/bge/if_bgereg.h new file mode 100644 index 00000000..6a9c2e81 --- /dev/null +++ b/freebsd/dev/bge/if_bgereg.h @@ -0,0 +1,2826 @@ +/*- + * Copyright (c) 2001 Wind River Systems + * Copyright (c) 1997, 1998, 1999, 2001 + * Bill Paul . All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Bill Paul. + * 4. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * BCM570x memory map. The internal memory layout varies somewhat + * depending on whether or not we have external SSRAM attached. + * The BCM5700 can have up to 16MB of external memory. The BCM5701 + * is apparently not designed to use external SSRAM. The mappings + * up to the first 4 send rings are the same for both internal and + * external memory configurations. Note that mini RX ring space is + * only available with external SSRAM configurations, which means + * the mini RX ring is not supported on the BCM5701. + * + * The NIC's memory can be accessed by the host in one of 3 ways: + * + * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA + * registers in PCI config space can be used to read any 32-bit + * address within the NIC's memory. + * + * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config + * space can be used in conjunction with the memory window in the + * device register space at offset 0x8000 to read any 32K chunk + * of NIC memory. + * + * 3) Flat mode. If the 'flat mode' bit in the PCI state register is + * set, the device I/O mapping consumes 32MB of host address space, + * allowing all of the registers and internal NIC memory to be + * accessed directly. NIC memory addresses are offset by 0x01000000. + * Flat mode consumes so much host address space that it is not + * recommended. + */ +#define BGE_PAGE_ZERO 0x00000000 +#define BGE_PAGE_ZERO_END 0x000000FF +#define BGE_SEND_RING_RCB 0x00000100 +#define BGE_SEND_RING_RCB_END 0x000001FF +#define BGE_RX_RETURN_RING_RCB 0x00000200 +#define BGE_RX_RETURN_RING_RCB_END 0x000002FF +#define BGE_STATS_BLOCK 0x00000300 +#define BGE_STATS_BLOCK_END 0x00000AFF +#define BGE_STATUS_BLOCK 0x00000B00 +#define BGE_STATUS_BLOCK_END 0x00000B4F +#define BGE_SOFTWARE_GENCOMM 0x00000B50 +#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 +#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 +#define BGE_SOFTWARE_GENCOMM_FW 0x00000B78 +#define BGE_SOFTWARE_GENNCOMM_FW_LEN 0x00000B7C +#define BGE_SOFTWARE_GENNCOMM_FW_DATA 0x00000B80 +#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF +#define BGE_UNMAPPED 0x00001000 +#define BGE_UNMAPPED_END 0x00001FFF +#define BGE_DMA_DESCRIPTORS 0x00002000 +#define BGE_DMA_DESCRIPTORS_END 0x00003FFF +#define BGE_SEND_RING_5717 0x00004000 +#define BGE_SEND_RING_1_TO_4 0x00004000 +#define BGE_SEND_RING_1_TO_4_END 0x00005FFF + +/* Firmware interface */ +#define BGE_FW_DRV_ALIVE 0x00000001 +#define BGE_FW_PAUSE 0x00000002 + +/* Mappings for internal memory configuration */ +#define BGE_STD_RX_RINGS 0x00006000 +#define BGE_STD_RX_RINGS_END 0x00006FFF +#define BGE_JUMBO_RX_RINGS 0x00007000 +#define BGE_JUMBO_RX_RINGS_END 0x00007FFF +#define BGE_BUFFPOOL_1 0x00008000 +#define BGE_BUFFPOOL_1_END 0x0000FFFF +#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ +#define BGE_BUFFPOOL_2_END 0x00017FFF +#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ +#define BGE_BUFFPOOL_3_END 0x0001FFFF +#define BGE_STD_RX_RINGS_5717 0x00040000 +#define BGE_JUMBO_RX_RINGS_5717 0x00044400 + +/* Mappings for external SSRAM configurations */ +#define BGE_SEND_RING_5_TO_6 0x00006000 +#define BGE_SEND_RING_5_TO_6_END 0x00006FFF +#define BGE_SEND_RING_7_TO_8 0x00007000 +#define BGE_SEND_RING_7_TO_8_END 0x00007FFF +#define BGE_SEND_RING_9_TO_16 0x00008000 +#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF +#define BGE_EXT_STD_RX_RINGS 0x0000C000 +#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF +#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 +#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF +#define BGE_MINI_RX_RINGS 0x0000E000 +#define BGE_MINI_RX_RINGS_END 0x0000FFFF +#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ +#define BGE_AVAIL_REGION1_END 0x00017FFF +#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ +#define BGE_AVAIL_REGION2_END 0x0001FFFF +#define BGE_EXT_SSRAM 0x00020000 +#define BGE_EXT_SSRAM_END 0x000FFFFF + + +/* + * BCM570x register offsets. These are memory mapped registers + * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. + * Each register must be accessed using 32 bit operations. + * + * All registers are accessed through a 32K shared memory block. + * The first group of registers are actually copies of the PCI + * configuration space registers. + */ + +/* + * PCI registers defined in the PCI 2.2 spec. + */ +#define BGE_PCI_VID 0x00 +#define BGE_PCI_DID 0x02 +#define BGE_PCI_CMD 0x04 +#define BGE_PCI_STS 0x06 +#define BGE_PCI_REV 0x08 +#define BGE_PCI_CLASS 0x09 +#define BGE_PCI_CACHESZ 0x0C +#define BGE_PCI_LATTIMER 0x0D +#define BGE_PCI_HDRTYPE 0x0E +#define BGE_PCI_BIST 0x0F +#define BGE_PCI_BAR0 0x10 +#define BGE_PCI_BAR1 0x14 +#define BGE_PCI_SUBSYS 0x2C +#define BGE_PCI_SUBVID 0x2E +#define BGE_PCI_ROMBASE 0x30 +#define BGE_PCI_CAPPTR 0x34 +#define BGE_PCI_INTLINE 0x3C +#define BGE_PCI_INTPIN 0x3D +#define BGE_PCI_MINGNT 0x3E +#define BGE_PCI_MAXLAT 0x3F +#define BGE_PCI_PCIXCAP 0x40 +#define BGE_PCI_NEXTPTR_PM 0x41 +#define BGE_PCI_PCIX_CMD 0x42 +#define BGE_PCI_PCIX_STS 0x44 +#define BGE_PCI_PWRMGMT_CAPID 0x48 +#define BGE_PCI_NEXTPTR_VPD 0x49 +#define BGE_PCI_PWRMGMT_CAPS 0x4A +#define BGE_PCI_PWRMGMT_CMD 0x4C +#define BGE_PCI_PWRMGMT_STS 0x4D +#define BGE_PCI_PWRMGMT_DATA 0x4F +#define BGE_PCI_VPD_CAPID 0x50 +#define BGE_PCI_NEXTPTR_MSI 0x51 +#define BGE_PCI_VPD_ADDR 0x52 +#define BGE_PCI_VPD_DATA 0x54 +#define BGE_PCI_MSI_CAPID 0x58 +#define BGE_PCI_NEXTPTR_NONE 0x59 +#define BGE_PCI_MSI_CTL 0x5A +#define BGE_PCI_MSI_ADDR_HI 0x5C +#define BGE_PCI_MSI_ADDR_LO 0x60 +#define BGE_PCI_MSI_DATA 0x64 + +/* + * PCI Express definitions + * According to + * PCI Express base specification, REV. 1.0a + */ + +/* PCI Express device control, 16bits */ +#define BGE_PCIE_DEVCTL 0x08 +#define BGE_PCIE_DEVCTL_MAX_READRQ_MASK 0x7000 +#define BGE_PCIE_DEVCTL_MAX_READRQ_128 0x0000 +#define BGE_PCIE_DEVCTL_MAX_READRQ_256 0x1000 +#define BGE_PCIE_DEVCTL_MAX_READRQ_512 0x2000 +#define BGE_PCIE_DEVCTL_MAX_READRQ_1024 0x3000 +#define BGE_PCIE_DEVCTL_MAX_READRQ_2048 0x4000 +#define BGE_PCIE_DEVCTL_MAX_READRQ_4096 0x5000 + +/* PCI MSI. ??? */ +#define BGE_PCIE_CAPID_REG 0xD0 +#define BGE_PCIE_CAPID 0x10 + +/* + * PCI registers specific to the BCM570x family. + */ +#define BGE_PCI_MISC_CTL 0x68 +#define BGE_PCI_DMA_RW_CTL 0x6C +#define BGE_PCI_PCISTATE 0x70 +#define BGE_PCI_CLKCTL 0x74 +#define BGE_PCI_REG_BASEADDR 0x78 +#define BGE_PCI_MEMWIN_BASEADDR 0x7C +#define BGE_PCI_REG_DATA 0x80 +#define BGE_PCI_MEMWIN_DATA 0x84 +#define BGE_PCI_MODECTL 0x88 +#define BGE_PCI_MISC_CFG 0x8C +#define BGE_PCI_MISC_LOCALCTL 0x90 +#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 +#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C +#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 +#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 +#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 +#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC +#define BGE_PCI_ISR_MBX_HI 0xB0 +#define BGE_PCI_ISR_MBX_LO 0xB4 +#define BGE_PCI_PRODID_ASICREV 0xBC +#define BGE_PCI_GEN2_PRODID_ASICREV 0xF4 + +/* PCI Misc. Host control register */ +#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 +#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 +#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 +#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 +#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 +#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 +#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 +#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 +#define BGE_PCIMISCCTL_TAGGED_STATUS 0x00000200 +#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 +#define BGE_PCIMISCCTL_ASICREV_SHIFT 16 + +#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) +#if BYTE_ORDER == LITTLE_ENDIAN +#define BGE_DMA_SWAP_OPTIONS \ + BGE_MODECTL_WORDSWAP_NONFRAME| \ + BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA +#else +#define BGE_DMA_SWAP_OPTIONS \ + BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ + BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA +#endif + +#define BGE_INIT \ + (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \ + BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) + +#define BGE_CHIPID_TIGON_I 0x4000 +#define BGE_CHIPID_TIGON_II 0x6000 +#define BGE_CHIPID_BCM5700_A0 0x7000 +#define BGE_CHIPID_BCM5700_A1 0x7001 +#define BGE_CHIPID_BCM5700_B0 0x7100 +#define BGE_CHIPID_BCM5700_B1 0x7101 +#define BGE_CHIPID_BCM5700_B2 0x7102 +#define BGE_CHIPID_BCM5700_B3 0x7103 +#define BGE_CHIPID_BCM5700_ALTIMA 0x7104 +#define BGE_CHIPID_BCM5700_C0 0x7200 +#define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr */ +#define BGE_CHIPID_BCM5701_B0 0x0100 +#define BGE_CHIPID_BCM5701_B2 0x0102 +#define BGE_CHIPID_BCM5701_B5 0x0105 +#define BGE_CHIPID_BCM5703_A0 0x1000 +#define BGE_CHIPID_BCM5703_A1 0x1001 +#define BGE_CHIPID_BCM5703_A2 0x1002 +#define BGE_CHIPID_BCM5703_A3 0x1003 +#define BGE_CHIPID_BCM5703_B0 0x1100 +#define BGE_CHIPID_BCM5704_A0 0x2000 +#define BGE_CHIPID_BCM5704_A1 0x2001 +#define BGE_CHIPID_BCM5704_A2 0x2002 +#define BGE_CHIPID_BCM5704_A3 0x2003 +#define BGE_CHIPID_BCM5704_B0 0x2100 +#define BGE_CHIPID_BCM5705_A0 0x3000 +#define BGE_CHIPID_BCM5705_A1 0x3001 +#define BGE_CHIPID_BCM5705_A2 0x3002 +#define BGE_CHIPID_BCM5705_A3 0x3003 +#define BGE_CHIPID_BCM5750_A0 0x4000 +#define BGE_CHIPID_BCM5750_A1 0x4001 +#define BGE_CHIPID_BCM5750_A3 0x4000 +#define BGE_CHIPID_BCM5750_B0 0x4100 +#define BGE_CHIPID_BCM5750_B1 0x4101 +#define BGE_CHIPID_BCM5750_C0 0x4200 +#define BGE_CHIPID_BCM5750_C1 0x4201 +#define BGE_CHIPID_BCM5750_C2 0x4202 +#define BGE_CHIPID_BCM5714_A0 0x5000 +#define BGE_CHIPID_BCM5752_A0 0x6000 +#define BGE_CHIPID_BCM5752_A1 0x6001 +#define BGE_CHIPID_BCM5752_A2 0x6002 +#define BGE_CHIPID_BCM5714_B0 0x8000 +#define BGE_CHIPID_BCM5714_B3 0x8003 +#define BGE_CHIPID_BCM5715_A0 0x9000 +#define BGE_CHIPID_BCM5715_A1 0x9001 +#define BGE_CHIPID_BCM5715_A3 0x9003 +#define BGE_CHIPID_BCM5755_A0 0xa000 +#define BGE_CHIPID_BCM5755_A1 0xa001 +#define BGE_CHIPID_BCM5755_A2 0xa002 +#define BGE_CHIPID_BCM5722_A0 0xa200 +#define BGE_CHIPID_BCM5754_A0 0xb000 +#define BGE_CHIPID_BCM5754_A1 0xb001 +#define BGE_CHIPID_BCM5754_A2 0xb002 +#define BGE_CHIPID_BCM5761_A0 0x5761000 +#define BGE_CHIPID_BCM5761_A1 0x5761100 +#define BGE_CHIPID_BCM5784_A0 0x5784000 +#define BGE_CHIPID_BCM5784_A1 0x5784100 +#define BGE_CHIPID_BCM5787_A0 0xb000 +#define BGE_CHIPID_BCM5787_A1 0xb001 +#define BGE_CHIPID_BCM5787_A2 0xb002 +#define BGE_CHIPID_BCM5906_A0 0xc000 +#define BGE_CHIPID_BCM5906_A1 0xc001 +#define BGE_CHIPID_BCM5906_A2 0xc002 +#define BGE_CHIPID_BCM57780_A0 0x57780000 +#define BGE_CHIPID_BCM57780_A1 0x57780001 +#define BGE_CHIPID_BCM5717_A0 0x05717000 +#define BGE_CHIPID_BCM5717_B0 0x05717100 + +/* shorthand one */ +#define BGE_ASICREV(x) ((x) >> 12) +#define BGE_ASICREV_BCM5701 0x00 +#define BGE_ASICREV_BCM5703 0x01 +#define BGE_ASICREV_BCM5704 0x02 +#define BGE_ASICREV_BCM5705 0x03 +#define BGE_ASICREV_BCM5750 0x04 +#define BGE_ASICREV_BCM5714_A0 0x05 +#define BGE_ASICREV_BCM5752 0x06 +#define BGE_ASICREV_BCM5700 0x07 +#define BGE_ASICREV_BCM5780 0x08 +#define BGE_ASICREV_BCM5714 0x09 +#define BGE_ASICREV_BCM5755 0x0a +#define BGE_ASICREV_BCM5754 0x0b +#define BGE_ASICREV_BCM5787 0x0b +#define BGE_ASICREV_BCM5906 0x0c +/* Should consult BGE_PCI_PRODID_ASICREV for ChipID */ +#define BGE_ASICREV_USE_PRODID_REG 0x0f +/* BGE_PCI_PRODID_ASICREV ASIC rev. identifiers. */ +#define BGE_ASICREV_BCM5717 0x5717 +#define BGE_ASICREV_BCM5761 0x5761 +#define BGE_ASICREV_BCM5784 0x5784 +#define BGE_ASICREV_BCM5785 0x5785 +#define BGE_ASICREV_BCM57780 0x57780 + +/* chip revisions */ +#define BGE_CHIPREV(x) ((x) >> 8) +#define BGE_CHIPREV_5700_AX 0x70 +#define BGE_CHIPREV_5700_BX 0x71 +#define BGE_CHIPREV_5700_CX 0x72 +#define BGE_CHIPREV_5701_AX 0x00 +#define BGE_CHIPREV_5703_AX 0x10 +#define BGE_CHIPREV_5704_AX 0x20 +#define BGE_CHIPREV_5704_BX 0x21 +#define BGE_CHIPREV_5750_AX 0x40 +#define BGE_CHIPREV_5750_BX 0x41 +/* BGE_PCI_PRODID_ASICREV chip rev. identifiers. */ +#define BGE_CHIPREV_5717_AX 0x57170 +#define BGE_CHIPREV_5717_BX 0x57171 +#define BGE_CHIPREV_5761_AX 0x57611 +#define BGE_CHIPREV_5784_AX 0x57841 + +/* PCI DMA Read/Write Control register */ +#define BGE_PCIDMARWCTL_MINDMA 0x000000FF +#define BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT 0x00000001 +#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 +#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 +#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000 +#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 +#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 +#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 +#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 +#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 +#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 +#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 +#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 + +#define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16) +#define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19) +#define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24) +#define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28) + +#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 +#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 +#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 +#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 +#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 +#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 +#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 +#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 + +#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 +#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 +#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 +#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 +#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 +#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 +#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 +#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 + +/* + * PCI state register -- note, this register is read only + * unless the PCISTATE_WR bit of the PCI Misc. Host Control + * register is set. + */ +#define BGE_PCISTATE_FORCE_RESET 0x00000001 +#define BGE_PCISTATE_INTR_STATE 0x00000002 +#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ +#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */ +#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ +#define BGE_PCISTATE_WANT_EXPROM 0x00000020 +#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 +#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 +#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 + +/* + * PCI Clock Control register -- note, this register is read only + * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control + * register is set. + */ +#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F +#define BGE_PCICLOCKCTL_M66EN 0x00000080 +#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 +#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 +#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 +#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 +#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 +#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 +#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 +#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 + + +#ifndef PCIM_CMD_MWIEN +#define PCIM_CMD_MWIEN 0x0010 +#endif +#ifndef PCIM_CMD_INTxDIS +#define PCIM_CMD_INTxDIS 0x0400 +#endif + +/* + * High priority mailbox registers + * Each mailbox is 64-bits wide, though we only use the + * lower 32 bits. To write a 64-bit value, write the upper 32 bits + * first. The NIC will load the mailbox after the lower 32 bit word + * has been updated. + */ +#define BGE_MBX_IRQ0_HI 0x0200 +#define BGE_MBX_IRQ0_LO 0x0204 +#define BGE_MBX_IRQ1_HI 0x0208 +#define BGE_MBX_IRQ1_LO 0x020C +#define BGE_MBX_IRQ2_HI 0x0210 +#define BGE_MBX_IRQ2_LO 0x0214 +#define BGE_MBX_IRQ3_HI 0x0218 +#define BGE_MBX_IRQ3_LO 0x021C +#define BGE_MBX_GEN0_HI 0x0220 +#define BGE_MBX_GEN0_LO 0x0224 +#define BGE_MBX_GEN1_HI 0x0228 +#define BGE_MBX_GEN1_LO 0x022C +#define BGE_MBX_GEN2_HI 0x0230 +#define BGE_MBX_GEN2_LO 0x0234 +#define BGE_MBX_GEN3_HI 0x0228 +#define BGE_MBX_GEN3_LO 0x022C +#define BGE_MBX_GEN4_HI 0x0240 +#define BGE_MBX_GEN4_LO 0x0244 +#define BGE_MBX_GEN5_HI 0x0248 +#define BGE_MBX_GEN5_LO 0x024C +#define BGE_MBX_GEN6_HI 0x0250 +#define BGE_MBX_GEN6_LO 0x0254 +#define BGE_MBX_GEN7_HI 0x0258 +#define BGE_MBX_GEN7_LO 0x025C +#define BGE_MBX_RELOAD_STATS_HI 0x0260 +#define BGE_MBX_RELOAD_STATS_LO 0x0264 +#define BGE_MBX_RX_STD_PROD_HI 0x0268 +#define BGE_MBX_RX_STD_PROD_LO 0x026C +#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 +#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 +#define BGE_MBX_RX_MINI_PROD_HI 0x0278 +#define BGE_MBX_RX_MINI_PROD_LO 0x027C +#define BGE_MBX_RX_CONS0_HI 0x0280 +#define BGE_MBX_RX_CONS0_LO 0x0284 +#define BGE_MBX_RX_CONS1_HI 0x0288 +#define BGE_MBX_RX_CONS1_LO 0x028C +#define BGE_MBX_RX_CONS2_HI 0x0290 +#define BGE_MBX_RX_CONS2_LO 0x0294 +#define BGE_MBX_RX_CONS3_HI 0x0298 +#define BGE_MBX_RX_CONS3_LO 0x029C +#define BGE_MBX_RX_CONS4_HI 0x02A0 +#define BGE_MBX_RX_CONS4_LO 0x02A4 +#define BGE_MBX_RX_CONS5_HI 0x02A8 +#define BGE_MBX_RX_CONS5_LO 0x02AC +#define BGE_MBX_RX_CONS6_HI 0x02B0 +#define BGE_MBX_RX_CONS6_LO 0x02B4 +#define BGE_MBX_RX_CONS7_HI 0x02B8 +#define BGE_MBX_RX_CONS7_LO 0x02BC +#define BGE_MBX_RX_CONS8_HI 0x02C0 +#define BGE_MBX_RX_CONS8_LO 0x02C4 +#define BGE_MBX_RX_CONS9_HI 0x02C8 +#define BGE_MBX_RX_CONS9_LO 0x02CC +#define BGE_MBX_RX_CONS10_HI 0x02D0 +#define BGE_MBX_RX_CONS10_LO 0x02D4 +#define BGE_MBX_RX_CONS11_HI 0x02D8 +#define BGE_MBX_RX_CONS11_LO 0x02DC +#define BGE_MBX_RX_CONS12_HI 0x02E0 +#define BGE_MBX_RX_CONS12_LO 0x02E4 +#define BGE_MBX_RX_CONS13_HI 0x02E8 +#define BGE_MBX_RX_CONS13_LO 0x02EC +#define BGE_MBX_RX_CONS14_HI 0x02F0 +#define BGE_MBX_RX_CONS14_LO 0x02F4 +#define BGE_MBX_RX_CONS15_HI 0x02F8 +#define BGE_MBX_RX_CONS15_LO 0x02FC +#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 +#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 +#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 +#define BGE_MBX_TX_HOST_PROD1_LO 0x030C +#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 +#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 +#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 +#define BGE_MBX_TX_HOST_PROD3_LO 0x031C +#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 +#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 +#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 +#define BGE_MBX_TX_HOST_PROD5_LO 0x032C +#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 +#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 +#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 +#define BGE_MBX_TX_HOST_PROD7_LO 0x033C +#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 +#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 +#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 +#define BGE_MBX_TX_HOST_PROD9_LO 0x034C +#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 +#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 +#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 +#define BGE_MBX_TX_HOST_PROD11_LO 0x035C +#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 +#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 +#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 +#define BGE_MBX_TX_HOST_PROD13_LO 0x036C +#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 +#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 +#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 +#define BGE_MBX_TX_HOST_PROD15_LO 0x037C +#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 +#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 +#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 +#define BGE_MBX_TX_NIC_PROD1_LO 0x038C +#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 +#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 +#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 +#define BGE_MBX_TX_NIC_PROD3_LO 0x039C +#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 +#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 +#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 +#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC +#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 +#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 +#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 +#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC +#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 +#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 +#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 +#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC +#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 +#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 +#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 +#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC +#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 +#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 +#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 +#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC +#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 +#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 +#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 +#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC + +#define BGE_TX_RINGS_MAX 4 +#define BGE_TX_RINGS_EXTSSRAM_MAX 16 +#define BGE_RX_RINGS_MAX 16 +#define BGE_RX_RINGS_MAX_5717 17 + +/* Ethernet MAC control registers */ +#define BGE_MAC_MODE 0x0400 +#define BGE_MAC_STS 0x0404 +#define BGE_MAC_EVT_ENB 0x0408 +#define BGE_MAC_LED_CTL 0x040C +#define BGE_MAC_ADDR1_LO 0x0410 +#define BGE_MAC_ADDR1_HI 0x0414 +#define BGE_MAC_ADDR2_LO 0x0418 +#define BGE_MAC_ADDR2_HI 0x041C +#define BGE_MAC_ADDR3_LO 0x0420 +#define BGE_MAC_ADDR3_HI 0x0424 +#define BGE_MAC_ADDR4_LO 0x0428 +#define BGE_MAC_ADDR4_HI 0x042C +#define BGE_WOL_PATPTR 0x0430 +#define BGE_WOL_PATCFG 0x0434 +#define BGE_TX_RANDOM_BACKOFF 0x0438 +#define BGE_RX_MTU 0x043C +#define BGE_GBIT_PCS_TEST 0x0440 +#define BGE_TX_TBI_AUTONEG 0x0444 +#define BGE_RX_TBI_AUTONEG 0x0448 +#define BGE_MI_COMM 0x044C +#define BGE_MI_STS 0x0450 +#define BGE_MI_MODE 0x0454 +#define BGE_AUTOPOLL_STS 0x0458 +#define BGE_TX_MODE 0x045C +#define BGE_TX_STS 0x0460 +#define BGE_TX_LENGTHS 0x0464 +#define BGE_RX_MODE 0x0468 +#define BGE_RX_STS 0x046C +#define BGE_MAR0 0x0470 +#define BGE_MAR1 0x0474 +#define BGE_MAR2 0x0478 +#define BGE_MAR3 0x047C +#define BGE_RX_BD_RULES_CTL0 0x0480 +#define BGE_RX_BD_RULES_MASKVAL0 0x0484 +#define BGE_RX_BD_RULES_CTL1 0x0488 +#define BGE_RX_BD_RULES_MASKVAL1 0x048C +#define BGE_RX_BD_RULES_CTL2 0x0490 +#define BGE_RX_BD_RULES_MASKVAL2 0x0494 +#define BGE_RX_BD_RULES_CTL3 0x0498 +#define BGE_RX_BD_RULES_MASKVAL3 0x049C +#define BGE_RX_BD_RULES_CTL4 0x04A0 +#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 +#define BGE_RX_BD_RULES_CTL5 0x04A8 +#define BGE_RX_BD_RULES_MASKVAL5 0x04AC +#define BGE_RX_BD_RULES_CTL6 0x04B0 +#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 +#define BGE_RX_BD_RULES_CTL7 0x04B8 +#define BGE_RX_BD_RULES_MASKVAL7 0x04BC +#define BGE_RX_BD_RULES_CTL8 0x04C0 +#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 +#define BGE_RX_BD_RULES_CTL9 0x04C8 +#define BGE_RX_BD_RULES_MASKVAL9 0x04CC +#define BGE_RX_BD_RULES_CTL10 0x04D0 +#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 +#define BGE_RX_BD_RULES_CTL11 0x04D8 +#define BGE_RX_BD_RULES_MASKVAL11 0x04DC +#define BGE_RX_BD_RULES_CTL12 0x04E0 +#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 +#define BGE_RX_BD_RULES_CTL13 0x04E8 +#define BGE_RX_BD_RULES_MASKVAL13 0x04EC +#define BGE_RX_BD_RULES_CTL14 0x04F0 +#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 +#define BGE_RX_BD_RULES_CTL15 0x04F8 +#define BGE_RX_BD_RULES_MASKVAL15 0x04FC +#define BGE_RX_RULES_CFG 0x0500 +#define BGE_MAX_RX_FRAME_LOWAT 0x0504 +#define BGE_SERDES_CFG 0x0590 +#define BGE_SERDES_STS 0x0594 +#define BGE_SGDIG_CFG 0x05B0 +#define BGE_SGDIG_STS 0x05B4 +#define BGE_TX_MAC_STATS_OCTETS 0x0800 +#define BGE_TX_MAC_STATS_RESERVE_0 0x0804 +#define BGE_TX_MAC_STATS_COLLS 0x0808 +#define BGE_TX_MAC_STATS_XON_SENT 0x080C +#define BGE_TX_MAC_STATS_XOFF_SENT 0x0810 +#define BGE_TX_MAC_STATS_RESERVE_1 0x0814 +#define BGE_TX_MAC_STATS_ERRORS 0x0818 +#define BGE_TX_MAC_STATS_SINGLE_COLL 0x081C +#define BGE_TX_MAC_STATS_MULTI_COLL 0x0820 +#define BGE_TX_MAC_STATS_DEFERRED 0x0824 +#define BGE_TX_MAC_STATS_RESERVE_2 0x0828 +#define BGE_TX_MAC_STATS_EXCESS_COLL 0x082C +#define BGE_TX_MAC_STATS_LATE_COLL 0x0830 +#define BGE_TX_MAC_STATS_RESERVE_3 0x0834 +#define BGE_TX_MAC_STATS_RESERVE_4 0x0838 +#define BGE_TX_MAC_STATS_RESERVE_5 0x083C +#define BGE_TX_MAC_STATS_RESERVE_6 0x0840 +#define BGE_TX_MAC_STATS_RESERVE_7 0x0844 +#define BGE_TX_MAC_STATS_RESERVE_8 0x0848 +#define BGE_TX_MAC_STATS_RESERVE_9 0x084C +#define BGE_TX_MAC_STATS_RESERVE_10 0x0850 +#define BGE_TX_MAC_STATS_RESERVE_11 0x0854 +#define BGE_TX_MAC_STATS_RESERVE_12 0x0858 +#define BGE_TX_MAC_STATS_RESERVE_13 0x085C +#define BGE_TX_MAC_STATS_RESERVE_14 0x0860 +#define BGE_TX_MAC_STATS_RESERVE_15 0x0864 +#define BGE_TX_MAC_STATS_RESERVE_16 0x0868 +#define BGE_TX_MAC_STATS_UCAST 0x086C +#define BGE_TX_MAC_STATS_MCAST 0x0870 +#define BGE_TX_MAC_STATS_BCAST 0x0874 +#define BGE_TX_MAC_STATS_RESERVE_17 0x0878 +#define BGE_TX_MAC_STATS_RESERVE_18 0x087C +#define BGE_RX_MAC_STATS_OCTESTS 0x0880 +#define BGE_RX_MAC_STATS_RESERVE_0 0x0884 +#define BGE_RX_MAC_STATS_FRAGMENTS 0x0888 +#define BGE_RX_MAC_STATS_UCAST 0x088C +#define BGE_RX_MAC_STATS_MCAST 0x0890 +#define BGE_RX_MAC_STATS_BCAST 0x0894 +#define BGE_RX_MAC_STATS_FCS_ERRORS 0x0898 +#define BGE_RX_MAC_STATS_ALGIN_ERRORS 0x089C +#define BGE_RX_MAC_STATS_XON_RCVD 0x08A0 +#define BGE_RX_MAC_STATS_XOFF_RCVD 0x08A4 +#define BGE_RX_MAC_STATS_CTRL_RCVD 0x08A8 +#define BGE_RX_MAC_STATS_XOFF_ENTERED 0x08AC +#define BGE_RX_MAC_STATS_FRAME_TOO_LONG 0x08B0 +#define BGE_RX_MAC_STATS_JABBERS 0x08B4 +#define BGE_RX_MAC_STATS_UNDERSIZE 0x08B8 + +/* Ethernet MAC Mode register */ +#define BGE_MACMODE_RESET 0x00000001 +#define BGE_MACMODE_HALF_DUPLEX 0x00000002 +#define BGE_MACMODE_PORTMODE 0x0000000C +#define BGE_MACMODE_LOOPBACK 0x00000010 +#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 +#define BGE_MACMODE_TX_BURST_ENB 0x00000100 +#define BGE_MACMODE_MAX_DEFER 0x00000200 +#define BGE_MACMODE_LINK_POLARITY 0x00000400 +#define BGE_MACMODE_RX_STATS_ENB 0x00000800 +#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 +#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 +#define BGE_MACMODE_TX_STATS_ENB 0x00004000 +#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 +#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 +#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 +#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 +#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 +#define BGE_MACMODE_MIP_ENB 0x00100000 +#define BGE_MACMODE_TXDMA_ENB 0x00200000 +#define BGE_MACMODE_RXDMA_ENB 0x00400000 +#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 + +#define BGE_PORTMODE_NONE 0x00000000 +#define BGE_PORTMODE_MII 0x00000004 +#define BGE_PORTMODE_GMII 0x00000008 +#define BGE_PORTMODE_TBI 0x0000000C + +/* MAC Status register */ +#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 +#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 +#define BGE_MACSTAT_RX_CFG 0x00000004 +#define BGE_MACSTAT_CFG_CHANGED 0x00000008 +#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 +#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 +#define BGE_MACSTAT_LINK_CHANGED 0x00001000 +#define BGE_MACSTAT_MI_COMPLETE 0x00400000 +#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 +#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 +#define BGE_MACSTAT_ODI_ERROR 0x02000000 +#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 +#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 + +/* MAC Event Enable Register */ +#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 +#define BGE_EVTENB_LINK_CHANGED 0x00001000 +#define BGE_EVTENB_MI_COMPLETE 0x00400000 +#define BGE_EVTENB_MI_INTERRUPT 0x00800000 +#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 +#define BGE_EVTENB_ODI_ERROR 0x02000000 +#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 +#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 + +/* LED Control Register */ +#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 +#define BGE_LEDCTL_1000MBPS_LED 0x00000002 +#define BGE_LEDCTL_100MBPS_LED 0x00000004 +#define BGE_LEDCTL_10MBPS_LED 0x00000008 +#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 +#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 +#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 +#define BGE_LEDCTL_1000MBPS_STS 0x00000080 +#define BGE_LEDCTL_100MBPS_STS 0x00000100 +#define BGE_LEDCTL_10MBPS_STS 0x00000200 +#define BGE_LEDCTL_TRADLED_STS 0x00000400 +#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 +#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 + +/* TX backoff seed register */ +#define BGE_TX_BACKOFF_SEED_MASK 0x3F + +/* Autopoll status register */ +#define BGE_AUTOPOLLSTS_ERROR 0x00000001 + +/* Transmit MAC mode register */ +#define BGE_TXMODE_RESET 0x00000001 +#define BGE_TXMODE_ENABLE 0x00000002 +#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 +#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 +#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 +#define BGE_TXMODE_MBUF_LOCKUP_FIX 0x00000100 + +/* Transmit MAC status register */ +#define BGE_TXSTAT_RX_XOFFED 0x00000001 +#define BGE_TXSTAT_SENT_XOFF 0x00000002 +#define BGE_TXSTAT_SENT_XON 0x00000004 +#define BGE_TXSTAT_LINK_UP 0x00000008 +#define BGE_TXSTAT_ODI_UFLOW 0x00000010 +#define BGE_TXSTAT_ODI_OFLOW 0x00000020 + +/* Transmit MAC lengths register */ +#define BGE_TXLEN_SLOTTIME 0x000000FF +#define BGE_TXLEN_IPG 0x00000F00 +#define BGE_TXLEN_CRS 0x00003000 + +/* Receive MAC mode register */ +#define BGE_RXMODE_RESET 0x00000001 +#define BGE_RXMODE_ENABLE 0x00000002 +#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 +#define BGE_RXMODE_RX_GIANTS 0x00000020 +#define BGE_RXMODE_RX_RUNTS 0x00000040 +#define BGE_RXMODE_8022_LENCHECK 0x00000080 +#define BGE_RXMODE_RX_PROMISC 0x00000100 +#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 +#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 + +/* Receive MAC status register */ +#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 +#define BGE_RXSTAT_RCVD_XOFF 0x00000002 +#define BGE_RXSTAT_RCVD_XON 0x00000004 + +/* Receive Rules Control register */ +#define BGE_RXRULECTL_OFFSET 0x000000FF +#define BGE_RXRULECTL_CLASS 0x00001F00 +#define BGE_RXRULECTL_HDRTYPE 0x0000E000 +#define BGE_RXRULECTL_COMPARE_OP 0x00030000 +#define BGE_RXRULECTL_MAP 0x01000000 +#define BGE_RXRULECTL_DISCARD 0x02000000 +#define BGE_RXRULECTL_MASK 0x04000000 +#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 +#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 +#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 +#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 + +/* Receive Rules Mask register */ +#define BGE_RXRULEMASK_VALUE 0x0000FFFF +#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 + +/* SERDES configuration register */ +#define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */ +#define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */ +#define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */ +#define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */ +#define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */ +#define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */ +#define BGE_SERDESCFG_TXMODE 0x00001000 +#define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */ +#define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */ +#define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */ +#define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */ +#define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */ +#define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */ +#define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */ +#define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */ +#define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */ + +/* SERDES status register */ +#define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */ +#define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */ + +/* SGDIG config (not documented) */ +#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 +#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 +#define BGE_SGDIGCFG_SEND 0x40000000 +#define BGE_SGDIGCFG_AUTO 0x80000000 + +/* SGDIG status (not documented) */ +#define BGE_SGDIGSTS_DONE 0x00000002 +#define BGE_SGDIGSTS_IS_SERDES 0x00000100 +#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 +#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 + + +/* MI communication register */ +#define BGE_MICOMM_DATA 0x0000FFFF +#define BGE_MICOMM_REG 0x001F0000 +#define BGE_MICOMM_PHY 0x03E00000 +#define BGE_MICOMM_CMD 0x0C000000 +#define BGE_MICOMM_READFAIL 0x10000000 +#define BGE_MICOMM_BUSY 0x20000000 + +#define BGE_MIREG(x) ((x & 0x1F) << 16) +#define BGE_MIPHY(x) ((x & 0x1F) << 21) +#define BGE_MICMD_WRITE 0x04000000 +#define BGE_MICMD_READ 0x08000000 + +/* MI status register */ +#define BGE_MISTS_LINK 0x00000001 +#define BGE_MISTS_10MBPS 0x00000002 + +#define BGE_MIMODE_CLK_10MHZ 0x00000001 +#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 +#define BGE_MIMODE_AUTOPOLL 0x00000010 +#define BGE_MIMODE_CLKCNT 0x001F0000 +#define BGE_MIMODE_500KHZ_CONST 0x00008000 +#define BGE_MIMODE_BASE 0x000C0000 + + +/* + * Send data initiator control registers. + */ +#define BGE_SDI_MODE 0x0C00 +#define BGE_SDI_STATUS 0x0C04 +#define BGE_SDI_STATS_CTL 0x0C08 +#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C +#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 +#define BGE_ISO_PKT_TX 0x0C20 +#define BGE_LOCSTATS_COS0 0x0C80 +#define BGE_LOCSTATS_COS1 0x0C84 +#define BGE_LOCSTATS_COS2 0x0C88 +#define BGE_LOCSTATS_COS3 0x0C8C +#define BGE_LOCSTATS_COS4 0x0C90 +#define BGE_LOCSTATS_COS5 0x0C84 +#define BGE_LOCSTATS_COS6 0x0C98 +#define BGE_LOCSTATS_COS7 0x0C9C +#define BGE_LOCSTATS_COS8 0x0CA0 +#define BGE_LOCSTATS_COS9 0x0CA4 +#define BGE_LOCSTATS_COS10 0x0CA8 +#define BGE_LOCSTATS_COS11 0x0CAC +#define BGE_LOCSTATS_COS12 0x0CB0 +#define BGE_LOCSTATS_COS13 0x0CB4 +#define BGE_LOCSTATS_COS14 0x0CB8 +#define BGE_LOCSTATS_COS15 0x0CBC +#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 +#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 +#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 +#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC +#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 +#define BGE_LOCSTATS_IRQS 0x0CD4 +#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 +#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC + +/* Send Data Initiator mode register */ +#define BGE_SDIMODE_RESET 0x00000001 +#define BGE_SDIMODE_ENABLE 0x00000002 +#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 +#define BGE_SDIMODE_HW_LSO_PRE_DMA 0x00000008 + +/* Send Data Initiator stats register */ +#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 + +/* Send Data Initiator stats control register */ +#define BGE_SDISTATSCTL_ENABLE 0x00000001 +#define BGE_SDISTATSCTL_FASTER 0x00000002 +#define BGE_SDISTATSCTL_CLEAR 0x00000004 +#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 +#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 + +/* + * Send Data Completion Control registers + */ +#define BGE_SDC_MODE 0x1000 +#define BGE_SDC_STATUS 0x1004 + +/* Send Data completion mode register */ +#define BGE_SDCMODE_RESET 0x00000001 +#define BGE_SDCMODE_ENABLE 0x00000002 +#define BGE_SDCMODE_ATTN 0x00000004 +#define BGE_SDCMODE_CDELAY 0x00000010 + +/* Send Data completion status register */ +#define BGE_SDCSTAT_ATTN 0x00000004 + +/* + * Send BD Ring Selector Control registers + */ +#define BGE_SRS_MODE 0x1400 +#define BGE_SRS_STATUS 0x1404 +#define BGE_SRS_HWDIAG 0x1408 +#define BGE_SRS_LOC_NIC_CONS0 0x1440 +#define BGE_SRS_LOC_NIC_CONS1 0x1444 +#define BGE_SRS_LOC_NIC_CONS2 0x1448 +#define BGE_SRS_LOC_NIC_CONS3 0x144C +#define BGE_SRS_LOC_NIC_CONS4 0x1450 +#define BGE_SRS_LOC_NIC_CONS5 0x1454 +#define BGE_SRS_LOC_NIC_CONS6 0x1458 +#define BGE_SRS_LOC_NIC_CONS7 0x145C +#define BGE_SRS_LOC_NIC_CONS8 0x1460 +#define BGE_SRS_LOC_NIC_CONS9 0x1464 +#define BGE_SRS_LOC_NIC_CONS10 0x1468 +#define BGE_SRS_LOC_NIC_CONS11 0x146C +#define BGE_SRS_LOC_NIC_CONS12 0x1470 +#define BGE_SRS_LOC_NIC_CONS13 0x1474 +#define BGE_SRS_LOC_NIC_CONS14 0x1478 +#define BGE_SRS_LOC_NIC_CONS15 0x147C + +/* Send BD Ring Selector Mode register */ +#define BGE_SRSMODE_RESET 0x00000001 +#define BGE_SRSMODE_ENABLE 0x00000002 +#define BGE_SRSMODE_ATTN 0x00000004 + +/* Send BD Ring Selector Status register */ +#define BGE_SRSSTAT_ERROR 0x00000004 + +/* Send BD Ring Selector HW Diagnostics register */ +#define BGE_SRSHWDIAG_STATE 0x0000000F +#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 +#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 +#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 + +/* + * Send BD Initiator Selector Control registers + */ +#define BGE_SBDI_MODE 0x1800 +#define BGE_SBDI_STATUS 0x1804 +#define BGE_SBDI_LOC_NIC_PROD0 0x1808 +#define BGE_SBDI_LOC_NIC_PROD1 0x180C +#define BGE_SBDI_LOC_NIC_PROD2 0x1810 +#define BGE_SBDI_LOC_NIC_PROD3 0x1814 +#define BGE_SBDI_LOC_NIC_PROD4 0x1818 +#define BGE_SBDI_LOC_NIC_PROD5 0x181C +#define BGE_SBDI_LOC_NIC_PROD6 0x1820 +#define BGE_SBDI_LOC_NIC_PROD7 0x1824 +#define BGE_SBDI_LOC_NIC_PROD8 0x1828 +#define BGE_SBDI_LOC_NIC_PROD9 0x182C +#define BGE_SBDI_LOC_NIC_PROD10 0x1830 +#define BGE_SBDI_LOC_NIC_PROD11 0x1834 +#define BGE_SBDI_LOC_NIC_PROD12 0x1838 +#define BGE_SBDI_LOC_NIC_PROD13 0x183C +#define BGE_SBDI_LOC_NIC_PROD14 0x1840 +#define BGE_SBDI_LOC_NIC_PROD15 0x1844 + +/* Send BD Initiator Mode register */ +#define BGE_SBDIMODE_RESET 0x00000001 +#define BGE_SBDIMODE_ENABLE 0x00000002 +#define BGE_SBDIMODE_ATTN 0x00000004 + +/* Send BD Initiator Status register */ +#define BGE_SBDISTAT_ERROR 0x00000004 + +/* + * Send BD Completion Control registers + */ +#define BGE_SBDC_MODE 0x1C00 +#define BGE_SBDC_STATUS 0x1C04 + +/* Send BD Completion Control Mode register */ +#define BGE_SBDCMODE_RESET 0x00000001 +#define BGE_SBDCMODE_ENABLE 0x00000002 +#define BGE_SBDCMODE_ATTN 0x00000004 + +/* Send BD Completion Control Status register */ +#define BGE_SBDCSTAT_ATTN 0x00000004 + +/* + * Receive List Placement Control registers + */ +#define BGE_RXLP_MODE 0x2000 +#define BGE_RXLP_STATUS 0x2004 +#define BGE_RXLP_SEL_LIST_LOCK 0x2008 +#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C +#define BGE_RXLP_CFG 0x2010 +#define BGE_RXLP_STATS_CTL 0x2014 +#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 +#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C +#define BGE_RXLP_HEAD0 0x2100 +#define BGE_RXLP_TAIL0 0x2104 +#define BGE_RXLP_COUNT0 0x2108 +#define BGE_RXLP_HEAD1 0x2110 +#define BGE_RXLP_TAIL1 0x2114 +#define BGE_RXLP_COUNT1 0x2118 +#define BGE_RXLP_HEAD2 0x2120 +#define BGE_RXLP_TAIL2 0x2124 +#define BGE_RXLP_COUNT2 0x2128 +#define BGE_RXLP_HEAD3 0x2130 +#define BGE_RXLP_TAIL3 0x2134 +#define BGE_RXLP_COUNT3 0x2138 +#define BGE_RXLP_HEAD4 0x2140 +#define BGE_RXLP_TAIL4 0x2144 +#define BGE_RXLP_COUNT4 0x2148 +#define BGE_RXLP_HEAD5 0x2150 +#define BGE_RXLP_TAIL5 0x2154 +#define BGE_RXLP_COUNT5 0x2158 +#define BGE_RXLP_HEAD6 0x2160 +#define BGE_RXLP_TAIL6 0x2164 +#define BGE_RXLP_COUNT6 0x2168 +#define BGE_RXLP_HEAD7 0x2170 +#define BGE_RXLP_TAIL7 0x2174 +#define BGE_RXLP_COUNT7 0x2178 +#define BGE_RXLP_HEAD8 0x2180 +#define BGE_RXLP_TAIL8 0x2184 +#define BGE_RXLP_COUNT8 0x2188 +#define BGE_RXLP_HEAD9 0x2190 +#define BGE_RXLP_TAIL9 0x2194 +#define BGE_RXLP_COUNT9 0x2198 +#define BGE_RXLP_HEAD10 0x21A0 +#define BGE_RXLP_TAIL10 0x21A4 +#define BGE_RXLP_COUNT10 0x21A8 +#define BGE_RXLP_HEAD11 0x21B0 +#define BGE_RXLP_TAIL11 0x21B4 +#define BGE_RXLP_COUNT11 0x21B8 +#define BGE_RXLP_HEAD12 0x21C0 +#define BGE_RXLP_TAIL12 0x21C4 +#define BGE_RXLP_COUNT12 0x21C8 +#define BGE_RXLP_HEAD13 0x21D0 +#define BGE_RXLP_TAIL13 0x21D4 +#define BGE_RXLP_COUNT13 0x21D8 +#define BGE_RXLP_HEAD14 0x21E0 +#define BGE_RXLP_TAIL14 0x21E4 +#define BGE_RXLP_COUNT14 0x21E8 +#define BGE_RXLP_HEAD15 0x21F0 +#define BGE_RXLP_TAIL15 0x21F4 +#define BGE_RXLP_COUNT15 0x21F8 +#define BGE_RXLP_LOCSTAT_COS0 0x2200 +#define BGE_RXLP_LOCSTAT_COS1 0x2204 +#define BGE_RXLP_LOCSTAT_COS2 0x2208 +#define BGE_RXLP_LOCSTAT_COS3 0x220C +#define BGE_RXLP_LOCSTAT_COS4 0x2210 +#define BGE_RXLP_LOCSTAT_COS5 0x2214 +#define BGE_RXLP_LOCSTAT_COS6 0x2218 +#define BGE_RXLP_LOCSTAT_COS7 0x221C +#define BGE_RXLP_LOCSTAT_COS8 0x2220 +#define BGE_RXLP_LOCSTAT_COS9 0x2224 +#define BGE_RXLP_LOCSTAT_COS10 0x2228 +#define BGE_RXLP_LOCSTAT_COS11 0x222C +#define BGE_RXLP_LOCSTAT_COS12 0x2230 +#define BGE_RXLP_LOCSTAT_COS13 0x2234 +#define BGE_RXLP_LOCSTAT_COS14 0x2238 +#define BGE_RXLP_LOCSTAT_COS15 0x223C +#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 +#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 +#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 +#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C +#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 +#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 +#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 + + +/* Receive List Placement mode register */ +#define BGE_RXLPMODE_RESET 0x00000001 +#define BGE_RXLPMODE_ENABLE 0x00000002 +#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 +#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 +#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 + +/* Receive List Placement Status register */ +#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 +#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 +#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 + +/* + * Receive Data and Receive BD Initiator Control Registers + */ +#define BGE_RDBDI_MODE 0x2400 +#define BGE_RDBDI_STATUS 0x2404 +#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 +#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 +#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 +#define BGE_RX_JUMBO_RCB_NICADDR 0x244C +#define BGE_RX_STD_RCB_HADDR_HI 0x2450 +#define BGE_RX_STD_RCB_HADDR_LO 0x2454 +#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 +#define BGE_RX_STD_RCB_NICADDR 0x245C +#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 +#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 +#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 +#define BGE_RX_MINI_RCB_NICADDR 0x246C +#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 +#define BGE_RDBDI_STD_RX_CONS 0x2474 +#define BGE_RDBDI_MINI_RX_CONS 0x2478 +#define BGE_RDBDI_RETURN_PROD0 0x2480 +#define BGE_RDBDI_RETURN_PROD1 0x2484 +#define BGE_RDBDI_RETURN_PROD2 0x2488 +#define BGE_RDBDI_RETURN_PROD3 0x248C +#define BGE_RDBDI_RETURN_PROD4 0x2490 +#define BGE_RDBDI_RETURN_PROD5 0x2494 +#define BGE_RDBDI_RETURN_PROD6 0x2498 +#define BGE_RDBDI_RETURN_PROD7 0x249C +#define BGE_RDBDI_RETURN_PROD8 0x24A0 +#define BGE_RDBDI_RETURN_PROD9 0x24A4 +#define BGE_RDBDI_RETURN_PROD10 0x24A8 +#define BGE_RDBDI_RETURN_PROD11 0x24AC +#define BGE_RDBDI_RETURN_PROD12 0x24B0 +#define BGE_RDBDI_RETURN_PROD13 0x24B4 +#define BGE_RDBDI_RETURN_PROD14 0x24B8 +#define BGE_RDBDI_RETURN_PROD15 0x24BC +#define BGE_RDBDI_HWDIAG 0x24C0 + + +/* Receive Data and Receive BD Initiator Mode register */ +#define BGE_RDBDIMODE_RESET 0x00000001 +#define BGE_RDBDIMODE_ENABLE 0x00000002 +#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 +#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 +#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 + +/* Receive Data and Receive BD Initiator Status register */ +#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 +#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 +#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 + + +/* + * Receive Data Completion Control registers + */ +#define BGE_RDC_MODE 0x2800 + +/* Receive Data Completion Mode register */ +#define BGE_RDCMODE_RESET 0x00000001 +#define BGE_RDCMODE_ENABLE 0x00000002 +#define BGE_RDCMODE_ATTN 0x00000004 + +/* + * Receive BD Initiator Control registers + */ +#define BGE_RBDI_MODE 0x2C00 +#define BGE_RBDI_STATUS 0x2C04 +#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 +#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C +#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 +#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 +#define BGE_RBDI_STD_REPL_THRESH 0x2C18 +#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C + +#define BGE_STD_REPLENISH_LWM 0x2D00 +#define BGE_JMB_REPLENISH_LWM 0x2D04 + +/* Receive BD Initiator Mode register */ +#define BGE_RBDIMODE_RESET 0x00000001 +#define BGE_RBDIMODE_ENABLE 0x00000002 +#define BGE_RBDIMODE_ATTN 0x00000004 + +/* Receive BD Initiator Status register */ +#define BGE_RBDISTAT_ATTN 0x00000004 + +/* + * Receive BD Completion Control registers + */ +#define BGE_RBDC_MODE 0x3000 +#define BGE_RBDC_STATUS 0x3004 +#define BGE_RBDC_JUMBO_BD_PROD 0x3008 +#define BGE_RBDC_STD_BD_PROD 0x300C +#define BGE_RBDC_MINI_BD_PROD 0x3010 + +/* Receive BD completion mode register */ +#define BGE_RBDCMODE_RESET 0x00000001 +#define BGE_RBDCMODE_ENABLE 0x00000002 +#define BGE_RBDCMODE_ATTN 0x00000004 + +/* Receive BD completion status register */ +#define BGE_RBDCSTAT_ERROR 0x00000004 + +/* + * Receive List Selector Control registers + */ +#define BGE_RXLS_MODE 0x3400 +#define BGE_RXLS_STATUS 0x3404 + +/* Receive List Selector Mode register */ +#define BGE_RXLSMODE_RESET 0x00000001 +#define BGE_RXLSMODE_ENABLE 0x00000002 +#define BGE_RXLSMODE_ATTN 0x00000004 + +/* Receive List Selector Status register */ +#define BGE_RXLSSTAT_ERROR 0x00000004 + +#define BGE_CPMU_CTRL 0x3600 +#define BGE_CPMU_LSPD_10MB_CLK 0x3604 +#define BGE_CPMU_LSPD_1000MB_CLK 0x360C +#define BGE_CPMU_LNK_AWARE_PWRMD 0x3610 +#define BGE_CPMU_HST_ACC 0x361C +#define BGE_CPMU_CLCK_STAT 0x3630 +#define BGE_CPMU_MUTEX_REQ 0x365C +#define BGE_CPMU_MUTEX_GNT 0x3660 +#define BGE_CPMU_PHY_STRAP 0x3664 + +/* Central Power Management Unit (CPMU) register */ +#define BGE_CPMU_CTRL_LINK_IDLE_MODE 0x00000200 +#define BGE_CPMU_CTRL_LINK_AWARE_MODE 0x00000400 +#define BGE_CPMU_CTRL_LINK_SPEED_MODE 0x00004000 +#define BGE_CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000 + +/* Link Speed 10MB/No Link Power Mode Clock Policy register */ +#define BGE_CPMU_LSPD_10MB_MACCLK_MASK 0x001F0000 +#define BGE_CPMU_LSPD_10MB_MACCLK_6_25 0x00130000 + +/* Link Speed 1000MB Power Mode Clock Policy register */ +#define BGE_CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000 +#define BGE_CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000 +#define BGE_CPMU_LSPD_1000MB_MACCLK_MASK 0x001F0000 + +/* Link Aware Power Mode Clock Policy register */ +#define BGE_CPMU_LNK_AWARE_MACCLK_MASK 0x001F0000 +#define BGE_CPMU_LNK_AWARE_MACCLK_6_25 0x00130000 + +#define BGE_CPMU_HST_ACC_MACCLK_MASK 0x001F0000 +#define BGE_CPMU_HST_ACC_MACCLK_6_25 0x00130000 + +/* CPMU Clock Status register */ +#define BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001F0000 +#define BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000 +#define BGE_CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000 +#define BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000 + +/* CPMU Mutex Request register */ +#define BGE_CPMU_MUTEX_REQ_DRIVER 0x00001000 +#define BGE_CPMU_MUTEX_GNT_DRIVER 0x00001000 + +/* CPMU GPHY Strap register */ +#define BGE_CPMU_PHY_STRAP_IS_SERDES 0x00000020 + +/* + * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) + */ +#define BGE_MBCF_MODE 0x3800 +#define BGE_MBCF_STATUS 0x3804 + +/* Mbuf Cluster Free mode register */ +#define BGE_MBCFMODE_RESET 0x00000001 +#define BGE_MBCFMODE_ENABLE 0x00000002 +#define BGE_MBCFMODE_ATTN 0x00000004 + +/* Mbuf Cluster Free status register */ +#define BGE_MBCFSTAT_ERROR 0x00000004 + +/* + * Host Coalescing Control registers + */ +#define BGE_HCC_MODE 0x3C00 +#define BGE_HCC_STATUS 0x3C04 +#define BGE_HCC_RX_COAL_TICKS 0x3C08 +#define BGE_HCC_TX_COAL_TICKS 0x3C0C +#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 +#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 +#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ +#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ +#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ +#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ +#define BGE_HCC_STATS_TICKS 0x3C28 +#define BGE_HCC_STATS_ADDR_HI 0x3C30 +#define BGE_HCC_STATS_ADDR_LO 0x3C34 +#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 +#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C +#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ +#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ +#define BGE_FLOW_ATTN 0x3C48 +#define BGE_HCC_JUMBO_BD_CONS 0x3C50 +#define BGE_HCC_STD_BD_CONS 0x3C54 +#define BGE_HCC_MINI_BD_CONS 0x3C58 +#define BGE_HCC_RX_RETURN_PROD0 0x3C80 +#define BGE_HCC_RX_RETURN_PROD1 0x3C84 +#define BGE_HCC_RX_RETURN_PROD2 0x3C88 +#define BGE_HCC_RX_RETURN_PROD3 0x3C8C +#define BGE_HCC_RX_RETURN_PROD4 0x3C90 +#define BGE_HCC_RX_RETURN_PROD5 0x3C94 +#define BGE_HCC_RX_RETURN_PROD6 0x3C98 +#define BGE_HCC_RX_RETURN_PROD7 0x3C9C +#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 +#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 +#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 +#define BGE_HCC_RX_RETURN_PROD11 0x3CAC +#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 +#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 +#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 +#define BGE_HCC_RX_RETURN_PROD15 0x3CBC +#define BGE_HCC_TX_BD_CONS0 0x3CC0 +#define BGE_HCC_TX_BD_CONS1 0x3CC4 +#define BGE_HCC_TX_BD_CONS2 0x3CC8 +#define BGE_HCC_TX_BD_CONS3 0x3CCC +#define BGE_HCC_TX_BD_CONS4 0x3CD0 +#define BGE_HCC_TX_BD_CONS5 0x3CD4 +#define BGE_HCC_TX_BD_CONS6 0x3CD8 +#define BGE_HCC_TX_BD_CONS7 0x3CDC +#define BGE_HCC_TX_BD_CONS8 0x3CE0 +#define BGE_HCC_TX_BD_CONS9 0x3CE4 +#define BGE_HCC_TX_BD_CONS10 0x3CE8 +#define BGE_HCC_TX_BD_CONS11 0x3CEC +#define BGE_HCC_TX_BD_CONS12 0x3CF0 +#define BGE_HCC_TX_BD_CONS13 0x3CF4 +#define BGE_HCC_TX_BD_CONS14 0x3CF8 +#define BGE_HCC_TX_BD_CONS15 0x3CFC + + +/* Host coalescing mode register */ +#define BGE_HCCMODE_RESET 0x00000001 +#define BGE_HCCMODE_ENABLE 0x00000002 +#define BGE_HCCMODE_ATTN 0x00000004 +#define BGE_HCCMODE_COAL_NOW 0x00000008 +#define BGE_HCCMODE_MSI_BITS 0x00000070 +#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 + +#define BGE_STATBLKSZ_FULL 0x00000000 +#define BGE_STATBLKSZ_64BYTE 0x00000080 +#define BGE_STATBLKSZ_32BYTE 0x00000100 + +/* Host coalescing status register */ +#define BGE_HCCSTAT_ERROR 0x00000004 + +/* Flow attention register */ +#define BGE_FLOWATTN_MB_LOWAT 0x00000040 +#define BGE_FLOWATTN_MEMARB 0x00000080 +#define BGE_FLOWATTN_HOSTCOAL 0x00008000 +#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 +#define BGE_FLOWATTN_RCB_INVAL 0x00020000 +#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 +#define BGE_FLOWATTN_RDBDI 0x00080000 +#define BGE_FLOWATTN_RXLS 0x00100000 +#define BGE_FLOWATTN_RXLP 0x00200000 +#define BGE_FLOWATTN_RBDC 0x00400000 +#define BGE_FLOWATTN_RBDI 0x00800000 +#define BGE_FLOWATTN_SDC 0x08000000 +#define BGE_FLOWATTN_SDI 0x10000000 +#define BGE_FLOWATTN_SRS 0x20000000 +#define BGE_FLOWATTN_SBDC 0x40000000 +#define BGE_FLOWATTN_SBDI 0x80000000 + +/* + * Memory arbiter registers + */ +#define BGE_MARB_MODE 0x4000 +#define BGE_MARB_STATUS 0x4004 +#define BGE_MARB_TRAPADDR_HI 0x4008 +#define BGE_MARB_TRAPADDR_LO 0x400C + +/* Memory arbiter mode register */ +#define BGE_MARBMODE_RESET 0x00000001 +#define BGE_MARBMODE_ENABLE 0x00000002 +#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 +#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 +#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 +#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 +#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 +#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 +#define BGE_MARBMODE_PCI_TRAP 0x00000100 +#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 +#define BGE_MARBMODE_RXQ_TRAP 0x00000400 +#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 +#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 +#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 +#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 +#define BGE_MARBMODE_MBUF_TRAP 0x00008000 +#define BGE_MARBMODE_TXDI_TRAP 0x00010000 +#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 +#define BGE_MARBMODE_TXBD_TRAP 0x00040000 +#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 +#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 +#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 +#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 +#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 +#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 +#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 + +/* Memory arbiter status register */ +#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 +#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 +#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 +#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 +#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 +#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 +#define BGE_MARBSTAT_PCI_TRAP 0x00000100 +#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 +#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 +#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 +#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 +#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 +#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 +#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 +#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 +#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 +#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 +#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 +#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 +#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 +#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 +#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 +#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 +#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 + +/* + * Buffer manager control registers + */ +#define BGE_BMAN_MODE 0x4400 +#define BGE_BMAN_STATUS 0x4404 +#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 +#define BGE_BMAN_MBUFPOOL_LEN 0x440C +#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 +#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 +#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 +#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C +#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 +#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 +#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 +#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C +#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 +#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 +#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 +#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C +#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 +#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 +#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 +#define BGE_BMAN_HWDIAG_1 0x444C +#define BGE_BMAN_HWDIAG_2 0x4450 +#define BGE_BMAN_HWDIAG_3 0x4454 + +/* Buffer manager mode register */ +#define BGE_BMANMODE_RESET 0x00000001 +#define BGE_BMANMODE_ENABLE 0x00000002 +#define BGE_BMANMODE_ATTN 0x00000004 +#define BGE_BMANMODE_TESTMODE 0x00000008 +#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 + +/* Buffer manager status register */ +#define BGE_BMANSTAT_ERRO 0x00000004 +#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 + + +/* + * Read DMA Control registers + */ +#define BGE_RDMA_MODE 0x4800 +#define BGE_RDMA_STATUS 0x4804 +#define BGE_RDMA_RSRVCTRL 0x4900 + +/* Read DMA mode register */ +#define BGE_RDMAMODE_RESET 0x00000001 +#define BGE_RDMAMODE_ENABLE 0x00000002 +#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 +#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 +#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 +#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 +#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 +#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 +#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 +#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 +#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC +#define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800 +#define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000 +#define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000 +#define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000 +#define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000 +#define BGE_RDMAMODE_MULT_DMA_RD_DIS 0x01000000 +#define BGE_RDMAMODE_TSO4_ENABLE 0x08000000 +#define BGE_RDMAMODE_TSO6_ENABLE 0x10000000 + +/* Read DMA status register */ +#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 +#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 +#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 +#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 +#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 +#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 +#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 +#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 + +/* Read DMA Reserved Control register */ +#define BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004 + +/* + * Write DMA control registers + */ +#define BGE_WDMA_MODE 0x4C00 +#define BGE_WDMA_STATUS 0x4C04 + +/* Write DMA mode register */ +#define BGE_WDMAMODE_RESET 0x00000001 +#define BGE_WDMAMODE_ENABLE 0x00000002 +#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 +#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 +#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 +#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 +#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 +#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 +#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 +#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 +#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC +#define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000 +#define BGE_WDMAMODE_BURST_ALL_DATA 0xC0000000 + +/* Write DMA status register */ +#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 +#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 +#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 +#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 +#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 +#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 +#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 +#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 + + +/* + * RX CPU registers + */ +#define BGE_RXCPU_MODE 0x5000 +#define BGE_RXCPU_STATUS 0x5004 +#define BGE_RXCPU_PC 0x501C + +/* RX CPU mode register */ +#define BGE_RXCPUMODE_RESET 0x00000001 +#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 +#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 +#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 +#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 +#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 +#define BGE_RXCPUMODE_ROMFAIL 0x00000040 +#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 +#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 +#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 +#define BGE_RXCPUMODE_HALTCPU 0x00000400 +#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 +#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 +#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 + +/* RX CPU status register */ +#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 +#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 +#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 +#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 +#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 +#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 +#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 +#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 +#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 +#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 +#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 +#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 +#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 +#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 +#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 +#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 +#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 + +/* + * V? CPU registers + */ +#define BGE_VCPU_STATUS 0x5100 +#define BGE_VCPU_EXT_CTRL 0x6890 + +#define BGE_VCPU_STATUS_INIT_DONE 0x04000000 +#define BGE_VCPU_STATUS_DRV_RESET 0x08000000 + +#define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000 +#define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 + +/* + * TX CPU registers + */ +#define BGE_TXCPU_MODE 0x5400 +#define BGE_TXCPU_STATUS 0x5404 +#define BGE_TXCPU_PC 0x541C + +/* TX CPU mode register */ +#define BGE_TXCPUMODE_RESET 0x00000001 +#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 +#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 +#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 +#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 +#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 +#define BGE_TXCPUMODE_ROMFAIL 0x00000040 +#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 +#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 +#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 +#define BGE_TXCPUMODE_HALTCPU 0x00000400 +#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 +#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 + +/* TX CPU status register */ +#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 +#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 +#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 +#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 +#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 +#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 +#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 +#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 +#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 +#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 +#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 +#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 +#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 +#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 +#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 +#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 +#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 + + +/* + * Low priority mailbox registers + */ +#define BGE_LPMBX_IRQ0_HI 0x5800 +#define BGE_LPMBX_IRQ0_LO 0x5804 +#define BGE_LPMBX_IRQ1_HI 0x5808 +#define BGE_LPMBX_IRQ1_LO 0x580C +#define BGE_LPMBX_IRQ2_HI 0x5810 +#define BGE_LPMBX_IRQ2_LO 0x5814 +#define BGE_LPMBX_IRQ3_HI 0x5818 +#define BGE_LPMBX_IRQ3_LO 0x581C +#define BGE_LPMBX_GEN0_HI 0x5820 +#define BGE_LPMBX_GEN0_LO 0x5824 +#define BGE_LPMBX_GEN1_HI 0x5828 +#define BGE_LPMBX_GEN1_LO 0x582C +#define BGE_LPMBX_GEN2_HI 0x5830 +#define BGE_LPMBX_GEN2_LO 0x5834 +#define BGE_LPMBX_GEN3_HI 0x5828 +#define BGE_LPMBX_GEN3_LO 0x582C +#define BGE_LPMBX_GEN4_HI 0x5840 +#define BGE_LPMBX_GEN4_LO 0x5844 +#define BGE_LPMBX_GEN5_HI 0x5848 +#define BGE_LPMBX_GEN5_LO 0x584C +#define BGE_LPMBX_GEN6_HI 0x5850 +#define BGE_LPMBX_GEN6_LO 0x5854 +#define BGE_LPMBX_GEN7_HI 0x5858 +#define BGE_LPMBX_GEN7_LO 0x585C +#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 +#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 +#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 +#define BGE_LPMBX_RX_STD_PROD_LO 0x586C +#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 +#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 +#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 +#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C +#define BGE_LPMBX_RX_CONS0_HI 0x5880 +#define BGE_LPMBX_RX_CONS0_LO 0x5884 +#define BGE_LPMBX_RX_CONS1_HI 0x5888 +#define BGE_LPMBX_RX_CONS1_LO 0x588C +#define BGE_LPMBX_RX_CONS2_HI 0x5890 +#define BGE_LPMBX_RX_CONS2_LO 0x5894 +#define BGE_LPMBX_RX_CONS3_HI 0x5898 +#define BGE_LPMBX_RX_CONS3_LO 0x589C +#define BGE_LPMBX_RX_CONS4_HI 0x58A0 +#define BGE_LPMBX_RX_CONS4_LO 0x58A4 +#define BGE_LPMBX_RX_CONS5_HI 0x58A8 +#define BGE_LPMBX_RX_CONS5_LO 0x58AC +#define BGE_LPMBX_RX_CONS6_HI 0x58B0 +#define BGE_LPMBX_RX_CONS6_LO 0x58B4 +#define BGE_LPMBX_RX_CONS7_HI 0x58B8 +#define BGE_LPMBX_RX_CONS7_LO 0x58BC +#define BGE_LPMBX_RX_CONS8_HI 0x58C0 +#define BGE_LPMBX_RX_CONS8_LO 0x58C4 +#define BGE_LPMBX_RX_CONS9_HI 0x58C8 +#define BGE_LPMBX_RX_CONS9_LO 0x58CC +#define BGE_LPMBX_RX_CONS10_HI 0x58D0 +#define BGE_LPMBX_RX_CONS10_LO 0x58D4 +#define BGE_LPMBX_RX_CONS11_HI 0x58D8 +#define BGE_LPMBX_RX_CONS11_LO 0x58DC +#define BGE_LPMBX_RX_CONS12_HI 0x58E0 +#define BGE_LPMBX_RX_CONS12_LO 0x58E4 +#define BGE_LPMBX_RX_CONS13_HI 0x58E8 +#define BGE_LPMBX_RX_CONS13_LO 0x58EC +#define BGE_LPMBX_RX_CONS14_HI 0x58F0 +#define BGE_LPMBX_RX_CONS14_LO 0x58F4 +#define BGE_LPMBX_RX_CONS15_HI 0x58F8 +#define BGE_LPMBX_RX_CONS15_LO 0x58FC +#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 +#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 +#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 +#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C +#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 +#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 +#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 +#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C +#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 +#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 +#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 +#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C +#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 +#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 +#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 +#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C +#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 +#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 +#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 +#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C +#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 +#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 +#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 +#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C +#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 +#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 +#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 +#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C +#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 +#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 +#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 +#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C +#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 +#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 +#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 +#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C +#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 +#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 +#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 +#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C +#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 +#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 +#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 +#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC +#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 +#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 +#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 +#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC +#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 +#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 +#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 +#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC +#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 +#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 +#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 +#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC +#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 +#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 +#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 +#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC +#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 +#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 +#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 +#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC + +/* + * Flow throw Queue reset register + */ +#define BGE_FTQ_RESET 0x5C00 + +#define BGE_FTQRESET_DMAREAD 0x00000002 +#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 +#define BGE_FTQRESET_DMADONE 0x00000010 +#define BGE_FTQRESET_SBDC 0x00000020 +#define BGE_FTQRESET_SDI 0x00000040 +#define BGE_FTQRESET_WDMA 0x00000080 +#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 +#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 +#define BGE_FTQRESET_SDC 0x00000400 +#define BGE_FTQRESET_HCC 0x00000800 +#define BGE_FTQRESET_TXFIFO 0x00001000 +#define BGE_FTQRESET_MBC 0x00002000 +#define BGE_FTQRESET_RBDC 0x00004000 +#define BGE_FTQRESET_RXLP 0x00008000 +#define BGE_FTQRESET_RDBDI 0x00010000 +#define BGE_FTQRESET_RDC 0x00020000 +#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 + +/* + * Message Signaled Interrupt registers + */ +#define BGE_MSI_MODE 0x6000 +#define BGE_MSI_STATUS 0x6004 +#define BGE_MSI_FIFOACCESS 0x6008 + +/* MSI mode register */ +#define BGE_MSIMODE_RESET 0x00000001 +#define BGE_MSIMODE_ENABLE 0x00000002 +#define BGE_MSIMODE_ONE_SHOT_DISABLE 0x00000020 +#define BGE_MSIMODE_MULTIVEC_ENABLE 0x00000080 + +/* MSI status register */ +#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 +#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 +#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 +#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 +#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 + + +/* + * DMA Completion registers + */ +#define BGE_DMAC_MODE 0x6400 + +/* DMA Completion mode register */ +#define BGE_DMACMODE_RESET 0x00000001 +#define BGE_DMACMODE_ENABLE 0x00000002 + + +/* + * General control registers. + */ +#define BGE_MODE_CTL 0x6800 +#define BGE_MISC_CFG 0x6804 +#define BGE_MISC_LOCAL_CTL 0x6808 +#define BGE_CPU_EVENT 0x6810 +#define BGE_EE_ADDR 0x6838 +#define BGE_EE_DATA 0x683C +#define BGE_EE_CTL 0x6840 +#define BGE_MDI_CTL 0x6844 +#define BGE_EE_DELAY 0x6848 +#define BGE_FASTBOOT_PC 0x6894 + +/* + * NVRAM Control registers + */ +#define BGE_NVRAM_CMD 0x7000 +#define BGE_NVRAM_STAT 0x7004 +#define BGE_NVRAM_WRDATA 0x7008 +#define BGE_NVRAM_ADDR 0x700c +#define BGE_NVRAM_RDDATA 0x7010 +#define BGE_NVRAM_CFG1 0x7014 +#define BGE_NVRAM_CFG2 0x7018 +#define BGE_NVRAM_CFG3 0x701c +#define BGE_NVRAM_SWARB 0x7020 +#define BGE_NVRAM_ACCESS 0x7024 +#define BGE_NVRAM_WRITE1 0x7028 + +#define BGE_NVRAMCMD_RESET 0x00000001 +#define BGE_NVRAMCMD_DONE 0x00000008 +#define BGE_NVRAMCMD_START 0x00000010 +#define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd */ +#define BGE_NVRAMCMD_ERASE 0x00000040 +#define BGE_NVRAMCMD_FIRST 0x00000080 +#define BGE_NVRAMCMD_LAST 0x00000100 + +#define BGE_NVRAM_READCMD \ + (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ + BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE) +#define BGE_NVRAM_WRITECMD \ + (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ + BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE|BGE_NVRAMCMD_WR) + +#define BGE_NVRAMSWARB_SET0 0x00000001 +#define BGE_NVRAMSWARB_SET1 0x00000002 +#define BGE_NVRAMSWARB_SET2 0x00000003 +#define BGE_NVRAMSWARB_SET3 0x00000004 +#define BGE_NVRAMSWARB_CLR0 0x00000010 +#define BGE_NVRAMSWARB_CLR1 0x00000020 +#define BGE_NVRAMSWARB_CLR2 0x00000040 +#define BGE_NVRAMSWARB_CLR3 0x00000080 +#define BGE_NVRAMSWARB_GNT0 0x00000100 +#define BGE_NVRAMSWARB_GNT1 0x00000200 +#define BGE_NVRAMSWARB_GNT2 0x00000400 +#define BGE_NVRAMSWARB_GNT3 0x00000800 +#define BGE_NVRAMSWARB_REQ0 0x00001000 +#define BGE_NVRAMSWARB_REQ1 0x00002000 +#define BGE_NVRAMSWARB_REQ2 0x00004000 +#define BGE_NVRAMSWARB_REQ3 0x00008000 + +#define BGE_NVRAMACC_ENABLE 0x00000001 +#define BGE_NVRAMACC_WRENABLE 0x00000002 + +/* Mode control register */ +#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 +#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 +#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 +#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 +#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 +#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 +#define BGE_MODECTL_NO_RX_CRC 0x00000400 +#define BGE_MODECTL_RX_BADFRAMES 0x00000800 +#define BGE_MODECTL_NO_TX_INTR 0x00002000 +#define BGE_MODECTL_NO_RX_INTR 0x00004000 +#define BGE_MODECTL_FORCE_PCI32 0x00008000 +#define BGE_MODECTL_STACKUP 0x00010000 +#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 +#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 +#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 +#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 +#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 +#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 +#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 +#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 +#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 +#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 + +/* Misc. config register */ +#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 +#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE +#define BGE_MISCCFG_BOARD_ID 0x0001E000 +#define BGE_MISCCFG_BOARD_ID_5788 0x00010000 +#define BGE_MISCCFG_BOARD_ID_5788M 0x00018000 +#define BGE_MISCCFG_EPHY_IDDQ 0x00200000 +#define BGE_MISCCFG_GPHY_PD_OVERRIDE 0x04000000 + +#define BGE_32BITTIME_66MHZ (0x41 << 1) + +/* Misc. Local Control */ +#define BGE_MLC_INTR_STATE 0x00000001 +#define BGE_MLC_INTR_CLR 0x00000002 +#define BGE_MLC_INTR_SET 0x00000004 +#define BGE_MLC_INTR_ONATTN 0x00000008 +#define BGE_MLC_MISCIO_IN0 0x00000100 +#define BGE_MLC_MISCIO_IN1 0x00000200 +#define BGE_MLC_MISCIO_IN2 0x00000400 +#define BGE_MLC_MISCIO_OUTEN0 0x00000800 +#define BGE_MLC_MISCIO_OUTEN1 0x00001000 +#define BGE_MLC_MISCIO_OUTEN2 0x00002000 +#define BGE_MLC_MISCIO_OUT0 0x00004000 +#define BGE_MLC_MISCIO_OUT1 0x00008000 +#define BGE_MLC_MISCIO_OUT2 0x00010000 +#define BGE_MLC_EXTRAM_ENB 0x00020000 +#define BGE_MLC_SRAM_SIZE 0x001C0000 +#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ +#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ +#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 +#define BGE_MLC_AUTO_EEPROM 0x01000000 + +#define BGE_SSRAMSIZE_256KB 0x00000000 +#define BGE_SSRAMSIZE_512KB 0x00040000 +#define BGE_SSRAMSIZE_1MB 0x00080000 +#define BGE_SSRAMSIZE_2MB 0x000C0000 +#define BGE_SSRAMSIZE_4MB 0x00100000 +#define BGE_SSRAMSIZE_8MB 0x00140000 +#define BGE_SSRAMSIZE_16M 0x00180000 + +/* EEPROM address register */ +#define BGE_EEADDR_ADDRESS 0x0000FFFC +#define BGE_EEADDR_HALFCLK 0x01FF0000 +#define BGE_EEADDR_START 0x02000000 +#define BGE_EEADDR_DEVID 0x1C000000 +#define BGE_EEADDR_RESET 0x20000000 +#define BGE_EEADDR_DONE 0x40000000 +#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ + +#define BGE_EEDEVID(x) ((x & 7) << 26) +#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) +#define BGE_HALFCLK_384SCL 0x60 +#define BGE_EE_READCMD \ + (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ + BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) +#define BGE_EE_WRCMD \ + (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ + BGE_EEADDR_START|BGE_EEADDR_DONE) + +/* EEPROM Control register */ +#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 +#define BGE_EECTL_CLKOUT 0x00000002 +#define BGE_EECTL_CLKIN 0x00000004 +#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 +#define BGE_EECTL_DATAOUT 0x00000010 +#define BGE_EECTL_DATAIN 0x00000020 + +/* MDI (MII/GMII) access register */ +#define BGE_MDI_DATA 0x00000001 +#define BGE_MDI_DIR 0x00000002 +#define BGE_MDI_SEL 0x00000004 +#define BGE_MDI_CLK 0x00000008 + +#define BGE_MEMWIN_START 0x00008000 +#define BGE_MEMWIN_END 0x0000FFFF + + +#define BGE_MEMWIN_READ(sc, x, val) \ + do { \ + pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ + (0xFFFF0000 & x), 4); \ + val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ + } while(0) + +#define BGE_MEMWIN_WRITE(sc, x, val) \ + do { \ + pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ + (0xFFFF0000 & x), 4); \ + CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ + } while(0) + +/* + * This magic number is written to the firmware mailbox at 0xb50 + * before a software reset is issued. After the internal firmware + * has completed its initialization it will write the opposite of + * this value, ~BGE_MAGIC_NUMBER, to the same location, allowing the + * driver to synchronize with the firmware. + */ +#define BGE_MAGIC_NUMBER 0x4B657654 + +typedef struct { + uint32_t bge_addr_hi; + uint32_t bge_addr_lo; +} bge_hostaddr; + +#define BGE_HOSTADDR(x, y) \ + do { \ + (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \ + (x).bge_addr_hi = ((uint64_t) (y) >> 32); \ + } while(0) + +#define BGE_ADDR_LO(y) \ + ((uint64_t) (y) & 0xFFFFFFFF) +#define BGE_ADDR_HI(y) \ + ((uint64_t) (y) >> 32) + +/* Ring control block structure */ +struct bge_rcb { + bge_hostaddr bge_hostaddr; + uint32_t bge_maxlen_flags; + uint32_t bge_nicaddr; +}; + +#define RCB_WRITE_4(sc, rcb, offset, val) \ + bus_write_4(sc->bge_res, rcb + offsetof(struct bge_rcb, offset), val) +#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) + +#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 +#define BGE_RCB_FLAG_RING_DISABLED 0x0002 + +struct bge_tx_bd { + bge_hostaddr bge_addr; +#if BYTE_ORDER == LITTLE_ENDIAN + uint16_t bge_flags; + uint16_t bge_len; + uint16_t bge_vlan_tag; + uint16_t bge_mss; +#else + uint16_t bge_len; + uint16_t bge_flags; + uint16_t bge_mss; + uint16_t bge_vlan_tag; +#endif +}; + +#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 +#define BGE_TXBDFLAG_IP_CSUM 0x0002 +#define BGE_TXBDFLAG_END 0x0004 +#define BGE_TXBDFLAG_IP_FRAG 0x0008 +#define BGE_TXBDFLAG_JUMBO_FRAME 0x0008 /* 5717 */ +#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 +#define BGE_TXBDFLAG_HDRLEN_BIT2 0x0010 /* 5717 */ +#define BGE_TXBDFLAG_SNAP 0x0020 /* 5717 */ +#define BGE_TXBDFLAG_VLAN_TAG 0x0040 +#define BGE_TXBDFLAG_COAL_NOW 0x0080 +#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 +#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 +#define BGE_TXBDFLAG_HDRLEN_BIT3 0x0400 /* 5717 */ +#define BGE_TXBDFLAG_HDRLEN_BIT4 0x0800 /* 5717 */ +#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 +#define BGE_TXBDFLAG_HDRLEN_BIT5 0x1000 /* 5717 */ +#define BGE_TXBDFLAG_HDRLEN_BIT6 0x2000 /* 5717 */ +#define BGE_TXBDFLAG_HDRLEN_BIT7 0x4000 /* 5717 */ +#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 +#define BGE_TXBDFLAG_NO_CRC 0x8000 + +#define BGE_TXBDFLAG_MSS_SIZE_MASK 0x3FFF /* 5717 */ +/* Bits [1:0] of the MSS header length. */ +#define BGE_TXBDFLAG_MSS_HDRLEN_MASK 0xC000 /* 5717 */ + +#define BGE_NIC_TXRING_ADDR(ringno, size) \ + BGE_SEND_RING_1_TO_4 + \ + ((ringno * sizeof(struct bge_tx_bd) * size) / 4) + +struct bge_rx_bd { + bge_hostaddr bge_addr; +#if BYTE_ORDER == LITTLE_ENDIAN + uint16_t bge_len; + uint16_t bge_idx; + uint16_t bge_flags; + uint16_t bge_type; + uint16_t bge_tcp_udp_csum; + uint16_t bge_ip_csum; + uint16_t bge_vlan_tag; + uint16_t bge_error_flag; +#else + uint16_t bge_idx; + uint16_t bge_len; + uint16_t bge_type; + uint16_t bge_flags; + uint16_t bge_ip_csum; + uint16_t bge_tcp_udp_csum; + uint16_t bge_error_flag; + uint16_t bge_vlan_tag; +#endif + uint32_t bge_rsvd; + uint32_t bge_opaque; +}; + +struct bge_extrx_bd { + bge_hostaddr bge_addr1; + bge_hostaddr bge_addr2; + bge_hostaddr bge_addr3; +#if BYTE_ORDER == LITTLE_ENDIAN + uint16_t bge_len2; + uint16_t bge_len1; + uint16_t bge_rsvd1; + uint16_t bge_len3; +#else + uint16_t bge_len1; + uint16_t bge_len2; + uint16_t bge_len3; + uint16_t bge_rsvd1; +#endif + bge_hostaddr bge_addr0; +#if BYTE_ORDER == LITTLE_ENDIAN + uint16_t bge_len0; + uint16_t bge_idx; + uint16_t bge_flags; + uint16_t bge_type; + uint16_t bge_tcp_udp_csum; + uint16_t bge_ip_csum; + uint16_t bge_vlan_tag; + uint16_t bge_error_flag; +#else + uint16_t bge_idx; + uint16_t bge_len0; + uint16_t bge_type; + uint16_t bge_flags; + uint16_t bge_ip_csum; + uint16_t bge_tcp_udp_csum; + uint16_t bge_error_flag; + uint16_t bge_vlan_tag; +#endif + uint32_t bge_rsvd0; + uint32_t bge_opaque; +}; + +#define BGE_RXBDFLAG_END 0x0004 +#define BGE_RXBDFLAG_JUMBO_RING 0x0020 +#define BGE_RXBDFLAG_VLAN_TAG 0x0040 +#define BGE_RXBDFLAG_ERROR 0x0400 +#define BGE_RXBDFLAG_MINI_RING 0x0800 +#define BGE_RXBDFLAG_IP_CSUM 0x1000 +#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 +#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 +#define BGE_RXBDFLAG_IPV6 0x8000 + +#define BGE_RXERRFLAG_BAD_CRC 0x0001 +#define BGE_RXERRFLAG_COLL_DETECT 0x0002 +#define BGE_RXERRFLAG_LINK_LOST 0x0004 +#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 +#define BGE_RXERRFLAG_MAC_ABORT 0x0010 +#define BGE_RXERRFLAG_RUNT 0x0020 +#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 +#define BGE_RXERRFLAG_GIANT 0x0080 +#define BGE_RXERRFLAG_IP_CSUM_NOK 0x1000 /* 5717 */ + +struct bge_sts_idx { +#if BYTE_ORDER == LITTLE_ENDIAN + uint16_t bge_rx_prod_idx; + uint16_t bge_tx_cons_idx; +#else + uint16_t bge_tx_cons_idx; + uint16_t bge_rx_prod_idx; +#endif +}; + +struct bge_status_block { + uint32_t bge_status; + uint32_t bge_status_tag; +#if BYTE_ORDER == LITTLE_ENDIAN + uint16_t bge_rx_jumbo_cons_idx; + uint16_t bge_rx_std_cons_idx; + uint16_t bge_rx_mini_cons_idx; + uint16_t bge_rsvd1; +#else + uint16_t bge_rx_std_cons_idx; + uint16_t bge_rx_jumbo_cons_idx; + uint16_t bge_rsvd1; + uint16_t bge_rx_mini_cons_idx; +#endif + struct bge_sts_idx bge_idx[16]; +}; + +#define BGE_STATFLAG_UPDATED 0x00000001 +#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 +#define BGE_STATFLAG_ERROR 0x00000004 + + +/* + * Broadcom Vendor ID + * (Note: the BCM570x still defaults to the Alteon PCI vendor ID + * even though they're now manufactured by Broadcom) + */ +#define BCOM_VENDORID 0x14E4 +#define BCOM_DEVICEID_BCM5700 0x1644 +#define BCOM_DEVICEID_BCM5701 0x1645 +#define BCOM_DEVICEID_BCM5702 0x1646 +#define BCOM_DEVICEID_BCM5702X 0x16A6 +#define BCOM_DEVICEID_BCM5702_ALT 0x16C6 +#define BCOM_DEVICEID_BCM5703 0x1647 +#define BCOM_DEVICEID_BCM5703X 0x16A7 +#define BCOM_DEVICEID_BCM5703_ALT 0x16C7 +#define BCOM_DEVICEID_BCM5704C 0x1648 +#define BCOM_DEVICEID_BCM5704S 0x16A8 +#define BCOM_DEVICEID_BCM5704S_ALT 0x1649 +#define BCOM_DEVICEID_BCM5705 0x1653 +#define BCOM_DEVICEID_BCM5705K 0x1654 +#define BCOM_DEVICEID_BCM5705F 0x166E +#define BCOM_DEVICEID_BCM5705M 0x165D +#define BCOM_DEVICEID_BCM5705M_ALT 0x165E +#define BCOM_DEVICEID_BCM5714C 0x1668 +#define BCOM_DEVICEID_BCM5714S 0x1669 +#define BCOM_DEVICEID_BCM5715 0x1678 +#define BCOM_DEVICEID_BCM5715S 0x1679 +#define BCOM_DEVICEID_BCM5717 0x1655 +#define BCOM_DEVICEID_BCM5718 0x1656 +#define BCOM_DEVICEID_BCM5720 0x1658 +#define BCOM_DEVICEID_BCM5721 0x1659 +#define BCOM_DEVICEID_BCM5722 0x165A +#define BCOM_DEVICEID_BCM5723 0x165B +#define BCOM_DEVICEID_BCM5750 0x1676 +#define BCOM_DEVICEID_BCM5750M 0x167C +#define BCOM_DEVICEID_BCM5751 0x1677 +#define BCOM_DEVICEID_BCM5751F 0x167E +#define BCOM_DEVICEID_BCM5751M 0x167D +#define BCOM_DEVICEID_BCM5752 0x1600 +#define BCOM_DEVICEID_BCM5752M 0x1601 +#define BCOM_DEVICEID_BCM5753 0x16F7 +#define BCOM_DEVICEID_BCM5753F 0x16FE +#define BCOM_DEVICEID_BCM5753M 0x16FD +#define BCOM_DEVICEID_BCM5754 0x167A +#define BCOM_DEVICEID_BCM5754M 0x1672 +#define BCOM_DEVICEID_BCM5755 0x167B +#define BCOM_DEVICEID_BCM5755M 0x1673 +#define BCOM_DEVICEID_BCM5756 0x1674 +#define BCOM_DEVICEID_BCM5761 0x1681 +#define BCOM_DEVICEID_BCM5761E 0x1680 +#define BCOM_DEVICEID_BCM5761S 0x1688 +#define BCOM_DEVICEID_BCM5761SE 0x1689 +#define BCOM_DEVICEID_BCM5764 0x1684 +#define BCOM_DEVICEID_BCM5780 0x166A +#define BCOM_DEVICEID_BCM5780S 0x166B +#define BCOM_DEVICEID_BCM5781 0x16DD +#define BCOM_DEVICEID_BCM5782 0x1696 +#define BCOM_DEVICEID_BCM5784 0x1698 +#define BCOM_DEVICEID_BCM5785F 0x16a0 +#define BCOM_DEVICEID_BCM5785G 0x1699 +#define BCOM_DEVICEID_BCM5786 0x169A +#define BCOM_DEVICEID_BCM5787 0x169B +#define BCOM_DEVICEID_BCM5787M 0x1693 +#define BCOM_DEVICEID_BCM5787F 0x167f +#define BCOM_DEVICEID_BCM5788 0x169C +#define BCOM_DEVICEID_BCM5789 0x169D +#define BCOM_DEVICEID_BCM5901 0x170D +#define BCOM_DEVICEID_BCM5901A2 0x170E +#define BCOM_DEVICEID_BCM5903M 0x16FF +#define BCOM_DEVICEID_BCM5906 0x1712 +#define BCOM_DEVICEID_BCM5906M 0x1713 +#define BCOM_DEVICEID_BCM57760 0x1690 +#define BCOM_DEVICEID_BCM57780 0x1692 +#define BCOM_DEVICEID_BCM57788 0x1691 +#define BCOM_DEVICEID_BCM57790 0x1694 + +/* + * Alteon AceNIC PCI vendor/device ID. + */ +#define ALTEON_VENDORID 0x12AE +#define ALTEON_DEVICEID_ACENIC 0x0001 +#define ALTEON_DEVICEID_ACENIC_COPPER 0x0002 +#define ALTEON_DEVICEID_BCM5700 0x0003 +#define ALTEON_DEVICEID_BCM5701 0x0004 + +/* + * 3Com 3c996 PCI vendor/device ID. + */ +#define TC_VENDORID 0x10B7 +#define TC_DEVICEID_3C996 0x0003 + +/* + * SysKonnect PCI vendor ID + */ +#define SK_VENDORID 0x1148 +#define SK_DEVICEID_ALTIMA 0x4400 +#define SK_SUBSYSID_9D21 0x4421 +#define SK_SUBSYSID_9D41 0x4441 + +/* + * Altima PCI vendor/device ID. + */ +#define ALTIMA_VENDORID 0x173b +#define ALTIMA_DEVICE_AC1000 0x03e8 +#define ALTIMA_DEVICE_AC1002 0x03e9 +#define ALTIMA_DEVICE_AC9100 0x03ea + +/* + * Dell PCI vendor ID + */ + +#define DELL_VENDORID 0x1028 + +/* + * Apple PCI vendor ID. + */ +#define APPLE_VENDORID 0x106b +#define APPLE_DEVICE_BCM5701 0x1645 + +/* + * Sun PCI vendor ID + */ +#define SUN_VENDORID 0x108e + +/* + * Fujitsu vendor/device IDs + */ +#define FJTSU_VENDORID 0x10cf +#define FJTSU_DEVICEID_PW008GE5 0x11a1 +#define FJTSU_DEVICEID_PW008GE4 0x11a2 +#define FJTSU_DEVICEID_PP250450 0x11cc /* PRIMEPOWER250/450 LAN */ + +/* + * Offset of MAC address inside EEPROM. + */ +#define BGE_EE_MAC_OFFSET 0x7C +#define BGE_EE_MAC_OFFSET_5906 0x10 +#define BGE_EE_HWCFG_OFFSET 0xC8 + +#define BGE_HWCFG_VOLTAGE 0x00000003 +#define BGE_HWCFG_PHYLED_MODE 0x0000000C +#define BGE_HWCFG_MEDIA 0x00000030 +#define BGE_HWCFG_ASF 0x00000080 + +#define BGE_VOLTAGE_1POINT3 0x00000000 +#define BGE_VOLTAGE_1POINT8 0x00000001 + +#define BGE_PHYLEDMODE_UNSPEC 0x00000000 +#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 +#define BGE_PHYLEDMODE_SINGLELED 0x00000008 + +#define BGE_MEDIA_UNSPEC 0x00000000 +#define BGE_MEDIA_COPPER 0x00000010 +#define BGE_MEDIA_FIBER 0x00000020 + +#define BGE_TICKS_PER_SEC 1000000 + +/* + * Ring size constants. + */ +#define BGE_EVENT_RING_CNT 256 +#define BGE_CMD_RING_CNT 64 +#define BGE_STD_RX_RING_CNT 512 +#define BGE_JUMBO_RX_RING_CNT 256 +#define BGE_MINI_RX_RING_CNT 1024 +#define BGE_RETURN_RING_CNT 1024 + +/* 5705 has smaller return ring size */ + +#define BGE_RETURN_RING_CNT_5705 512 + +/* + * Possible TX ring sizes. + */ +#define BGE_TX_RING_CNT_128 128 +#define BGE_TX_RING_BASE_128 0x3800 + +#define BGE_TX_RING_CNT_256 256 +#define BGE_TX_RING_BASE_256 0x3000 + +#define BGE_TX_RING_CNT_512 512 +#define BGE_TX_RING_BASE_512 0x2000 + +#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 +#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 + +/* + * Tigon III statistics counters. + */ +/* Statistics maintained MAC Receive block. */ +struct bge_rx_mac_stats { + bge_hostaddr ifHCInOctets; + bge_hostaddr Reserved1; + bge_hostaddr etherStatsFragments; + bge_hostaddr ifHCInUcastPkts; + bge_hostaddr ifHCInMulticastPkts; + bge_hostaddr ifHCInBroadcastPkts; + bge_hostaddr dot3StatsFCSErrors; + bge_hostaddr dot3StatsAlignmentErrors; + bge_hostaddr xonPauseFramesReceived; + bge_hostaddr xoffPauseFramesReceived; + bge_hostaddr macControlFramesReceived; + bge_hostaddr xoffStateEntered; + bge_hostaddr dot3StatsFramesTooLong; + bge_hostaddr etherStatsJabbers; + bge_hostaddr etherStatsUndersizePkts; + bge_hostaddr inRangeLengthError; + bge_hostaddr outRangeLengthError; + bge_hostaddr etherStatsPkts64Octets; + bge_hostaddr etherStatsPkts65Octetsto127Octets; + bge_hostaddr etherStatsPkts128Octetsto255Octets; + bge_hostaddr etherStatsPkts256Octetsto511Octets; + bge_hostaddr etherStatsPkts512Octetsto1023Octets; + bge_hostaddr etherStatsPkts1024Octetsto1522Octets; + bge_hostaddr etherStatsPkts1523Octetsto2047Octets; + bge_hostaddr etherStatsPkts2048Octetsto4095Octets; + bge_hostaddr etherStatsPkts4096Octetsto8191Octets; + bge_hostaddr etherStatsPkts8192Octetsto9022Octets; +}; + + +/* Statistics maintained MAC Transmit block. */ +struct bge_tx_mac_stats { + bge_hostaddr ifHCOutOctets; + bge_hostaddr Reserved2; + bge_hostaddr etherStatsCollisions; + bge_hostaddr outXonSent; + bge_hostaddr outXoffSent; + bge_hostaddr flowControlDone; + bge_hostaddr dot3StatsInternalMacTransmitErrors; + bge_hostaddr dot3StatsSingleCollisionFrames; + bge_hostaddr dot3StatsMultipleCollisionFrames; + bge_hostaddr dot3StatsDeferredTransmissions; + bge_hostaddr Reserved3; + bge_hostaddr dot3StatsExcessiveCollisions; + bge_hostaddr dot3StatsLateCollisions; + bge_hostaddr dot3Collided2Times; + bge_hostaddr dot3Collided3Times; + bge_hostaddr dot3Collided4Times; + bge_hostaddr dot3Collided5Times; + bge_hostaddr dot3Collided6Times; + bge_hostaddr dot3Collided7Times; + bge_hostaddr dot3Collided8Times; + bge_hostaddr dot3Collided9Times; + bge_hostaddr dot3Collided10Times; + bge_hostaddr dot3Collided11Times; + bge_hostaddr dot3Collided12Times; + bge_hostaddr dot3Collided13Times; + bge_hostaddr dot3Collided14Times; + bge_hostaddr dot3Collided15Times; + bge_hostaddr ifHCOutUcastPkts; + bge_hostaddr ifHCOutMulticastPkts; + bge_hostaddr ifHCOutBroadcastPkts; + bge_hostaddr dot3StatsCarrierSenseErrors; + bge_hostaddr ifOutDiscards; + bge_hostaddr ifOutErrors; +}; + +/* Stats counters access through registers */ +struct bge_mac_stats { + /* TX MAC statistics */ + uint64_t ifHCOutOctets; + uint64_t Reserved0; + uint64_t etherStatsCollisions; + uint64_t outXonSent; + uint64_t outXoffSent; + uint64_t Reserved1; + uint64_t dot3StatsInternalMacTransmitErrors; + uint64_t dot3StatsSingleCollisionFrames; + uint64_t dot3StatsMultipleCollisionFrames; + uint64_t dot3StatsDeferredTransmissions; + uint64_t Reserved2; + uint64_t dot3StatsExcessiveCollisions; + uint64_t dot3StatsLateCollisions; + uint64_t Reserved3[14]; + uint64_t ifHCOutUcastPkts; + uint64_t ifHCOutMulticastPkts; + uint64_t ifHCOutBroadcastPkts; + uint64_t Reserved4[2]; + /* RX MAC statistics */ + uint64_t ifHCInOctets; + uint64_t Reserved5; + uint64_t etherStatsFragments; + uint64_t ifHCInUcastPkts; + uint64_t ifHCInMulticastPkts; + uint64_t ifHCInBroadcastPkts; + uint64_t dot3StatsFCSErrors; + uint64_t dot3StatsAlignmentErrors; + uint64_t xonPauseFramesReceived; + uint64_t xoffPauseFramesReceived; + uint64_t macControlFramesReceived; + uint64_t xoffStateEntered; + uint64_t dot3StatsFramesTooLong; + uint64_t etherStatsJabbers; + uint64_t etherStatsUndersizePkts; + /* Receive List Placement control */ + uint64_t FramesDroppedDueToFilters; + uint64_t DmaWriteQueueFull; + uint64_t DmaWriteHighPriQueueFull; + uint64_t NoMoreRxBDs; + uint64_t InputDiscards; + uint64_t InputErrors; + uint64_t RecvThresholdHit; +}; + +struct bge_stats { + uint8_t Reserved0[256]; + + /* Statistics maintained by Receive MAC. */ + struct bge_rx_mac_stats rxstats; + + bge_hostaddr Unused1[37]; + + /* Statistics maintained by Transmit MAC. */ + struct bge_tx_mac_stats txstats; + + bge_hostaddr Unused2[31]; + + /* Statistics maintained by Receive List Placement. */ + bge_hostaddr COSIfHCInPkts[16]; + bge_hostaddr COSFramesDroppedDueToFilters; + bge_hostaddr nicDmaWriteQueueFull; + bge_hostaddr nicDmaWriteHighPriQueueFull; + bge_hostaddr nicNoMoreRxBDs; + bge_hostaddr ifInDiscards; + bge_hostaddr ifInErrors; + bge_hostaddr nicRecvThresholdHit; + + bge_hostaddr Unused3[9]; + + /* Statistics maintained by Send Data Initiator. */ + bge_hostaddr COSIfHCOutPkts[16]; + bge_hostaddr nicDmaReadQueueFull; + bge_hostaddr nicDmaReadHighPriQueueFull; + bge_hostaddr nicSendDataCompQueueFull; + + /* Statistics maintained by Host Coalescing. */ + bge_hostaddr nicRingSetSendProdIndex; + bge_hostaddr nicRingStatusUpdate; + bge_hostaddr nicInterrupts; + bge_hostaddr nicAvoidedInterrupts; + bge_hostaddr nicSendThresholdHit; + + uint8_t Reserved4[320]; +}; + +/* + * Tigon general information block. This resides in host memory + * and contains the status counters, ring control blocks and + * producer pointers. + */ + +struct bge_gib { + struct bge_stats bge_stats; + struct bge_rcb bge_tx_rcb[16]; + struct bge_rcb bge_std_rx_rcb; + struct bge_rcb bge_jumbo_rx_rcb; + struct bge_rcb bge_mini_rx_rcb; + struct bge_rcb bge_return_rcb; +}; + +#define BGE_FRAMELEN 1518 +#define BGE_MAX_FRAMELEN 1536 +#define BGE_JUMBO_FRAMELEN 9018 +#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) +#define BGE_MIN_FRAMELEN 60 + +/* + * Other utility macros. + */ +#define BGE_INC(x, y) (x) = (x + 1) % y + +/* + * Register access macros. The Tigon always uses memory mapped register + * accesses and all registers must be accessed with 32 bit operations. + */ + +#define CSR_WRITE_4(sc, reg, val) \ + bus_write_4(sc->bge_res, reg, val) + +#define CSR_READ_4(sc, reg) \ + bus_read_4(sc->bge_res, reg) + +#define BGE_SETBIT(sc, reg, x) \ + CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) +#define BGE_CLRBIT(sc, reg, x) \ + CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) + +#define PCI_SETBIT(dev, reg, x, s) \ + pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) +#define PCI_CLRBIT(dev, reg, x, s) \ + pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) + +/* + * Memory management stuff. + */ + +#define BGE_NSEG_JUMBO 4 +#define BGE_NSEG_NEW 32 +#define BGE_TSOSEG_SZ 4096 + +/* Maximum DMA address for controllers that have 40bit DMA address bug. */ +#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) +#define BGE_DMA_MAXADDR BUS_SPACE_MAXADDR +#else +#define BGE_DMA_MAXADDR 0xFFFFFFFFFF +#endif + +#ifdef PAE +#define BGE_DMA_BNDRY 0x80000000 +#else +#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) +#define BGE_DMA_BNDRY 0x100000000 +#else +#define BGE_DMA_BNDRY 0 +#endif +#endif + +/* + * Ring structures. Most of these reside in host memory and we tell + * the NIC where they are via the ring control blocks. The exceptions + * are the tx and command rings, which live in NIC memory and which + * we access via the shared memory window. + */ + +struct bge_ring_data { + struct bge_rx_bd *bge_rx_std_ring; + bus_addr_t bge_rx_std_ring_paddr; + struct bge_extrx_bd *bge_rx_jumbo_ring; + bus_addr_t bge_rx_jumbo_ring_paddr; + struct bge_rx_bd *bge_rx_return_ring; + bus_addr_t bge_rx_return_ring_paddr; + struct bge_tx_bd *bge_tx_ring; + bus_addr_t bge_tx_ring_paddr; + struct bge_status_block *bge_status_block; + bus_addr_t bge_status_block_paddr; + struct bge_stats *bge_stats; + bus_addr_t bge_stats_paddr; + struct bge_gib bge_info; +}; + +#define BGE_STD_RX_RING_SZ \ + (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT) +#define BGE_JUMBO_RX_RING_SZ \ + (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT) +#define BGE_TX_RING_SZ \ + (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT) +#define BGE_RX_RTN_RING_SZ(x) \ + (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt) + +#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) + +#define BGE_STATS_SZ sizeof (struct bge_stats) + +/* + * Mbuf pointers. We need these to keep track of the virtual addresses + * of our mbuf chains since we can only convert from physical to virtual, + * not the other way around. + */ +struct bge_chain_data { + bus_dma_tag_t bge_parent_tag; + bus_dma_tag_t bge_buffer_tag; + bus_dma_tag_t bge_rx_std_ring_tag; + bus_dma_tag_t bge_rx_jumbo_ring_tag; + bus_dma_tag_t bge_rx_return_ring_tag; + bus_dma_tag_t bge_tx_ring_tag; + bus_dma_tag_t bge_status_tag; + bus_dma_tag_t bge_stats_tag; + bus_dma_tag_t bge_rx_mtag; /* Rx mbuf mapping tag */ + bus_dma_tag_t bge_tx_mtag; /* Tx mbuf mapping tag */ + bus_dma_tag_t bge_mtag_jumbo; /* Jumbo mbuf mapping tag */ + bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT]; + bus_dmamap_t bge_rx_std_sparemap; + bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT]; + bus_dmamap_t bge_rx_jumbo_sparemap; + bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT]; + bus_dmamap_t bge_rx_std_ring_map; + bus_dmamap_t bge_rx_jumbo_ring_map; + bus_dmamap_t bge_tx_ring_map; + bus_dmamap_t bge_rx_return_ring_map; + bus_dmamap_t bge_status_map; + bus_dmamap_t bge_stats_map; + struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; + struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; + struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; + int bge_rx_std_seglen[BGE_STD_RX_RING_CNT]; + int bge_rx_jumbo_seglen[BGE_JUMBO_RX_RING_CNT][4]; +}; + +struct bge_dmamap_arg { + bus_addr_t bge_busaddr; +}; + +#define BGE_HWREV_TIGON 0x01 +#define BGE_HWREV_TIGON_II 0x02 +#define BGE_TIMEOUT 100000 +#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ + +struct bge_bcom_hack { + int reg; + int val; +}; + +#define ASF_ENABLE 1 +#define ASF_NEW_HANDSHAKE 2 +#define ASF_STACKUP 4 + +struct bge_softc { + struct ifnet *bge_ifp; /* interface info */ + device_t bge_dev; + struct mtx bge_mtx; + device_t bge_miibus; + void *bge_intrhand; + struct resource *bge_irq; + struct resource *bge_res; + struct ifmedia bge_ifmedia; /* TBI media info */ + int bge_expcap; + int bge_msicap; + int bge_pcixcap; + uint32_t bge_flags; +#define BGE_FLAG_TBI 0x00000001 +#define BGE_FLAG_JUMBO 0x00000002 +#define BGE_FLAG_EADDR 0x00000008 +#define BGE_FLAG_MII_SERDES 0x00000010 +#define BGE_FLAG_CPMU_PRESENT 0x00000020 +#define BGE_FLAG_TAGGED_STATUS 0x00000040 +#define BGE_FLAG_MSI 0x00000100 +#define BGE_FLAG_PCIX 0x00000200 +#define BGE_FLAG_PCIE 0x00000400 +#define BGE_FLAG_TSO 0x00000800 +#define BGE_FLAG_TSO3 0x00001000 +#define BGE_FLAG_JUMBO_FRAME 0x00002000 +#define BGE_FLAG_5700_FAMILY 0x00010000 +#define BGE_FLAG_5705_PLUS 0x00020000 +#define BGE_FLAG_5714_FAMILY 0x00040000 +#define BGE_FLAG_575X_PLUS 0x00080000 +#define BGE_FLAG_5755_PLUS 0x00100000 +#define BGE_FLAG_5788 0x00200000 +#define BGE_FLAG_5717_PLUS 0x00400000 +#define BGE_FLAG_40BIT_BUG 0x01000000 +#define BGE_FLAG_4G_BNDRY_BUG 0x02000000 +#define BGE_FLAG_RX_ALIGNBUG 0x04000000 +#define BGE_FLAG_SHORT_DMA_BUG 0x08000000 + uint32_t bge_phy_flags; +#define BGE_PHY_WIRESPEED 0x00000001 +#define BGE_PHY_ADC_BUG 0x00000002 +#define BGE_PHY_5704_A0_BUG 0x00000004 +#define BGE_PHY_JITTER_BUG 0x00000008 +#define BGE_PHY_BER_BUG 0x00000010 +#define BGE_PHY_ADJUST_TRIM 0x00000020 +#define BGE_PHY_CRC_BUG 0x00000040 +#define BGE_PHY_NO_3LED 0x00000080 + uint32_t bge_chipid; + uint32_t bge_asicrev; + uint32_t bge_chiprev; + uint8_t bge_asf_mode; + uint8_t bge_asf_count; + struct bge_ring_data bge_ldata; /* rings */ + struct bge_chain_data bge_cdata; /* mbufs */ + uint16_t bge_tx_saved_considx; + uint16_t bge_rx_saved_considx; + uint16_t bge_ev_saved_considx; + uint16_t bge_return_ring_cnt; + uint16_t bge_std; /* current std ring head */ + uint16_t bge_jumbo; /* current jumo ring head */ + uint32_t bge_stat_ticks; + uint32_t bge_rx_coal_ticks; + uint32_t bge_tx_coal_ticks; + uint32_t bge_tx_prodidx; + uint32_t bge_rx_max_coal_bds; + uint32_t bge_tx_max_coal_bds; + uint32_t bge_mi_mode; + int bge_if_flags; + int bge_txcnt; + int bge_link; /* link state */ + int bge_link_evt; /* pending link event */ + int bge_timer; + int bge_forced_collapse; + int bge_forced_udpcsum; + int bge_csum_features; + struct callout bge_stat_ch; + uint32_t bge_rx_discards; + uint32_t bge_tx_discards; + uint32_t bge_tx_collisions; +#ifdef DEVICE_POLLING + int rxcycles; +#endif /* DEVICE_POLLING */ + struct bge_mac_stats bge_mac_stats; + struct task bge_intr_task; + struct taskqueue *bge_tq; +}; + +#define BGE_LOCK_INIT(_sc, _name) \ + mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) +#define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx) +#define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED) +#define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx) +#define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx) diff --git a/freebsd/dev/dc/dcphy.c b/freebsd/dev/dc/dcphy.c new file mode 100644 index 00000000..75ba2ce5 --- /dev/null +++ b/freebsd/dev/dc/dcphy.c @@ -0,0 +1,423 @@ +#include + +/*- + * Copyright (c) 1997, 1998, 1999 + * Bill Paul . All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Bill Paul. + * 4. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +/* + * Pseudo-driver for internal NWAY support on DEC 21143 and workalike + * controllers. Technically we're abusing the miibus code to handle + * media selection and NWAY support here since there is no MII + * interface. However the logical operations are roughly the same, + * and the alternative is to create a fake MII interface in the driver, + * which is harder to do. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include + +#include + +#define DC_SETBIT(sc, reg, x) \ + CSR_WRITE_4(sc, reg, \ + CSR_READ_4(sc, reg) | x) + +#define DC_CLRBIT(sc, reg, x) \ + CSR_WRITE_4(sc, reg, \ + CSR_READ_4(sc, reg) & ~x) + +#define MIIF_AUTOTIMEOUT 0x0004 + +/* + * This is the subsystem ID for the built-in 21143 ethernet + * in several Compaq Presario systems. Apparently these are + * 10Mbps only, so we need to treat them specially. + */ +#define COMPAQ_PRESARIO_ID 0xb0bb0e11 + +static int dcphy_probe(device_t); +static int dcphy_attach(device_t); + +static device_method_t dcphy_methods[] = { + /* device interface */ + DEVMETHOD(device_probe, dcphy_probe), + DEVMETHOD(device_attach, dcphy_attach), + DEVMETHOD(device_detach, mii_phy_detach), + DEVMETHOD(device_shutdown, bus_generic_shutdown), + { 0, 0 } +}; + +static devclass_t dcphy_devclass; + +static driver_t dcphy_driver = { + "dcphy", + dcphy_methods, + sizeof(struct mii_softc) +}; + +DRIVER_MODULE(dcphy, miibus, dcphy_driver, dcphy_devclass, 0, 0); + +static int dcphy_service(struct mii_softc *, struct mii_data *, int); +static void dcphy_status(struct mii_softc *); +static void dcphy_reset(struct mii_softc *); +static int dcphy_auto(struct mii_softc *); + +static int +dcphy_probe(device_t dev) +{ + struct mii_attach_args *ma; + + ma = device_get_ivars(dev); + + /* + * The dc driver will report the 21143 vendor and device + * ID to let us know that it wants us to attach. + */ + if (ma->mii_id1 != DC_VENDORID_DEC || + ma->mii_id2 != DC_DEVICEID_21143) + return (ENXIO); + + device_set_desc(dev, "Intel 21143 NWAY media interface"); + + return (BUS_PROBE_DEFAULT); +} + +static int +dcphy_attach(device_t dev) +{ + struct mii_softc *sc; + struct mii_attach_args *ma; + struct mii_data *mii; + struct dc_softc *dc_sc; + device_t brdev; + + sc = device_get_softc(dev); + ma = device_get_ivars(dev); + sc->mii_dev = device_get_parent(dev); + mii = ma->mii_data; + LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); + + sc->mii_flags = miibus_get_flags(dev); + sc->mii_inst = mii->mii_instance++; + sc->mii_phy = ma->mii_phyno; + sc->mii_service = dcphy_service; + sc->mii_pdata = mii; + + /* + * Apparently, we can neither isolate nor do loopback. + */ + sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP; + + /*dcphy_reset(sc);*/ + dc_sc = mii->mii_ifp->if_softc; + CSR_WRITE_4(dc_sc, DC_10BTSTAT, 0); + CSR_WRITE_4(dc_sc, DC_10BTCTRL, 0); + + brdev = device_get_parent(sc->mii_dev); + switch (pci_get_subdevice(brdev) << 16 | pci_get_subvendor(brdev)) { + case COMPAQ_PRESARIO_ID: + /* Example of how to only allow 10Mbps modes. */ + sc->mii_capabilities = BMSR_ANEG | BMSR_10TFDX | BMSR_10THDX; + break; + default: + if (dc_sc->dc_pmode == DC_PMODE_SIA) + sc->mii_capabilities = + BMSR_ANEG | BMSR_10TFDX | BMSR_10THDX; + else + sc->mii_capabilities = + BMSR_ANEG | BMSR_100TXFDX | BMSR_100TXHDX | + BMSR_10TFDX | BMSR_10THDX; + break; + } + + sc->mii_capabilities &= ma->mii_capmask; + device_printf(dev, " "); + mii_phy_add_media(sc); + printf("\n"); + + MIIBUS_MEDIAINIT(sc->mii_dev); + return (0); +} + +static int +dcphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) +{ + struct dc_softc *dc_sc; + struct ifmedia_entry *ife = mii->mii_media.ifm_cur; + int reg; + u_int32_t mode; + + dc_sc = mii->mii_ifp->if_softc; + + switch (cmd) { + case MII_POLLSTAT: + break; + + case MII_MEDIACHG: + /* + * If the interface is not up, don't do anything. + */ + if ((mii->mii_ifp->if_flags & IFF_UP) == 0) + break; + + mii->mii_media_active = IFM_NONE; + mode = CSR_READ_4(dc_sc, DC_NETCFG); + mode &= ~(DC_NETCFG_FULLDUPLEX | DC_NETCFG_PORTSEL | + DC_NETCFG_PCS | DC_NETCFG_SCRAMBLER | DC_NETCFG_SPEEDSEL); + + switch (IFM_SUBTYPE(ife->ifm_media)) { + case IFM_AUTO: + /*dcphy_reset(sc);*/ + (void) dcphy_auto(sc); + break; + case IFM_100_T4: + /* + * XXX Not supported as a manual setting right now. + */ + return (EINVAL); + case IFM_100_TX: + dcphy_reset(sc); + DC_CLRBIT(dc_sc, DC_10BTCTRL, DC_TCTL_AUTONEGENBL); + mode |= DC_NETCFG_PORTSEL | DC_NETCFG_PCS | + DC_NETCFG_SCRAMBLER; + if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) + mode |= DC_NETCFG_FULLDUPLEX; + else + mode &= ~DC_NETCFG_FULLDUPLEX; + CSR_WRITE_4(dc_sc, DC_NETCFG, mode); + break; + case IFM_10_T: + DC_CLRBIT(dc_sc, DC_SIARESET, DC_SIA_RESET); + DC_CLRBIT(dc_sc, DC_10BTCTRL, 0xFFFF); + if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) + DC_SETBIT(dc_sc, DC_10BTCTRL, 0x7F3D); + else + DC_SETBIT(dc_sc, DC_10BTCTRL, 0x7F3F); + DC_SETBIT(dc_sc, DC_SIARESET, DC_SIA_RESET); + DC_CLRBIT(dc_sc, DC_10BTCTRL, DC_TCTL_AUTONEGENBL); + mode &= ~DC_NETCFG_PORTSEL; + mode |= DC_NETCFG_SPEEDSEL; + if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) + mode |= DC_NETCFG_FULLDUPLEX; + else + mode &= ~DC_NETCFG_FULLDUPLEX; + CSR_WRITE_4(dc_sc, DC_NETCFG, mode); + break; + default: + return (EINVAL); + } + break; + + case MII_TICK: + /* + * Is the interface even up? + */ + if ((mii->mii_ifp->if_flags & IFF_UP) == 0) + return (0); + + /* + * Only used for autonegotiation. + */ + if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) + break; + + reg = CSR_READ_4(dc_sc, DC_10BTSTAT); + if (!(reg & DC_TSTAT_LS10) || !(reg & DC_TSTAT_LS100)) + break; + + /* + * Only retry autonegotiation every 5 seconds. + * + * Otherwise, fall through to calling dcphy_status() + * since real Intel 21143 chips don't show valid link + * status until autonegotiation is switched off, and + * that only happens in dcphy_status(). Without this, + * successful autonegotiation is never recognised on + * these chips. + */ + if (++sc->mii_ticks <= 50) + break; + + sc->mii_ticks = 0; + dcphy_auto(sc); + + break; + } + + /* Update the media status. */ + dcphy_status(sc); + + /* Callback if something changed. */ + mii_phy_update(sc, cmd); + return (0); +} + +static void +dcphy_status(struct mii_softc *sc) +{ + struct mii_data *mii = sc->mii_pdata; + int reg, anlpar, tstat = 0; + struct dc_softc *dc_sc; + + dc_sc = mii->mii_ifp->if_softc; + + mii->mii_media_status = IFM_AVALID; + mii->mii_media_active = IFM_ETHER; + + if ((mii->mii_ifp->if_flags & IFF_UP) == 0) + return; + + reg = CSR_READ_4(dc_sc, DC_10BTSTAT); + if (!(reg & DC_TSTAT_LS10) || !(reg & DC_TSTAT_LS100)) + mii->mii_media_status |= IFM_ACTIVE; + + if (CSR_READ_4(dc_sc, DC_10BTCTRL) & DC_TCTL_AUTONEGENBL) { + /* Erg, still trying, I guess... */ + tstat = CSR_READ_4(dc_sc, DC_10BTSTAT); + if ((tstat & DC_TSTAT_ANEGSTAT) != DC_ASTAT_AUTONEGCMP) { + if ((DC_IS_MACRONIX(dc_sc) || DC_IS_PNICII(dc_sc)) && + (tstat & DC_TSTAT_ANEGSTAT) == DC_ASTAT_DISABLE) + goto skip; + mii->mii_media_active |= IFM_NONE; + return; + } + + if (tstat & DC_TSTAT_LP_CAN_NWAY) { + anlpar = tstat >> 16; + if (anlpar & ANLPAR_TX_FD && + sc->mii_capabilities & BMSR_100TXFDX) + mii->mii_media_active |= IFM_100_TX | IFM_FDX; + else if (anlpar & ANLPAR_T4 && + sc->mii_capabilities & BMSR_100T4) + mii->mii_media_active |= IFM_100_T4 | IFM_HDX; + else if (anlpar & ANLPAR_TX && + sc->mii_capabilities & BMSR_100TXHDX) + mii->mii_media_active |= IFM_100_TX | IFM_HDX; + else if (anlpar & ANLPAR_10_FD) + mii->mii_media_active |= IFM_10_T | IFM_FDX; + else if (anlpar & ANLPAR_10) + mii->mii_media_active |= IFM_10_T | IFM_HDX; + else + mii->mii_media_active |= IFM_NONE; + if (DC_IS_INTEL(dc_sc)) + DC_CLRBIT(dc_sc, DC_10BTCTRL, + DC_TCTL_AUTONEGENBL); + return; + } + + /* + * If the other side doesn't support NWAY, then the + * best we can do is determine if we have a 10Mbps or + * 100Mbps link. There's no way to know if the link + * is full or half duplex, so we default to half duplex + * and hope that the user is clever enough to manually + * change the media settings if we're wrong. + */ + if (!(reg & DC_TSTAT_LS100)) + mii->mii_media_active |= IFM_100_TX | IFM_HDX; + else if (!(reg & DC_TSTAT_LS10)) + mii->mii_media_active |= IFM_10_T | IFM_HDX; + else + mii->mii_media_active |= IFM_NONE; + if (DC_IS_INTEL(dc_sc)) + DC_CLRBIT(dc_sc, DC_10BTCTRL, DC_TCTL_AUTONEGENBL); + return; + } + +skip: + if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_SPEEDSEL) + mii->mii_media_active |= IFM_10_T; + else + mii->mii_media_active |= IFM_100_TX; + if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_FULLDUPLEX) + mii->mii_media_active |= IFM_FDX; + else + mii->mii_media_active |= IFM_HDX; +} + +static int +dcphy_auto(struct mii_softc *mii) +{ + struct dc_softc *sc; + + sc = mii->mii_pdata->mii_ifp->if_softc; + + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); + DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); + if (mii->mii_capabilities & BMSR_100TXHDX) + CSR_WRITE_4(sc, DC_10BTCTRL, 0x3FFFF); + else + CSR_WRITE_4(sc, DC_10BTCTRL, 0xFFFF); + DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); + DC_SETBIT(sc, DC_10BTCTRL, DC_TCTL_AUTONEGENBL); + DC_SETBIT(sc, DC_10BTSTAT, DC_ASTAT_TXDISABLE); + + return (EJUSTRETURN); +} + +static void +dcphy_reset(struct mii_softc *mii) +{ + struct dc_softc *sc; + + sc = mii->mii_pdata->mii_ifp->if_softc; + + DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); + DELAY(1000); + DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); +} diff --git a/freebsd/dev/dc/if_dc.c b/freebsd/dev/dc/if_dc.c new file mode 100644 index 00000000..512555b5 --- /dev/null +++ b/freebsd/dev/dc/if_dc.c @@ -0,0 +1,3806 @@ +#include + +/*- + * Copyright (c) 1997, 1998, 1999 + * Bill Paul . All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Bill Paul. + * 4. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +/* + * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 + * series chips and several workalikes including the following: + * + * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) + * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) + * Lite-On 82c168/82c169 PNIC (www.litecom.com) + * ASIX Electronics AX88140A (www.asix.com.tw) + * ASIX Electronics AX88141 (www.asix.com.tw) + * ADMtek AL981 (www.admtek.com.tw) + * ADMtek AN983 (www.admtek.com.tw) + * ADMtek cardbus AN985 (www.admtek.com.tw) + * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek cardbus AN985 + * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) + * Accton EN1217 (www.accton.com) + * Xircom X3201 (www.xircom.com) + * Abocom FE2500 + * Conexant LANfinity (www.conexant.com) + * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) + * + * Datasheets for the 21143 are available at developer.intel.com. + * Datasheets for the clone parts can be found at their respective sites. + * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) + * The PNIC II is essentially a Macronix 98715A chip; the only difference + * worth noting is that its multicast hash table is only 128 bits wide + * instead of 512. + * + * Written by Bill Paul + * Electrical Engineering Department + * Columbia University, New York City + */ +/* + * The Intel 21143 is the successor to the DEC 21140. It is basically + * the same as the 21140 but with a few new features. The 21143 supports + * three kinds of media attachments: + * + * o MII port, for 10Mbps and 100Mbps support and NWAY + * autonegotiation provided by an external PHY. + * o SYM port, for symbol mode 100Mbps support. + * o 10baseT port. + * o AUI/BNC port. + * + * The 100Mbps SYM port and 10baseT port can be used together in + * combination with the internal NWAY support to create a 10/100 + * autosensing configuration. + * + * Note that not all tulip workalikes are handled in this driver: we only + * deal with those which are relatively well behaved. The Winbond is + * handled separately due to its different register offsets and the + * special handling needed for its various bugs. The PNIC is handled + * here, but I'm not thrilled about it. + * + * All of the workalike chips use some form of MII transceiver support + * with the exception of the Macronix chips, which also have a SYM port. + * The ASIX AX88140A is also documented to have a SYM port, but all + * the cards I've seen use an MII transceiver, probably because the + * AX88140A doesn't support internal NWAY. + */ + +#ifdef HAVE_KERNEL_OPTION_HEADERS +#include +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +#include +#include + +#include +#include + +#define DC_USEIOSPACE + +#include + +#ifdef __sparc64__ +#include +#include +#endif + +MODULE_DEPEND(dc, pci, 1, 1, 1); +MODULE_DEPEND(dc, ether, 1, 1, 1); +MODULE_DEPEND(dc, miibus, 1, 1, 1); + +/* + * "device miibus" is required in kernel config. See GENERIC if you get + * errors here. + */ +#include + +/* + * Various supported device vendors/types and their names. + */ +static const struct dc_type dc_devs[] = { + { DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0, + "Intel 21143 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0, + "Davicom DM9009 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100), 0, + "Davicom DM9100 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), DC_REVISION_DM9102A, + "Davicom DM9102A 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), 0, + "Davicom DM9102 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981), 0, + "ADMtek AL981 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983), 0, + "ADMtek AN983 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985), 0, + "ADMtek AN985 cardBus 10/100BaseTX or clone" }, + { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511), 0, + "ADMtek ADM9511 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513), 0, + "ADMtek ADM9513 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), DC_REVISION_88141, + "ASIX AX88141 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), 0, + "ASIX AX88140A 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), DC_REVISION_98713A, + "Macronix 98713A 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), 0, + "Macronix 98713 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), DC_REVISION_98713A, + "Compex RL100-TX 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), 0, + "Compex RL100-TX 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98725, + "Macronix 98725 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98715AEC_C, + "Macronix 98715AEC-C 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), 0, + "Macronix 98715/98715A 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727), 0, + "Macronix 98727/98732 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115), 0, + "LC82C115 PNIC II 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), DC_REVISION_82C169, + "82c169 PNIC 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), 0, + "82c168 PNIC 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217), 0, + "Accton EN1217 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242), 0, + "Accton EN2242 MiniPCI 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201), 0, + "Xircom X3201 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD), 0, + "Neteasy DRP-32TXD Cardbus 10/100" }, + { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500), 0, + "Abocom FE2500 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX), 0, + "Abocom FE2500MX 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112), 0, + "Conexant LANfinity MiniPCI 10/100BaseTX" }, + { DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX), 0, + "Hawking CB102 CardBus 10/100" }, + { DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T), 0, + "PlaneX FNW-3602-T CardBus 10/100" }, + { DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB), 0, + "3Com OfficeConnect 10/100B" }, + { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120), 0, + "Microsoft MN-120 CardBus 10/100" }, + { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130), 0, + "Microsoft MN-130 10/100" }, + { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08), 0, + "Linksys PCMPC200 CardBus 10/100" }, + { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09), 0, + "Linksys PCMPC200 CardBus 10/100" }, + { 0, 0, NULL } +}; + +static int dc_probe(device_t); +static int dc_attach(device_t); +static int dc_detach(device_t); +static int dc_suspend(device_t); +static int dc_resume(device_t); +static const struct dc_type *dc_devtype(device_t); +static int dc_newbuf(struct dc_softc *, int, int); +static int dc_encap(struct dc_softc *, struct mbuf **); +static void dc_pnic_rx_bug_war(struct dc_softc *, int); +static int dc_rx_resync(struct dc_softc *); +static int dc_rxeof(struct dc_softc *); +static void dc_txeof(struct dc_softc *); +static void dc_tick(void *); +static void dc_tx_underrun(struct dc_softc *); +static void dc_intr(void *); +static void dc_start(struct ifnet *); +static void dc_start_locked(struct ifnet *); +static int dc_ioctl(struct ifnet *, u_long, caddr_t); +static void dc_init(void *); +static void dc_init_locked(struct dc_softc *); +static void dc_stop(struct dc_softc *); +static void dc_watchdog(void *); +static int dc_shutdown(device_t); +static int dc_ifmedia_upd(struct ifnet *); +static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *); + +static void dc_delay(struct dc_softc *); +static void dc_eeprom_idle(struct dc_softc *); +static void dc_eeprom_putbyte(struct dc_softc *, int); +static void dc_eeprom_getword(struct dc_softc *, int, u_int16_t *); +static void dc_eeprom_getword_pnic(struct dc_softc *, int, u_int16_t *); +static void dc_eeprom_getword_xircom(struct dc_softc *, int, u_int16_t *); +static void dc_eeprom_width(struct dc_softc *); +static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int); + +static void dc_mii_writebit(struct dc_softc *, int); +static int dc_mii_readbit(struct dc_softc *); +static void dc_mii_sync(struct dc_softc *); +static void dc_mii_send(struct dc_softc *, u_int32_t, int); +static int dc_mii_readreg(struct dc_softc *, struct dc_mii_frame *); +static int dc_mii_writereg(struct dc_softc *, struct dc_mii_frame *); +static int dc_miibus_readreg(device_t, int, int); +static int dc_miibus_writereg(device_t, int, int, int); +static void dc_miibus_statchg(device_t); +static void dc_miibus_mediainit(device_t); + +static void dc_setcfg(struct dc_softc *, int); +static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *); +static uint32_t dc_mchash_be(const uint8_t *); +static void dc_setfilt_21143(struct dc_softc *); +static void dc_setfilt_asix(struct dc_softc *); +static void dc_setfilt_admtek(struct dc_softc *); +static void dc_setfilt_xircom(struct dc_softc *); + +static void dc_setfilt(struct dc_softc *); + +static void dc_reset(struct dc_softc *); +static int dc_list_rx_init(struct dc_softc *); +static int dc_list_tx_init(struct dc_softc *); + +static void dc_read_srom(struct dc_softc *, int); +static void dc_parse_21143_srom(struct dc_softc *); +static void dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *); +static void dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *); +static void dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *); +static void dc_apply_fixup(struct dc_softc *, int); + +#ifdef DC_USEIOSPACE +#define DC_RES SYS_RES_IOPORT +#define DC_RID DC_PCI_CFBIO +#else +#define DC_RES SYS_RES_MEMORY +#define DC_RID DC_PCI_CFBMA +#endif + +static device_method_t dc_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, dc_probe), + DEVMETHOD(device_attach, dc_attach), + DEVMETHOD(device_detach, dc_detach), + DEVMETHOD(device_suspend, dc_suspend), + DEVMETHOD(device_resume, dc_resume), + DEVMETHOD(device_shutdown, dc_shutdown), + + /* bus interface */ + DEVMETHOD(bus_print_child, bus_generic_print_child), + DEVMETHOD(bus_driver_added, bus_generic_driver_added), + + /* MII interface */ + DEVMETHOD(miibus_readreg, dc_miibus_readreg), + DEVMETHOD(miibus_writereg, dc_miibus_writereg), + DEVMETHOD(miibus_statchg, dc_miibus_statchg), + DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), + + { 0, 0 } +}; + +static driver_t dc_driver = { + "dc", + dc_methods, + sizeof(struct dc_softc) +}; + +static devclass_t dc_devclass; + +DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); +DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); + +#define DC_SETBIT(sc, reg, x) \ + CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) + +#define DC_CLRBIT(sc, reg, x) \ + CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) + +#define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) +#define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) + +static void +dc_delay(struct dc_softc *sc) +{ + int idx; + + for (idx = (300 / 33) + 1; idx > 0; idx--) + CSR_READ_4(sc, DC_BUSCTL); +} + +static void +dc_eeprom_width(struct dc_softc *sc) +{ + int i; + + /* Force EEPROM to idle state. */ + dc_eeprom_idle(sc); + + /* Enter EEPROM access mode. */ + CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); + dc_delay(sc); + DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); + dc_delay(sc); + DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); + dc_delay(sc); + DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); + dc_delay(sc); + + for (i = 3; i--;) { + if (6 & (1 << i)) + DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); + else + DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); + dc_delay(sc); + DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); + dc_delay(sc); + DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); + dc_delay(sc); + } + + for (i = 1; i <= 12; i++) { + DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); + dc_delay(sc); + if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { + DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); + dc_delay(sc); + break; + } + DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); + dc_delay(sc); + } + + /* Turn off EEPROM access mode. */ + dc_eeprom_idle(sc); + + if (i < 4 || i > 12) + sc->dc_romwidth = 6; + else + sc->dc_romwidth = i; + + /* Enter EEPROM access mode. */ + CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); + dc_delay(sc); + DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); + dc_delay(sc); + DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); + dc_delay(sc); + DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); + dc_delay(sc); + + /* Turn off EEPROM access mode. */ + dc_eeprom_idle(sc); +} + +static void +dc_eeprom_idle(struct dc_softc *sc) +{ + int i; + + CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); + dc_delay(sc); + DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); + dc_delay(sc); + DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); + dc_delay(sc); + DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); + dc_delay(sc); + + for (i = 0; i < 25; i++) { + DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); + dc_delay(sc); + DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); + dc_delay(sc); + } + + DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); + dc_delay(sc); + DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); + dc_delay(sc); + CSR_WRITE_4(sc, DC_SIO, 0x00000000); +} + +/* + * Send a read command and address to the EEPROM, check for ACK. + */ +static void +dc_eeprom_putbyte(struct dc_softc *sc, int addr) +{ + int d, i; + + d = DC_EECMD_READ >> 6; + for (i = 3; i--; ) { + if (d & (1 << i)) + DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); + else + DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); + dc_delay(sc); + DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); + dc_delay(sc); + DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); + dc_delay(sc); + } + + /* + * Feed in each bit and strobe the clock. + */ + for (i = sc->dc_romwidth; i--;) { + if (addr & (1 << i)) { + SIO_SET(DC_SIO_EE_DATAIN); + } else { + SIO_CLR(DC_SIO_EE_DATAIN); + } + dc_delay(sc); + SIO_SET(DC_SIO_EE_CLK); + dc_delay(sc); + SIO_CLR(DC_SIO_EE_CLK); + dc_delay(sc); + } +} + +/* + * Read a word of data stored in the EEPROM at address 'addr.' + * The PNIC 82c168/82c169 has its own non-standard way to read + * the EEPROM. + */ +static void +dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) +{ + int i; + u_int32_t r; + + CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); + + for (i = 0; i < DC_TIMEOUT; i++) { + DELAY(1); + r = CSR_READ_4(sc, DC_SIO); + if (!(r & DC_PN_SIOCTL_BUSY)) { + *dest = (u_int16_t)(r & 0xFFFF); + return; + } + } +} + +/* + * Read a word of data stored in the EEPROM at address 'addr.' + * The Xircom X3201 has its own non-standard way to read + * the EEPROM, too. + */ +static void +dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) +{ + + SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); + + addr *= 2; + CSR_WRITE_4(sc, DC_ROM, addr | 0x160); + *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff; + addr += 1; + CSR_WRITE_4(sc, DC_ROM, addr | 0x160); + *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; + + SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); +} + +/* + * Read a word of data stored in the EEPROM at address 'addr.' + */ +static void +dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) +{ + int i; + u_int16_t word = 0; + + /* Force EEPROM to idle state. */ + dc_eeprom_idle(sc); + + /* Enter EEPROM access mode. */ + CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); + dc_delay(sc); + DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); + dc_delay(sc); + DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); + dc_delay(sc); + DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); + dc_delay(sc); + + /* + * Send address of word we want to read. + */ + dc_eeprom_putbyte(sc, addr); + + /* + * Start reading bits from EEPROM. + */ + for (i = 0x8000; i; i >>= 1) { + SIO_SET(DC_SIO_EE_CLK); + dc_delay(sc); + if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) + word |= i; + dc_delay(sc); + SIO_CLR(DC_SIO_EE_CLK); + dc_delay(sc); + } + + /* Turn off EEPROM access mode. */ + dc_eeprom_idle(sc); + + *dest = word; +} + +/* + * Read a sequence of words from the EEPROM. + */ +static void +dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be) +{ + int i; + u_int16_t word = 0, *ptr; + + for (i = 0; i < cnt; i++) { + if (DC_IS_PNIC(sc)) + dc_eeprom_getword_pnic(sc, off + i, &word); + else if (DC_IS_XIRCOM(sc)) + dc_eeprom_getword_xircom(sc, off + i, &word); + else + dc_eeprom_getword(sc, off + i, &word); + ptr = (u_int16_t *)(dest + (i * 2)); + if (be) + *ptr = be16toh(word); + else + *ptr = le16toh(word); + } +} + +/* + * The following two routines are taken from the Macronix 98713 + * Application Notes pp.19-21. + */ +/* + * Write a bit to the MII bus. + */ +static void +dc_mii_writebit(struct dc_softc *sc, int bit) +{ + uint32_t reg; + + reg = DC_SIO_ROMCTL_WRITE | (bit != 0 ? DC_SIO_MII_DATAOUT : 0); + CSR_WRITE_4(sc, DC_SIO, reg); + CSR_BARRIER_4(sc, DC_SIO, + BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); + DELAY(1); + + CSR_WRITE_4(sc, DC_SIO, reg | DC_SIO_MII_CLK); + CSR_BARRIER_4(sc, DC_SIO, + BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); + DELAY(1); + CSR_WRITE_4(sc, DC_SIO, reg); + CSR_BARRIER_4(sc, DC_SIO, + BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); + DELAY(1); +} + +/* + * Read a bit from the MII bus. + */ +static int +dc_mii_readbit(struct dc_softc *sc) +{ + uint32_t reg; + + reg = DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR; + CSR_WRITE_4(sc, DC_SIO, reg); + CSR_BARRIER_4(sc, DC_SIO, + BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); + DELAY(1); + (void)CSR_READ_4(sc, DC_SIO); + CSR_WRITE_4(sc, DC_SIO, reg | DC_SIO_MII_CLK); + CSR_BARRIER_4(sc, DC_SIO, + BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); + DELAY(1); + CSR_WRITE_4(sc, DC_SIO, reg); + CSR_BARRIER_4(sc, DC_SIO, + BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); + DELAY(1); + if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) + return (1); + + return (0); +} + +/* + * Sync the PHYs by setting data bit and strobing the clock 32 times. + */ +static void +dc_mii_sync(struct dc_softc *sc) +{ + int i; + + CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); + CSR_BARRIER_4(sc, DC_SIO, + BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); + DELAY(1); + + for (i = 0; i < 32; i++) + dc_mii_writebit(sc, 1); +} + +/* + * Clock a series of bits through the MII. + */ +static void +dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) +{ + int i; + + for (i = (0x1 << (cnt - 1)); i; i >>= 1) + dc_mii_writebit(sc, bits & i); +} + +/* + * Read an PHY register through the MII. + */ +static int +dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) +{ + int i; + + /* + * Set up frame for RX. + */ + frame->mii_stdelim = DC_MII_STARTDELIM; + frame->mii_opcode = DC_MII_READOP; + + /* + * Sync the PHYs. + */ + dc_mii_sync(sc); + + /* + * Send command/address info. + */ + dc_mii_send(sc, frame->mii_stdelim, 2); + dc_mii_send(sc, frame->mii_opcode, 2); + dc_mii_send(sc, frame->mii_phyaddr, 5); + dc_mii_send(sc, frame->mii_regaddr, 5); + + /* + * Now try reading data bits. If the turnaround failed, we still + * need to clock through 16 cycles to keep the PHY(s) in sync. + */ + frame->mii_turnaround = dc_mii_readbit(sc); + if (frame->mii_turnaround != 0) { + for (i = 0; i < 16; i++) + dc_mii_readbit(sc); + goto fail; + } + for (i = 0x8000; i; i >>= 1) { + if (dc_mii_readbit(sc)) + frame->mii_data |= i; + } + +fail: + + /* Clock the idle bits. */ + dc_mii_writebit(sc, 0); + dc_mii_writebit(sc, 0); + + if (frame->mii_turnaround != 0) + return (1); + return (0); +} + +/* + * Write to a PHY register through the MII. + */ +static int +dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) +{ + + /* + * Set up frame for TX. + */ + frame->mii_stdelim = DC_MII_STARTDELIM; + frame->mii_opcode = DC_MII_WRITEOP; + frame->mii_turnaround = DC_MII_TURNAROUND; + + /* + * Sync the PHYs. + */ + dc_mii_sync(sc); + + dc_mii_send(sc, frame->mii_stdelim, 2); + dc_mii_send(sc, frame->mii_opcode, 2); + dc_mii_send(sc, frame->mii_phyaddr, 5); + dc_mii_send(sc, frame->mii_regaddr, 5); + dc_mii_send(sc, frame->mii_turnaround, 2); + dc_mii_send(sc, frame->mii_data, 16); + + /* Clock the idle bits. */ + dc_mii_writebit(sc, 0); + dc_mii_writebit(sc, 0); + + return (0); +} + +static int +dc_miibus_readreg(device_t dev, int phy, int reg) +{ + struct dc_mii_frame frame; + struct dc_softc *sc; + int i, rval, phy_reg = 0; + + sc = device_get_softc(dev); + bzero(&frame, sizeof(frame)); + + if (sc->dc_pmode != DC_PMODE_MII) { + if (phy == (MII_NPHY - 1)) { + switch (reg) { + case MII_BMSR: + /* + * Fake something to make the probe + * code think there's a PHY here. + */ + return (BMSR_MEDIAMASK); + break; + case MII_PHYIDR1: + if (DC_IS_PNIC(sc)) + return (DC_VENDORID_LO); + return (DC_VENDORID_DEC); + break; + case MII_PHYIDR2: + if (DC_IS_PNIC(sc)) + return (DC_DEVICEID_82C168); + return (DC_DEVICEID_21143); + break; + default: + return (0); + break; + } + } else + return (0); + } + + if (DC_IS_PNIC(sc)) { + CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | + (phy << 23) | (reg << 18)); + for (i = 0; i < DC_TIMEOUT; i++) { + DELAY(1); + rval = CSR_READ_4(sc, DC_PN_MII); + if (!(rval & DC_PN_MII_BUSY)) { + rval &= 0xFFFF; + return (rval == 0xFFFF ? 0 : rval); + } + } + return (0); + } + + if (DC_IS_COMET(sc)) { + switch (reg) { + case MII_BMCR: + phy_reg = DC_AL_BMCR; + break; + case MII_BMSR: + phy_reg = DC_AL_BMSR; + break; + case MII_PHYIDR1: + phy_reg = DC_AL_VENID; + break; + case MII_PHYIDR2: + phy_reg = DC_AL_DEVID; + break; + case MII_ANAR: + phy_reg = DC_AL_ANAR; + break; + case MII_ANLPAR: + phy_reg = DC_AL_LPAR; + break; + case MII_ANER: + phy_reg = DC_AL_ANER; + break; + default: + device_printf(dev, "phy_read: bad phy register %x\n", + reg); + return (0); + break; + } + + rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; + + if (rval == 0xFFFF) + return (0); + return (rval); + } + + frame.mii_phyaddr = phy; + frame.mii_regaddr = reg; + if (sc->dc_type == DC_TYPE_98713) { + phy_reg = CSR_READ_4(sc, DC_NETCFG); + CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); + } + dc_mii_readreg(sc, &frame); + if (sc->dc_type == DC_TYPE_98713) + CSR_WRITE_4(sc, DC_NETCFG, phy_reg); + + return (frame.mii_data); +} + +static int +dc_miibus_writereg(device_t dev, int phy, int reg, int data) +{ + struct dc_softc *sc; + struct dc_mii_frame frame; + int i, phy_reg = 0; + + sc = device_get_softc(dev); + bzero(&frame, sizeof(frame)); + + if (DC_IS_PNIC(sc)) { + CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | + (phy << 23) | (reg << 10) | data); + for (i = 0; i < DC_TIMEOUT; i++) { + if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) + break; + } + return (0); + } + + if (DC_IS_COMET(sc)) { + switch (reg) { + case MII_BMCR: + phy_reg = DC_AL_BMCR; + break; + case MII_BMSR: + phy_reg = DC_AL_BMSR; + break; + case MII_PHYIDR1: + phy_reg = DC_AL_VENID; + break; + case MII_PHYIDR2: + phy_reg = DC_AL_DEVID; + break; + case MII_ANAR: + phy_reg = DC_AL_ANAR; + break; + case MII_ANLPAR: + phy_reg = DC_AL_LPAR; + break; + case MII_ANER: + phy_reg = DC_AL_ANER; + break; + default: + device_printf(dev, "phy_write: bad phy register %x\n", + reg); + return (0); + break; + } + + CSR_WRITE_4(sc, phy_reg, data); + return (0); + } + + frame.mii_phyaddr = phy; + frame.mii_regaddr = reg; + frame.mii_data = data; + + if (sc->dc_type == DC_TYPE_98713) { + phy_reg = CSR_READ_4(sc, DC_NETCFG); + CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); + } + dc_mii_writereg(sc, &frame); + if (sc->dc_type == DC_TYPE_98713) + CSR_WRITE_4(sc, DC_NETCFG, phy_reg); + + return (0); +} + +static void +dc_miibus_statchg(device_t dev) +{ + struct dc_softc *sc; + struct mii_data *mii; + struct ifmedia *ifm; + + sc = device_get_softc(dev); + if (DC_IS_ADMTEK(sc)) + return; + + mii = device_get_softc(sc->dc_miibus); + ifm = &mii->mii_media; + if (DC_IS_DAVICOM(sc) && + IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { + dc_setcfg(sc, ifm->ifm_media); + sc->dc_if_media = ifm->ifm_media; + } else { + dc_setcfg(sc, mii->mii_media_active); + sc->dc_if_media = mii->mii_media_active; + } +} + +/* + * Special support for DM9102A cards with HomePNA PHYs. Note: + * with the Davicom DM9102A/DM9801 eval board that I have, it seems + * to be impossible to talk to the management interface of the DM9801 + * PHY (its MDIO pin is not connected to anything). Consequently, + * the driver has to just 'know' about the additional mode and deal + * with it itself. *sigh* + */ +static void +dc_miibus_mediainit(device_t dev) +{ + struct dc_softc *sc; + struct mii_data *mii; + struct ifmedia *ifm; + int rev; + + rev = pci_get_revid(dev); + + sc = device_get_softc(dev); + mii = device_get_softc(sc->dc_miibus); + ifm = &mii->mii_media; + + if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) + ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); +} + +#define DC_BITS_512 9 +#define DC_BITS_128 7 +#define DC_BITS_64 6 + +static uint32_t +dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) +{ + uint32_t crc; + + /* Compute CRC for the address value. */ + crc = ether_crc32_le(addr, ETHER_ADDR_LEN); + + /* + * The hash table on the PNIC II and the MX98715AEC-C/D/E + * chips is only 128 bits wide. + */ + if (sc->dc_flags & DC_128BIT_HASH) + return (crc & ((1 << DC_BITS_128) - 1)); + + /* The hash table on the MX98715BEC is only 64 bits wide. */ + if (sc->dc_flags & DC_64BIT_HASH) + return (crc & ((1 << DC_BITS_64) - 1)); + + /* Xircom's hash filtering table is different (read: weird) */ + /* Xircom uses the LEAST significant bits */ + if (DC_IS_XIRCOM(sc)) { + if ((crc & 0x180) == 0x180) + return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); + else + return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + + (12 << 4)); + } + + return (crc & ((1 << DC_BITS_512) - 1)); +} + +/* + * Calculate CRC of a multicast group address, return the lower 6 bits. + */ +static uint32_t +dc_mchash_be(const uint8_t *addr) +{ + uint32_t crc; + + /* Compute CRC for the address value. */ + crc = ether_crc32_be(addr, ETHER_ADDR_LEN); + + /* Return the filter bit position. */ + return ((crc >> 26) & 0x0000003F); +} + +/* + * 21143-style RX filter setup routine. Filter programming is done by + * downloading a special setup frame into the TX engine. 21143, Macronix, + * PNIC, PNIC II and Davicom chips are programmed this way. + * + * We always program the chip using 'hash perfect' mode, i.e. one perfect + * address (our node address) and a 512-bit hash filter for multicast + * frames. We also sneak the broadcast address into the hash filter since + * we need that too. + */ +static void +dc_setfilt_21143(struct dc_softc *sc) +{ + uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; + struct dc_desc *sframe; + u_int32_t h, *sp; + struct ifmultiaddr *ifma; + struct ifnet *ifp; + int i; + + ifp = sc->dc_ifp; + + i = sc->dc_cdata.dc_tx_prod; + DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); + sc->dc_cdata.dc_tx_cnt++; + sframe = &sc->dc_ldata->dc_tx_list[i]; + sp = sc->dc_cdata.dc_sbuf; + bzero(sp, DC_SFRAME_LEN); + + sframe->dc_data = htole32(sc->dc_saddr); + sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | + DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); + + sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; + + /* If we want promiscuous mode, set the allframes bit. */ + if (ifp->if_flags & IFF_PROMISC) + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); + else + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); + + if (ifp->if_flags & IFF_ALLMULTI) + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); + else + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); + + if_maddr_rlock(ifp); + TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { + if (ifma->ifma_addr->sa_family != AF_LINK) + continue; + h = dc_mchash_le(sc, + LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); + sp[h >> 4] |= htole32(1 << (h & 0xF)); + } + if_maddr_runlock(ifp); + + if (ifp->if_flags & IFF_BROADCAST) { + h = dc_mchash_le(sc, ifp->if_broadcastaddr); + sp[h >> 4] |= htole32(1 << (h & 0xF)); + } + + /* Set our MAC address. */ + bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); + sp[39] = DC_SP_MAC(eaddr[0]); + sp[40] = DC_SP_MAC(eaddr[1]); + sp[41] = DC_SP_MAC(eaddr[2]); + + sframe->dc_status = htole32(DC_TXSTAT_OWN); + CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); + + /* + * The PNIC takes an exceedingly long time to process its + * setup frame; wait 10ms after posting the setup frame + * before proceeding, just so it has time to swallow its + * medicine. + */ + DELAY(10000); + + sc->dc_wdog_timer = 5; +} + +static void +dc_setfilt_admtek(struct dc_softc *sc) +{ + uint8_t eaddr[ETHER_ADDR_LEN]; + struct ifnet *ifp; + struct ifmultiaddr *ifma; + int h = 0; + u_int32_t hashes[2] = { 0, 0 }; + + ifp = sc->dc_ifp; + + /* Init our MAC address. */ + bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); + CSR_WRITE_4(sc, DC_AL_PAR0, eaddr[3] << 24 | eaddr[2] << 16 | + eaddr[1] << 8 | eaddr[0]); + CSR_WRITE_4(sc, DC_AL_PAR1, eaddr[5] << 8 | eaddr[4]); + + /* If we want promiscuous mode, set the allframes bit. */ + if (ifp->if_flags & IFF_PROMISC) + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); + else + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); + + if (ifp->if_flags & IFF_ALLMULTI) + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); + else + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); + + /* First, zot all the existing hash bits. */ + CSR_WRITE_4(sc, DC_AL_MAR0, 0); + CSR_WRITE_4(sc, DC_AL_MAR1, 0); + + /* + * If we're already in promisc or allmulti mode, we + * don't have to bother programming the multicast filter. + */ + if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) + return; + + /* Now program new ones. */ + if_maddr_rlock(ifp); + TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { + if (ifma->ifma_addr->sa_family != AF_LINK) + continue; + if (DC_IS_CENTAUR(sc)) + h = dc_mchash_le(sc, + LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); + else + h = dc_mchash_be( + LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); + if (h < 32) + hashes[0] |= (1 << h); + else + hashes[1] |= (1 << (h - 32)); + } + if_maddr_runlock(ifp); + + CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); + CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); +} + +static void +dc_setfilt_asix(struct dc_softc *sc) +{ + uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; + struct ifnet *ifp; + struct ifmultiaddr *ifma; + int h = 0; + u_int32_t hashes[2] = { 0, 0 }; + + ifp = sc->dc_ifp; + + /* Init our MAC address. */ + bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); + CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); + CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[0]); + CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); + CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[1]); + + /* If we want promiscuous mode, set the allframes bit. */ + if (ifp->if_flags & IFF_PROMISC) + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); + else + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); + + if (ifp->if_flags & IFF_ALLMULTI) + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); + else + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); + + /* + * The ASIX chip has a special bit to enable reception + * of broadcast frames. + */ + if (ifp->if_flags & IFF_BROADCAST) + DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); + else + DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); + + /* first, zot all the existing hash bits */ + CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); + CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); + CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); + CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); + + /* + * If we're already in promisc or allmulti mode, we + * don't have to bother programming the multicast filter. + */ + if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) + return; + + /* now program new ones */ + if_maddr_rlock(ifp); + TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { + if (ifma->ifma_addr->sa_family != AF_LINK) + continue; + h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); + if (h < 32) + hashes[0] |= (1 << h); + else + hashes[1] |= (1 << (h - 32)); + } + if_maddr_runlock(ifp); + + CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); + CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); + CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); + CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); +} + +static void +dc_setfilt_xircom(struct dc_softc *sc) +{ + uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; + struct ifnet *ifp; + struct ifmultiaddr *ifma; + struct dc_desc *sframe; + u_int32_t h, *sp; + int i; + + ifp = sc->dc_ifp; + DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); + + i = sc->dc_cdata.dc_tx_prod; + DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); + sc->dc_cdata.dc_tx_cnt++; + sframe = &sc->dc_ldata->dc_tx_list[i]; + sp = sc->dc_cdata.dc_sbuf; + bzero(sp, DC_SFRAME_LEN); + + sframe->dc_data = htole32(sc->dc_saddr); + sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | + DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); + + sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; + + /* If we want promiscuous mode, set the allframes bit. */ + if (ifp->if_flags & IFF_PROMISC) + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); + else + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); + + if (ifp->if_flags & IFF_ALLMULTI) + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); + else + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); + + if_maddr_rlock(ifp); + TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { + if (ifma->ifma_addr->sa_family != AF_LINK) + continue; + h = dc_mchash_le(sc, + LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); + sp[h >> 4] |= htole32(1 << (h & 0xF)); + } + if_maddr_runlock(ifp); + + if (ifp->if_flags & IFF_BROADCAST) { + h = dc_mchash_le(sc, ifp->if_broadcastaddr); + sp[h >> 4] |= htole32(1 << (h & 0xF)); + } + + /* Set our MAC address. */ + bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); + sp[0] = DC_SP_MAC(eaddr[0]); + sp[1] = DC_SP_MAC(eaddr[1]); + sp[2] = DC_SP_MAC(eaddr[2]); + + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); + ifp->if_drv_flags |= IFF_DRV_RUNNING; + sframe->dc_status = htole32(DC_TXSTAT_OWN); + CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); + + /* + * Wait some time... + */ + DELAY(1000); + + sc->dc_wdog_timer = 5; +} + +static void +dc_setfilt(struct dc_softc *sc) +{ + + if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || + DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) + dc_setfilt_21143(sc); + + if (DC_IS_ASIX(sc)) + dc_setfilt_asix(sc); + + if (DC_IS_ADMTEK(sc)) + dc_setfilt_admtek(sc); + + if (DC_IS_XIRCOM(sc)) + dc_setfilt_xircom(sc); +} + +/* + * In order to fiddle with the 'full-duplex' and '100Mbps' bits in + * the netconfig register, we first have to put the transmit and/or + * receive logic in the idle state. + */ +static void +dc_setcfg(struct dc_softc *sc, int media) +{ + int i, restart = 0, watchdogreg; + u_int32_t isr; + + if (IFM_SUBTYPE(media) == IFM_NONE) + return; + + if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { + restart = 1; + DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); + + for (i = 0; i < DC_TIMEOUT; i++) { + isr = CSR_READ_4(sc, DC_ISR); + if (isr & DC_ISR_TX_IDLE && + ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || + (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) + break; + DELAY(10); + } + + if (i == DC_TIMEOUT) { + if (!(isr & DC_ISR_TX_IDLE) && !DC_IS_ASIX(sc)) + device_printf(sc->dc_dev, + "%s: failed to force tx to idle state\n", + __func__); + if (!((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || + (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && + !DC_HAS_BROKEN_RXSTATE(sc)) + device_printf(sc->dc_dev, + "%s: failed to force rx to idle state\n", + __func__); + } + } + + if (IFM_SUBTYPE(media) == IFM_100_TX) { + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); + if (sc->dc_pmode == DC_PMODE_MII) { + if (DC_IS_INTEL(sc)) { + /* There's a write enable bit here that reads as 1. */ + watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); + watchdogreg &= ~DC_WDOG_CTLWREN; + watchdogreg |= DC_WDOG_JABBERDIS; + CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); + } else { + DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); + } + DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | + DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); + if (sc->dc_type == DC_TYPE_98713) + DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | + DC_NETCFG_SCRAMBLER)); + if (!DC_IS_DAVICOM(sc)) + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); + DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); + if (DC_IS_INTEL(sc)) + dc_apply_fixup(sc, IFM_AUTO); + } else { + if (DC_IS_PNIC(sc)) { + DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); + DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); + DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); + } + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); + if (DC_IS_INTEL(sc)) + dc_apply_fixup(sc, + (media & IFM_GMASK) == IFM_FDX ? + IFM_100_TX | IFM_FDX : IFM_100_TX); + } + } + + if (IFM_SUBTYPE(media) == IFM_10_T) { + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); + if (sc->dc_pmode == DC_PMODE_MII) { + /* There's a write enable bit here that reads as 1. */ + if (DC_IS_INTEL(sc)) { + watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); + watchdogreg &= ~DC_WDOG_CTLWREN; + watchdogreg |= DC_WDOG_JABBERDIS; + CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); + } else { + DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); + } + DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | + DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); + if (sc->dc_type == DC_TYPE_98713) + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); + if (!DC_IS_DAVICOM(sc)) + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); + DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); + if (DC_IS_INTEL(sc)) + dc_apply_fixup(sc, IFM_AUTO); + } else { + if (DC_IS_PNIC(sc)) { + DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); + DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); + DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); + } + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); + if (DC_IS_INTEL(sc)) { + DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); + DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); + if ((media & IFM_GMASK) == IFM_FDX) + DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); + else + DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); + DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); + DC_CLRBIT(sc, DC_10BTCTRL, + DC_TCTL_AUTONEGENBL); + dc_apply_fixup(sc, + (media & IFM_GMASK) == IFM_FDX ? + IFM_10_T | IFM_FDX : IFM_10_T); + DELAY(20000); + } + } + } + + /* + * If this is a Davicom DM9102A card with a DM9801 HomePNA + * PHY and we want HomePNA mode, set the portsel bit to turn + * on the external MII port. + */ + if (DC_IS_DAVICOM(sc)) { + if (IFM_SUBTYPE(media) == IFM_HPNA_1) { + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); + sc->dc_link = 1; + } else { + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); + } + } + + if ((media & IFM_GMASK) == IFM_FDX) { + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); + if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) + DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); + } else { + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); + if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) + DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); + } + + if (restart) + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); +} + +static void +dc_reset(struct dc_softc *sc) +{ + int i; + + DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); + + for (i = 0; i < DC_TIMEOUT; i++) { + DELAY(10); + if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) + break; + } + + if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || + DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { + DELAY(10000); + DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); + i = 0; + } + + if (i == DC_TIMEOUT) + device_printf(sc->dc_dev, "reset never completed!\n"); + + /* Wait a little while for the chip to get its brains in order. */ + DELAY(1000); + + CSR_WRITE_4(sc, DC_IMR, 0x00000000); + CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); + CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); + + /* + * Bring the SIA out of reset. In some cases, it looks + * like failing to unreset the SIA soon enough gets it + * into a state where it will never come out of reset + * until we reset the whole chip again. + */ + if (DC_IS_INTEL(sc)) { + DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); + CSR_WRITE_4(sc, DC_10BTCTRL, 0); + CSR_WRITE_4(sc, DC_WATCHDOG, 0); + } +} + +static const struct dc_type * +dc_devtype(device_t dev) +{ + const struct dc_type *t; + u_int32_t devid; + u_int8_t rev; + + t = dc_devs; + devid = pci_get_devid(dev); + rev = pci_get_revid(dev); + + while (t->dc_name != NULL) { + if (devid == t->dc_devid && rev >= t->dc_minrev) + return (t); + t++; + } + + return (NULL); +} + +/* + * Probe for a 21143 or clone chip. Check the PCI vendor and device + * IDs against our list and return a device name if we find a match. + * We do a little bit of extra work to identify the exact type of + * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, + * but different revision IDs. The same is true for 98715/98715A + * chips and the 98725, as well as the ASIX and ADMtek chips. In some + * cases, the exact chip revision affects driver behavior. + */ +static int +dc_probe(device_t dev) +{ + const struct dc_type *t; + + t = dc_devtype(dev); + + if (t != NULL) { + device_set_desc(dev, t->dc_name); + return (BUS_PROBE_DEFAULT); + } + + return (ENXIO); +} + +static void +dc_apply_fixup(struct dc_softc *sc, int media) +{ + struct dc_mediainfo *m; + u_int8_t *p; + int i; + u_int32_t reg; + + m = sc->dc_mi; + + while (m != NULL) { + if (m->dc_media == media) + break; + m = m->dc_next; + } + + if (m == NULL) + return; + + for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { + reg = (p[0] | (p[1] << 8)) << 16; + CSR_WRITE_4(sc, DC_WATCHDOG, reg); + } + + for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { + reg = (p[0] | (p[1] << 8)) << 16; + CSR_WRITE_4(sc, DC_WATCHDOG, reg); + } +} + +static void +dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) +{ + struct dc_mediainfo *m; + + m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); + switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { + case DC_SIA_CODE_10BT: + m->dc_media = IFM_10_T; + break; + case DC_SIA_CODE_10BT_FDX: + m->dc_media = IFM_10_T | IFM_FDX; + break; + case DC_SIA_CODE_10B2: + m->dc_media = IFM_10_2; + break; + case DC_SIA_CODE_10B5: + m->dc_media = IFM_10_5; + break; + default: + break; + } + + /* + * We need to ignore CSR13, CSR14, CSR15 for SIA mode. + * Things apparently already work for cards that do + * supply Media Specific Data. + */ + if (l->dc_sia_code & DC_SIA_CODE_EXT) { + m->dc_gp_len = 2; + m->dc_gp_ptr = + (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; + } else { + m->dc_gp_len = 2; + m->dc_gp_ptr = + (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; + } + + m->dc_next = sc->dc_mi; + sc->dc_mi = m; + + sc->dc_pmode = DC_PMODE_SIA; +} + +static void +dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) +{ + struct dc_mediainfo *m; + + m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); + if (l->dc_sym_code == DC_SYM_CODE_100BT) + m->dc_media = IFM_100_TX; + + if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) + m->dc_media = IFM_100_TX | IFM_FDX; + + m->dc_gp_len = 2; + m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; + + m->dc_next = sc->dc_mi; + sc->dc_mi = m; + + sc->dc_pmode = DC_PMODE_SYM; +} + +static void +dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) +{ + struct dc_mediainfo *m; + u_int8_t *p; + + m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); + /* We abuse IFM_AUTO to represent MII. */ + m->dc_media = IFM_AUTO; + m->dc_gp_len = l->dc_gpr_len; + + p = (u_int8_t *)l; + p += sizeof(struct dc_eblock_mii); + m->dc_gp_ptr = p; + p += 2 * l->dc_gpr_len; + m->dc_reset_len = *p; + p++; + m->dc_reset_ptr = p; + + m->dc_next = sc->dc_mi; + sc->dc_mi = m; +} + +static void +dc_read_srom(struct dc_softc *sc, int bits) +{ + int size; + + size = 2 << bits; + sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); + dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); +} + +static void +dc_parse_21143_srom(struct dc_softc *sc) +{ + struct dc_leaf_hdr *lhdr; + struct dc_eblock_hdr *hdr; + int have_mii, i, loff; + char *ptr; + + have_mii = 0; + loff = sc->dc_srom[27]; + lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); + + ptr = (char *)lhdr; + ptr += sizeof(struct dc_leaf_hdr) - 1; + /* + * Look if we got a MII media block. + */ + for (i = 0; i < lhdr->dc_mcnt; i++) { + hdr = (struct dc_eblock_hdr *)ptr; + if (hdr->dc_type == DC_EBLOCK_MII) + have_mii++; + + ptr += (hdr->dc_len & 0x7F); + ptr++; + } + + /* + * Do the same thing again. Only use SIA and SYM media + * blocks if no MII media block is available. + */ + ptr = (char *)lhdr; + ptr += sizeof(struct dc_leaf_hdr) - 1; + for (i = 0; i < lhdr->dc_mcnt; i++) { + hdr = (struct dc_eblock_hdr *)ptr; + switch (hdr->dc_type) { + case DC_EBLOCK_MII: + dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); + break; + case DC_EBLOCK_SIA: + if (! have_mii) + dc_decode_leaf_sia(sc, + (struct dc_eblock_sia *)hdr); + break; + case DC_EBLOCK_SYM: + if (! have_mii) + dc_decode_leaf_sym(sc, + (struct dc_eblock_sym *)hdr); + break; + default: + /* Don't care. Yet. */ + break; + } + ptr += (hdr->dc_len & 0x7F); + ptr++; + } +} + +static void +dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) +{ + u_int32_t *paddr; + + KASSERT(nseg == 1, + ("%s: wrong number of segments (%d)", __func__, nseg)); + paddr = arg; + *paddr = segs->ds_addr; +} + +/* + * Attach the interface. Allocate softc structures, do ifmedia + * setup and ethernet/BPF attach. + */ +static int +dc_attach(device_t dev) +{ + uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; + u_int32_t command; + struct dc_softc *sc; + struct ifnet *ifp; + u_int32_t reg, revision; + int error, i, mac_offset, phy, rid, tmp; + u_int8_t *mac; + + sc = device_get_softc(dev); + sc->dc_dev = dev; + + mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, + MTX_DEF); + + /* + * Map control/status registers. + */ + pci_enable_busmaster(dev); + + rid = DC_RID; + sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); + + if (sc->dc_res == NULL) { + device_printf(dev, "couldn't map ports/memory\n"); + error = ENXIO; + goto fail; + } + + sc->dc_btag = rman_get_bustag(sc->dc_res); + sc->dc_bhandle = rman_get_bushandle(sc->dc_res); + + /* Allocate interrupt. */ + rid = 0; + sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, + RF_SHAREABLE | RF_ACTIVE); + + if (sc->dc_irq == NULL) { + device_printf(dev, "couldn't map interrupt\n"); + error = ENXIO; + goto fail; + } + + /* Need this info to decide on a chip type. */ + sc->dc_info = dc_devtype(dev); + revision = pci_get_revid(dev); + + /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ + if (sc->dc_info->dc_devid != + DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168) && + sc->dc_info->dc_devid != + DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201)) + dc_eeprom_width(sc); + + switch (sc->dc_info->dc_devid) { + case DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143): + sc->dc_type = DC_TYPE_21143; + sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; + sc->dc_flags |= DC_REDUCED_MII_POLL; + /* Save EEPROM contents so we can parse them later. */ + dc_read_srom(sc, sc->dc_romwidth); + break; + case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009): + case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100): + case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102): + sc->dc_type = DC_TYPE_DM9102; + sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; + sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; + sc->dc_flags |= DC_TX_ALIGN; + sc->dc_pmode = DC_PMODE_MII; + + /* Increase the latency timer value. */ + pci_write_config(dev, PCIR_LATTIMER, 0x80, 1); + break; + case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981): + sc->dc_type = DC_TYPE_AL981; + sc->dc_flags |= DC_TX_USE_TX_INTR; + sc->dc_flags |= DC_TX_ADMTEK_WAR; + sc->dc_pmode = DC_PMODE_MII; + dc_read_srom(sc, sc->dc_romwidth); + break; + case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983): + case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985): + case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511): + case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513): + case DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD): + case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500): + case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX): + case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242): + case DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX): + case DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T): + case DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB): + case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120): + case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130): + case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08): + case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09): + sc->dc_type = DC_TYPE_AN983; + sc->dc_flags |= DC_64BIT_HASH; + sc->dc_flags |= DC_TX_USE_TX_INTR; + sc->dc_flags |= DC_TX_ADMTEK_WAR; + sc->dc_pmode = DC_PMODE_MII; + /* Don't read SROM for - auto-loaded on reset */ + break; + case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713): + case DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP): + if (revision < DC_REVISION_98713A) { + sc->dc_type = DC_TYPE_98713; + } + if (revision >= DC_REVISION_98713A) { + sc->dc_type = DC_TYPE_98713A; + sc->dc_flags |= DC_21143_NWAY; + } + sc->dc_flags |= DC_REDUCED_MII_POLL; + sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; + break; + case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5): + case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217): + /* + * Macronix MX98715AEC-C/D/E parts have only a + * 128-bit hash table. We need to deal with these + * in the same manner as the PNIC II so that we + * get the right number of bits out of the + * CRC routine. + */ + if (revision >= DC_REVISION_98715AEC_C && + revision < DC_REVISION_98725) + sc->dc_flags |= DC_128BIT_HASH; + sc->dc_type = DC_TYPE_987x5; + sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; + sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; + break; + case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727): + sc->dc_type = DC_TYPE_987x5; + sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; + sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; + break; + case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115): + sc->dc_type = DC_TYPE_PNICII; + sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; + sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; + break; + case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168): + sc->dc_type = DC_TYPE_PNIC; + sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; + sc->dc_flags |= DC_PNIC_RX_BUG_WAR; + sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); + if (revision < DC_REVISION_82C169) + sc->dc_pmode = DC_PMODE_SYM; + break; + case DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A): + sc->dc_type = DC_TYPE_ASIX; + sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; + sc->dc_flags |= DC_REDUCED_MII_POLL; + sc->dc_pmode = DC_PMODE_MII; + break; + case DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201): + sc->dc_type = DC_TYPE_XIRCOM; + sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | + DC_TX_ALIGN; + /* + * We don't actually need to coalesce, but we're doing + * it to obtain a double word aligned buffer. + * The DC_TX_COALESCE flag is required. + */ + sc->dc_pmode = DC_PMODE_MII; + break; + case DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112): + sc->dc_type = DC_TYPE_CONEXANT; + sc->dc_flags |= DC_TX_INTR_ALWAYS; + sc->dc_flags |= DC_REDUCED_MII_POLL; + sc->dc_pmode = DC_PMODE_MII; + dc_read_srom(sc, sc->dc_romwidth); + break; + default: + device_printf(dev, "unknown device: %x\n", + sc->dc_info->dc_devid); + break; + } + + /* Save the cache line size. */ + if (DC_IS_DAVICOM(sc)) + sc->dc_cachesize = 0; + else + sc->dc_cachesize = pci_get_cachelnsz(dev); + + /* Reset the adapter. */ + dc_reset(sc); + + /* Take 21143 out of snooze mode */ + if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { + command = pci_read_config(dev, DC_PCI_CFDD, 4); + command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); + pci_write_config(dev, DC_PCI_CFDD, command, 4); + } + + /* + * Try to learn something about the supported media. + * We know that ASIX and ADMtek and Davicom devices + * will *always* be using MII media, so that's a no-brainer. + * The tricky ones are the Macronix/PNIC II and the + * Intel 21143. + */ + if (DC_IS_INTEL(sc)) + dc_parse_21143_srom(sc); + else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { + if (sc->dc_type == DC_TYPE_98713) + sc->dc_pmode = DC_PMODE_MII; + else + sc->dc_pmode = DC_PMODE_SYM; + } else if (!sc->dc_pmode) + sc->dc_pmode = DC_PMODE_MII; + + /* + * Get station address from the EEPROM. + */ + switch(sc->dc_type) { + case DC_TYPE_98713: + case DC_TYPE_98713A: + case DC_TYPE_987x5: + case DC_TYPE_PNICII: + dc_read_eeprom(sc, (caddr_t)&mac_offset, + (DC_EE_NODEADDR_OFFSET / 2), 1, 0); + dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); + break; + case DC_TYPE_PNIC: + dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); + break; + case DC_TYPE_DM9102: + dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); +#ifdef __sparc64__ + /* + * If this is an onboard dc(4) the station address read from + * the EEPROM is all zero and we have to get it from the FCode. + */ + if (eaddr[0] == 0 && (eaddr[1] & ~0xffff) == 0) + OF_getetheraddr(dev, (caddr_t)&eaddr); +#endif + break; + case DC_TYPE_21143: + case DC_TYPE_ASIX: + dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); + break; + case DC_TYPE_AL981: + case DC_TYPE_AN983: + reg = CSR_READ_4(sc, DC_AL_PAR0); + mac = (uint8_t *)&eaddr[0]; + mac[0] = (reg >> 0) & 0xff; + mac[1] = (reg >> 8) & 0xff; + mac[2] = (reg >> 16) & 0xff; + mac[3] = (reg >> 24) & 0xff; + reg = CSR_READ_4(sc, DC_AL_PAR1); + mac[4] = (reg >> 0) & 0xff; + mac[5] = (reg >> 8) & 0xff; + break; + case DC_TYPE_CONEXANT: + bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, + ETHER_ADDR_LEN); + break; + case DC_TYPE_XIRCOM: + /* The MAC comes from the CIS. */ + mac = pci_get_ether(dev); + if (!mac) { + device_printf(dev, "No station address in CIS!\n"); + error = ENXIO; + goto fail; + } + bcopy(mac, eaddr, ETHER_ADDR_LEN); + break; + default: + dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); + break; + } + + /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ + error = bus_dma_tag_create(bus_get_dma_tag(dev), PAGE_SIZE, 0, + BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, + sizeof(struct dc_list_data), 1, sizeof(struct dc_list_data), + 0, NULL, NULL, &sc->dc_ltag); + if (error) { + device_printf(dev, "failed to allocate busdma tag\n"); + error = ENXIO; + goto fail; + } + error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata, + BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap); + if (error) { + device_printf(dev, "failed to allocate DMA safe memory\n"); + error = ENXIO; + goto fail; + } + error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata, + sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr, + BUS_DMA_NOWAIT); + if (error) { + device_printf(dev, "cannot get address of the descriptors\n"); + error = ENXIO; + goto fail; + } + + /* + * Allocate a busdma tag and DMA safe memory for the multicast + * setup frame. + */ + error = bus_dma_tag_create(bus_get_dma_tag(dev), PAGE_SIZE, 0, + BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, + DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, DC_SFRAME_LEN + DC_MIN_FRAMELEN, + 0, NULL, NULL, &sc->dc_stag); + if (error) { + device_printf(dev, "failed to allocate busdma tag\n"); + error = ENXIO; + goto fail; + } + error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, + BUS_DMA_NOWAIT, &sc->dc_smap); + if (error) { + device_printf(dev, "failed to allocate DMA safe memory\n"); + error = ENXIO; + goto fail; + } + error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, + DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); + if (error) { + device_printf(dev, "cannot get address of the descriptors\n"); + error = ENXIO; + goto fail; + } + + /* Allocate a busdma tag for mbufs. */ + error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, + BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, + MCLBYTES * DC_MAXFRAGS, DC_MAXFRAGS, MCLBYTES, + 0, NULL, NULL, &sc->dc_mtag); + if (error) { + device_printf(dev, "failed to allocate busdma tag\n"); + error = ENXIO; + goto fail; + } + + /* Create the TX/RX busdma maps. */ + for (i = 0; i < DC_TX_LIST_CNT; i++) { + error = bus_dmamap_create(sc->dc_mtag, 0, + &sc->dc_cdata.dc_tx_map[i]); + if (error) { + device_printf(dev, "failed to init TX ring\n"); + error = ENXIO; + goto fail; + } + } + for (i = 0; i < DC_RX_LIST_CNT; i++) { + error = bus_dmamap_create(sc->dc_mtag, 0, + &sc->dc_cdata.dc_rx_map[i]); + if (error) { + device_printf(dev, "failed to init RX ring\n"); + error = ENXIO; + goto fail; + } + } + error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap); + if (error) { + device_printf(dev, "failed to init RX ring\n"); + error = ENXIO; + goto fail; + } + + ifp = sc->dc_ifp = if_alloc(IFT_ETHER); + if (ifp == NULL) { + device_printf(dev, "can not if_alloc()\n"); + error = ENOSPC; + goto fail; + } + ifp->if_softc = sc; + if_initname(ifp, device_get_name(dev), device_get_unit(dev)); + ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; + ifp->if_ioctl = dc_ioctl; + ifp->if_start = dc_start; + ifp->if_init = dc_init; + IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1); + ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1; + IFQ_SET_READY(&ifp->if_snd); + + /* + * Do MII setup. If this is a 21143, check for a PHY on the + * MII bus after applying any necessary fixups to twiddle the + * GPIO bits. If we don't end up finding a PHY, restore the + * old selection (SIA only or SIA/SYM) and attach the dcphy + * driver instead. + */ + tmp = 0; + if (DC_IS_INTEL(sc)) { + dc_apply_fixup(sc, IFM_AUTO); + tmp = sc->dc_pmode; + sc->dc_pmode = DC_PMODE_MII; + } + + /* + * Setup General Purpose port mode and data so the tulip can talk + * to the MII. This needs to be done before mii_attach so that + * we can actually see them. + */ + if (DC_IS_XIRCOM(sc)) { + CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | + DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); + DELAY(10); + CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | + DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); + DELAY(10); + } + + phy = MII_PHY_ANY; + /* + * Note: both the AL981 and AN983 have internal PHYs, however the + * AL981 provides direct access to the PHY registers while the AN983 + * uses a serial MII interface. The AN983's MII interface is also + * buggy in that you can read from any MII address (0 to 31), but + * only address 1 behaves normally. To deal with both cases, we + * pretend that the PHY is at MII address 1. + */ + if (DC_IS_ADMTEK(sc)) + phy = DC_ADMTEK_PHYADDR; + + /* + * Note: the ukphy probes of the RS7112 report a PHY at MII address + * 0 (possibly HomePNA?) and 1 (ethernet) so we only respond to the + * correct one. + */ + if (DC_IS_CONEXANT(sc)) + phy = DC_CONEXANT_PHYADDR; + + error = mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd, + dc_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); + + if (error && DC_IS_INTEL(sc)) { + sc->dc_pmode = tmp; + if (sc->dc_pmode != DC_PMODE_SIA) + sc->dc_pmode = DC_PMODE_SYM; + sc->dc_flags |= DC_21143_NWAY; + mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd, + dc_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, + MII_OFFSET_ANY, 0); + /* + * For non-MII cards, we need to have the 21143 + * drive the LEDs. Except there are some systems + * like the NEC VersaPro NoteBook PC which have no + * LEDs, and twiddling these bits has adverse effects + * on them. (I.e. you suddenly can't get a link.) + */ + if (!(pci_get_subvendor(dev) == 0x1033 && + pci_get_subdevice(dev) == 0x8028)) + sc->dc_flags |= DC_TULIP_LEDS; + error = 0; + } + + if (error) { + device_printf(dev, "attaching PHYs failed\n"); + goto fail; + } + + if (DC_IS_ADMTEK(sc)) { + /* + * Set automatic TX underrun recovery for the ADMtek chips + */ + DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); + } + + /* + * Tell the upper layer(s) we support long frames. + */ + ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); + ifp->if_capabilities |= IFCAP_VLAN_MTU; + ifp->if_capenable = ifp->if_capabilities; +#ifdef DEVICE_POLLING + ifp->if_capabilities |= IFCAP_POLLING; +#endif + + callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0); + callout_init_mtx(&sc->dc_wdog_ch, &sc->dc_mtx, 0); + + /* + * Call MI attach routine. + */ + ether_ifattach(ifp, (caddr_t)eaddr); + + /* Hook interrupt last to avoid having to lock softc */ + error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE, + NULL, dc_intr, sc, &sc->dc_intrhand); + + if (error) { + device_printf(dev, "couldn't set up irq\n"); + ether_ifdetach(ifp); + goto fail; + } + +fail: + if (error) + dc_detach(dev); + return (error); +} + +/* + * Shutdown hardware and free up resources. This can be called any + * time after the mutex has been initialized. It is called in both + * the error case in attach and the normal detach case so it needs + * to be careful about only freeing resources that have actually been + * allocated. + */ +static int +dc_detach(device_t dev) +{ + struct dc_softc *sc; + struct ifnet *ifp; + struct dc_mediainfo *m; + int i; + + sc = device_get_softc(dev); + KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); + + ifp = sc->dc_ifp; + +#ifdef DEVICE_POLLING + if (ifp->if_capenable & IFCAP_POLLING) + ether_poll_deregister(ifp); +#endif + + /* These should only be active if attach succeeded */ + if (device_is_attached(dev)) { + DC_LOCK(sc); + dc_stop(sc); + DC_UNLOCK(sc); + callout_drain(&sc->dc_stat_ch); + callout_drain(&sc->dc_wdog_ch); + ether_ifdetach(ifp); + } + if (sc->dc_miibus) + device_delete_child(dev, sc->dc_miibus); + bus_generic_detach(dev); + + if (sc->dc_intrhand) + bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); + if (sc->dc_irq) + bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); + if (sc->dc_res) + bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); + + if (ifp) + if_free(ifp); + + if (sc->dc_cdata.dc_sbuf != NULL) + bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap); + if (sc->dc_ldata != NULL) + bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap); + if (sc->dc_mtag) { + for (i = 0; i < DC_TX_LIST_CNT; i++) + if (sc->dc_cdata.dc_tx_map[i] != NULL) + bus_dmamap_destroy(sc->dc_mtag, + sc->dc_cdata.dc_tx_map[i]); + for (i = 0; i < DC_RX_LIST_CNT; i++) + if (sc->dc_cdata.dc_rx_map[i] != NULL) + bus_dmamap_destroy(sc->dc_mtag, + sc->dc_cdata.dc_rx_map[i]); + bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap); + } + if (sc->dc_stag) + bus_dma_tag_destroy(sc->dc_stag); + if (sc->dc_mtag) + bus_dma_tag_destroy(sc->dc_mtag); + if (sc->dc_ltag) + bus_dma_tag_destroy(sc->dc_ltag); + + free(sc->dc_pnic_rx_buf, M_DEVBUF); + + while (sc->dc_mi != NULL) { + m = sc->dc_mi->dc_next; + free(sc->dc_mi, M_DEVBUF); + sc->dc_mi = m; + } + free(sc->dc_srom, M_DEVBUF); + + mtx_destroy(&sc->dc_mtx); + + return (0); +} + +/* + * Initialize the transmit descriptors. + */ +static int +dc_list_tx_init(struct dc_softc *sc) +{ + struct dc_chain_data *cd; + struct dc_list_data *ld; + int i, nexti; + + cd = &sc->dc_cdata; + ld = sc->dc_ldata; + for (i = 0; i < DC_TX_LIST_CNT; i++) { + if (i == DC_TX_LIST_CNT - 1) + nexti = 0; + else + nexti = i + 1; + ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); + cd->dc_tx_chain[i] = NULL; + ld->dc_tx_list[i].dc_data = 0; + ld->dc_tx_list[i].dc_ctl = 0; + } + + cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; + bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, + BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); + return (0); +} + + +/* + * Initialize the RX descriptors and allocate mbufs for them. Note that + * we arrange the descriptors in a closed ring, so that the last descriptor + * points back to the first. + */ +static int +dc_list_rx_init(struct dc_softc *sc) +{ + struct dc_chain_data *cd; + struct dc_list_data *ld; + int i, nexti; + + cd = &sc->dc_cdata; + ld = sc->dc_ldata; + + for (i = 0; i < DC_RX_LIST_CNT; i++) { + if (dc_newbuf(sc, i, 1) != 0) + return (ENOBUFS); + if (i == DC_RX_LIST_CNT - 1) + nexti = 0; + else + nexti = i + 1; + ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); + } + + cd->dc_rx_prod = 0; + bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, + BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); + return (0); +} + +/* + * Initialize an RX descriptor and attach an MBUF cluster. + */ +static int +dc_newbuf(struct dc_softc *sc, int i, int alloc) +{ + struct mbuf *m_new; + bus_dmamap_t tmp; + bus_dma_segment_t segs[1]; + int error, nseg; + + if (alloc) { + m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + if (m_new == NULL) + return (ENOBUFS); + } else { + m_new = sc->dc_cdata.dc_rx_chain[i]; + m_new->m_data = m_new->m_ext.ext_buf; + } + m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; + m_adj(m_new, sizeof(u_int64_t)); + + /* + * If this is a PNIC chip, zero the buffer. This is part + * of the workaround for the receive bug in the 82c168 and + * 82c169 chips. + */ + if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) + bzero(mtod(m_new, char *), m_new->m_len); + + /* No need to remap the mbuf if we're reusing it. */ + if (alloc) { + error = bus_dmamap_load_mbuf_sg(sc->dc_mtag, sc->dc_sparemap, + m_new, segs, &nseg, 0); + if (error) { + m_freem(m_new); + return (error); + } + KASSERT(nseg == 1, + ("%s: wrong number of segments (%d)", __func__, nseg)); + sc->dc_ldata->dc_rx_list[i].dc_data = htole32(segs->ds_addr); + bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); + tmp = sc->dc_cdata.dc_rx_map[i]; + sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; + sc->dc_sparemap = tmp; + sc->dc_cdata.dc_rx_chain[i] = m_new; + } + + sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); + sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); + bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], + BUS_DMASYNC_PREREAD); + bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, + BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); + return (0); +} + +/* + * Grrrrr. + * The PNIC chip has a terrible bug in it that manifests itself during + * periods of heavy activity. The exact mode of failure if difficult to + * pinpoint: sometimes it only happens in promiscuous mode, sometimes it + * will happen on slow machines. The bug is that sometimes instead of + * uploading one complete frame during reception, it uploads what looks + * like the entire contents of its FIFO memory. The frame we want is at + * the end of the whole mess, but we never know exactly how much data has + * been uploaded, so salvaging the frame is hard. + * + * There is only one way to do it reliably, and it's disgusting. + * Here's what we know: + * + * - We know there will always be somewhere between one and three extra + * descriptors uploaded. + * + * - We know the desired received frame will always be at the end of the + * total data upload. + * + * - We know the size of the desired received frame because it will be + * provided in the length field of the status word in the last descriptor. + * + * Here's what we do: + * + * - When we allocate buffers for the receive ring, we bzero() them. + * This means that we know that the buffer contents should be all + * zeros, except for data uploaded by the chip. + * + * - We also force the PNIC chip to upload frames that include the + * ethernet CRC at the end. + * + * - We gather all of the bogus frame data into a single buffer. + * + * - We then position a pointer at the end of this buffer and scan + * backwards until we encounter the first non-zero byte of data. + * This is the end of the received frame. We know we will encounter + * some data at the end of the frame because the CRC will always be + * there, so even if the sender transmits a packet of all zeros, + * we won't be fooled. + * + * - We know the size of the actual received frame, so we subtract + * that value from the current pointer location. This brings us + * to the start of the actual received packet. + * + * - We copy this into an mbuf and pass it on, along with the actual + * frame length. + * + * The performance hit is tremendous, but it beats dropping frames all + * the time. + */ + +#define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) +static void +dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) +{ + struct dc_desc *cur_rx; + struct dc_desc *c = NULL; + struct mbuf *m = NULL; + unsigned char *ptr; + int i, total_len; + u_int32_t rxstat = 0; + + i = sc->dc_pnic_rx_bug_save; + cur_rx = &sc->dc_ldata->dc_rx_list[idx]; + ptr = sc->dc_pnic_rx_buf; + bzero(ptr, DC_RXLEN * 5); + + /* Copy all the bytes from the bogus buffers. */ + while (1) { + c = &sc->dc_ldata->dc_rx_list[i]; + rxstat = le32toh(c->dc_status); + m = sc->dc_cdata.dc_rx_chain[i]; + bcopy(mtod(m, char *), ptr, DC_RXLEN); + ptr += DC_RXLEN; + /* If this is the last buffer, break out. */ + if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) + break; + dc_newbuf(sc, i, 0); + DC_INC(i, DC_RX_LIST_CNT); + } + + /* Find the length of the actual receive frame. */ + total_len = DC_RXBYTES(rxstat); + + /* Scan backwards until we hit a non-zero byte. */ + while (*ptr == 0x00) + ptr--; + + /* Round off. */ + if ((uintptr_t)(ptr) & 0x3) + ptr -= 1; + + /* Now find the start of the frame. */ + ptr -= total_len; + if (ptr < sc->dc_pnic_rx_buf) + ptr = sc->dc_pnic_rx_buf; + + /* + * Now copy the salvaged frame to the last mbuf and fake up + * the status word to make it look like a successful + * frame reception. + */ + dc_newbuf(sc, i, 0); + bcopy(ptr, mtod(m, char *), total_len); + cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); +} + +/* + * This routine searches the RX ring for dirty descriptors in the + * event that the rxeof routine falls out of sync with the chip's + * current descriptor pointer. This may happen sometimes as a result + * of a "no RX buffer available" condition that happens when the chip + * consumes all of the RX buffers before the driver has a chance to + * process the RX ring. This routine may need to be called more than + * once to bring the driver back in sync with the chip, however we + * should still be getting RX DONE interrupts to drive the search + * for new packets in the RX ring, so we should catch up eventually. + */ +static int +dc_rx_resync(struct dc_softc *sc) +{ + struct dc_desc *cur_rx; + int i, pos; + + pos = sc->dc_cdata.dc_rx_prod; + + for (i = 0; i < DC_RX_LIST_CNT; i++) { + cur_rx = &sc->dc_ldata->dc_rx_list[pos]; + if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) + break; + DC_INC(pos, DC_RX_LIST_CNT); + } + + /* If the ring really is empty, then just return. */ + if (i == DC_RX_LIST_CNT) + return (0); + + /* We've fallen behing the chip: catch it. */ + sc->dc_cdata.dc_rx_prod = pos; + + return (EAGAIN); +} + +/* + * A frame has been uploaded: pass the resulting mbuf chain up to + * the higher level protocols. + */ +static int +dc_rxeof(struct dc_softc *sc) +{ + struct mbuf *m, *m0; + struct ifnet *ifp; + struct dc_desc *cur_rx; + int i, total_len, rx_npkts; + u_int32_t rxstat; + + DC_LOCK_ASSERT(sc); + + ifp = sc->dc_ifp; + i = sc->dc_cdata.dc_rx_prod; + total_len = 0; + rx_npkts = 0; + + bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); + while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) & + DC_RXSTAT_OWN)) { +#ifdef DEVICE_POLLING + if (ifp->if_capenable & IFCAP_POLLING) { + if (sc->rxcycles <= 0) + break; + sc->rxcycles--; + } +#endif + cur_rx = &sc->dc_ldata->dc_rx_list[i]; + rxstat = le32toh(cur_rx->dc_status); + m = sc->dc_cdata.dc_rx_chain[i]; + bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], + BUS_DMASYNC_POSTREAD); + total_len = DC_RXBYTES(rxstat); + + if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { + if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { + if (rxstat & DC_RXSTAT_FIRSTFRAG) + sc->dc_pnic_rx_bug_save = i; + if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { + DC_INC(i, DC_RX_LIST_CNT); + continue; + } + dc_pnic_rx_bug_war(sc, i); + rxstat = le32toh(cur_rx->dc_status); + total_len = DC_RXBYTES(rxstat); + } + } + + /* + * If an error occurs, update stats, clear the + * status word and leave the mbuf cluster in place: + * it should simply get re-used next time this descriptor + * comes up in the ring. However, don't report long + * frames as errors since they could be vlans. + */ + if ((rxstat & DC_RXSTAT_RXERR)) { + if (!(rxstat & DC_RXSTAT_GIANT) || + (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | + DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | + DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { + ifp->if_ierrors++; + if (rxstat & DC_RXSTAT_COLLSEEN) + ifp->if_collisions++; + dc_newbuf(sc, i, 0); + if (rxstat & DC_RXSTAT_CRCERR) { + DC_INC(i, DC_RX_LIST_CNT); + continue; + } else { + dc_init_locked(sc); + return (rx_npkts); + } + } + } + + /* No errors; receive the packet. */ + total_len -= ETHER_CRC_LEN; +#ifdef __NO_STRICT_ALIGNMENT + /* + * On architectures without alignment problems we try to + * allocate a new buffer for the receive ring, and pass up + * the one where the packet is already, saving the expensive + * copy done in m_devget(). + * If we are on an architecture with alignment problems, or + * if the allocation fails, then use m_devget and leave the + * existing buffer in the receive ring. + */ + if (dc_newbuf(sc, i, 1) == 0) { + m->m_pkthdr.rcvif = ifp; + m->m_pkthdr.len = m->m_len = total_len; + DC_INC(i, DC_RX_LIST_CNT); + } else +#endif + { + m0 = m_devget(mtod(m, char *), total_len, + ETHER_ALIGN, ifp, NULL); + dc_newbuf(sc, i, 0); + DC_INC(i, DC_RX_LIST_CNT); + if (m0 == NULL) { + ifp->if_ierrors++; + continue; + } + m = m0; + } + + ifp->if_ipackets++; + DC_UNLOCK(sc); + (*ifp->if_input)(ifp, m); + DC_LOCK(sc); + rx_npkts++; + } + + sc->dc_cdata.dc_rx_prod = i; + return (rx_npkts); +} + +/* + * A frame was downloaded to the chip. It's safe for us to clean up + * the list buffers. + */ +static void +dc_txeof(struct dc_softc *sc) +{ + struct dc_desc *cur_tx = NULL; + struct ifnet *ifp; + int idx; + u_int32_t ctl, txstat; + + ifp = sc->dc_ifp; + + /* + * Go through our tx list and free mbufs for those + * frames that have been transmitted. + */ + bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); + idx = sc->dc_cdata.dc_tx_cons; + while (idx != sc->dc_cdata.dc_tx_prod) { + + cur_tx = &sc->dc_ldata->dc_tx_list[idx]; + txstat = le32toh(cur_tx->dc_status); + ctl = le32toh(cur_tx->dc_ctl); + + if (txstat & DC_TXSTAT_OWN) + break; + + if (!(ctl & DC_TXCTL_LASTFRAG) || ctl & DC_TXCTL_SETUP) { + if (ctl & DC_TXCTL_SETUP) { + /* + * Yes, the PNIC is so brain damaged + * that it will sometimes generate a TX + * underrun error while DMAing the RX + * filter setup frame. If we detect this, + * we have to send the setup frame again, + * or else the filter won't be programmed + * correctly. + */ + if (DC_IS_PNIC(sc)) { + if (txstat & DC_TXSTAT_ERRSUM) + dc_setfilt(sc); + } + sc->dc_cdata.dc_tx_chain[idx] = NULL; + } + sc->dc_cdata.dc_tx_cnt--; + DC_INC(idx, DC_TX_LIST_CNT); + continue; + } + + if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { + /* + * XXX: Why does my Xircom taunt me so? + * For some reason it likes setting the CARRLOST flag + * even when the carrier is there. wtf?!? + * Who knows, but Conexant chips have the + * same problem. Maybe they took lessons + * from Xircom. + */ + if (/*sc->dc_type == DC_TYPE_21143 &&*/ + sc->dc_pmode == DC_PMODE_MII && + ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | + DC_TXSTAT_NOCARRIER))) + txstat &= ~DC_TXSTAT_ERRSUM; + } else { + if (/*sc->dc_type == DC_TYPE_21143 &&*/ + sc->dc_pmode == DC_PMODE_MII && + ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | + DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) + txstat &= ~DC_TXSTAT_ERRSUM; + } + + if (txstat & DC_TXSTAT_ERRSUM) { + ifp->if_oerrors++; + if (txstat & DC_TXSTAT_EXCESSCOLL) + ifp->if_collisions++; + if (txstat & DC_TXSTAT_LATECOLL) + ifp->if_collisions++; + if (!(txstat & DC_TXSTAT_UNDERRUN)) { + dc_init_locked(sc); + return; + } + } + + ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; + + ifp->if_opackets++; + if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { + bus_dmamap_sync(sc->dc_mtag, + sc->dc_cdata.dc_tx_map[idx], + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(sc->dc_mtag, + sc->dc_cdata.dc_tx_map[idx]); + m_freem(sc->dc_cdata.dc_tx_chain[idx]); + sc->dc_cdata.dc_tx_chain[idx] = NULL; + } + + sc->dc_cdata.dc_tx_cnt--; + DC_INC(idx, DC_TX_LIST_CNT); + } + sc->dc_cdata.dc_tx_cons = idx; + + if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt > DC_TX_LIST_RSVD) + ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; + + if (sc->dc_cdata.dc_tx_cnt == 0) + sc->dc_wdog_timer = 0; +} + +static void +dc_tick(void *xsc) +{ + struct dc_softc *sc; + struct mii_data *mii; + struct ifnet *ifp; + u_int32_t r; + + sc = xsc; + DC_LOCK_ASSERT(sc); + ifp = sc->dc_ifp; + mii = device_get_softc(sc->dc_miibus); + + if (sc->dc_flags & DC_REDUCED_MII_POLL) { + if (sc->dc_flags & DC_21143_NWAY) { + r = CSR_READ_4(sc, DC_10BTSTAT); + if (IFM_SUBTYPE(mii->mii_media_active) == + IFM_100_TX && (r & DC_TSTAT_LS100)) { + sc->dc_link = 0; + mii_mediachg(mii); + } + if (IFM_SUBTYPE(mii->mii_media_active) == + IFM_10_T && (r & DC_TSTAT_LS10)) { + sc->dc_link = 0; + mii_mediachg(mii); + } + if (sc->dc_link == 0) + mii_tick(mii); + } else { + /* + * For NICs which never report DC_RXSTATE_WAIT, we + * have to bite the bullet... + */ + if ((DC_HAS_BROKEN_RXSTATE(sc) || (CSR_READ_4(sc, + DC_ISR) & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && + sc->dc_cdata.dc_tx_cnt == 0) { + mii_tick(mii); + if (!(mii->mii_media_status & IFM_ACTIVE)) + sc->dc_link = 0; + } + } + } else + mii_tick(mii); + + /* + * When the init routine completes, we expect to be able to send + * packets right away, and in fact the network code will send a + * gratuitous ARP the moment the init routine marks the interface + * as running. However, even though the MAC may have been initialized, + * there may be a delay of a few seconds before the PHY completes + * autonegotiation and the link is brought up. Any transmissions + * made during that delay will be lost. Dealing with this is tricky: + * we can't just pause in the init routine while waiting for the + * PHY to come ready since that would bring the whole system to + * a screeching halt for several seconds. + * + * What we do here is prevent the TX start routine from sending + * any packets until a link has been established. After the + * interface has been initialized, the tick routine will poll + * the state of the PHY until the IFM_ACTIVE flag is set. Until + * that time, packets will stay in the send queue, and once the + * link comes up, they will be flushed out to the wire. + */ + if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && + IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { + sc->dc_link++; + if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) + dc_start_locked(ifp); + } + + if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) + callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); + else + callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); +} + +/* + * A transmit underrun has occurred. Back off the transmit threshold, + * or switch to store and forward mode if we have to. + */ +static void +dc_tx_underrun(struct dc_softc *sc) +{ + u_int32_t isr; + int i; + + if (DC_IS_DAVICOM(sc)) + dc_init_locked(sc); + + if (DC_IS_INTEL(sc)) { + /* + * The real 21143 requires that the transmitter be idle + * in order to change the transmit threshold or store + * and forward state. + */ + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); + + for (i = 0; i < DC_TIMEOUT; i++) { + isr = CSR_READ_4(sc, DC_ISR); + if (isr & DC_ISR_TX_IDLE) + break; + DELAY(10); + } + if (i == DC_TIMEOUT) { + device_printf(sc->dc_dev, + "%s: failed to force tx to idle state\n", + __func__); + dc_init_locked(sc); + } + } + + device_printf(sc->dc_dev, "TX underrun -- "); + sc->dc_txthresh += DC_TXTHRESH_INC; + if (sc->dc_txthresh > DC_TXTHRESH_MAX) { + printf("using store and forward mode\n"); + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); + } else { + printf("increasing TX threshold\n"); + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); + DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); + } + + if (DC_IS_INTEL(sc)) + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); +} + +#ifdef DEVICE_POLLING +static poll_handler_t dc_poll; + +static int +dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) +{ + struct dc_softc *sc = ifp->if_softc; + int rx_npkts = 0; + + DC_LOCK(sc); + + if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { + DC_UNLOCK(sc); + return (rx_npkts); + } + + sc->rxcycles = count; + rx_npkts = dc_rxeof(sc); + dc_txeof(sc); + if (!IFQ_IS_EMPTY(&ifp->if_snd) && + !(ifp->if_drv_flags & IFF_DRV_OACTIVE)) + dc_start_locked(ifp); + + if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ + u_int32_t status; + + status = CSR_READ_4(sc, DC_ISR); + status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | + DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | + DC_ISR_BUS_ERR); + if (!status) { + DC_UNLOCK(sc); + return (rx_npkts); + } + /* ack what we have */ + CSR_WRITE_4(sc, DC_ISR, status); + + if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { + u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); + ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); + + if (dc_rx_resync(sc)) + dc_rxeof(sc); + } + /* restart transmit unit if necessary */ + if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) + CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); + + if (status & DC_ISR_TX_UNDERRUN) + dc_tx_underrun(sc); + + if (status & DC_ISR_BUS_ERR) { + if_printf(ifp, "%s: bus error\n", __func__); + dc_reset(sc); + dc_init_locked(sc); + } + } + DC_UNLOCK(sc); + return (rx_npkts); +} +#endif /* DEVICE_POLLING */ + +static void +dc_intr(void *arg) +{ + struct dc_softc *sc; + struct ifnet *ifp; + u_int32_t status; + + sc = arg; + + if (sc->suspended) + return; + + if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) + return; + + DC_LOCK(sc); + ifp = sc->dc_ifp; +#ifdef DEVICE_POLLING + if (ifp->if_capenable & IFCAP_POLLING) { + DC_UNLOCK(sc); + return; + } +#endif + + /* Suppress unwanted interrupts */ + if (!(ifp->if_flags & IFF_UP)) { + if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) + dc_stop(sc); + DC_UNLOCK(sc); + return; + } + + /* Disable interrupts. */ + CSR_WRITE_4(sc, DC_IMR, 0x00000000); + + while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) && + status != 0xFFFFFFFF && + (ifp->if_drv_flags & IFF_DRV_RUNNING)) { + + CSR_WRITE_4(sc, DC_ISR, status); + + if (status & DC_ISR_RX_OK) { + int curpkts; + curpkts = ifp->if_ipackets; + dc_rxeof(sc); + if (curpkts == ifp->if_ipackets) { + while (dc_rx_resync(sc)) + dc_rxeof(sc); + } + } + + if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) + dc_txeof(sc); + + if (status & DC_ISR_TX_IDLE) { + dc_txeof(sc); + if (sc->dc_cdata.dc_tx_cnt) { + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); + CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); + } + } + + if (status & DC_ISR_TX_UNDERRUN) + dc_tx_underrun(sc); + + if ((status & DC_ISR_RX_WATDOGTIMEO) + || (status & DC_ISR_RX_NOBUF)) { + int curpkts; + curpkts = ifp->if_ipackets; + dc_rxeof(sc); + if (curpkts == ifp->if_ipackets) { + while (dc_rx_resync(sc)) + dc_rxeof(sc); + } + } + + if (status & DC_ISR_BUS_ERR) { + dc_reset(sc); + dc_init_locked(sc); + } + } + + /* Re-enable interrupts. */ + CSR_WRITE_4(sc, DC_IMR, DC_INTRS); + + if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) + dc_start_locked(ifp); + + DC_UNLOCK(sc); +} + +/* + * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data + * pointers to the fragment pointers. + */ +static int +dc_encap(struct dc_softc *sc, struct mbuf **m_head) +{ + bus_dma_segment_t segs[DC_MAXFRAGS]; + struct dc_desc *f; + struct mbuf *m; + int cur, defragged, error, first, frag, i, idx, nseg; + + /* + * If there's no way we can send any packets, return now. + */ + if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt <= DC_TX_LIST_RSVD) + return (ENOBUFS); + + m = NULL; + defragged = 0; + if (sc->dc_flags & DC_TX_COALESCE && + ((*m_head)->m_next != NULL || sc->dc_flags & DC_TX_ALIGN)) { + m = m_defrag(*m_head, M_DONTWAIT); + defragged = 1; + } else { + /* + * Count the number of frags in this chain to see if we + * need to m_collapse. Since the descriptor list is shared + * by all packets, we'll m_collapse long chains so that they + * do not use up the entire list, even if they would fit. + */ + i = 0; + for (m = *m_head; m != NULL; m = m->m_next) + i++; + if (i > DC_TX_LIST_CNT / 4 || + DC_TX_LIST_CNT - i + sc->dc_cdata.dc_tx_cnt <= + DC_TX_LIST_RSVD) { + m = m_collapse(*m_head, M_DONTWAIT, DC_MAXFRAGS); + defragged = 1; + } + } + if (defragged != 0) { + if (m == NULL) { + m_freem(*m_head); + *m_head = NULL; + return (ENOBUFS); + } + *m_head = m; + } + + idx = sc->dc_cdata.dc_tx_prod; + error = bus_dmamap_load_mbuf_sg(sc->dc_mtag, + sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); + if (error == EFBIG) { + if (defragged != 0 || (m = m_collapse(*m_head, M_DONTWAIT, + DC_MAXFRAGS)) == NULL) { + m_freem(*m_head); + *m_head = NULL; + return (defragged != 0 ? error : ENOBUFS); + } + *m_head = m; + error = bus_dmamap_load_mbuf_sg(sc->dc_mtag, + sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); + if (error != 0) { + m_freem(*m_head); + *m_head = NULL; + return (error); + } + } else if (error != 0) + return (error); + KASSERT(nseg <= DC_MAXFRAGS, + ("%s: wrong number of segments (%d)", __func__, nseg)); + if (nseg == 0) { + m_freem(*m_head); + *m_head = NULL; + return (EIO); + } + + first = cur = frag = sc->dc_cdata.dc_tx_prod; + for (i = 0; i < nseg; i++) { + if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && + (frag == (DC_TX_LIST_CNT - 1)) && + (first != sc->dc_cdata.dc_tx_first)) { + bus_dmamap_unload(sc->dc_mtag, + sc->dc_cdata.dc_tx_map[first]); + m_freem(*m_head); + *m_head = NULL; + return (ENOBUFS); + } + + f = &sc->dc_ldata->dc_tx_list[frag]; + f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); + if (i == 0) { + f->dc_status = 0; + f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); + } else + f->dc_status = htole32(DC_TXSTAT_OWN); + f->dc_data = htole32(segs[i].ds_addr); + cur = frag; + DC_INC(frag, DC_TX_LIST_CNT); + } + + sc->dc_cdata.dc_tx_prod = frag; + sc->dc_cdata.dc_tx_cnt += nseg; + sc->dc_cdata.dc_tx_chain[cur] = *m_head; + sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); + if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) + sc->dc_ldata->dc_tx_list[first].dc_ctl |= + htole32(DC_TXCTL_FINT); + if (sc->dc_flags & DC_TX_INTR_ALWAYS) + sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); + if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) + sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); + sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); + + bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], + BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, + BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); + return (0); +} + +static void +dc_start(struct ifnet *ifp) +{ + struct dc_softc *sc; + + sc = ifp->if_softc; + DC_LOCK(sc); + dc_start_locked(ifp); + DC_UNLOCK(sc); +} + +/* + * Main transmit routine + * To avoid having to do mbuf copies, we put pointers to the mbuf data + * regions directly in the transmit lists. We also save a copy of the + * pointers since the transmit list fragment pointers are physical + * addresses. + */ +static void +dc_start_locked(struct ifnet *ifp) +{ + struct dc_softc *sc; + struct mbuf *m_head = NULL; + unsigned int queued = 0; + int idx; + + sc = ifp->if_softc; + + DC_LOCK_ASSERT(sc); + + if (!sc->dc_link && ifp->if_snd.ifq_len < 10) + return; + + if (ifp->if_drv_flags & IFF_DRV_OACTIVE) + return; + + idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; + + while (sc->dc_cdata.dc_tx_chain[idx] == NULL) { + IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); + if (m_head == NULL) + break; + + if (dc_encap(sc, &m_head)) { + if (m_head == NULL) + break; + IFQ_DRV_PREPEND(&ifp->if_snd, m_head); + ifp->if_drv_flags |= IFF_DRV_OACTIVE; + break; + } + idx = sc->dc_cdata.dc_tx_prod; + + queued++; + /* + * If there's a BPF listener, bounce a copy of this frame + * to him. + */ + BPF_MTAP(ifp, m_head); + + if (sc->dc_flags & DC_TX_ONE) { + ifp->if_drv_flags |= IFF_DRV_OACTIVE; + break; + } + } + + if (queued > 0) { + /* Transmit */ + if (!(sc->dc_flags & DC_TX_POLL)) + CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); + + /* + * Set a timeout in case the chip goes out to lunch. + */ + sc->dc_wdog_timer = 5; + } +} + +static void +dc_init(void *xsc) +{ + struct dc_softc *sc = xsc; + + DC_LOCK(sc); + dc_init_locked(sc); + DC_UNLOCK(sc); +} + +static void +dc_init_locked(struct dc_softc *sc) +{ + struct ifnet *ifp = sc->dc_ifp; + struct mii_data *mii; + + DC_LOCK_ASSERT(sc); + + mii = device_get_softc(sc->dc_miibus); + + /* + * Cancel pending I/O and free all RX/TX buffers. + */ + dc_stop(sc); + dc_reset(sc); + + /* + * Set cache alignment and burst length. + */ + if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) + CSR_WRITE_4(sc, DC_BUSCTL, 0); + else + CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); + /* + * Evenly share the bus between receive and transmit process. + */ + if (DC_IS_INTEL(sc)) + DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); + if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { + DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); + } else { + DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); + } + if (sc->dc_flags & DC_TX_POLL) + DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); + switch(sc->dc_cachesize) { + case 32: + DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); + break; + case 16: + DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); + break; + case 8: + DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); + break; + case 0: + default: + DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); + break; + } + + if (sc->dc_flags & DC_TX_STORENFWD) + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); + else { + if (sc->dc_txthresh > DC_TXTHRESH_MAX) { + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); + } else { + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); + DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); + } + } + + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); + + if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { + /* + * The app notes for the 98713 and 98715A say that + * in order to have the chips operate properly, a magic + * number must be written to CSR16. Macronix does not + * document the meaning of these bits so there's no way + * to know exactly what they do. The 98713 has a magic + * number all its own; the rest all use a different one. + */ + DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); + if (sc->dc_type == DC_TYPE_98713) + DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); + else + DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); + } + + if (DC_IS_XIRCOM(sc)) { + /* + * setup General Purpose Port mode and data so the tulip + * can talk to the MII. + */ + CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | + DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); + DELAY(10); + CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | + DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); + DELAY(10); + } + + DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); + DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); + + /* Init circular RX list. */ + if (dc_list_rx_init(sc) == ENOBUFS) { + device_printf(sc->dc_dev, + "initialization failed: no memory for rx buffers\n"); + dc_stop(sc); + return; + } + + /* + * Init TX descriptors. + */ + dc_list_tx_init(sc); + + /* + * Load the address of the RX list. + */ + CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); + CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); + + /* + * Enable interrupts. + */ +#ifdef DEVICE_POLLING + /* + * ... but only if we are not polling, and make sure they are off in + * the case of polling. Some cards (e.g. fxp) turn interrupts on + * after a reset. + */ + if (ifp->if_capenable & IFCAP_POLLING) + CSR_WRITE_4(sc, DC_IMR, 0x00000000); + else +#endif + CSR_WRITE_4(sc, DC_IMR, DC_INTRS); + CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); + + /* Enable transmitter. */ + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); + + /* + * If this is an Intel 21143 and we're not using the + * MII port, program the LED control pins so we get + * link and activity indications. + */ + if (sc->dc_flags & DC_TULIP_LEDS) { + CSR_WRITE_4(sc, DC_WATCHDOG, + DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); + CSR_WRITE_4(sc, DC_WATCHDOG, 0); + } + + /* + * Load the RX/multicast filter. We do this sort of late + * because the filter programming scheme on the 21143 and + * some clones requires DMAing a setup frame via the TX + * engine, and we need the transmitter enabled for that. + */ + dc_setfilt(sc); + + /* Enable receiver. */ + DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); + CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); + + mii_mediachg(mii); + dc_setcfg(sc, sc->dc_if_media); + + ifp->if_drv_flags |= IFF_DRV_RUNNING; + ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; + + /* Don't start the ticker if this is a homePNA link. */ + if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) + sc->dc_link = 1; + else { + if (sc->dc_flags & DC_21143_NWAY) + callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); + else + callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); + } + + sc->dc_wdog_timer = 0; + callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); +} + +/* + * Set media options. + */ +static int +dc_ifmedia_upd(struct ifnet *ifp) +{ + struct dc_softc *sc; + struct mii_data *mii; + struct ifmedia *ifm; + + sc = ifp->if_softc; + mii = device_get_softc(sc->dc_miibus); + DC_LOCK(sc); + mii_mediachg(mii); + ifm = &mii->mii_media; + + if (DC_IS_DAVICOM(sc) && + IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) + dc_setcfg(sc, ifm->ifm_media); + else + sc->dc_link = 0; + DC_UNLOCK(sc); + + return (0); +} + +/* + * Report current media status. + */ +static void +dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) +{ + struct dc_softc *sc; + struct mii_data *mii; + struct ifmedia *ifm; + + sc = ifp->if_softc; + mii = device_get_softc(sc->dc_miibus); + DC_LOCK(sc); + mii_pollstat(mii); + ifm = &mii->mii_media; + if (DC_IS_DAVICOM(sc)) { + if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { + ifmr->ifm_active = ifm->ifm_media; + ifmr->ifm_status = 0; + DC_UNLOCK(sc); + return; + } + } + ifmr->ifm_active = mii->mii_media_active; + ifmr->ifm_status = mii->mii_media_status; + DC_UNLOCK(sc); +} + +static int +dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) +{ + struct dc_softc *sc = ifp->if_softc; + struct ifreq *ifr = (struct ifreq *)data; + struct mii_data *mii; + int error = 0; + + switch (command) { + case SIOCSIFFLAGS: + DC_LOCK(sc); + if (ifp->if_flags & IFF_UP) { + int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & + (IFF_PROMISC | IFF_ALLMULTI); + + if (ifp->if_drv_flags & IFF_DRV_RUNNING) { + if (need_setfilt) + dc_setfilt(sc); + } else { + sc->dc_txthresh = 0; + dc_init_locked(sc); + } + } else { + if (ifp->if_drv_flags & IFF_DRV_RUNNING) + dc_stop(sc); + } + sc->dc_if_flags = ifp->if_flags; + DC_UNLOCK(sc); + error = 0; + break; + case SIOCADDMULTI: + case SIOCDELMULTI: + DC_LOCK(sc); + dc_setfilt(sc); + DC_UNLOCK(sc); + error = 0; + break; + case SIOCGIFMEDIA: + case SIOCSIFMEDIA: + mii = device_get_softc(sc->dc_miibus); + error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); + break; + case SIOCSIFCAP: +#ifdef DEVICE_POLLING + if (ifr->ifr_reqcap & IFCAP_POLLING && + !(ifp->if_capenable & IFCAP_POLLING)) { + error = ether_poll_register(dc_poll, ifp); + if (error) + return(error); + DC_LOCK(sc); + /* Disable interrupts */ + CSR_WRITE_4(sc, DC_IMR, 0x00000000); + ifp->if_capenable |= IFCAP_POLLING; + DC_UNLOCK(sc); + return (error); + } + if (!(ifr->ifr_reqcap & IFCAP_POLLING) && + ifp->if_capenable & IFCAP_POLLING) { + error = ether_poll_deregister(ifp); + /* Enable interrupts. */ + DC_LOCK(sc); + CSR_WRITE_4(sc, DC_IMR, DC_INTRS); + ifp->if_capenable &= ~IFCAP_POLLING; + DC_UNLOCK(sc); + return (error); + } +#endif /* DEVICE_POLLING */ + break; + default: + error = ether_ioctl(ifp, command, data); + break; + } + + return (error); +} + +static void +dc_watchdog(void *xsc) +{ + struct dc_softc *sc = xsc; + struct ifnet *ifp; + + DC_LOCK_ASSERT(sc); + + if (sc->dc_wdog_timer == 0 || --sc->dc_wdog_timer != 0) { + callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); + return; + } + + ifp = sc->dc_ifp; + ifp->if_oerrors++; + device_printf(sc->dc_dev, "watchdog timeout\n"); + + dc_stop(sc); + dc_reset(sc); + dc_init_locked(sc); + + if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) + dc_start_locked(ifp); +} + +/* + * Stop the adapter and free any mbufs allocated to the + * RX and TX lists. + */ +static void +dc_stop(struct dc_softc *sc) +{ + struct ifnet *ifp; + struct dc_list_data *ld; + struct dc_chain_data *cd; + int i; + u_int32_t ctl; + + DC_LOCK_ASSERT(sc); + + ifp = sc->dc_ifp; + ld = sc->dc_ldata; + cd = &sc->dc_cdata; + + callout_stop(&sc->dc_stat_ch); + callout_stop(&sc->dc_wdog_ch); + sc->dc_wdog_timer = 0; + + ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); + + DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); + CSR_WRITE_4(sc, DC_IMR, 0x00000000); + CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); + CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); + sc->dc_link = 0; + + /* + * Free data in the RX lists. + */ + for (i = 0; i < DC_RX_LIST_CNT; i++) { + if (cd->dc_rx_chain[i] != NULL) { + m_freem(cd->dc_rx_chain[i]); + cd->dc_rx_chain[i] = NULL; + } + } + bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list)); + + /* + * Free the TX list buffers. + */ + for (i = 0; i < DC_TX_LIST_CNT; i++) { + if (cd->dc_tx_chain[i] != NULL) { + ctl = le32toh(ld->dc_tx_list[i].dc_ctl); + if ((ctl & DC_TXCTL_SETUP) || + !(ctl & DC_TXCTL_LASTFRAG)) { + cd->dc_tx_chain[i] = NULL; + continue; + } + bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]); + m_freem(cd->dc_tx_chain[i]); + cd->dc_tx_chain[i] = NULL; + } + } + bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list)); +} + +/* + * Device suspend routine. Stop the interface and save some PCI + * settings in case the BIOS doesn't restore them properly on + * resume. + */ +static int +dc_suspend(device_t dev) +{ + struct dc_softc *sc; + + sc = device_get_softc(dev); + DC_LOCK(sc); + dc_stop(sc); + sc->suspended = 1; + DC_UNLOCK(sc); + + return (0); +} + +/* + * Device resume routine. Restore some PCI settings in case the BIOS + * doesn't, re-enable busmastering, and restart the interface if + * appropriate. + */ +static int +dc_resume(device_t dev) +{ + struct dc_softc *sc; + struct ifnet *ifp; + + sc = device_get_softc(dev); + ifp = sc->dc_ifp; + + /* reinitialize interface if necessary */ + DC_LOCK(sc); + if (ifp->if_flags & IFF_UP) + dc_init_locked(sc); + + sc->suspended = 0; + DC_UNLOCK(sc); + + return (0); +} + +/* + * Stop all chip I/O so that the kernel's probe routines don't + * get confused by errant DMAs when rebooting. + */ +static int +dc_shutdown(device_t dev) +{ + struct dc_softc *sc; + + sc = device_get_softc(dev); + + DC_LOCK(sc); + dc_stop(sc); + DC_UNLOCK(sc); + + return (0); +} diff --git a/freebsd/dev/dc/if_dcreg.h b/freebsd/dev/dc/if_dcreg.h new file mode 100644 index 00000000..b918ce49 --- /dev/null +++ b/freebsd/dev/dc/if_dcreg.h @@ -0,0 +1,1172 @@ +/*- + * Copyright (c) 1997, 1998, 1999 + * Bill Paul . All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Bill Paul. + * 4. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * 21143 and clone common register definitions. + */ + +#define DC_BUSCTL 0x00 /* bus control */ +#define DC_TXSTART 0x08 /* tx start demand */ +#define DC_RXSTART 0x10 /* rx start demand */ +#define DC_RXADDR 0x18 /* rx descriptor list start addr */ +#define DC_TXADDR 0x20 /* tx descriptor list start addr */ +#define DC_ISR 0x28 /* interrupt status register */ +#define DC_NETCFG 0x30 /* network config register */ +#define DC_IMR 0x38 /* interrupt mask */ +#define DC_FRAMESDISCARDED 0x40 /* # of discarded frames */ +#define DC_SIO 0x48 /* MII and ROM/EEPROM access */ +#define DC_ROM 0x50 /* ROM programming address */ +#define DC_TIMER 0x58 /* general timer */ +#define DC_10BTSTAT 0x60 /* SIA status */ +#define DC_SIARESET 0x68 /* SIA connectivity */ +#define DC_10BTCTRL 0x70 /* SIA transmit and receive */ +#define DC_WATCHDOG 0x78 /* SIA and general purpose port */ +#define DC_SIAGP 0x78 /* SIA and general purpose port (X3201) */ + +/* + * There are two general 'types' of MX chips that we need to be + * concerned with. One is the original 98713, which has its internal + * NWAY support controlled via the MDIO bits in the serial I/O + * register. The other is everything else (from the 98713A on up), + * which has its internal NWAY controlled via CSR13, CSR14 and CSR15, + * just like the 21143. This type setting also governs which of the + * 'magic' numbers we write to CSR16. The PNIC II falls into the + * 98713A/98715/98715A/98725 category. + */ +#define DC_TYPE_98713 0x1 +#define DC_TYPE_98713A 0x2 +#define DC_TYPE_987x5 0x3 + +/* Other type of supported chips. */ +#define DC_TYPE_21143 0x4 /* Intel 21143 */ +#define DC_TYPE_ASIX 0x5 /* ASIX AX88140A/AX88141 */ +#define DC_TYPE_AL981 0x6 /* ADMtek AL981 Comet */ +#define DC_TYPE_AN983 0x7 /* ADMtek AN983 Centaur */ +#define DC_TYPE_DM9102 0x8 /* Davicom DM9102 */ +#define DC_TYPE_PNICII 0x9 /* 82c115 PNIC II */ +#define DC_TYPE_PNIC 0xA /* 82c168/82c169 PNIC I */ +#define DC_TYPE_XIRCOM 0xB /* Xircom X3201 */ +#define DC_TYPE_CONEXANT 0xC /* Conexant LANfinity RS7112 */ + +#define DC_IS_MACRONIX(x) \ + (x->dc_type == DC_TYPE_98713 || \ + x->dc_type == DC_TYPE_98713A || \ + x->dc_type == DC_TYPE_987x5) + +#define DC_IS_ADMTEK(x) \ + (x->dc_type == DC_TYPE_AL981 || \ + x->dc_type == DC_TYPE_AN983) + +#define DC_IS_INTEL(x) (x->dc_type == DC_TYPE_21143) +#define DC_IS_ASIX(x) (x->dc_type == DC_TYPE_ASIX) +#define DC_IS_COMET(x) (x->dc_type == DC_TYPE_AL981) +#define DC_IS_CENTAUR(x) (x->dc_type == DC_TYPE_AN983) +#define DC_IS_DAVICOM(x) (x->dc_type == DC_TYPE_DM9102) +#define DC_IS_PNICII(x) (x->dc_type == DC_TYPE_PNICII) +#define DC_IS_PNIC(x) (x->dc_type == DC_TYPE_PNIC) +#define DC_IS_XIRCOM(x) (x->dc_type == DC_TYPE_XIRCOM) +#define DC_IS_CONEXANT(x) (x->dc_type == DC_TYPE_CONEXANT) + +/* MII/symbol mode port types */ +#define DC_PMODE_MII 0x1 +#define DC_PMODE_SYM 0x2 +#define DC_PMODE_SIA 0x3 + +/* + * Bus control bits. + */ +#define DC_BUSCTL_RESET 0x00000001 +#define DC_BUSCTL_ARBITRATION 0x00000002 +#define DC_BUSCTL_SKIPLEN 0x0000007C +#define DC_BUSCTL_BUF_BIGENDIAN 0x00000080 +#define DC_BUSCTL_BURSTLEN 0x00003F00 +#define DC_BUSCTL_CACHEALIGN 0x0000C000 +#define DC_BUSCTL_TXPOLL 0x000E0000 +#define DC_BUSCTL_DBO 0x00100000 +#define DC_BUSCTL_MRME 0x00200000 +#define DC_BUSCTL_MRLE 0x00800000 +#define DC_BUSCTL_MWIE 0x01000000 +#define DC_BUSCTL_ONNOW_ENB 0x04000000 + +#define DC_SKIPLEN_1LONG 0x00000004 +#define DC_SKIPLEN_2LONG 0x00000008 +#define DC_SKIPLEN_3LONG 0x00000010 +#define DC_SKIPLEN_4LONG 0x00000020 +#define DC_SKIPLEN_5LONG 0x00000040 + +#define DC_CACHEALIGN_NONE 0x00000000 +#define DC_CACHEALIGN_8LONG 0x00004000 +#define DC_CACHEALIGN_16LONG 0x00008000 +#define DC_CACHEALIGN_32LONG 0x0000C000 + +#define DC_BURSTLEN_USECA 0x00000000 +#define DC_BURSTLEN_1LONG 0x00000100 +#define DC_BURSTLEN_2LONG 0x00000200 +#define DC_BURSTLEN_4LONG 0x00000400 +#define DC_BURSTLEN_8LONG 0x00000800 +#define DC_BURSTLEN_16LONG 0x00001000 +#define DC_BURSTLEN_32LONG 0x00002000 + +#define DC_TXPOLL_OFF 0x00000000 +#define DC_TXPOLL_1 0x00020000 +#define DC_TXPOLL_2 0x00040000 +#define DC_TXPOLL_3 0x00060000 +#define DC_TXPOLL_4 0x00080000 +#define DC_TXPOLL_5 0x000A0000 +#define DC_TXPOLL_6 0x000C0000 +#define DC_TXPOLL_7 0x000E0000 + +/* + * Interrupt status bits. + */ +#define DC_ISR_TX_OK 0x00000001 +#define DC_ISR_TX_IDLE 0x00000002 +#define DC_ISR_TX_NOBUF 0x00000004 +#define DC_ISR_TX_JABBERTIMEO 0x00000008 +#define DC_ISR_LINKGOOD 0x00000010 +#define DC_ISR_TX_UNDERRUN 0x00000020 +#define DC_ISR_RX_OK 0x00000040 +#define DC_ISR_RX_NOBUF 0x00000080 +#define DC_ISR_RX_READ 0x00000100 +#define DC_ISR_RX_WATDOGTIMEO 0x00000200 +#define DC_ISR_TX_EARLY 0x00000400 +#define DC_ISR_TIMER_EXPIRED 0x00000800 +#define DC_ISR_LINKFAIL 0x00001000 +#define DC_ISR_BUS_ERR 0x00002000 +#define DC_ISR_RX_EARLY 0x00004000 +#define DC_ISR_ABNORMAL 0x00008000 +#define DC_ISR_NORMAL 0x00010000 +#define DC_ISR_RX_STATE 0x000E0000 +#define DC_ISR_TX_STATE 0x00700000 +#define DC_ISR_BUSERRTYPE 0x03800000 +#define DC_ISR_100MBPSLINK 0x08000000 +#define DC_ISR_MAGICKPACK 0x10000000 + +#define DC_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */ +#define DC_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */ +#define DC_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */ +#define DC_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */ +#define DC_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */ +#define DC_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */ +#define DC_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */ +#define DC_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */ + +#define DC_HAS_BROKEN_RXSTATE(x) \ + (DC_IS_CENTAUR(x) || DC_IS_CONEXANT(x) || (DC_IS_DAVICOM(x) && \ + pci_get_revid((x)->dc_dev) >= DC_REVISION_DM9102A)) + +#define DC_TXSTATE_RESET 0x00000000 /* 000 - reset */ +#define DC_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */ +#define DC_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */ +#define DC_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */ +#define DC_TXSTATE_RSVD 0x00400000 /* 100 - reserved */ +#define DC_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */ +#define DC_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */ +#define DC_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */ + +/* + * Network config bits. + */ +#define DC_NETCFG_RX_HASHPERF 0x00000001 +#define DC_NETCFG_RX_ON 0x00000002 +#define DC_NETCFG_RX_HASHONLY 0x00000004 +#define DC_NETCFG_RX_BADFRAMES 0x00000008 +#define DC_NETCFG_RX_INVFILT 0x00000010 +#define DC_NETCFG_BACKOFFCNT 0x00000020 +#define DC_NETCFG_RX_PROMISC 0x00000040 +#define DC_NETCFG_RX_ALLMULTI 0x00000080 +#define DC_NETCFG_FULLDUPLEX 0x00000200 +#define DC_NETCFG_LOOPBACK 0x00000C00 +#define DC_NETCFG_FORCECOLL 0x00001000 +#define DC_NETCFG_TX_ON 0x00002000 +#define DC_NETCFG_TX_THRESH 0x0000C000 +#define DC_NETCFG_TX_BACKOFF 0x00020000 +#define DC_NETCFG_PORTSEL 0x00040000 /* 0 == 10, 1 == 100 */ +#define DC_NETCFG_HEARTBEAT 0x00080000 +#define DC_NETCFG_STORENFWD 0x00200000 +#define DC_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */ +#define DC_NETCFG_PCS 0x00800000 +#define DC_NETCFG_SCRAMBLER 0x01000000 +#define DC_NETCFG_NO_RXCRC 0x02000000 +#define DC_NETCFG_RX_ALL 0x40000000 +#define DC_NETCFG_CAPEFFECT 0x80000000 + +#define DC_OPMODE_NORM 0x00000000 +#define DC_OPMODE_INTLOOP 0x00000400 +#define DC_OPMODE_EXTLOOP 0x00000800 + +#if 0 +#define DC_TXTHRESH_72BYTES 0x00000000 +#define DC_TXTHRESH_96BYTES 0x00004000 +#define DC_TXTHRESH_128BYTES 0x00008000 +#define DC_TXTHRESH_160BYTES 0x0000C000 +#endif + +#define DC_TXTHRESH_MIN 0x00000000 +#define DC_TXTHRESH_INC 0x00004000 +#define DC_TXTHRESH_MAX 0x0000C000 + + +/* + * Interrupt mask bits. + */ +#define DC_IMR_TX_OK 0x00000001 +#define DC_IMR_TX_IDLE 0x00000002 +#define DC_IMR_TX_NOBUF 0x00000004 +#define DC_IMR_TX_JABBERTIMEO 0x00000008 +#define DC_IMR_LINKGOOD 0x00000010 +#define DC_IMR_TX_UNDERRUN 0x00000020 +#define DC_IMR_RX_OK 0x00000040 +#define DC_IMR_RX_NOBUF 0x00000080 +#define DC_IMR_RX_READ 0x00000100 +#define DC_IMR_RX_WATDOGTIMEO 0x00000200 +#define DC_IMR_TX_EARLY 0x00000400 +#define DC_IMR_TIMER_EXPIRED 0x00000800 +#define DC_IMR_LINKFAIL 0x00001000 +#define DC_IMR_BUS_ERR 0x00002000 +#define DC_IMR_RX_EARLY 0x00004000 +#define DC_IMR_ABNORMAL 0x00008000 +#define DC_IMR_NORMAL 0x00010000 +#define DC_IMR_100MBPSLINK 0x08000000 +#define DC_IMR_MAGICKPACK 0x10000000 + +#define DC_INTRS \ + (DC_IMR_RX_OK|DC_IMR_TX_OK|DC_IMR_RX_NOBUF|DC_IMR_RX_WATDOGTIMEO|\ + DC_IMR_TX_NOBUF|DC_IMR_TX_UNDERRUN|DC_IMR_BUS_ERR| \ + DC_IMR_ABNORMAL|DC_IMR_NORMAL/*|DC_IMR_TX_EARLY*/) +/* + * Serial I/O (EEPROM/ROM) bits. + */ +#define DC_SIO_EE_CS 0x00000001 /* EEPROM chip select */ +#define DC_SIO_EE_CLK 0x00000002 /* EEPROM clock */ +#define DC_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */ +#define DC_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */ +#define DC_SIO_ROMDATA4 0x00000010 +#define DC_SIO_ROMDATA5 0x00000020 +#define DC_SIO_ROMDATA6 0x00000040 +#define DC_SIO_ROMDATA7 0x00000080 +#define DC_SIO_EESEL 0x00000800 +#define DC_SIO_ROMSEL 0x00001000 +#define DC_SIO_ROMCTL_WRITE 0x00002000 +#define DC_SIO_ROMCTL_READ 0x00004000 +#define DC_SIO_MII_CLK 0x00010000 /* MDIO clock */ +#define DC_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */ +#define DC_SIO_MII_DIR 0x00040000 /* MDIO dir */ +#define DC_SIO_MII_DATAIN 0x00080000 /* MDIO data in */ + +#define DC_EECMD_WRITE 0x140 +#define DC_EECMD_READ 0x180 +#define DC_EECMD_ERASE 0x1c0 + +#define DC_EE_NODEADDR_OFFSET 0x70 +#define DC_EE_NODEADDR 10 + +/* + * General purpose timer register + */ +#define DC_TIMER_VALUE 0x0000FFFF +#define DC_TIMER_CONTINUOUS 0x00010000 + +/* + * 10baseT status register + */ +#define DC_TSTAT_MIIACT 0x00000001 /* MII port activity */ +#define DC_TSTAT_LS100 0x00000002 /* link status of 100baseTX */ +#define DC_TSTAT_LS10 0x00000004 /* link status of 10baseT */ +#define DC_TSTAT_AUTOPOLARITY 0x00000008 +#define DC_TSTAT_AUIACT 0x00000100 /* AUI activity */ +#define DC_TSTAT_10BTACT 0x00000200 /* 10baseT activity */ +#define DC_TSTAT_NSN 0x00000400 /* non-stable FLPs detected */ +#define DC_TSTAT_REMFAULT 0x00000800 +#define DC_TSTAT_ANEGSTAT 0x00007000 +#define DC_TSTAT_LP_CAN_NWAY 0x00008000 /* link partner supports NWAY */ +#define DC_TSTAT_LPCODEWORD 0xFFFF0000 /* link partner's code word */ + +#define DC_ASTAT_DISABLE 0x00000000 +#define DC_ASTAT_TXDISABLE 0x00001000 +#define DC_ASTAT_ABDETECT 0x00002000 +#define DC_ASTAT_ACKDETECT 0x00003000 +#define DC_ASTAT_CMPACKDETECT 0x00004000 +#define DC_ASTAT_AUTONEGCMP 0x00005000 +#define DC_ASTAT_LINKCHECK 0x00006000 + +/* + * PHY reset register + */ +#define DC_SIA_RESET 0x00000001 +#define DC_SIA_AUI 0x00000008 /* AUI or 10baseT */ + +/* + * 10baseT control register + */ +#define DC_TCTL_ENCODER_ENB 0x00000001 +#define DC_TCTL_LOOPBACK 0x00000002 +#define DC_TCTL_DRIVER_ENB 0x00000004 +#define DC_TCTL_LNKPULSE_ENB 0x00000008 +#define DC_TCTL_HALFDUPLEX 0x00000040 +#define DC_TCTL_AUTONEGENBL 0x00000080 +#define DC_TCTL_RX_SQUELCH 0x00000100 +#define DC_TCTL_COLL_SQUELCH 0x00000200 +#define DC_TCTL_COLL_DETECT 0x00000400 +#define DC_TCTL_SQE_ENB 0x00000800 +#define DC_TCTL_LINKTEST 0x00001000 +#define DC_TCTL_AUTOPOLARITY 0x00002000 +#define DC_TCTL_SET_POL_PLUS 0x00004000 +#define DC_TCTL_AUTOSENSE 0x00008000 /* 10bt/AUI autosense */ +#define DC_TCTL_100BTXHALF 0x00010000 +#define DC_TCTL_100BTXFULL 0x00020000 +#define DC_TCTL_100BT4 0x00040000 + +/* + * Watchdog timer register + */ +#define DC_WDOG_JABBERDIS 0x00000001 +#define DC_WDOG_HOSTUNJAB 0x00000002 +#define DC_WDOG_JABBERCLK 0x00000004 +#define DC_WDOG_RXWDOGDIS 0x00000010 +#define DC_WDOG_RXWDOGCLK 0x00000020 +#define DC_WDOG_MUSTBEZERO 0x00000100 +#define DC_WDOG_AUIBNC 0x00100000 +#define DC_WDOG_ACTIVITY 0x00200000 +#define DC_WDOG_RX_MATCH 0x00400000 +#define DC_WDOG_LINK 0x00800000 +#define DC_WDOG_CTLWREN 0x08000000 + +/* + * SIA and General Purpose Port register (X3201) + */ +#define DC_SIAGP_RXMATCH 0x40000000 +#define DC_SIAGP_INT1 0x20000000 +#define DC_SIAGP_INT0 0x10000000 +#define DC_SIAGP_WRITE_EN 0x08000000 +#define DC_SIAGP_RXMATCH_EN 0x04000000 +#define DC_SIAGP_INT1_EN 0x02000000 +#define DC_SIAGP_INT0_EN 0x01000000 +#define DC_SIAGP_LED3 0x00800000 +#define DC_SIAGP_LED2 0x00400000 +#define DC_SIAGP_LED1 0x00200000 +#define DC_SIAGP_LED0 0x00100000 +#define DC_SIAGP_MD_GP3_OUTPUT 0x00080000 +#define DC_SIAGP_MD_GP2_OUTPUT 0x00040000 +#define DC_SIAGP_MD_GP1_OUTPUT 0x00020000 +#define DC_SIAGP_MD_GP0_OUTPUT 0x00010000 + +/* + * Size of a setup frame. + */ +#define DC_SFRAME_LEN 192 + +/* + * 21x4x TX/RX list structure. + */ + +struct dc_desc { + u_int32_t dc_status; + u_int32_t dc_ctl; + u_int32_t dc_ptr1; + u_int32_t dc_ptr2; +}; + +#define dc_data dc_ptr1 +#define dc_next dc_ptr2 + +#define DC_RXSTAT_FIFOOFLOW 0x00000001 +#define DC_RXSTAT_CRCERR 0x00000002 +#define DC_RXSTAT_DRIBBLE 0x00000004 +#define DC_RXSTAT_MIIERE 0x00000008 +#define DC_RXSTAT_WATCHDOG 0x00000010 +#define DC_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */ +#define DC_RXSTAT_COLLSEEN 0x00000040 +#define DC_RXSTAT_GIANT 0x00000080 +#define DC_RXSTAT_LASTFRAG 0x00000100 +#define DC_RXSTAT_FIRSTFRAG 0x00000200 +#define DC_RXSTAT_MULTICAST 0x00000400 +#define DC_RXSTAT_RUNT 0x00000800 +#define DC_RXSTAT_RXTYPE 0x00003000 +#define DC_RXSTAT_DE 0x00004000 +#define DC_RXSTAT_RXERR 0x00008000 +#define DC_RXSTAT_RXLEN 0x3FFF0000 +#define DC_RXSTAT_OWN 0x80000000 + +#define DC_RXBYTES(x) ((x & DC_RXSTAT_RXLEN) >> 16) +#define DC_RXSTAT (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG|DC_RXSTAT_OWN) + +#define DC_RXCTL_BUFLEN1 0x00000FFF +#define DC_RXCTL_BUFLEN2 0x00FFF000 +#define DC_RXCTL_RLINK 0x01000000 +#define DC_RXCTL_RLAST 0x02000000 + +#define DC_TXSTAT_DEFER 0x00000001 +#define DC_TXSTAT_UNDERRUN 0x00000002 +#define DC_TXSTAT_LINKFAIL 0x00000003 +#define DC_TXSTAT_COLLCNT 0x00000078 +#define DC_TXSTAT_SQE 0x00000080 +#define DC_TXSTAT_EXCESSCOLL 0x00000100 +#define DC_TXSTAT_LATECOLL 0x00000200 +#define DC_TXSTAT_NOCARRIER 0x00000400 +#define DC_TXSTAT_CARRLOST 0x00000800 +#define DC_TXSTAT_JABTIMEO 0x00004000 +#define DC_TXSTAT_ERRSUM 0x00008000 +#define DC_TXSTAT_OWN 0x80000000 + +#define DC_TXCTL_BUFLEN1 0x000007FF +#define DC_TXCTL_BUFLEN2 0x003FF800 +#define DC_TXCTL_FILTTYPE0 0x00400000 +#define DC_TXCTL_PAD 0x00800000 +#define DC_TXCTL_TLINK 0x01000000 +#define DC_TXCTL_TLAST 0x02000000 +#define DC_TXCTL_NOCRC 0x04000000 +#define DC_TXCTL_SETUP 0x08000000 +#define DC_TXCTL_FILTTYPE1 0x10000000 +#define DC_TXCTL_FIRSTFRAG 0x20000000 +#define DC_TXCTL_LASTFRAG 0x40000000 +#define DC_TXCTL_FINT 0x80000000 + +#define DC_FILTER_PERFECT 0x00000000 +#define DC_FILTER_HASHPERF 0x00400000 +#define DC_FILTER_INVERSE 0x10000000 +#define DC_FILTER_HASHONLY 0x10400000 + +#define DC_MAXFRAGS 16 +#ifdef DEVICE_POLLING +#define DC_RX_LIST_CNT 192 +#else +#define DC_RX_LIST_CNT 64 +#endif +#define DC_TX_LIST_CNT 256 +#define DC_TX_LIST_RSVD 5 +#define DC_MIN_FRAMELEN 60 +#define DC_RXLEN 1536 + +#define DC_INC(x, y) (x) = (x + 1) % y + +/* Macros to easily get the DMA address of a descriptor. */ +#define DC_RXDESC(sc, i) (sc->dc_laddr + \ + (uintptr_t)(sc->dc_ldata->dc_rx_list + i) - (uintptr_t)sc->dc_ldata) +#define DC_TXDESC(sc, i) (sc->dc_laddr + \ + (uintptr_t)(sc->dc_ldata->dc_tx_list + i) - (uintptr_t)sc->dc_ldata) + +#if BYTE_ORDER == BIG_ENDIAN +#define DC_SP_MAC(x) ((x) << 16) +#else +#define DC_SP_MAC(x) (x) +#endif + +struct dc_list_data { + struct dc_desc dc_rx_list[DC_RX_LIST_CNT]; + struct dc_desc dc_tx_list[DC_TX_LIST_CNT]; +}; + +struct dc_chain_data { + struct mbuf *dc_rx_chain[DC_RX_LIST_CNT]; + struct mbuf *dc_tx_chain[DC_TX_LIST_CNT]; + bus_dmamap_t dc_rx_map[DC_RX_LIST_CNT]; + bus_dmamap_t dc_tx_map[DC_TX_LIST_CNT]; + u_int32_t *dc_sbuf; + u_int8_t dc_pad[DC_MIN_FRAMELEN]; + int dc_tx_first; + int dc_tx_prod; + int dc_tx_cons; + int dc_tx_cnt; + int dc_rx_prod; +}; + +struct dc_mediainfo { + int dc_media; + u_int8_t *dc_gp_ptr; + u_int8_t dc_gp_len; + u_int8_t *dc_reset_ptr; + u_int8_t dc_reset_len; + struct dc_mediainfo *dc_next; +}; + + +struct dc_type { + u_int32_t dc_devid; + u_int8_t dc_minrev; + char *dc_name; +}; + +struct dc_mii_frame { + u_int8_t mii_stdelim; + u_int8_t mii_opcode; + u_int8_t mii_phyaddr; + u_int8_t mii_regaddr; + u_int8_t mii_turnaround; + u_int16_t mii_data; +}; + +/* + * MII constants + */ +#define DC_MII_STARTDELIM 0x01 +#define DC_MII_READOP 0x02 +#define DC_MII_WRITEOP 0x01 +#define DC_MII_TURNAROUND 0x02 + + +/* + * Registers specific to clone devices. + * This mainly relates to RX filter programming: not all 21x4x clones + * use the standard DEC filter programming mechanism. + */ + +/* + * ADMtek specific registers and constants for the AL981 and AN983. + * The AN983 doesn't use the magic PHY registers. + */ +#define DC_AL_CR 0x88 /* command register */ +#define DC_AL_PAR0 0xA4 /* station address */ +#define DC_AL_PAR1 0xA8 /* station address */ +#define DC_AL_MAR0 0xAC /* multicast hash filter */ +#define DC_AL_MAR1 0xB0 /* multicast hash filter */ +#define DC_AL_BMCR 0xB4 /* built in PHY control */ +#define DC_AL_BMSR 0xB8 /* built in PHY status */ +#define DC_AL_VENID 0xBC /* built in PHY ID0 */ +#define DC_AL_DEVID 0xC0 /* built in PHY ID1 */ +#define DC_AL_ANAR 0xC4 /* built in PHY autoneg advert */ +#define DC_AL_LPAR 0xC8 /* bnilt in PHY link part. ability */ +#define DC_AL_ANER 0xCC /* built in PHY autoneg expansion */ + +#define DC_AL_CR_ATUR 0x00000001 /* automatic TX underrun recovery */ +#define DC_ADMTEK_PHYADDR 0x1 +#define DC_AL_EE_NODEADDR 4 +/* End of ADMtek specific registers */ + +/* + * ASIX specific registers. + */ +#define DC_AX_FILTIDX 0x68 /* RX filter index */ +#define DC_AX_FILTDATA 0x70 /* RX filter data */ + +/* + * Special ASIX-specific bits in the ASIX NETCFG register (CSR6). + */ +#define DC_AX_NETCFG_RX_BROAD 0x00000100 + +/* + * RX Filter Index Register values + */ +#define DC_AX_FILTIDX_PAR0 0x00000000 +#define DC_AX_FILTIDX_PAR1 0x00000001 +#define DC_AX_FILTIDX_MAR0 0x00000002 +#define DC_AX_FILTIDX_MAR1 0x00000003 +/* End of ASIX specific registers */ + +/* + * Macronix specific registers. The Macronix chips have a special + * register for reading the NWAY status, which we don't use, plus + * a magic packet register, which we need to tweak a bit per the + * Macronix application notes. + */ +#define DC_MX_MAGICPACKET 0x80 +#define DC_MX_NWAYSTAT 0xA0 + +/* + * Magic packet register + */ +#define DC_MX_MPACK_DISABLE 0x00400000 + +/* + * NWAY status register. + */ +#define DC_MX_NWAY_10BTHALF 0x08000000 +#define DC_MX_NWAY_10BTFULL 0x10000000 +#define DC_MX_NWAY_100BTHALF 0x20000000 +#define DC_MX_NWAY_100BTFULL 0x40000000 +#define DC_MX_NWAY_100BT4 0x80000000 + +/* + * These are magic values that must be written into CSR16 + * (DC_MX_MAGICPACKET) in order to put the chip into proper + * operating mode. The magic numbers are documented in the + * Macronix 98715 application notes. + */ +#define DC_MX_MAGIC_98713 0x0F370000 +#define DC_MX_MAGIC_98713A 0x0B3C0000 +#define DC_MX_MAGIC_98715 0x0B3C0000 +#define DC_MX_MAGIC_98725 0x0B3C0000 +/* End of Macronix specific registers */ + +/* + * PNIC 82c168/82c169 specific registers. + * The PNIC has its own special NWAY support, which doesn't work, + * and shortcut ways of reading the EEPROM and MII bus. + */ +#define DC_PN_GPIO 0x60 /* general purpose pins control */ +#define DC_PN_PWRUP_CFG 0x90 /* config register, set by EEPROM */ +#define DC_PN_SIOCTL 0x98 /* serial EEPROM control register */ +#define DC_PN_MII 0xA0 /* MII access register */ +#define DC_PN_NWAY 0xB8 /* Internal NWAY register */ + +/* Serial I/O EEPROM register */ +#define DC_PN_SIOCTL_DATA 0x0000003F +#define DC_PN_SIOCTL_OPCODE 0x00000300 +#define DC_PN_SIOCTL_BUSY 0x80000000 + +#define DC_PN_EEOPCODE_ERASE 0x00000300 +#define DC_PN_EEOPCODE_READ 0x00000600 +#define DC_PN_EEOPCODE_WRITE 0x00000100 + +/* + * The first two general purpose pins control speed selection and + * 100Mbps loopback on the 82c168 chip. The control bits should always + * be set (to make the data pins outputs) and the speed selction and + * loopback bits set accordingly when changing media. Physically, this + * will set the state of a relay mounted on the card. + */ +#define DC_PN_GPIO_DATA0 0x000000001 +#define DC_PN_GPIO_DATA1 0x000000002 +#define DC_PN_GPIO_DATA2 0x000000004 +#define DC_PN_GPIO_DATA3 0x000000008 +#define DC_PN_GPIO_CTL0 0x000000010 +#define DC_PN_GPIO_CTL1 0x000000020 +#define DC_PN_GPIO_CTL2 0x000000040 +#define DC_PN_GPIO_CTL3 0x000000080 +#define DC_PN_GPIO_SPEEDSEL DC_PN_GPIO_DATA0/* 1 == 100Mbps, 0 == 10Mbps */ +#define DC_PN_GPIO_100TX_LOOP DC_PN_GPIO_DATA1/* 1 == normal, 0 == loop */ +#define DC_PN_GPIO_BNC_ENB DC_PN_GPIO_DATA2 +#define DC_PN_GPIO_100TX_LNK DC_PN_GPIO_DATA3 +#define DC_PN_GPIO_SETBIT(sc, r) \ + DC_SETBIT(sc, DC_PN_GPIO, ((r) | (r << 4))) +#define DC_PN_GPIO_CLRBIT(sc, r) \ + { \ + DC_SETBIT(sc, DC_PN_GPIO, ((r) << 4)); \ + DC_CLRBIT(sc, DC_PN_GPIO, (r)); \ + } + +/* shortcut MII access register */ +#define DC_PN_MII_DATA 0x0000FFFF +#define DC_PN_MII_RESERVER 0x00020000 +#define DC_PN_MII_REGADDR 0x007C0000 +#define DC_PN_MII_PHYADDR 0x0F800000 +#define DC_PN_MII_OPCODE 0x30000000 +#define DC_PN_MII_BUSY 0x80000000 + +#define DC_PN_MIIOPCODE_READ 0x60020000 +#define DC_PN_MIIOPCODE_WRITE 0x50020000 + +/* Internal NWAY bits */ +#define DC_PN_NWAY_RESET 0x00000001 /* reset */ +#define DC_PN_NWAY_PDOWN 0x00000002 /* power down */ +#define DC_PN_NWAY_BYPASS 0x00000004 /* bypass */ +#define DC_PN_NWAY_AUILOWCUR 0x00000008 /* AUI low current */ +#define DC_PN_NWAY_TPEXTEND 0x00000010 /* low squelch voltage */ +#define DC_PN_NWAY_POLARITY 0x00000020 /* 0 == on, 1 == off */ +#define DC_PN_NWAY_TP 0x00000040 /* 1 == tp, 0 == AUI */ +#define DC_PN_NWAY_AUIVOLT 0x00000080 /* 1 == full, 0 == half */ +#define DC_PN_NWAY_DUPLEX 0x00000100 /* LED, 1 == full, 0 == half */ +#define DC_PN_NWAY_LINKTEST 0x00000200 /* 0 == on, 1 == off */ +#define DC_PN_NWAY_AUTODETECT 0x00000400 /* 1 == off, 0 == on */ +#define DC_PN_NWAY_SPEEDSEL 0x00000800 /* LED, 0 = 10, 1 == 100 */ +#define DC_PN_NWAY_NWAY_ENB 0x00001000 /* 0 == off, 1 == on */ +#define DC_PN_NWAY_CAP10HDX 0x00002000 +#define DC_PN_NWAY_CAP10FDX 0x00004000 +#define DC_PN_NWAY_CAP100FDX 0x00008000 +#define DC_PN_NWAY_CAP100HDX 0x00010000 +#define DC_PN_NWAY_CAP100T4 0x00020000 +#define DC_PN_NWAY_ANEGRESTART 0x02000000 /* resets when aneg done */ +#define DC_PN_NWAY_REMFAULT 0x04000000 +#define DC_PN_NWAY_LPAR10HDX 0x08000000 +#define DC_PN_NWAY_LPAR10FDX 0x10000000 +#define DC_PN_NWAY_LPAR100FDX 0x20000000 +#define DC_PN_NWAY_LPAR100HDX 0x40000000 +#define DC_PN_NWAY_LPAR100T4 0x80000000 + +/* End of PNIC specific registers */ + +/* + * CONEXANT specific registers. + */ + +#define DC_CONEXANT_PHYADDR 0x1 +#define DC_CONEXANT_EE_NODEADDR 0x19A + +/* End of CONEXANT specific registers */ + + +struct dc_softc { + struct ifnet *dc_ifp; /* interface info */ + device_t dc_dev; /* device info */ + bus_space_handle_t dc_bhandle; /* bus space handle */ + bus_space_tag_t dc_btag; /* bus space tag */ + bus_dma_tag_t dc_ltag; /* tag for descriptor ring */ + bus_dmamap_t dc_lmap; /* map for descriptor ring */ + u_int32_t dc_laddr; /* DMA address of dc_ldata */ + bus_dma_tag_t dc_mtag; /* tag for mbufs */ + bus_dmamap_t dc_sparemap; + bus_dma_tag_t dc_stag; /* tag for the setup frame */ + bus_dmamap_t dc_smap; /* map for the setup frame */ + u_int32_t dc_saddr; /* DMA address of setup frame */ + void *dc_intrhand; + struct resource *dc_irq; + struct resource *dc_res; + const struct dc_type *dc_info; /* adapter info */ + device_t dc_miibus; + u_int8_t dc_type; + u_int8_t dc_pmode; + u_int8_t dc_link; + u_int8_t dc_cachesize; + int dc_romwidth; + int dc_pnic_rx_bug_save; + unsigned char *dc_pnic_rx_buf; + int dc_if_flags; + int dc_if_media; + u_int32_t dc_flags; + u_int32_t dc_txthresh; + u_int8_t *dc_srom; + struct dc_mediainfo *dc_mi; + struct dc_list_data *dc_ldata; + struct dc_chain_data dc_cdata; + struct callout dc_stat_ch; + struct callout dc_wdog_ch; + int dc_wdog_timer; + struct mtx dc_mtx; +#ifdef DEVICE_POLLING + int rxcycles; /* ... when polling */ +#endif + int suspended; /* 0 = normal 1 = suspended */ +}; + + +#define DC_LOCK(_sc) mtx_lock(&(_sc)->dc_mtx) +#define DC_UNLOCK(_sc) mtx_unlock(&(_sc)->dc_mtx) +#define DC_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->dc_mtx, MA_OWNED) + +#define DC_TX_POLL 0x00000001 +#define DC_TX_COALESCE 0x00000002 +#define DC_TX_ADMTEK_WAR 0x00000004 +#define DC_TX_USE_TX_INTR 0x00000008 +#define DC_RX_FILTER_TULIP 0x00000010 +#define DC_TX_INTR_FIRSTFRAG 0x00000020 +#define DC_PNIC_RX_BUG_WAR 0x00000040 +#define DC_TX_FIXED_RING 0x00000080 +#define DC_TX_STORENFWD 0x00000100 +#define DC_REDUCED_MII_POLL 0x00000200 +#define DC_TX_INTR_ALWAYS 0x00000400 +#define DC_21143_NWAY 0x00000800 +#define DC_128BIT_HASH 0x00001000 +#define DC_64BIT_HASH 0x00002000 +#define DC_TULIP_LEDS 0x00004000 +#define DC_TX_ONE 0x00008000 +#define DC_TX_ALIGN 0x00010000 /* align mbuf on tx */ + +/* + * register space access macros + */ +#define CSR_WRITE_4(sc, reg, val) \ + bus_space_write_4(sc->dc_btag, sc->dc_bhandle, reg, val) + +#define CSR_READ_4(sc, reg) \ + bus_space_read_4(sc->dc_btag, sc->dc_bhandle, reg) + +#define CSR_BARRIER_4(sc, reg, flags) \ + bus_space_barrier(sc->dc_btag, sc->dc_bhandle, reg, 4, flags) + +#define DC_TIMEOUT 1000 +#define ETHER_ALIGN 2 + +/* + * General constants that are fun to know. + */ + +/* + * DEC PCI vendor ID + */ +#define DC_VENDORID_DEC 0x1011 + +/* + * DEC/Intel 21143 PCI device ID + */ +#define DC_DEVICEID_21143 0x0019 + +/* + * Macronix PCI vendor ID + */ +#define DC_VENDORID_MX 0x10D9 + +/* + * Macronix PMAC device IDs. + */ +#define DC_DEVICEID_98713 0x0512 +#define DC_DEVICEID_987x5 0x0531 +#define DC_DEVICEID_98727 0x0532 +#define DC_DEVICEID_98732 0x0532 + +/* Macronix PCI revision codes. */ +#define DC_REVISION_98713 0x00 +#define DC_REVISION_98713A 0x10 +#define DC_REVISION_98715 0x20 +#define DC_REVISION_98715AEC_C 0x25 +#define DC_REVISION_98725 0x30 + +/* + * Compex PCI vendor ID. + */ +#define DC_VENDORID_CP 0x11F6 + +/* + * Compex PMAC PCI device IDs. + */ +#define DC_DEVICEID_98713_CP 0x9881 + +/* + * Lite-On PNIC PCI vendor ID + */ +#define DC_VENDORID_LO 0x11AD + +/* + * 82c168/82c169 PNIC device IDs. Both chips have the same device + * ID but different revisions. Revision 0x10 is the 82c168, and + * 0x20 is the 82c169. + */ +#define DC_DEVICEID_82C168 0x0002 + +#define DC_REVISION_82C168 0x10 +#define DC_REVISION_82C169 0x20 + +/* + * Lite-On PNIC II device ID. Note: this is actually a Macronix 98715A + * with wake on lan/magic packet support. + */ +#define DC_DEVICEID_82C115 0xc115 + +/* + * Davicom vendor ID. + */ +#define DC_VENDORID_DAVICOM 0x1282 + +/* + * Davicom device IDs. + */ +#define DC_DEVICEID_DM9009 0x9009 +#define DC_DEVICEID_DM9100 0x9100 +#define DC_DEVICEID_DM9102 0x9102 + +/* + * The DM9102A has the same PCI device ID as the DM9102, + * but a higher revision code. + */ +#define DC_REVISION_DM9102 0x10 +#define DC_REVISION_DM9102A 0x30 + +/* + * ADMtek vendor ID. + */ +#define DC_VENDORID_ADMTEK 0x1317 + +/* + * ADMtek device IDs. + */ +#define DC_DEVICEID_AL981 0x0981 +#define DC_DEVICEID_AN983 0x0985 +#define DC_DEVICEID_AN985 0x1985 +#define DC_DEVICEID_ADM9511 0x9511 +#define DC_DEVICEID_ADM9513 0x9513 + +/* + * 3COM PCI vendor ID + */ +#define DC_VENDORID_3COM 0x10b7 + +/* + * 3COM OfficeConnect 10/100B (3CSOHO100B-TX) + */ +#define DC_DEVICEID_3CSOHOB 0x9300 + +/* + * ASIX vendor ID. + */ +#define DC_VENDORID_ASIX 0x125B + +/* + * ASIX device IDs. + */ +#define DC_DEVICEID_AX88140A 0x1400 + +/* + * The ASIX AX88140 and ASIX AX88141 have the same vendor and + * device IDs but different revision values. + */ +#define DC_REVISION_88140 0x00 +#define DC_REVISION_88141 0x10 + +/* + * Accton vendor ID. + */ +#define DC_VENDORID_ACCTON 0x1113 + +/* + * Accton device IDs. + */ +#define DC_DEVICEID_EN1217 0x1217 +#define DC_DEVICEID_EN2242 0x1216 + +/* + * Xircom vendor ID + */ +#define DC_VENDORID_XIRCOM 0x115d + +/* + * Xircom device IDs. + */ +#define DC_DEVICEID_X3201 0x0003 + +/* + * D-Link vendor ID + */ +#define DC_VENDORID_DLINK 0x1186 + +/* + * D-Link device IDs. + */ +#define DC_DEVICEID_DRP32TXD 0x1561 + +/* + * Abocom vendor ID + */ +#define DC_VENDORID_ABOCOM 0x13d1 + +/* + * Abocom device IDs. + */ +#define DC_DEVICEID_FE2500 0xAB02 +#define DC_DEVICEID_FE2500MX 0xab08 + +/* + * Conexant vendor ID. + */ +#define DC_VENDORID_CONEXANT 0x14f1 + +/* + * Conexant device IDs. + */ +#define DC_DEVICEID_RS7112 0x1803 + +/* + * Planex vendor ID + */ +#define DC_VENDORID_PLANEX 0x14ea + +/* + * Planex device IDs. + */ +#define DC_DEVICEID_FNW3602T 0xab08 + +/* + * Not sure who this vendor should be, so we'll go with HAWKING until + * I can locate the right one. + */ +#define DC_VENDORID_HAWKING 0x17b3 + +/* + * Sure looks like an abocom device ID, but it found on my hawking PN672TX + * card. Use that for now, and upgrade later. + */ +#define DC_DEVICEID_HAWKING_PN672TX 0xab08 + +/* + * Microsoft device ID. + */ +#define DC_VENDORID_MICROSOFT 0x1414 + +/* + * Supported Microsoft PCI and cardbus NICs. These are really + * ADMtek parts in disguise. + */ + +#define DC_DEVICEID_MSMN120 0x0001 +#define DC_DEVICEID_MSMN130 0x0002 + +/* + * Linksys vendor ID. + */ +#define DC_VENDORID_LINKSYS 0x1737 + +/* + * Linksys device IDs. + */ +#define DC_DEVICEID_PCMPC200_AB08 0xab08 +#define DC_DEVICEID_PCMPC200_AB09 0xab09 + +#define DC_DEVID(vendor, device) ((device) << 16 | (vendor)) + +/* + * PCI low memory base and low I/O base register, and + * other PCI registers. + */ + +#define DC_PCI_CFBIO PCIR_BAR(0) /* Base I/O address */ +#define DC_PCI_CFBMA PCIR_BAR(1) /* Base memory address */ +#define DC_PCI_CFDD 0x40 /* Device and driver area */ +#define DC_PCI_CWUA0 0x44 /* Wake-Up LAN addr 0 */ +#define DC_PCI_CWUA1 0x48 /* Wake-Up LAN addr 1 */ +#define DC_PCI_SOP0 0x4C /* SecureON passwd 0 */ +#define DC_PCI_SOP1 0x50 /* SecureON passwd 1 */ +#define DC_PCI_CWUC 0x54 /* Configuration Wake-Up cmd */ + +#define DC_21143_PB_REV 0x00000030 +#define DC_21143_TB_REV 0x00000030 +#define DC_21143_PC_REV 0x00000030 +#define DC_21143_TC_REV 0x00000030 +#define DC_21143_PD_REV 0x00000041 +#define DC_21143_TD_REV 0x00000041 + +/* Configuration and driver area */ +#define DC_CFDD_DRVUSE 0x0000FFFF +#define DC_CFDD_SNOOZE_MODE 0x40000000 +#define DC_CFDD_SLEEP_MODE 0x80000000 + +/* Configuration wake-up command register */ +#define DC_CWUC_MUST_BE_ZERO 0x00000001 +#define DC_CWUC_SECUREON_ENB 0x00000002 +#define DC_CWUC_FORCE_WUL 0x00000004 +#define DC_CWUC_BNC_ABILITY 0x00000008 +#define DC_CWUC_AUI_ABILITY 0x00000010 +#define DC_CWUC_TP10_ABILITY 0x00000020 +#define DC_CWUC_MII_ABILITY 0x00000040 +#define DC_CWUC_SYM_ABILITY 0x00000080 +#define DC_CWUC_LOCK 0x00000100 + +/* + * SROM nonsense. + */ + +#define DC_IB_CTLRCNT 0x13 +#define DC_IB_LEAF0_CNUM 0x1A +#define DC_IB_LEAF0_OFFSET 0x1B + +struct dc_info_leaf { + u_int16_t dc_conntype; + u_int8_t dc_blkcnt; + u_int8_t dc_rsvd; + u_int16_t dc_infoblk; +}; + +#define DC_CTYPE_10BT 0x0000 +#define DC_CTYPE_10BT_NWAY 0x0100 +#define DC_CTYPE_10BT_FDX 0x0204 +#define DC_CTYPE_10B2 0x0001 +#define DC_CTYPE_10B5 0x0002 +#define DC_CTYPE_100BT 0x0003 +#define DC_CTYPE_100BT_FDX 0x0205 +#define DC_CTYPE_100T4 0x0006 +#define DC_CTYPE_100FX 0x0007 +#define DC_CTYPE_100FX_FDX 0x0208 +#define DC_CTYPE_MII_10BT 0x0009 +#define DC_CTYPE_MII_10BT_FDX 0x020A +#define DC_CTYPE_MII_100BT 0x000D +#define DC_CTYPE_MII_100BT_FDX 0x020E +#define DC_CTYPE_MII_100T4 0x000F +#define DC_CTYPE_MII_100FX 0x0010 +#define DC_CTYPE_MII_100FX_FDX 0x0211 +#define DC_CTYPE_DYN_PUP_AUTOSENSE 0x0800 +#define DC_CTYPE_PUP_AUTOSENSE 0x8800 +#define DC_CTYPE_NOMEDIA 0xFFFF + +#define DC_EBLOCK_SIA 0x0002 +#define DC_EBLOCK_MII 0x0003 +#define DC_EBLOCK_SYM 0x0004 +#define DC_EBLOCK_RESET 0x0005 +#define DC_EBLOCK_PHY_SHUTDOWN 0x0006 + +struct dc_leaf_hdr { + u_int16_t dc_mtype; + u_int8_t dc_mcnt; + u_int8_t dc_rsvd; +}; + +struct dc_eblock_hdr { + u_int8_t dc_len; + u_int8_t dc_type; +}; + +struct dc_eblock_sia { + struct dc_eblock_hdr dc_sia_hdr; + u_int8_t dc_sia_code; + union { + struct dc_sia_ext { /* if (dc_sia_code & DC_SIA_CODE_EXT) */ + u_int8_t dc_sia_mediaspec[6]; /* CSR13, CSR14, CSR15 */ + u_int8_t dc_sia_gpio_ctl[2]; + u_int8_t dc_sia_gpio_dat[2]; + } dc_sia_ext; + struct dc_sia_noext { + u_int8_t dc_sia_gpio_ctl[2]; + u_int8_t dc_sia_gpio_dat[2]; + } dc_sia_noext; + } dc_un; +}; + +#define DC_SIA_CODE_10BT 0x00 +#define DC_SIA_CODE_10B2 0x01 +#define DC_SIA_CODE_10B5 0x02 +#define DC_SIA_CODE_10BT_FDX 0x04 +#define DC_SIA_CODE_EXT 0x40 + +/* + * Note that the first word in the gpr and reset + * sequences is always a control word. + */ +struct dc_eblock_mii { + struct dc_eblock_hdr dc_mii_hdr; + u_int8_t dc_mii_phynum; + u_int8_t dc_gpr_len; +/* u_int16_t dc_gpr_dat[n]; */ +/* u_int8_t dc_reset_len; */ +/* u_int16_t dc_reset_dat[n]; */ +/* There are other fields after these, but we don't + * care about them since they can be determined by looking + * at the PHY. + */ +}; + +struct dc_eblock_sym { + struct dc_eblock_hdr dc_sym_hdr; + u_int8_t dc_sym_code; + u_int8_t dc_sym_gpio_ctl[2]; + u_int8_t dc_sym_gpio_dat[2]; + u_int8_t dc_sym_cmd[2]; +}; + +#define DC_SYM_CODE_100BT 0x03 +#define DC_SYM_CODE_100BT_FDX 0x05 +#define DC_SYM_CODE_100T4 0x06 +#define DC_SYM_CODE_100FX 0x07 +#define DC_SYM_CODE_100FX_FDX 0x08 + +struct dc_eblock_reset { + struct dc_eblock_hdr dc_reset_hdr; + u_int8_t dc_reset_len; +/* u_int16_t dc_reset_dat[n]; */ +}; diff --git a/freebsd/dev/dc/pnphy.c b/freebsd/dev/dc/pnphy.c new file mode 100644 index 00000000..d5837e54 --- /dev/null +++ b/freebsd/dev/dc/pnphy.c @@ -0,0 +1,243 @@ +#include + +/* + * Copyright (c) 1997, 1998, 1999 + * Bill Paul . All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Bill Paul. + * 4. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +/* + * Pseudo-driver for media selection on the Lite-On PNIC 82c168 + * chip. The NWAY support on this chip is horribly broken, so we + * only support manual mode selection. This is lame, but getting + * NWAY to work right is amazingly difficult. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include + +#define DC_SETBIT(sc, reg, x) \ + CSR_WRITE_4(sc, reg, \ + CSR_READ_4(sc, reg) | x) + +#define DC_CLRBIT(sc, reg, x) \ + CSR_WRITE_4(sc, reg, \ + CSR_READ_4(sc, reg) & ~x) + +static int pnphy_probe(device_t); +static int pnphy_attach(device_t); + +static device_method_t pnphy_methods[] = { + /* device interface */ + DEVMETHOD(device_probe, pnphy_probe), + DEVMETHOD(device_attach, pnphy_attach), + DEVMETHOD(device_detach, mii_phy_detach), + DEVMETHOD(device_shutdown, bus_generic_shutdown), + { 0, 0 } +}; + +static devclass_t pnphy_devclass; + +static driver_t pnphy_driver = { + "pnphy", + pnphy_methods, + sizeof(struct mii_softc) +}; + +DRIVER_MODULE(pnphy, miibus, pnphy_driver, pnphy_devclass, 0, 0); + +static int pnphy_service(struct mii_softc *, struct mii_data *, int); +static void pnphy_status(struct mii_softc *); + +static int +pnphy_probe(device_t dev) +{ + struct mii_attach_args *ma; + + ma = device_get_ivars(dev); + + /* + * The dc driver will report the 82c168 vendor and device + * ID to let us know that it wants us to attach. + */ + if (ma->mii_id1 != DC_VENDORID_LO || + ma->mii_id2 != DC_DEVICEID_82C168) + return (ENXIO); + + device_set_desc(dev, "PNIC 82c168 media interface"); + + return (BUS_PROBE_DEFAULT); +} + +static int +pnphy_attach(device_t dev) +{ + struct mii_softc *sc; + struct mii_attach_args *ma; + struct mii_data *mii; + + sc = device_get_softc(dev); + ma = device_get_ivars(dev); + sc->mii_dev = device_get_parent(dev); + mii = ma->mii_data; + LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); + + sc->mii_flags = miibus_get_flags(dev); + sc->mii_inst = mii->mii_instance++; + sc->mii_phy = ma->mii_phyno; + sc->mii_service = pnphy_service; + sc->mii_pdata = mii; + + /* + * Apparently, we can neither isolate nor do loopback. + */ + sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP; + + sc->mii_capabilities = + BMSR_100TXFDX | BMSR_100TXHDX | BMSR_10TFDX | BMSR_10THDX; + sc->mii_capabilities &= ma->mii_capmask; + device_printf(dev, " "); + mii_phy_add_media(sc); + printf("\n"); + + MIIBUS_MEDIAINIT(sc->mii_dev); + return (0); +} + +static int +pnphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) +{ + struct ifmedia_entry *ife = mii->mii_media.ifm_cur; + + switch (cmd) { + case MII_POLLSTAT: + break; + + case MII_MEDIACHG: + /* + * If the interface is not up, don't do anything. + */ + if ((mii->mii_ifp->if_flags & IFF_UP) == 0) + break; + + switch (IFM_SUBTYPE(ife->ifm_media)) { + case IFM_AUTO: + /* NWAY is busted on this chip */ + case IFM_100_T4: + /* + * XXX Not supported as a manual setting right now. + */ + return (EINVAL); + case IFM_100_TX: + mii->mii_media_active = IFM_ETHER | IFM_100_TX; + if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) + mii->mii_media_active |= IFM_FDX; + MIIBUS_STATCHG(sc->mii_dev); + return (0); + case IFM_10_T: + mii->mii_media_active = IFM_ETHER | IFM_10_T; + if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) + mii->mii_media_active |= IFM_FDX; + MIIBUS_STATCHG(sc->mii_dev); + return (0); + default: + return (EINVAL); + } + break; + + case MII_TICK: + /* + * Is the interface even up? + */ + if ((mii->mii_ifp->if_flags & IFF_UP) == 0) + return (0); + + break; + } + + /* Update the media status. */ + pnphy_status(sc); + + /* Callback if something changed. */ + mii_phy_update(sc, cmd); + return (0); +} + +static void +pnphy_status(struct mii_softc *sc) +{ + struct mii_data *mii = sc->mii_pdata; + int reg; + struct dc_softc *dc_sc; + + dc_sc = mii->mii_ifp->if_softc; + + mii->mii_media_status = IFM_AVALID; + mii->mii_media_active = IFM_ETHER; + + reg = CSR_READ_4(dc_sc, DC_ISR); + + if (!(reg & DC_ISR_LINKFAIL)) + mii->mii_media_status |= IFM_ACTIVE; + + if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_SPEEDSEL) + mii->mii_media_active |= IFM_10_T; + else + mii->mii_media_active |= IFM_100_TX; + if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_FULLDUPLEX) + mii->mii_media_active |= IFM_FDX; + else + mii->mii_media_active |= IFM_HDX; +} diff --git a/freebsd/dev/mii/brgphy.c b/freebsd/dev/mii/brgphy.c new file mode 100644 index 00000000..9b53c83d --- /dev/null +++ b/freebsd/dev/mii/brgphy.c @@ -0,0 +1,1090 @@ +#include + +/*- + * Copyright (c) 2000 + * Bill Paul . All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Bill Paul. + * 4. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +/* + * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include + +static int brgphy_probe(device_t); +static int brgphy_attach(device_t); + +struct brgphy_softc { + struct mii_softc mii_sc; + int mii_oui; + int mii_model; + int mii_rev; + int serdes_flags; /* Keeps track of the serdes type used */ +#define BRGPHY_5706S 0x0001 +#define BRGPHY_5708S 0x0002 +#define BRGPHY_NOANWAIT 0x0004 +#define BRGPHY_5709S 0x0008 + int bce_phy_flags; /* PHY flags transferred from the MAC driver */ +}; + +static device_method_t brgphy_methods[] = { + /* device interface */ + DEVMETHOD(device_probe, brgphy_probe), + DEVMETHOD(device_attach, brgphy_attach), + DEVMETHOD(device_detach, mii_phy_detach), + DEVMETHOD(device_shutdown, bus_generic_shutdown), + { 0, 0 } +}; + +static devclass_t brgphy_devclass; + +static driver_t brgphy_driver = { + "brgphy", + brgphy_methods, + sizeof(struct brgphy_softc) +}; + +DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); + +static int brgphy_service(struct mii_softc *, struct mii_data *, int); +static void brgphy_setmedia(struct mii_softc *, int); +static void brgphy_status(struct mii_softc *); +static void brgphy_mii_phy_auto(struct mii_softc *, int); +static void brgphy_reset(struct mii_softc *); +static void brgphy_enable_loopback(struct mii_softc *); +static void bcm5401_load_dspcode(struct mii_softc *); +static void bcm5411_load_dspcode(struct mii_softc *); +static void bcm54k2_load_dspcode(struct mii_softc *); +static void brgphy_fixup_5704_a0_bug(struct mii_softc *); +static void brgphy_fixup_adc_bug(struct mii_softc *); +static void brgphy_fixup_adjust_trim(struct mii_softc *); +static void brgphy_fixup_ber_bug(struct mii_softc *); +static void brgphy_fixup_crc_bug(struct mii_softc *); +static void brgphy_fixup_jitter_bug(struct mii_softc *); +static void brgphy_ethernet_wirespeed(struct mii_softc *); +static void brgphy_jumbo_settings(struct mii_softc *, u_long); + +static const struct mii_phydesc brgphys[] = { + MII_PHY_DESC(xxBROADCOM, BCM5400), + MII_PHY_DESC(xxBROADCOM, BCM5401), + MII_PHY_DESC(xxBROADCOM, BCM5411), + MII_PHY_DESC(xxBROADCOM, BCM54K2), + MII_PHY_DESC(xxBROADCOM, BCM5701), + MII_PHY_DESC(xxBROADCOM, BCM5703), + MII_PHY_DESC(xxBROADCOM, BCM5704), + MII_PHY_DESC(xxBROADCOM, BCM5705), + MII_PHY_DESC(xxBROADCOM, BCM5706), + MII_PHY_DESC(xxBROADCOM, BCM5714), + MII_PHY_DESC(xxBROADCOM, BCM5750), + MII_PHY_DESC(xxBROADCOM, BCM5752), + MII_PHY_DESC(xxBROADCOM, BCM5754), + MII_PHY_DESC(xxBROADCOM, BCM5780), + MII_PHY_DESC(xxBROADCOM, BCM5708C), + MII_PHY_DESC(xxBROADCOM_ALT1, BCM5755), + MII_PHY_DESC(xxBROADCOM_ALT1, BCM5787), + MII_PHY_DESC(xxBROADCOM_ALT1, BCM5708S), + MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709CAX), + MII_PHY_DESC(xxBROADCOM_ALT1, BCM5722), + MII_PHY_DESC(xxBROADCOM_ALT1, BCM5784), + MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709C), + MII_PHY_DESC(xxBROADCOM_ALT1, BCM5761), + MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709S), + MII_PHY_DESC(xxBROADCOM_ALT2, BCM5717C), + MII_PHY_DESC(BROADCOM2, BCM5906), + MII_PHY_END +}; + +#define HS21_PRODUCT_ID "IBM eServer BladeCenter HS21" +#define HS21_BCM_CHIPID 0x57081021 + +static int +detect_hs21(struct bce_softc *bce_sc) +{ + char *sysenv; + int found; + + found = 0; + if (bce_sc->bce_chipid == HS21_BCM_CHIPID) { + sysenv = getenv("smbios.system.product"); + if (sysenv != NULL) { + if (strncmp(sysenv, HS21_PRODUCT_ID, + strlen(HS21_PRODUCT_ID)) == 0) + found = 1; + freeenv(sysenv); + } + } + return (found); +} + +/* Search for our PHY in the list of known PHYs */ +static int +brgphy_probe(device_t dev) +{ + + return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT)); +} + +/* Attach the PHY to the MII bus */ +static int +brgphy_attach(device_t dev) +{ + struct brgphy_softc *bsc; + struct bge_softc *bge_sc = NULL; + struct bce_softc *bce_sc = NULL; + struct mii_softc *sc; + struct mii_attach_args *ma; + struct mii_data *mii; + struct ifnet *ifp; + + bsc = device_get_softc(dev); + sc = &bsc->mii_sc; + ma = device_get_ivars(dev); + sc->mii_dev = device_get_parent(dev); + mii = ma->mii_data; + LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); + + /* Initialize mii_softc structure */ + sc->mii_flags = miibus_get_flags(dev); + sc->mii_inst = mii->mii_instance++; + sc->mii_phy = ma->mii_phyno; + sc->mii_service = brgphy_service; + sc->mii_pdata = mii; + + /* + * At least some variants wedge when isolating, at least some also + * don't support loopback. + */ + sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP | MIIF_NOMANPAUSE; + + /* Initialize brgphy_softc structure */ + bsc->mii_oui = MII_OUI(ma->mii_id1, ma->mii_id2); + bsc->mii_model = MII_MODEL(ma->mii_id2); + bsc->mii_rev = MII_REV(ma->mii_id2); + bsc->serdes_flags = 0; + + if (bootverbose) + device_printf(dev, "OUI 0x%06x, model 0x%04x, rev. %d\n", + bsc->mii_oui, bsc->mii_model, bsc->mii_rev); + + /* Handle any special cases based on the PHY ID */ + switch (bsc->mii_oui) { + case MII_OUI_BROADCOM: + case MII_OUI_BROADCOM2: + break; + case MII_OUI_xxBROADCOM: + switch (bsc->mii_model) { + case MII_MODEL_xxBROADCOM_BCM5706: + case MII_MODEL_xxBROADCOM_BCM5714: + /* + * The 5464 PHY used in the 5706 supports both copper + * and fiber interfaces over GMII. Need to check the + * shadow registers to see which mode is actually + * in effect, and therefore whether we have 5706C or + * 5706S. + */ + PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, + BRGPHY_SHADOW_1C_MODE_CTRL); + if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) & + BRGPHY_SHADOW_1C_ENA_1000X) { + bsc->serdes_flags |= BRGPHY_5706S; + sc->mii_flags |= MIIF_HAVEFIBER; + } + break; + } break; + case MII_OUI_xxBROADCOM_ALT1: + switch (bsc->mii_model) { + case MII_MODEL_xxBROADCOM_ALT1_BCM5708S: + bsc->serdes_flags |= BRGPHY_5708S; + sc->mii_flags |= MIIF_HAVEFIBER; + break; + case MII_MODEL_xxBROADCOM_ALT1_BCM5709S: + bsc->serdes_flags |= BRGPHY_5709S; + sc->mii_flags |= MIIF_HAVEFIBER; + break; + } + break; + case MII_OUI_xxBROADCOM_ALT2: + /* No special handling yet. */ + break; + default: + device_printf(dev, "Unrecognized OUI for PHY!\n"); + } + + ifp = sc->mii_pdata->mii_ifp; + + /* Find the MAC driver associated with this PHY. */ + if (strcmp(ifp->if_dname, "bge") == 0) { + bge_sc = ifp->if_softc; + } else if (strcmp(ifp->if_dname, "bce") == 0) { + bce_sc = ifp->if_softc; + } + + brgphy_reset(sc); + + /* Read the PHY's capabilities. */ + sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; + if (sc->mii_capabilities & BMSR_EXTSTAT) + sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); + device_printf(dev, " "); + +#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) + + /* Add the supported media types */ + if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { + mii_phy_add_media(sc); + printf("\n"); + } else { + sc->mii_anegticks = MII_ANEGTICKS_GIGE; + ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst), + BRGPHY_S1000 | BRGPHY_BMCR_FDX); + printf("1000baseSX-FDX, "); + /* 2.5G support is a software enabled feature on the 5708S and 5709S. */ + if (bce_sc && (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) { + ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX, sc->mii_inst), 0); + printf("2500baseSX-FDX, "); + } else if ((bsc->serdes_flags & BRGPHY_5708S) && bce_sc && + (detect_hs21(bce_sc) != 0)) { + /* + * There appears to be certain silicon revision + * in IBM HS21 blades that is having issues with + * this driver wating for the auto-negotiation to + * complete. This happens with a specific chip id + * only and when the 1000baseSX-FDX is the only + * mode. Workaround this issue since it's unlikely + * to be ever addressed. + */ + printf("auto-neg workaround, "); + bsc->serdes_flags |= BRGPHY_NOANWAIT; + } + ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); + printf("auto\n"); + } + +#undef ADD + MIIBUS_MEDIAINIT(sc->mii_dev); + return (0); +} + +static int +brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) +{ + struct brgphy_softc *bsc = (struct brgphy_softc *)sc; + struct ifmedia_entry *ife = mii->mii_media.ifm_cur; + int val; + + switch (cmd) { + case MII_POLLSTAT: + break; + case MII_MEDIACHG: + /* If the interface is not up, don't do anything. */ + if ((mii->mii_ifp->if_flags & IFF_UP) == 0) + break; + + /* Todo: Why is this here? Is it really needed? */ + brgphy_reset(sc); /* XXX hardware bug work-around */ + + switch (IFM_SUBTYPE(ife->ifm_media)) { + case IFM_AUTO: + brgphy_mii_phy_auto(sc, ife->ifm_media); + break; + case IFM_2500_SX: + case IFM_1000_SX: + case IFM_1000_T: + case IFM_100_TX: + case IFM_10_T: + brgphy_setmedia(sc, ife->ifm_media); + break; + default: + return (EINVAL); + } + break; + case MII_TICK: + /* Bail if the interface isn't up. */ + if ((mii->mii_ifp->if_flags & IFF_UP) == 0) + return (0); + + + /* Bail if autoneg isn't in process. */ + if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { + sc->mii_ticks = 0; + break; + } + + /* + * Check to see if we have link. If we do, we don't + * need to restart the autonegotiation process. + */ + val = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); + if (val & BMSR_LINK) { + sc->mii_ticks = 0; /* Reset autoneg timer. */ + break; + } + + /* Announce link loss right after it happens. */ + if (sc->mii_ticks++ == 0) + break; + + /* Only retry autonegotiation every mii_anegticks seconds. */ + if (sc->mii_ticks <= sc->mii_anegticks) + break; + + + /* Retry autonegotiation */ + sc->mii_ticks = 0; + brgphy_mii_phy_auto(sc, ife->ifm_media); + break; + } + + /* Update the media status. */ + brgphy_status(sc); + + /* + * Callback if something changed. Note that we need to poke + * the DSP on the Broadcom PHYs if the media changes. + */ + if (sc->mii_media_active != mii->mii_media_active || + sc->mii_media_status != mii->mii_media_status || + cmd == MII_MEDIACHG) { + switch (bsc->mii_oui) { + case MII_OUI_BROADCOM: + break; + case MII_OUI_xxBROADCOM: + switch (bsc->mii_model) { + case MII_MODEL_xxBROADCOM_BCM5400: + bcm5401_load_dspcode(sc); + break; + case MII_MODEL_xxBROADCOM_BCM5401: + if (bsc->mii_rev == 1 || bsc->mii_rev == 3) + bcm5401_load_dspcode(sc); + break; + case MII_MODEL_xxBROADCOM_BCM5411: + bcm5411_load_dspcode(sc); + break; + case MII_MODEL_xxBROADCOM_BCM54K2: + bcm54k2_load_dspcode(sc); + break; + } + break; + case MII_OUI_xxBROADCOM_ALT1: + break; + } + } + mii_phy_update(sc, cmd); + return (0); +} + +/****************************************************************************/ +/* Sets the PHY link speed. */ +/* */ +/* Returns: */ +/* None */ +/****************************************************************************/ +static void +brgphy_setmedia(struct mii_softc *sc, int media) +{ + int bmcr = 0, gig; + + switch (IFM_SUBTYPE(media)) { + case IFM_2500_SX: + break; + case IFM_1000_SX: + case IFM_1000_T: + bmcr = BRGPHY_S1000; + break; + case IFM_100_TX: + bmcr = BRGPHY_S100; + break; + case IFM_10_T: + default: + bmcr = BRGPHY_S10; + break; + } + + if ((media & IFM_GMASK) == IFM_FDX) { + bmcr |= BRGPHY_BMCR_FDX; + gig = BRGPHY_1000CTL_AFD; + } else { + gig = BRGPHY_1000CTL_AHD; + } + + /* Force loopback to disconnect PHY from Ethernet medium. */ + brgphy_enable_loopback(sc); + + PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); + PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); + + if (IFM_SUBTYPE(media) != IFM_1000_T && + IFM_SUBTYPE(media) != IFM_1000_SX) { + PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr); + return; + } + + if (IFM_SUBTYPE(media) == IFM_1000_T) { + gig |= BRGPHY_1000CTL_MSE; + if ((media & IFM_ETH_MASTER) != 0 || + (sc->mii_pdata->mii_ifp->if_flags & IFF_LINK0) != 0) + gig |= BRGPHY_1000CTL_MSC; + } + PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); + PHY_WRITE(sc, BRGPHY_MII_BMCR, + bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); +} + +/****************************************************************************/ +/* Set the media status based on the PHY settings. */ +/* */ +/* Returns: */ +/* None */ +/****************************************************************************/ +static void +brgphy_status(struct mii_softc *sc) +{ + struct brgphy_softc *bsc = (struct brgphy_softc *)sc; + struct mii_data *mii = sc->mii_pdata; + int aux, bmcr, bmsr, val, xstat; + u_int flowstat; + + mii->mii_media_status = IFM_AVALID; + mii->mii_media_active = IFM_ETHER; + + bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR); + bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); + + if (bmcr & BRGPHY_BMCR_LOOP) { + mii->mii_media_active |= IFM_LOOP; + } + + if ((bmcr & BRGPHY_BMCR_AUTOEN) && + (bmsr & BRGPHY_BMSR_ACOMP) == 0 && + (bsc->serdes_flags & BRGPHY_NOANWAIT) == 0) { + /* Erg, still trying, I guess... */ + mii->mii_media_active |= IFM_NONE; + return; + } + + if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { + /* + * NB: reading the ANAR, ANLPAR or 1000STS after the AUXSTS + * wedges at least the PHY of BCM5704 (but not others). + */ + flowstat = mii_phy_flowstatus(sc); + xstat = PHY_READ(sc, BRGPHY_MII_1000STS); + aux = PHY_READ(sc, BRGPHY_MII_AUXSTS); + + /* If copper link is up, get the negotiated speed/duplex. */ + if (aux & BRGPHY_AUXSTS_LINK) { + mii->mii_media_status |= IFM_ACTIVE; + switch (aux & BRGPHY_AUXSTS_AN_RES) { + case BRGPHY_RES_1000FD: + mii->mii_media_active |= IFM_1000_T | IFM_FDX; break; + case BRGPHY_RES_1000HD: + mii->mii_media_active |= IFM_1000_T | IFM_HDX; break; + case BRGPHY_RES_100FD: + mii->mii_media_active |= IFM_100_TX | IFM_FDX; break; + case BRGPHY_RES_100T4: + mii->mii_media_active |= IFM_100_T4; break; + case BRGPHY_RES_100HD: + mii->mii_media_active |= IFM_100_TX | IFM_HDX; break; + case BRGPHY_RES_10FD: + mii->mii_media_active |= IFM_10_T | IFM_FDX; break; + case BRGPHY_RES_10HD: + mii->mii_media_active |= IFM_10_T | IFM_HDX; break; + default: + mii->mii_media_active |= IFM_NONE; break; + } + + if ((mii->mii_media_active & IFM_FDX) != 0) + mii->mii_media_active |= flowstat; + + if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T && + (xstat & BRGPHY_1000STS_MSR) != 0) + mii->mii_media_active |= IFM_ETH_MASTER; + } + } else { + /* Todo: Add support for flow control. */ + /* If serdes link is up, get the negotiated speed/duplex. */ + if (bmsr & BRGPHY_BMSR_LINK) { + mii->mii_media_status |= IFM_ACTIVE; + } + + /* Check the link speed/duplex based on the PHY type. */ + if (bsc->serdes_flags & BRGPHY_5706S) { + mii->mii_media_active |= IFM_1000_SX; + + /* If autoneg enabled, read negotiated duplex settings */ + if (bmcr & BRGPHY_BMCR_AUTOEN) { + val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR); + if (val & BRGPHY_SERDES_ANAR_FDX) + mii->mii_media_active |= IFM_FDX; + else + mii->mii_media_active |= IFM_HDX; + } + } else if (bsc->serdes_flags & BRGPHY_5708S) { + PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); + xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1); + + /* Check for MRBE auto-negotiated speed results. */ + switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) { + case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10: + mii->mii_media_active |= IFM_10_FL; break; + case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100: + mii->mii_media_active |= IFM_100_FX; break; + case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G: + mii->mii_media_active |= IFM_1000_SX; break; + case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G: + mii->mii_media_active |= IFM_2500_SX; break; + } + + /* Check for MRBE auto-negotiated duplex results. */ + if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX) + mii->mii_media_active |= IFM_FDX; + else + mii->mii_media_active |= IFM_HDX; + } else if (bsc->serdes_flags & BRGPHY_5709S) { + /* Select GP Status Block of the AN MMD, get autoneg results. */ + PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS); + xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS); + + /* Restore IEEE0 block (assumed in all brgphy(4) code). */ + PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); + + /* Check for MRBE auto-negotiated speed results. */ + switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) { + case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10: + mii->mii_media_active |= IFM_10_FL; break; + case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100: + mii->mii_media_active |= IFM_100_FX; break; + case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G: + mii->mii_media_active |= IFM_1000_SX; break; + case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G: + mii->mii_media_active |= IFM_2500_SX; break; + } + + /* Check for MRBE auto-negotiated duplex results. */ + if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX) + mii->mii_media_active |= IFM_FDX; + else + mii->mii_media_active |= IFM_HDX; + } + } +} + +static void +brgphy_mii_phy_auto(struct mii_softc *sc, int media) +{ + struct brgphy_softc *bsc = (struct brgphy_softc *)sc; + int anar, ktcr = 0; + + brgphy_reset(sc); + + if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { + anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; + if ((media & IFM_FLOW) != 0 || + (sc->mii_flags & MIIF_FORCEPAUSE) != 0) + anar |= BRGPHY_ANAR_PC | BRGPHY_ANAR_ASP; + PHY_WRITE(sc, BRGPHY_MII_ANAR, anar); + } else { + anar = BRGPHY_SERDES_ANAR_FDX | BRGPHY_SERDES_ANAR_HDX; + if ((media & IFM_FLOW) != 0 || + (sc->mii_flags & MIIF_FORCEPAUSE) != 0) + anar |= BRGPHY_SERDES_ANAR_BOTH_PAUSE; + PHY_WRITE(sc, BRGPHY_SERDES_ANAR, anar); + } + + ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD; + if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5701) + ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC; + PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr); + ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL); + + PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_AUTOEN | + BRGPHY_BMCR_STARTNEG); + PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); +} + +/* Enable loopback to force the link down. */ +static void +brgphy_enable_loopback(struct mii_softc *sc) +{ + int i; + + PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); + for (i = 0; i < 15000; i++) { + if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK)) + break; + DELAY(10); + } +} + +/* Turn off tap power management on 5401. */ +static void +bcm5401_load_dspcode(struct mii_softc *sc) +{ + static const struct { + int reg; + uint16_t val; + } dspcode[] = { + { BRGPHY_MII_AUXCTL, 0x0c20 }, + { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, + { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, + { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, + { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, + { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, + { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, + { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, + { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, + { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, + { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, + { 0, 0 }, + }; + int i; + + for (i = 0; dspcode[i].reg != 0; i++) + PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); + DELAY(40); +} + +static void +bcm5411_load_dspcode(struct mii_softc *sc) +{ + static const struct { + int reg; + uint16_t val; + } dspcode[] = { + { 0x1c, 0x8c23 }, + { 0x1c, 0x8ca3 }, + { 0x1c, 0x8c23 }, + { 0, 0 }, + }; + int i; + + for (i = 0; dspcode[i].reg != 0; i++) + PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); +} + +void +bcm54k2_load_dspcode(struct mii_softc *sc) +{ + static const struct { + int reg; + uint16_t val; + } dspcode[] = { + { 4, 0x01e1 }, + { 9, 0x0300 }, + { 0, 0 }, + }; + int i; + + for (i = 0; dspcode[i].reg != 0; i++) + PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); + +} + +static void +brgphy_fixup_5704_a0_bug(struct mii_softc *sc) +{ + static const struct { + int reg; + uint16_t val; + } dspcode[] = { + { 0x1c, 0x8d68 }, + { 0x1c, 0x8d68 }, + { 0, 0 }, + }; + int i; + + for (i = 0; dspcode[i].reg != 0; i++) + PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); +} + +static void +brgphy_fixup_adc_bug(struct mii_softc *sc) +{ + static const struct { + int reg; + uint16_t val; + } dspcode[] = { + { BRGPHY_MII_AUXCTL, 0x0c00 }, + { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, + { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, + { 0, 0 }, + }; + int i; + + for (i = 0; dspcode[i].reg != 0; i++) + PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); +} + +static void +brgphy_fixup_adjust_trim(struct mii_softc *sc) +{ + static const struct { + int reg; + uint16_t val; + } dspcode[] = { + { BRGPHY_MII_AUXCTL, 0x0c00 }, + { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, + { BRGPHY_MII_DSP_RW_PORT, 0x110b }, + { BRGPHY_MII_TEST1, 0x0014 }, + { BRGPHY_MII_AUXCTL, 0x0400 }, + { 0, 0 }, + }; + int i; + + for (i = 0; dspcode[i].reg != 0; i++) + PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); +} + +static void +brgphy_fixup_ber_bug(struct mii_softc *sc) +{ + static const struct { + int reg; + uint16_t val; + } dspcode[] = { + { BRGPHY_MII_AUXCTL, 0x0c00 }, + { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, + { BRGPHY_MII_DSP_RW_PORT, 0x310b }, + { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, + { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, + { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, + { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, + { BRGPHY_MII_AUXCTL, 0x0400 }, + { 0, 0 }, + }; + int i; + + for (i = 0; dspcode[i].reg != 0; i++) + PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); +} + +static void +brgphy_fixup_crc_bug(struct mii_softc *sc) +{ + static const struct { + int reg; + uint16_t val; + } dspcode[] = { + { BRGPHY_MII_DSP_RW_PORT, 0x0a75 }, + { 0x1c, 0x8c68 }, + { 0x1c, 0x8d68 }, + { 0x1c, 0x8c68 }, + { 0, 0 }, + }; + int i; + + for (i = 0; dspcode[i].reg != 0; i++) + PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); +} + +static void +brgphy_fixup_jitter_bug(struct mii_softc *sc) +{ + static const struct { + int reg; + uint16_t val; + } dspcode[] = { + { BRGPHY_MII_AUXCTL, 0x0c00 }, + { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, + { BRGPHY_MII_DSP_RW_PORT, 0x010b }, + { BRGPHY_MII_AUXCTL, 0x0400 }, + { 0, 0 }, + }; + int i; + + for (i = 0; dspcode[i].reg != 0; i++) + PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); +} + +static void +brgphy_fixup_disable_early_dac(struct mii_softc *sc) +{ + uint32_t val; + + PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08); + val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); + val &= ~(1 << 8); + PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val); + +} + +static void +brgphy_ethernet_wirespeed(struct mii_softc *sc) +{ + uint32_t val; + + /* Enable Ethernet@WireSpeed. */ + PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); + val = PHY_READ(sc, BRGPHY_MII_AUXCTL); + PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); +} + +static void +brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu) +{ + struct brgphy_softc *bsc = (struct brgphy_softc *)sc; + uint32_t val; + + /* Set or clear jumbo frame settings in the PHY. */ + if (mtu > ETHER_MAX_LEN) { + if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5401) { + /* BCM5401 PHY cannot read-modify-write. */ + PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20); + } else { + PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); + val = PHY_READ(sc, BRGPHY_MII_AUXCTL); + PHY_WRITE(sc, BRGPHY_MII_AUXCTL, + val | BRGPHY_AUXCTL_LONG_PKT); + } + + val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); + PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, + val | BRGPHY_PHY_EXTCTL_HIGH_LA); + } else { + PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); + val = PHY_READ(sc, BRGPHY_MII_AUXCTL); + PHY_WRITE(sc, BRGPHY_MII_AUXCTL, + val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); + + val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); + PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, + val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); + } +} + +static void +brgphy_reset(struct mii_softc *sc) +{ + struct brgphy_softc *bsc = (struct brgphy_softc *)sc; + struct bge_softc *bge_sc = NULL; + struct bce_softc *bce_sc = NULL; + struct ifnet *ifp; + int val; + + /* Perform a standard PHY reset. */ + mii_phy_reset(sc); + + /* Handle any PHY specific procedures following the reset. */ + switch (bsc->mii_oui) { + case MII_OUI_BROADCOM: + break; + case MII_OUI_xxBROADCOM: + switch (bsc->mii_model) { + case MII_MODEL_xxBROADCOM_BCM5400: + bcm5401_load_dspcode(sc); + break; + case MII_MODEL_xxBROADCOM_BCM5401: + if (bsc->mii_rev == 1 || bsc->mii_rev == 3) + bcm5401_load_dspcode(sc); + break; + case MII_MODEL_xxBROADCOM_BCM5411: + bcm5411_load_dspcode(sc); + break; + case MII_MODEL_xxBROADCOM_BCM54K2: + bcm54k2_load_dspcode(sc); + break; + } + break; + case MII_OUI_xxBROADCOM_ALT1: + case MII_OUI_xxBROADCOM_ALT2: + break; + } + + ifp = sc->mii_pdata->mii_ifp; + + /* Find the driver associated with this PHY. */ + if (strcmp(ifp->if_dname, "bge") == 0) { + bge_sc = ifp->if_softc; + } else if (strcmp(ifp->if_dname, "bce") == 0) { + bce_sc = ifp->if_softc; + } + + if (bge_sc) { + /* Fix up various bugs */ + if (bge_sc->bge_phy_flags & BGE_PHY_5704_A0_BUG) + brgphy_fixup_5704_a0_bug(sc); + if (bge_sc->bge_phy_flags & BGE_PHY_ADC_BUG) + brgphy_fixup_adc_bug(sc); + if (bge_sc->bge_phy_flags & BGE_PHY_ADJUST_TRIM) + brgphy_fixup_adjust_trim(sc); + if (bge_sc->bge_phy_flags & BGE_PHY_BER_BUG) + brgphy_fixup_ber_bug(sc); + if (bge_sc->bge_phy_flags & BGE_PHY_CRC_BUG) + brgphy_fixup_crc_bug(sc); + if (bge_sc->bge_phy_flags & BGE_PHY_JITTER_BUG) + brgphy_fixup_jitter_bug(sc); + + brgphy_jumbo_settings(sc, ifp->if_mtu); + + if (bge_sc->bge_phy_flags & BGE_PHY_WIRESPEED) + brgphy_ethernet_wirespeed(sc); + + /* Enable Link LED on Dell boxes */ + if (bge_sc->bge_phy_flags & BGE_PHY_NO_3LED) { + PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, + PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) & + ~BRGPHY_PHY_EXTCTL_3_LED); + } + + /* Adjust output voltage (From Linux driver) */ + if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906) + PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); + } else if (bce_sc) { + if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 && + (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { + + /* Store autoneg capabilities/results in digital block (Page 0) */ + PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2); + PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0, + BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE); + PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); + + /* Enable fiber mode and autodetection */ + PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, + PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) | + BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN | + BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE); + + /* Enable parallel detection */ + PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2, + PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) | + BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN); + + /* Advertise 2.5G support through next page during autoneg */ + if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) + PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, + PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) | + BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); + + /* Increase TX signal amplitude */ + if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) || + (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) || + (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) { + PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, + BRGPHY_5708S_TX_MISC_PG5); + PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1, + PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30); + PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, + BRGPHY_5708S_DIG_PG0); + } + + /* Backplanes use special driver/pre-driver/pre-emphasis values. */ + if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) && + (bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) { + PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, + BRGPHY_5708S_TX_MISC_PG5); + PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3, + bce_sc->bce_port_hw_cfg & + BCE_PORT_HW_CFG_CFG_TXCTL3_MASK); + PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, + BRGPHY_5708S_DIG_PG0); + } + } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 && + (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { + + /* Select the SerDes Digital block of the AN MMD. */ + PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG); + val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1); + val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET; + val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER; + PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val); + + /* Select the Over 1G block of the AN MMD. */ + PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G); + + /* Enable autoneg "Next Page" to advertise 2.5G support. */ + val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1); + if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) + val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; + else + val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; + PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val); + + /* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */ + PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE); + + /* Enable MRBE speed autoneg. */ + val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP); + val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE | + BRGPHY_MRBE_MSG_PG5_NP_T2; + PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val); + + /* Select the Clause 73 User B0 block of the AN MMD. */ + PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0); + + /* Enable MRBE speed autoneg. */ + PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1, + BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP | + BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR | + BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG); + + /* Restore IEEE0 block (assumed in all brgphy(4) code). */ + PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); + } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) { + if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) || + (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx)) + brgphy_fixup_disable_early_dac(sc); + + brgphy_jumbo_settings(sc, ifp->if_mtu); + brgphy_ethernet_wirespeed(sc); + } else { + brgphy_fixup_ber_bug(sc); + brgphy_jumbo_settings(sc, ifp->if_mtu); + brgphy_ethernet_wirespeed(sc); + } + } +} diff --git a/freebsd/dev/mii/brgphyreg.h b/freebsd/dev/mii/brgphyreg.h new file mode 100644 index 00000000..fb8b65a5 --- /dev/null +++ b/freebsd/dev/mii/brgphyreg.h @@ -0,0 +1,420 @@ +/*- + * Copyright (c) 2000 + * Bill Paul . All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Bill Paul. + * 4. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _DEV_MII_BRGPHYREG_HH_ +#define _DEV_MII_BRGPHYREG_HH_ + +/* + * Broadcom BCM5400 registers + */ + +#define BRGPHY_MII_BMCR 0x00 +#define BRGPHY_BMCR_RESET 0x8000 +#define BRGPHY_BMCR_LOOP 0x4000 +#define BRGPHY_BMCR_SPD0 0x2000 /* Speed select, lower bit */ +#define BRGPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */ +#define BRGPHY_BMCR_PDOWN 0x0800 /* Power down */ +#define BRGPHY_BMCR_ISO 0x0400 /* Isolate */ +#define BRGPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */ +#define BRGPHY_BMCR_FDX 0x0100 /* Duplex mode */ +#define BRGPHY_BMCR_CTEST 0x0080 /* Collision test enable */ +#define BRGPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */ + +#define BRGPHY_S1000 BRGPHY_BMCR_SPD1 /* 1000mbps */ +#define BRGPHY_S100 BRGPHY_BMCR_SPD0 /* 100mpbs */ +#define BRGPHY_S10 0 /* 10mbps */ + +#define BRGPHY_MII_BMSR 0x01 +#define BRGPHY_BMSR_EXTSTS 0x0100 /* Extended status present */ +#define BRGPHY_BMSR_PRESUB 0x0040 /* Preamble surpression */ +#define BRGPHY_BMSR_ACOMP 0x0020 /* Autoneg complete */ +#define BRGPHY_BMSR_RFAULT 0x0010 /* Remote fault condition occured */ +#define BRGPHY_BMSR_ANEG 0x0008 /* Autoneg capable */ +#define BRGPHY_BMSR_LINK 0x0004 /* Link status */ +#define BRGPHY_BMSR_JABBER 0x0002 /* Jabber detected */ +#define BRGPHY_BMSR_EXT 0x0001 /* Extended capability */ + +#define BRGPHY_MII_ANAR 0x04 +#define BRGPHY_ANAR_NP 0x8000 /* Next page */ +#define BRGPHY_ANAR_RF 0x2000 /* Remote fault */ +#define BRGPHY_ANAR_ASP 0x0800 /* Asymmetric Pause */ +#define BRGPHY_ANAR_PC 0x0400 /* Pause capable */ +#define BRGPHY_ANAR_SEL 0x001F /* Selector field, 00001=Ethernet */ + +#define BRGPHY_MII_ANLPAR 0x05 +#define BRGPHY_ANLPAR_NP 0x8000 /* Next page */ +#define BRGPHY_ANLPAR_RF 0x2000 /* Remote fault */ +#define BRGPHY_ANLPAR_ASP 0x0800 /* Asymmetric Pause */ +#define BRGPHY_ANLPAR_PC 0x0400 /* Pause capable */ +#define BRGPHY_ANLPAR_SEL 0x001F /* Selector field, 00001=Ethernet */ + +#define BRGPHY_SEL_TYPE 0x0001 /* Ethernet */ + +#define BRGPHY_MII_ANER 0x06 +#define BRGPHY_ANER_PDF 0x0010 /* Parallel detection fault */ +#define BRGPHY_ANER_LPNP 0x0008 /* Link partner can next page */ +#define BRGPHY_ANER_NP 0x0004 /* Local PHY can next page */ +#define BRGPHY_ANER_RX 0x0002 /* Next page received */ +#define BRGPHY_ANER_LPAN 0x0001 /* Link partner autoneg capable */ + +#define BRGPHY_MII_NEXTP 0x07 /* Next page */ + +#define BRGPHY_MII_NEXTP_LP 0x08 /* Next page of link partner */ + +#define BRGPHY_MII_1000CTL 0x09 /* 1000baseT control */ +#define BRGPHY_1000CTL_TST 0xE000 /* Test modes */ +#define BRGPHY_1000CTL_MSE 0x1000 /* Master/Slave enable */ +#define BRGPHY_1000CTL_MSC 0x0800 /* Master/Slave configuration */ +#define BRGPHY_1000CTL_RD 0x0400 /* Repeater/DTE */ +#define BRGPHY_1000CTL_AFD 0x0200 /* Advertise full duplex */ +#define BRGPHY_1000CTL_AHD 0x0100 /* Advertise half duplex */ + +#define BRGPHY_MII_1000STS 0x0A /* 1000baseT status */ +#define BRGPHY_1000STS_MSF 0x8000 /* Master/slave fault */ +#define BRGPHY_1000STS_MSR 0x4000 /* Master/slave result */ +#define BRGPHY_1000STS_LRS 0x2000 /* Local receiver status */ +#define BRGPHY_1000STS_RRS 0x1000 /* Remote receiver status */ +#define BRGPHY_1000STS_LPFD 0x0800 /* Link partner can FD */ +#define BRGPHY_1000STS_LPHD 0x0400 /* Link partner can HD */ +#define BRGPHY_1000STS_IEC 0x00FF /* Idle error count */ + +#define BRGPHY_MII_EXTSTS 0x0F /* Extended status */ +#define BRGPHY_EXTSTS_X_FD_CAP 0x8000 /* 1000base-X FD capable */ +#define BRGPHY_EXTSTS_X_HD_CAP 0x4000 /* 1000base-X HD capable */ +#define BRGPHY_EXTSTS_T_FD_CAP 0x2000 /* 1000base-T FD capable */ +#define BRGPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */ + +#define BRGPHY_MII_PHY_EXTCTL 0x10 /* PHY extended control */ +#define BRGPHY_PHY_EXTCTL_MAC_PHY 0x8000 /* 10BIT/GMI-interface */ +#define BRGPHY_PHY_EXTCTL_DIS_CROSS 0x4000 /* Disable MDI crossover */ +#define BRGPHY_PHY_EXTCTL_TX_DIS 0x2000 /* TX output disabled */ +#define BRGPHY_PHY_EXTCTL_INT_DIS 0x1000 /* Interrupts disabled */ +#define BRGPHY_PHY_EXTCTL_F_INT 0x0800 /* Force interrupt */ +#define BRGPHY_PHY_EXTCTL_BY_45 0x0400 /* Bypass 4B5B-Decoder */ +#define BRGPHY_PHY_EXTCTL_BY_SCR 0x0200 /* Bypass scrambler */ +#define BRGPHY_PHY_EXTCTL_BY_MLT3 0x0100 /* Bypass MLT3 encoder */ +#define BRGPHY_PHY_EXTCTL_BY_RXA 0x0080 /* Bypass RX alignment */ +#define BRGPHY_PHY_EXTCTL_RES_SCR 0x0040 /* Reset scrambler */ +#define BRGPHY_PHY_EXTCTL_EN_LTR 0x0020 /* Enable LED traffic mode */ +#define BRGPHY_PHY_EXTCTL_LED_ON 0x0010 /* Force LEDs on */ +#define BRGPHY_PHY_EXTCTL_LED_OFF 0x0008 /* Force LEDs off */ +#define BRGPHY_PHY_EXTCTL_EX_IPG 0x0004 /* Extended TX IPG mode */ +#define BRGPHY_PHY_EXTCTL_3_LED 0x0002 /* Three link LED mode */ +#define BRGPHY_PHY_EXTCTL_HIGH_LA 0x0001 /* GMII Fifo Elasticy (?) */ + +#define BRGPHY_MII_PHY_EXTSTS 0x11 /* PHY extended status */ +#define BRGPHY_PHY_EXTSTS_CROSS_STAT 0x2000 /* MDI crossover status */ +#define BRGPHY_PHY_EXTSTS_INT_STAT 0x1000 /* Interrupt status */ +#define BRGPHY_PHY_EXTSTS_RRS 0x0800 /* Remote receiver status */ +#define BRGPHY_PHY_EXTSTS_LRS 0x0400 /* Local receiver status */ +#define BRGPHY_PHY_EXTSTS_LOCKED 0x0200 /* Locked */ +#define BRGPHY_PHY_EXTSTS_LS 0x0100 /* Link status */ +#define BRGPHY_PHY_EXTSTS_RF 0x0080 /* Remove fault */ +#define BRGPHY_PHY_EXTSTS_CE_ER 0x0040 /* Carrier ext error */ +#define BRGPHY_PHY_EXTSTS_BAD_SSD 0x0020 /* Bad SSD */ +#define BRGPHY_PHY_EXTSTS_BAD_ESD 0x0010 /* Bad ESS */ +#define BRGPHY_PHY_EXTSTS_RX_ER 0x0008 /* RX error */ +#define BRGPHY_PHY_EXTSTS_TX_ER 0x0004 /* TX error */ +#define BRGPHY_PHY_EXTSTS_LOCK_ER 0x0002 /* Lock error */ +#define BRGPHY_PHY_EXTSTS_MLT3_ER 0x0001 /* MLT3 code error */ + +#define BRGPHY_MII_RXERRCNT 0x12 /* RX error counter */ + +#define BRGPHY_MII_FCERRCNT 0x13 /* False carrier sense counter */ +#define BGRPHY_FCERRCNT 0x00FF /* False carrier counter */ + +#define BRGPHY_MII_RXNOCNT 0x14 /* RX not OK counter */ +#define BRGPHY_RXNOCNT_LOCAL 0xFF00 /* Local RX not OK counter */ +#define BRGPHY_RXNOCNT_REMOTE 0x00FF /* Local RX not OK counter */ + +#define BRGPHY_MII_DSP_RW_PORT 0x15 /* DSP coefficient r/w port */ + +#define BRGPHY_MII_DSP_ADDR_REG 0x17 /* DSP coefficient addr register */ +#define BRGPHY_MII_EPHY_PTEST 0x17 /* 5906 PHY register */ + +#define BRGPHY_DSP_TAP_NUMBER_MASK 0x00 +#define BRGPHY_DSP_AGC_A 0x00 +#define BRGPHY_DSP_AGC_B 0x01 +#define BRGPHY_DSP_MSE_PAIR_STATUS 0x02 +#define BRGPHY_DSP_SOFT_DECISION 0x03 +#define BRGPHY_DSP_PHASE_REG 0x04 +#define BRGPHY_DSP_SKEW 0x05 +#define BRGPHY_DSP_POWER_SAVER_UPPER_BOUND 0x06 +#define BRGPHY_DSP_POWER_SAVER_LOWER_BOUND 0x07 +#define BRGPHY_DSP_LAST_ECHO 0x08 +#define BRGPHY_DSP_FREQUENCY 0x09 +#define BRGPHY_DSP_PLL_BANDWIDTH 0x0A +#define BRGPHY_DSP_PLL_PHASE_OFFSET 0x0B + +#define BRGPHYDSP_FILTER_DCOFFSET 0x0C00 +#define BRGPHY_DSP_FILTER_FEXT3 0x0B00 +#define BRGPHY_DSP_FILTER_FEXT2 0x0A00 +#define BRGPHY_DSP_FILTER_FEXT1 0x0900 +#define BRGPHY_DSP_FILTER_FEXT0 0x0800 +#define BRGPHY_DSP_FILTER_NEXT3 0x0700 +#define BRGPHY_DSP_FILTER_NEXT2 0x0600 +#define BRGPHY_DSP_FILTER_NEXT1 0x0500 +#define BRGPHY_DSP_FILTER_NEXT0 0x0400 +#define BRGPHY_DSP_FILTER_ECHO 0x0300 +#define BRGPHY_DSP_FILTER_DFE 0x0200 +#define BRGPHY_DSP_FILTER_FFE 0x0100 + +#define BRGPHY_DSP_CONTROL_ALL_FILTERS 0x1000 + +#define BRGPHY_DSP_SEL_CH_0 0x0000 +#define BRGPHY_DSP_SEL_CH_1 0x2000 +#define BRGPHY_DSP_SEL_CH_2 0x4000 +#define BRGPHY_DSP_SEL_CH_3 0x6000 + +#define BRGPHY_MII_AUXCTL 0x18 /* AUX control */ +#define BRGPHY_AUXCTL_LOW_SQ 0x8000 /* Low squelch */ +#define BRGPHY_AUXCTL_LONG_PKT 0x4000 /* RX long packets */ +#define BRGPHY_AUXCTL_ER_CTL 0x3000 /* Edgerate control */ +#define BRGPHY_AUXCTL_TX_TST 0x0400 /* TX test, always 1 */ +#define BRGPHY_AUXCTL_DIS_PRF 0x0080 /* dis part resp filter */ +#define BRGPHY_AUXCTL_DIAG_MODE 0x0004 /* Diagnostic mode */ + +#define BRGPHY_MII_AUXSTS 0x19 /* AUX status */ +#define BRGPHY_AUXSTS_ACOMP 0x8000 /* Autoneg complete */ +#define BRGPHY_AUXSTS_AN_ACK 0x4000 /* Autoneg complete ack */ +#define BRGPHY_AUXSTS_AN_ACK_D 0x2000 /* Autoneg complete ack detect */ +#define BRGPHY_AUXSTS_AN_NPW 0x1000 /* Autoneg next page wait */ +#define BRGPHY_AUXSTS_AN_RES 0x0700 /* Autoneg HCD */ +#define BRGPHY_AUXSTS_PDF 0x0080 /* Parallel detect. fault */ +#define BRGPHY_AUXSTS_RF 0x0040 /* Remote fault */ +#define BRGPHY_AUXSTS_ANP_R 0x0020 /* Autoneg page received */ +#define BRGPHY_AUXSTS_LP_ANAB 0x0010 /* Link partner autoneg ability */ +#define BRGPHY_AUXSTS_LP_NPAB 0x0008 /* Link partner next page ability */ +#define BRGPHY_AUXSTS_LINK 0x0004 /* Link status */ +#define BRGPHY_AUXSTS_PRR 0x0002 /* Pause resolution-RX */ +#define BRGPHY_AUXSTS_PRT 0x0001 /* Pause resolution-TX */ + +#define BRGPHY_RES_1000FD 0x0700 /* 1000baseT full duplex */ +#define BRGPHY_RES_1000HD 0x0600 /* 1000baseT half duplex */ +#define BRGPHY_RES_100FD 0x0500 /* 100baseT full duplex */ +#define BRGPHY_RES_100T4 0x0400 /* 100baseT4 */ +#define BRGPHY_RES_100HD 0x0300 /* 100baseT half duplex */ +#define BRGPHY_RES_10FD 0x0200 /* 10baseT full duplex */ +#define BRGPHY_RES_10HD 0x0100 /* 10baseT half duplex */ + +#define BRGPHY_MII_ISR 0x1A /* Interrupt status */ +#define BRGPHY_ISR_PSERR 0x4000 /* Pair swap error */ +#define BRGPHY_ISR_MDXI_SC 0x2000 /* MDIX Status Change */ +#define BRGPHY_ISR_HCT 0x1000 /* Counter above 32K */ +#define BRGPHY_ISR_LCT 0x0800 /* All counter below 128 */ +#define BRGPHY_ISR_AN_PR 0x0400 /* Autoneg page received */ +#define BRGPHY_ISR_NO_HDCL 0x0200 /* No HCD Link */ +#define BRGPHY_ISR_NO_HDC 0x0100 /* No HCD */ +#define BRGPHY_ISR_USHDC 0x0080 /* Negotiated Unsupported HCD */ +#define BRGPHY_ISR_SCR_S_ERR 0x0040 /* Scrambler sync error */ +#define BRGPHY_ISR_RRS_CHG 0x0020 /* Remote RX status change */ +#define BRGPHY_ISR_LRS_CHG 0x0010 /* Local RX status change */ +#define BRGPHY_ISR_DUP_CHG 0x0008 /* Duplex mode change */ +#define BRGPHY_ISR_LSP_CHG 0x0004 /* Link speed changed */ +#define BRGPHY_ISR_LNK_CHG 0x0002 /* Link status change */ +#define BRGPHY_ISR_CRCERR 0x0001 /* CRC error */ + +#define BRGPHY_MII_IMR 0x1B /* Interrupt mask */ +#define BRGPHY_IMR_PSERR 0x4000 /* Pair swap error */ +#define BRGPHY_IMR_MDXI_SC 0x2000 /* MDIX Status Change */ +#define BRGPHY_IMR_HCT 0x1000 /* Counter above 32K */ +#define BRGPHY_IMR_LCT 0x0800 /* All counter below 128 */ +#define BRGPHY_IMR_AN_PR 0x0400 /* Autoneg page received */ +#define BRGPHY_IMR_NO_HDCL 0x0200 /* No HCD Link */ +#define BRGPHY_IMR_NO_HDC 0x0100 /* No HCD */ +#define BRGPHY_IMR_USHDC 0x0080 /* Negotiated Unsupported HCD */ +#define BRGPHY_IMR_SCR_S_ERR 0x0040 /* Scrambler sync error */ +#define BRGPHY_IMR_RRS_CHG 0x0020 /* Remote RX status change */ +#define BRGPHY_IMR_LRS_CHG 0x0010 /* Local RX status change */ +#define BRGPHY_IMR_DUP_CHG 0x0008 /* Duplex mode change */ +#define BRGPHY_IMR_LSP_CHG 0x0004 /* Link speed changed */ +#define BRGPHY_IMR_LNK_CHG 0x0002 /* Link status change */ +#define BRGPHY_IMR_CRCERR 0x0001 /* CRC error */ + +/*******************************************************/ +/* Begin: Shared SerDes PHY register definitions */ +/*******************************************************/ + +/* SerDes autoneg is different from copper */ +#define BRGPHY_SERDES_ANAR 0x04 +#define BRGPHY_SERDES_ANAR_FDX 0x0020 +#define BRGPHY_SERDES_ANAR_HDX 0x0040 +#define BRGPHY_SERDES_ANAR_NO_PAUSE (0x0 << 7) +#define BRGPHY_SERDES_ANAR_SYM_PAUSE (0x1 << 7) +#define BRGPHY_SERDES_ANAR_ASYM_PAUSE (0x2 << 7) +#define BRGPHY_SERDES_ANAR_BOTH_PAUSE (0x3 << 7) + +#define BRGPHY_SERDES_ANLPAR 0x05 +#define BRGPHY_SERDES_ANLPAR_FDX 0x0020 +#define BRGPHY_SERDES_ANLPAR_HDX 0x0040 +#define BRGPHY_SERDES_ANLPAR_NO_PAUSE (0x0 << 7) +#define BRGPHY_SERDES_ANLPAR_SYM_PAUSE (0x1 << 7) +#define BRGPHY_SERDES_ANLPAR_ASYM_PAUSE (0x2 << 7) +#define BRGPHY_SERDES_ANLPAR_BOTH_PAUSE (0x3 << 7) + +/*******************************************************/ +/* End: Shared SerDes PHY register definitions */ +/*******************************************************/ + +/*******************************************************/ +/* Begin: PHY register values for the 5706 PHY */ +/*******************************************************/ + +/* + * Shadow register 0x1C, bit 15 is write enable, + * bits 14-10 select function (0x00 to 0x1F). + */ +#define BRGPHY_MII_SHADOW_1C 0x1C +#define BRGPHY_SHADOW_1C_WRITE_EN 0x8000 +#define BRGPHY_SHADOW_1C_SELECT_MASK 0x7C00 + +/* Shadow 0x1C Mode Control Register (select value 0x1F) */ +#define BRGPHY_SHADOW_1C_MODE_CTRL (0x1F << 10) +/* When set, Regs 0-0x0F are 1000X, else 1000T */ +#define BRGPHY_SHADOW_1C_ENA_1000X 0x0001 + +#define BRGPHY_MII_TEST1 0x1E +#define BRGPHY_TEST1_TRIM_EN 0x0010 +#define BRGPHY_TEST1_CRC_EN 0x8000 + +#define BRGPHY_MII_TEST2 0x1F + +/*******************************************************/ +/* End: PHY register values for the 5706 PHY */ +/*******************************************************/ + +/*******************************************************/ +/* Begin: PHY register values for the 5708S SerDes PHY */ +/*******************************************************/ + +/* Autoneg Next Page Transmit 1 Regiser */ +#define BRGPHY_5708S_ANEG_NXT_PG_XMIT1 0x0B +#define BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G 0x0001 + +/* Use the BLOCK_ADDR register to select the page for registers 0x10 to 0x1E */ +#define BRGPHY_5708S_BLOCK_ADDR 0x1f +#define BRGPHY_5708S_DIG_PG0 0x0000 +#define BRGPHY_5708S_DIG3_PG2 0x0002 +#define BRGPHY_5708S_TX_MISC_PG5 0x0005 + +/* 5708S SerDes "Digital" Registers (page 0) */ +#define BRGPHY_5708S_PG0_1000X_CTL1 0x10 +#define BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN 0x0010 +#define BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE 0x0001 + +#define BRGPHY_5708S_PG0_1000X_STAT1 0x14 +#define BRGPHY_5708S_PG0_1000X_STAT1_LINK 0x0002 +#define BRGPHY_5708S_PG0_1000X_STAT1_FDX 0x0004 +#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK 0x0018 +#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10 (0x0 << 3) +#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100 (0x1 << 3) +#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G (0x2 << 3) +#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G (0x3 << 3) + + +#define BRGPHY_5708S_PG0_1000X_CTL2 0x11 +#define BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN 0x0001 + +/* 5708S SerDes "Digital 3" Registers (page 2) */ +#define BRGPHY_5708S_PG2_DIGCTL_3_0 0x10 +#define BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE 0x0001 + +/* 5708S SerDes "TX Misc" Registers (page 5) */ +#define BRGPHY_5708S_PG5_2500STATUS1 0x10 +#define BRGPHY_5708S_PG5_TXACTL1 0x15 +#define BRGPHY_5708S_PG5_TXACTL3 0x17 + +/*******************************************************/ +/* End: PHY register values for the 5708S SerDes PHY */ +/*******************************************************/ + +/*******************************************************/ +/* Begin: PHY register values for the 5709S SerDes PHY */ +/*******************************************************/ + +/* 5709S SerDes "General Purpose Status" Registers */ +#define BRGPHY_BLOCK_ADDR_GP_STATUS 0x8120 +#define BRGPHY_GP_STATUS_TOP_ANEG_STATUS 0x1B +#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK 0x3F00 +#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10 0x0000 +#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100 0x0100 +#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G 0x0200 +#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G 0x0300 +#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1GKX 0x0D00 +#define BRGPHY_GP_STATUS_TOP_ANEG_FDX 0x0008 +#define BRGPHY_GP_STATUS_TOP_ANEG_LINK_UP 0x0004 +#define BRGPHY_GP_STATUS_TOP_ANEG_CL73_COMP 0x0001 + +/* 5709S SerDes "SerDes Digital" Registers */ +#define BRGPHY_BLOCK_ADDR_SERDES_DIG 0x8300 +#define BRGPHY_SERDES_DIG_1000X_CTL1 0x0010 +#define BRGPHY_SD_DIG_1000X_CTL1_AUTODET 0x0010 +#define BRGPHY_SD_DIG_1000X_CTL1_FIBER 0x0001 + +/* 5709S SerDes "Over 1G" Registers */ +#define BRGPHY_BLOCK_ADDR_OVER_1G 0x8320 +#define BRGPHY_OVER_1G_UNFORMAT_PG1 0x19 + +/* 5709S SerDes "Multi-Rate Backplane Ethernet" Registers */ +#define BRGPHY_BLOCK_ADDR_MRBE 0x8350 +#define BRGPHY_MRBE_MSG_PG5_NP 0x10 +#define BRGPHY_MRBE_MSG_PG5_NP_MBRE 0x0001 +#define BRGPHY_MRBE_MSG_PG5_NP_T2 0x0002 + +/* 5709S SerDes "IEEE Clause 73 User B0" Registers */ +#define BRGPHY_BLOCK_ADDR_CL73_USER_B0 0x8370 +#define BRGPHY_CL73_USER_B0_MBRE_CTL1 0x12 +#define BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP 0x2000 +#define BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR 0x4000 +#define BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG 0x8000 + +/* 5709S SerDes "IEEE Clause 73 User B0" Registers */ +#define BRGPHY_BLOCK_ADDR_ADDR_EXT 0xFFD0 + +/* 5709S SerDes "Combo IEEE 0" Registers */ +#define BRGPHY_BLOCK_ADDR_COMBO_IEEE0 0xFFE0 + +#define BRGPHY_ADDR_EXT 0x1E +#define BRGPHY_BLOCK_ADDR 0x1F + +#define BRGPHY_ADDR_EXT_AN_MMD 0x3800 + +/*******************************************************/ +/* End: PHY register values for the 5709S SerDes PHY */ +/*******************************************************/ + +#define BRGPHY_INTRS \ + ~(BRGPHY_IMR_LNK_CHG|BRGPHY_IMR_LSP_CHG|BRGPHY_IMR_DUP_CHG) + +#endif /* _DEV_BRGPHY_MIIREG_HH_ */ diff --git a/freebsd/dev/smc/if_smc.c b/freebsd/dev/smc/if_smc.c new file mode 100644 index 00000000..d943111f --- /dev/null +++ b/freebsd/dev/smc/if_smc.c @@ -0,0 +1,1342 @@ +#include + +/*- + * Copyright (c) 2008 Benno Rice. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +/* + * Driver for SMSC LAN91C111, may work for older variants. + */ + +#ifdef HAVE_KERNEL_OPTION_HEADERS +#include +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#ifdef INET +#include +#include +#include +#include +#endif + +#include +#include + +#include +#include + +#include +#include + +#define SMC_LOCK(sc) mtx_lock(&(sc)->smc_mtx) +#define SMC_UNLOCK(sc) mtx_unlock(&(sc)->smc_mtx) +#define SMC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->smc_mtx, MA_OWNED) + +#define SMC_INTR_PRIORITY 0 +#define SMC_RX_PRIORITY 5 +#define SMC_TX_PRIORITY 10 + +devclass_t smc_devclass; + +static const char *smc_chip_ids[16] = { + NULL, NULL, NULL, + /* 3 */ "SMSC LAN91C90 or LAN91C92", + /* 4 */ "SMSC LAN91C94", + /* 5 */ "SMSC LAN91C95", + /* 6 */ "SMSC LAN91C96", + /* 7 */ "SMSC LAN91C100", + /* 8 */ "SMSC LAN91C100FD", + /* 9 */ "SMSC LAN91C110FD or LAN91C111FD", + NULL, NULL, NULL, + NULL, NULL, NULL +}; + +static void smc_init(void *); +static void smc_start(struct ifnet *); +static void smc_stop(struct smc_softc *); +static int smc_ioctl(struct ifnet *, u_long, caddr_t); + +static void smc_init_locked(struct smc_softc *); +static void smc_start_locked(struct ifnet *); +static void smc_reset(struct smc_softc *); +static int smc_mii_ifmedia_upd(struct ifnet *); +static void smc_mii_ifmedia_sts(struct ifnet *, struct ifmediareq *); +static void smc_mii_tick(void *); +static void smc_mii_mediachg(struct smc_softc *); +static int smc_mii_mediaioctl(struct smc_softc *, struct ifreq *, u_long); + +static void smc_task_intr(void *, int); +static void smc_task_rx(void *, int); +static void smc_task_tx(void *, int); + +static driver_filter_t smc_intr; +static timeout_t smc_watchdog; +#ifdef DEVICE_POLLING +static poll_handler_t smc_poll; +#endif + +static __inline void +smc_select_bank(struct smc_softc *sc, uint16_t bank) +{ + + bus_write_2(sc->smc_reg, BSR, bank & BSR_BANK_MASK); +} + +/* Never call this when not in bank 2. */ +static __inline void +smc_mmu_wait(struct smc_softc *sc) +{ + + KASSERT((bus_read_2(sc->smc_reg, BSR) & + BSR_BANK_MASK) == 2, ("%s: smc_mmu_wait called when not in bank 2", + device_get_nameunit(sc->smc_dev))); + while (bus_read_2(sc->smc_reg, MMUCR) & MMUCR_BUSY) + ; +} + +static __inline uint8_t +smc_read_1(struct smc_softc *sc, bus_addr_t offset) +{ + + return (bus_read_1(sc->smc_reg, offset)); +} + +static __inline void +smc_write_1(struct smc_softc *sc, bus_addr_t offset, uint8_t val) +{ + + bus_write_1(sc->smc_reg, offset, val); +} + +static __inline uint16_t +smc_read_2(struct smc_softc *sc, bus_addr_t offset) +{ + + return (bus_read_2(sc->smc_reg, offset)); +} + +static __inline void +smc_write_2(struct smc_softc *sc, bus_addr_t offset, uint16_t val) +{ + + bus_write_2(sc->smc_reg, offset, val); +} + +static __inline void +smc_read_multi_2(struct smc_softc *sc, bus_addr_t offset, uint16_t *datap, + bus_size_t count) +{ + + bus_read_multi_2(sc->smc_reg, offset, datap, count); +} + +static __inline void +smc_write_multi_2(struct smc_softc *sc, bus_addr_t offset, uint16_t *datap, + bus_size_t count) +{ + + bus_write_multi_2(sc->smc_reg, offset, datap, count); +} + +int +smc_probe(device_t dev) +{ + int rid, type, error; + uint16_t val; + struct smc_softc *sc; + struct resource *reg; + + sc = device_get_softc(dev); + rid = 0; + type = SYS_RES_IOPORT; + error = 0; + + if (sc->smc_usemem) + type = SYS_RES_MEMORY; + + reg = bus_alloc_resource(dev, type, &rid, 0, ~0, 16, RF_ACTIVE); + if (reg == NULL) { + if (bootverbose) + device_printf(dev, + "could not allocate I/O resource for probe\n"); + return (ENXIO); + } + + /* Check for the identification value in the BSR. */ + val = bus_read_2(reg, BSR); + if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) { + if (bootverbose) + device_printf(dev, "identification value not in BSR\n"); + error = ENXIO; + goto done; + } + + /* + * Try switching banks and make sure we still get the identification + * value. + */ + bus_write_2(reg, BSR, 0); + val = bus_read_2(reg, BSR); + if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) { + if (bootverbose) + device_printf(dev, + "identification value not in BSR after write\n"); + error = ENXIO; + goto done; + } + +#if 0 + /* Check the BAR. */ + bus_write_2(reg, BSR, 1); + val = bus_read_2(reg, BAR); + val = BAR_ADDRESS(val); + if (rman_get_start(reg) != val) { + if (bootverbose) + device_printf(dev, "BAR address %x does not match " + "I/O resource address %lx\n", val, + rman_get_start(reg)); + error = ENXIO; + goto done; + } +#endif + + /* Compare REV against known chip revisions. */ + bus_write_2(reg, BSR, 3); + val = bus_read_2(reg, REV); + val = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT; + if (smc_chip_ids[val] == NULL) { + if (bootverbose) + device_printf(dev, "Unknown chip revision: %d\n", val); + error = ENXIO; + goto done; + } + + device_set_desc(dev, smc_chip_ids[val]); + +done: + bus_release_resource(dev, type, rid, reg); + return (error); +} + +int +smc_attach(device_t dev) +{ + int type, error; + uint16_t val; + u_char eaddr[ETHER_ADDR_LEN]; + struct smc_softc *sc; + struct ifnet *ifp; + + sc = device_get_softc(dev); + error = 0; + + sc->smc_dev = dev; + + ifp = sc->smc_ifp = if_alloc(IFT_ETHER); + if (ifp == NULL) { + error = ENOSPC; + goto done; + } + + mtx_init(&sc->smc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); + + /* Set up watchdog callout. */ + callout_init_mtx(&sc->smc_watchdog, &sc->smc_mtx, 0); + + type = SYS_RES_IOPORT; + if (sc->smc_usemem) + type = SYS_RES_MEMORY; + + sc->smc_reg_rid = 0; + sc->smc_reg = bus_alloc_resource(dev, type, &sc->smc_reg_rid, 0, ~0, + 16, RF_ACTIVE); + if (sc->smc_reg == NULL) { + error = ENXIO; + goto done; + } + + sc->smc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->smc_irq_rid, 0, + ~0, 1, RF_ACTIVE | RF_SHAREABLE); + if (sc->smc_irq == NULL) { + error = ENXIO; + goto done; + } + + SMC_LOCK(sc); + smc_reset(sc); + SMC_UNLOCK(sc); + + smc_select_bank(sc, 3); + val = smc_read_2(sc, REV); + sc->smc_chip = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT; + sc->smc_rev = (val * REV_REV_MASK) >> REV_REV_SHIFT; + if (bootverbose) + device_printf(dev, "revision %x\n", sc->smc_rev); + + callout_init_mtx(&sc->smc_mii_tick_ch, &sc->smc_mtx, + CALLOUT_RETURNUNLOCKED); + if (sc->smc_chip >= REV_CHIP_91110FD) { + (void)mii_attach(dev, &sc->smc_miibus, ifp, + smc_mii_ifmedia_upd, smc_mii_ifmedia_sts, BMSR_DEFCAPMASK, + MII_PHY_ANY, MII_OFFSET_ANY, 0); + if (sc->smc_miibus != NULL) { + sc->smc_mii_tick = smc_mii_tick; + sc->smc_mii_mediachg = smc_mii_mediachg; + sc->smc_mii_mediaioctl = smc_mii_mediaioctl; + } + } + + smc_select_bank(sc, 1); + eaddr[0] = smc_read_1(sc, IAR0); + eaddr[1] = smc_read_1(sc, IAR1); + eaddr[2] = smc_read_1(sc, IAR2); + eaddr[3] = smc_read_1(sc, IAR3); + eaddr[4] = smc_read_1(sc, IAR4); + eaddr[5] = smc_read_1(sc, IAR5); + + if_initname(ifp, device_get_name(dev), device_get_unit(dev)); + ifp->if_softc = sc; + ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; + ifp->if_init = smc_init; + ifp->if_ioctl = smc_ioctl; + ifp->if_start = smc_start; + IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); + IFQ_SET_READY(&ifp->if_snd); + + ifp->if_capabilities = ifp->if_capenable = 0; + +#ifdef DEVICE_POLLING + ifp->if_capabilities |= IFCAP_POLLING; +#endif + + ether_ifattach(ifp, eaddr); + + /* Set up taskqueue */ + TASK_INIT(&sc->smc_intr, SMC_INTR_PRIORITY, smc_task_intr, ifp); + TASK_INIT(&sc->smc_rx, SMC_RX_PRIORITY, smc_task_rx, ifp); + TASK_INIT(&sc->smc_tx, SMC_TX_PRIORITY, smc_task_tx, ifp); + sc->smc_tq = taskqueue_create_fast("smc_taskq", M_NOWAIT, + taskqueue_thread_enqueue, &sc->smc_tq); + taskqueue_start_threads(&sc->smc_tq, 1, PI_NET, "%s taskq", + device_get_nameunit(sc->smc_dev)); + + /* Mask all interrupts. */ + sc->smc_mask = 0; + smc_write_1(sc, MSK, 0); + + /* Wire up interrupt */ + error = bus_setup_intr(dev, sc->smc_irq, + INTR_TYPE_NET|INTR_MPSAFE, smc_intr, NULL, sc, &sc->smc_ih); + if (error != 0) + goto done; + +done: + if (error != 0) + smc_detach(dev); + return (error); +} + +int +smc_detach(device_t dev) +{ + int type; + struct smc_softc *sc; + + sc = device_get_softc(dev); + SMC_LOCK(sc); + smc_stop(sc); + SMC_UNLOCK(sc); + + if (sc->smc_ifp != NULL) { + ether_ifdetach(sc->smc_ifp); + } + + callout_drain(&sc->smc_watchdog); + callout_drain(&sc->smc_mii_tick_ch); + +#ifdef DEVICE_POLLING + if (sc->smc_ifp->if_capenable & IFCAP_POLLING) + ether_poll_deregister(sc->smc_ifp); +#endif + + if (sc->smc_ih != NULL) + bus_teardown_intr(sc->smc_dev, sc->smc_irq, sc->smc_ih); + + if (sc->smc_tq != NULL) { + taskqueue_drain(sc->smc_tq, &sc->smc_intr); + taskqueue_drain(sc->smc_tq, &sc->smc_rx); + taskqueue_drain(sc->smc_tq, &sc->smc_tx); + taskqueue_free(sc->smc_tq); + sc->smc_tq = NULL; + } + + if (sc->smc_ifp != NULL) { + if_free(sc->smc_ifp); + } + + if (sc->smc_miibus != NULL) { + device_delete_child(sc->smc_dev, sc->smc_miibus); + bus_generic_detach(sc->smc_dev); + } + + if (sc->smc_reg != NULL) { + type = SYS_RES_IOPORT; + if (sc->smc_usemem) + type = SYS_RES_MEMORY; + + bus_release_resource(sc->smc_dev, type, sc->smc_reg_rid, + sc->smc_reg); + } + + if (sc->smc_irq != NULL) + bus_release_resource(sc->smc_dev, SYS_RES_IRQ, sc->smc_irq_rid, + sc->smc_irq); + + if (mtx_initialized(&sc->smc_mtx)) + mtx_destroy(&sc->smc_mtx); + + return (0); +} + +static void +smc_start(struct ifnet *ifp) +{ + struct smc_softc *sc; + + sc = ifp->if_softc; + SMC_LOCK(sc); + smc_start_locked(ifp); + SMC_UNLOCK(sc); +} + +static void +smc_start_locked(struct ifnet *ifp) +{ + struct smc_softc *sc; + struct mbuf *m; + u_int len, npages, spin_count; + + sc = ifp->if_softc; + SMC_ASSERT_LOCKED(sc); + + if (ifp->if_drv_flags & IFF_DRV_OACTIVE) + return; + if (IFQ_IS_EMPTY(&ifp->if_snd)) + return; + + /* + * Grab the next packet. If it's too big, drop it. + */ + IFQ_DRV_DEQUEUE(&ifp->if_snd, m); + len = m_length(m, NULL); + len += (len & 1); + if (len > ETHER_MAX_LEN - ETHER_CRC_LEN) { + if_printf(ifp, "large packet discarded\n"); + ++ifp->if_oerrors; + m_freem(m); + return; /* XXX readcheck? */ + } + + /* + * Flag that we're busy. + */ + ifp->if_drv_flags |= IFF_DRV_OACTIVE; + sc->smc_pending = m; + + /* + * Work out how many 256 byte "pages" we need. We have to include the + * control data for the packet in this calculation. + */ + npages = (len * PKT_CTRL_DATA_LEN) >> 8; + if (npages == 0) + npages = 1; + + /* + * Request memory. + */ + smc_select_bank(sc, 2); + smc_mmu_wait(sc); + smc_write_2(sc, MMUCR, MMUCR_CMD_TX_ALLOC | npages); + + /* + * Spin briefly to see if the allocation succeeds. + */ + spin_count = TX_ALLOC_WAIT_TIME; + do { + if (smc_read_1(sc, IST) & ALLOC_INT) { + smc_write_1(sc, ACK, ALLOC_INT); + break; + } + } while (--spin_count); + + /* + * If the allocation is taking too long, unmask the alloc interrupt + * and wait. + */ + if (spin_count == 0) { + sc->smc_mask |= ALLOC_INT; + if ((ifp->if_capenable & IFCAP_POLLING) == 0) + smc_write_1(sc, MSK, sc->smc_mask); + return; + } + + taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx); +} + +static void +smc_task_tx(void *context, int pending) +{ + struct ifnet *ifp; + struct smc_softc *sc; + struct mbuf *m, *m0; + u_int packet, len; + uint8_t *data; + + (void)pending; + ifp = (struct ifnet *)context; + sc = ifp->if_softc; + + SMC_LOCK(sc); + + if (sc->smc_pending == NULL) { + SMC_UNLOCK(sc); + goto next_packet; + } + + m = m0 = sc->smc_pending; + sc->smc_pending = NULL; + smc_select_bank(sc, 2); + + /* + * Check the allocation result. + */ + packet = smc_read_1(sc, ARR); + + /* + * If the allocation failed, requeue the packet and retry. + */ + if (packet & ARR_FAILED) { + IFQ_DRV_PREPEND(&ifp->if_snd, m); + ++ifp->if_oerrors; + ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; + smc_start_locked(ifp); + SMC_UNLOCK(sc); + return; + } + + /* + * Tell the device to write to our packet number. + */ + smc_write_1(sc, PNR, packet); + smc_write_2(sc, PTR, 0 | PTR_AUTO_INCR); + + /* + * Tell the device how long the packet is (including control data). + */ + len = m_length(m, 0); + len += PKT_CTRL_DATA_LEN; + smc_write_2(sc, DATA0, 0); + smc_write_2(sc, DATA0, len); + + /* + * Push the data out to the device. + */ + data = NULL; + for (; m != NULL; m = m->m_next) { + data = mtod(m, uint8_t *); + smc_write_multi_2(sc, DATA0, (uint16_t *)data, m->m_len / 2); + } + + /* + * Push out the control byte and and the odd byte if needed. + */ + if ((len & 1) != 0 && data != NULL) + smc_write_2(sc, DATA0, (CTRL_ODD << 8) | data[m->m_len - 1]); + else + smc_write_2(sc, DATA0, 0); + + /* + * Unmask the TX empty interrupt. + */ + sc->smc_mask |= TX_EMPTY_INT; + if ((ifp->if_capenable & IFCAP_POLLING) == 0) + smc_write_1(sc, MSK, sc->smc_mask); + + /* + * Enqueue the packet. + */ + smc_mmu_wait(sc); + smc_write_2(sc, MMUCR, MMUCR_CMD_ENQUEUE); + callout_reset(&sc->smc_watchdog, hz * 2, smc_watchdog, sc); + + /* + * Finish up. + */ + ifp->if_opackets++; + ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; + SMC_UNLOCK(sc); + BPF_MTAP(ifp, m0); + m_freem(m0); + +next_packet: + /* + * See if there's anything else to do. + */ + smc_start(ifp); +} + +static void +smc_task_rx(void *context, int pending) +{ + u_int packet, status, len; + uint8_t *data; + struct ifnet *ifp; + struct smc_softc *sc; + struct mbuf *m, *mhead, *mtail; + + (void)pending; + ifp = (struct ifnet *)context; + sc = ifp->if_softc; + mhead = mtail = NULL; + + SMC_LOCK(sc); + + packet = smc_read_1(sc, FIFO_RX); + while ((packet & FIFO_EMPTY) == 0) { + /* + * Grab an mbuf and attach a cluster. + */ + MGETHDR(m, M_DONTWAIT, MT_DATA); + if (m == NULL) { + break; + } + MCLGET(m, M_DONTWAIT); + if ((m->m_flags & M_EXT) == 0) { + m_freem(m); + break; + } + + /* + * Point to the start of the packet. + */ + smc_select_bank(sc, 2); + smc_write_1(sc, PNR, packet); + smc_write_2(sc, PTR, 0 | PTR_READ | PTR_RCV | PTR_AUTO_INCR); + + /* + * Grab status and packet length. + */ + status = smc_read_2(sc, DATA0); + len = smc_read_2(sc, DATA0) & RX_LEN_MASK; + len -= 6; + if (status & RX_ODDFRM) + len += 1; + + /* + * Check for errors. + */ + if (status & (RX_TOOSHORT | RX_TOOLNG | RX_BADCRC | RX_ALGNERR)) { + smc_mmu_wait(sc); + smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE); + ifp->if_ierrors++; + m_freem(m); + break; + } + + /* + * Set the mbuf up the way we want it. + */ + m->m_pkthdr.rcvif = ifp; + m->m_pkthdr.len = m->m_len = len + 2; /* XXX: Is this right? */ + m_adj(m, ETHER_ALIGN); + + /* + * Pull the packet out of the device. Make sure we're in the + * right bank first as things may have changed while we were + * allocating our mbuf. + */ + smc_select_bank(sc, 2); + smc_write_1(sc, PNR, packet); + smc_write_2(sc, PTR, 4 | PTR_READ | PTR_RCV | PTR_AUTO_INCR); + data = mtod(m, uint8_t *); + smc_read_multi_2(sc, DATA0, (uint16_t *)data, len >> 1); + if (len & 1) { + data += len & ~1; + *data = smc_read_1(sc, DATA0); + } + + /* + * Tell the device we're done. + */ + smc_mmu_wait(sc); + smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE); + if (m == NULL) { + break; + } + + if (mhead == NULL) { + mhead = mtail = m; + m->m_next = NULL; + } else { + mtail->m_next = m; + mtail = m; + } + packet = smc_read_1(sc, FIFO_RX); + } + + sc->smc_mask |= RCV_INT; + if ((ifp->if_capenable & IFCAP_POLLING) == 0) + smc_write_1(sc, MSK, sc->smc_mask); + + SMC_UNLOCK(sc); + + while (mhead != NULL) { + m = mhead; + mhead = mhead->m_next; + m->m_next = NULL; + ifp->if_ipackets++; + (*ifp->if_input)(ifp, m); + } +} + +#ifdef DEVICE_POLLING +static void +smc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) +{ + struct smc_softc *sc; + + sc = ifp->if_softc; + + SMC_LOCK(sc); + if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { + SMC_UNLOCK(sc); + return; + } + SMC_UNLOCK(sc); + + if (cmd == POLL_AND_CHECK_STATUS) + taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_intr); +} +#endif + +static int +smc_intr(void *context) +{ + struct smc_softc *sc; + + sc = (struct smc_softc *)context; + taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_intr); + return (FILTER_HANDLED); +} + +static void +smc_task_intr(void *context, int pending) +{ + struct smc_softc *sc; + struct ifnet *ifp; + u_int status, packet, counter, tcr; + + (void)pending; + ifp = (struct ifnet *)context; + sc = ifp->if_softc; + + SMC_LOCK(sc); + + smc_select_bank(sc, 2); + + /* + * Get the current mask, and then block all interrupts while we're + * working. + */ + if ((ifp->if_capenable & IFCAP_POLLING) == 0) + smc_write_1(sc, MSK, 0); + + /* + * Find out what interrupts are flagged. + */ + status = smc_read_1(sc, IST) & sc->smc_mask; + + /* + * Transmit error + */ + if (status & TX_INT) { + /* + * Kill off the packet if there is one and re-enable transmit. + */ + packet = smc_read_1(sc, FIFO_TX); + if ((packet & FIFO_EMPTY) == 0) { + smc_write_1(sc, PNR, packet); + smc_write_2(sc, PTR, 0 | PTR_READ | + PTR_AUTO_INCR); + tcr = smc_read_2(sc, DATA0); + if ((tcr & EPHSR_TX_SUC) == 0) + device_printf(sc->smc_dev, + "bad packet\n"); + smc_mmu_wait(sc); + smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE_PKT); + + smc_select_bank(sc, 0); + tcr = smc_read_2(sc, TCR); + tcr |= TCR_TXENA | TCR_PAD_EN; + smc_write_2(sc, TCR, tcr); + smc_select_bank(sc, 2); + taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx); + } + + /* + * Ack the interrupt. + */ + smc_write_1(sc, ACK, TX_INT); + } + + /* + * Receive + */ + if (status & RCV_INT) { + smc_write_1(sc, ACK, RCV_INT); + sc->smc_mask &= ~RCV_INT; + taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_rx); + } + + /* + * Allocation + */ + if (status & ALLOC_INT) { + smc_write_1(sc, ACK, ALLOC_INT); + sc->smc_mask &= ~ALLOC_INT; + taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx); + } + + /* + * Receive overrun + */ + if (status & RX_OVRN_INT) { + smc_write_1(sc, ACK, RX_OVRN_INT); + ifp->if_ierrors++; + } + + /* + * Transmit empty + */ + if (status & TX_EMPTY_INT) { + smc_write_1(sc, ACK, TX_EMPTY_INT); + sc->smc_mask &= ~TX_EMPTY_INT; + callout_stop(&sc->smc_watchdog); + + /* + * Update collision stats. + */ + smc_select_bank(sc, 0); + counter = smc_read_2(sc, ECR); + smc_select_bank(sc, 2); + ifp->if_collisions += + (counter & ECR_SNGLCOL_MASK) >> ECR_SNGLCOL_SHIFT; + ifp->if_collisions += + (counter & ECR_MULCOL_MASK) >> ECR_MULCOL_SHIFT; + + /* + * See if there are any packets to transmit. + */ + taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx); + } + + /* + * Update the interrupt mask. + */ + if ((ifp->if_capenable & IFCAP_POLLING) == 0) + smc_write_1(sc, MSK, sc->smc_mask); + + SMC_UNLOCK(sc); +} + +static u_int +smc_mii_readbits(struct smc_softc *sc, int nbits) +{ + u_int mgmt, mask, val; + + SMC_ASSERT_LOCKED(sc); + KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3, + ("%s: smc_mii_readbits called with bank %d (!= 3)", + device_get_nameunit(sc->smc_dev), + smc_read_2(sc, BSR) & BSR_BANK_MASK)); + + /* + * Set up the MGMT (aka MII) register. + */ + mgmt = smc_read_2(sc, MGMT) & ~(MGMT_MCLK | MGMT_MDOE | MGMT_MDO); + smc_write_2(sc, MGMT, mgmt); + + /* + * Read the bits in. + */ + for (mask = 1 << (nbits - 1), val = 0; mask; mask >>= 1) { + if (smc_read_2(sc, MGMT) & MGMT_MDI) + val |= mask; + + smc_write_2(sc, MGMT, mgmt); + DELAY(1); + smc_write_2(sc, MGMT, mgmt | MGMT_MCLK); + DELAY(1); + } + + return (val); +} + +static void +smc_mii_writebits(struct smc_softc *sc, u_int val, int nbits) +{ + u_int mgmt, mask; + + SMC_ASSERT_LOCKED(sc); + KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3, + ("%s: smc_mii_writebits called with bank %d (!= 3)", + device_get_nameunit(sc->smc_dev), + smc_read_2(sc, BSR) & BSR_BANK_MASK)); + + /* + * Set up the MGMT (aka MII) register). + */ + mgmt = smc_read_2(sc, MGMT) & ~(MGMT_MCLK | MGMT_MDOE | MGMT_MDO); + mgmt |= MGMT_MDOE; + + /* + * Push the bits out. + */ + for (mask = 1 << (nbits - 1); mask; mask >>= 1) { + if (val & mask) + mgmt |= MGMT_MDO; + else + mgmt &= ~MGMT_MDO; + + smc_write_2(sc, MGMT, mgmt); + DELAY(1); + smc_write_2(sc, MGMT, mgmt | MGMT_MCLK); + DELAY(1); + } +} + +int +smc_miibus_readreg(device_t dev, int phy, int reg) +{ + struct smc_softc *sc; + int val; + + sc = device_get_softc(dev); + + SMC_LOCK(sc); + + smc_select_bank(sc, 3); + + /* + * Send out the idle pattern. + */ + smc_mii_writebits(sc, 0xffffffff, 32); + + /* + * Start code + read opcode + phy address + phy register + */ + smc_mii_writebits(sc, 6 << 10 | phy << 5 | reg, 14); + + /* + * Turnaround + data + */ + val = smc_mii_readbits(sc, 18); + + /* + * Reset the MDIO interface. + */ + smc_write_2(sc, MGMT, + smc_read_2(sc, MGMT) & ~(MGMT_MCLK | MGMT_MDOE | MGMT_MDO)); + + SMC_UNLOCK(sc); + return (val); +} + +int +smc_miibus_writereg(device_t dev, int phy, int reg, int data) +{ + struct smc_softc *sc; + + sc = device_get_softc(dev); + + SMC_LOCK(sc); + + smc_select_bank(sc, 3); + + /* + * Send idle pattern. + */ + smc_mii_writebits(sc, 0xffffffff, 32); + + /* + * Start code + write opcode + phy address + phy register + turnaround + * + data. + */ + smc_mii_writebits(sc, 5 << 28 | phy << 23 | reg << 18 | 2 << 16 | data, + 32); + + /* + * Reset MDIO interface. + */ + smc_write_2(sc, MGMT, + smc_read_2(sc, MGMT) & ~(MGMT_MCLK | MGMT_MDOE | MGMT_MDO)); + + SMC_UNLOCK(sc); + return (0); +} + +void +smc_miibus_statchg(device_t dev) +{ + struct smc_softc *sc; + struct mii_data *mii; + uint16_t tcr; + + sc = device_get_softc(dev); + mii = device_get_softc(sc->smc_miibus); + + SMC_LOCK(sc); + + smc_select_bank(sc, 0); + tcr = smc_read_2(sc, TCR); + + if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) + tcr |= TCR_SWFDUP; + else + tcr &= ~TCR_SWFDUP; + + smc_write_2(sc, TCR, tcr); + + SMC_UNLOCK(sc); +} + +static int +smc_mii_ifmedia_upd(struct ifnet *ifp) +{ + struct smc_softc *sc; + struct mii_data *mii; + + sc = ifp->if_softc; + if (sc->smc_miibus == NULL) + return (ENXIO); + + mii = device_get_softc(sc->smc_miibus); + return (mii_mediachg(mii)); +} + +static void +smc_mii_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) +{ + struct smc_softc *sc; + struct mii_data *mii; + + sc = ifp->if_softc; + if (sc->smc_miibus == NULL) + return; + + mii = device_get_softc(sc->smc_miibus); + mii_pollstat(mii); + ifmr->ifm_active = mii->mii_media_active; + ifmr->ifm_status = mii->mii_media_status; +} + +static void +smc_mii_tick(void *context) +{ + struct smc_softc *sc; + + sc = (struct smc_softc *)context; + + if (sc->smc_miibus == NULL) + return; + + SMC_UNLOCK(sc); + + mii_tick(device_get_softc(sc->smc_miibus)); + callout_reset(&sc->smc_mii_tick_ch, hz, smc_mii_tick, sc); +} + +static void +smc_mii_mediachg(struct smc_softc *sc) +{ + + if (sc->smc_miibus == NULL) + return; + mii_mediachg(device_get_softc(sc->smc_miibus)); +} + +static int +smc_mii_mediaioctl(struct smc_softc *sc, struct ifreq *ifr, u_long command) +{ + struct mii_data *mii; + + if (sc->smc_miibus == NULL) + return (EINVAL); + + mii = device_get_softc(sc->smc_miibus); + return (ifmedia_ioctl(sc->smc_ifp, ifr, &mii->mii_media, command)); +} + +static void +smc_reset(struct smc_softc *sc) +{ + u_int ctr; + + SMC_ASSERT_LOCKED(sc); + + smc_select_bank(sc, 2); + + /* + * Mask all interrupts. + */ + smc_write_1(sc, MSK, 0); + + /* + * Tell the device to reset. + */ + smc_select_bank(sc, 0); + smc_write_2(sc, RCR, RCR_SOFT_RST); + + /* + * Set up the configuration register. + */ + smc_select_bank(sc, 1); + smc_write_2(sc, CR, CR_EPH_POWER_EN); + DELAY(1); + + /* + * Turn off transmit and receive. + */ + smc_select_bank(sc, 0); + smc_write_2(sc, TCR, 0); + smc_write_2(sc, RCR, 0); + + /* + * Set up the control register. + */ + smc_select_bank(sc, 1); + ctr = smc_read_2(sc, CTR); + ctr |= CTR_LE_ENABLE | CTR_AUTO_RELEASE; + smc_write_2(sc, CTR, ctr); + + /* + * Reset the MMU. + */ + smc_select_bank(sc, 2); + smc_mmu_wait(sc); + smc_write_2(sc, MMUCR, MMUCR_CMD_MMU_RESET); +} + +static void +smc_enable(struct smc_softc *sc) +{ + struct ifnet *ifp; + + SMC_ASSERT_LOCKED(sc); + ifp = sc->smc_ifp; + + /* + * Set up the receive/PHY control register. + */ + smc_select_bank(sc, 0); + smc_write_2(sc, RPCR, RPCR_ANEG | (RPCR_LED_LINK_ANY << RPCR_LSA_SHIFT) + | (RPCR_LED_ACT_ANY << RPCR_LSB_SHIFT)); + + /* + * Set up the transmit and receive control registers. + */ + smc_write_2(sc, TCR, TCR_TXENA | TCR_PAD_EN); + smc_write_2(sc, RCR, RCR_RXEN | RCR_STRIP_CRC); + + /* + * Set up the interrupt mask. + */ + smc_select_bank(sc, 2); + sc->smc_mask = EPH_INT | RX_OVRN_INT | RCV_INT | TX_INT; + if ((ifp->if_capenable & IFCAP_POLLING) != 0) + smc_write_1(sc, MSK, sc->smc_mask); +} + +static void +smc_stop(struct smc_softc *sc) +{ + + SMC_ASSERT_LOCKED(sc); + + /* + * Turn off callouts. + */ + callout_stop(&sc->smc_watchdog); + callout_stop(&sc->smc_mii_tick_ch); + + /* + * Mask all interrupts. + */ + smc_select_bank(sc, 2); + sc->smc_mask = 0; + smc_write_1(sc, MSK, 0); +#ifdef DEVICE_POLLING + ether_poll_deregister(sc->smc_ifp); + sc->smc_ifp->if_capenable &= ~IFCAP_POLLING; + sc->smc_ifp->if_capenable &= ~IFCAP_POLLING_NOCOUNT; +#endif + + /* + * Disable transmit and receive. + */ + smc_select_bank(sc, 0); + smc_write_2(sc, TCR, 0); + smc_write_2(sc, RCR, 0); + + sc->smc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; +} + +static void +smc_watchdog(void *arg) +{ + struct smc_softc *sc; + + sc = (struct smc_softc *)arg; + device_printf(sc->smc_dev, "watchdog timeout\n"); + taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_intr); +} + +static void +smc_init(void *context) +{ + struct smc_softc *sc; + + sc = (struct smc_softc *)context; + SMC_LOCK(sc); + smc_init_locked(sc); + SMC_UNLOCK(sc); +} + +static void +smc_init_locked(struct smc_softc *sc) +{ + struct ifnet *ifp; + + ifp = sc->smc_ifp; + + SMC_ASSERT_LOCKED(sc); + + smc_reset(sc); + smc_enable(sc); + + ifp->if_drv_flags |= IFF_DRV_RUNNING; + ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; + + smc_start_locked(ifp); + + if (sc->smc_mii_tick != NULL) + callout_reset(&sc->smc_mii_tick_ch, hz, sc->smc_mii_tick, sc); + +#ifdef DEVICE_POLLING + SMC_UNLOCK(sc); + ether_poll_register(smc_poll, ifp); + SMC_LOCK(sc); + ifp->if_capenable |= IFCAP_POLLING; + ifp->if_capenable |= IFCAP_POLLING_NOCOUNT; +#endif +} + +static int +smc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) +{ + struct smc_softc *sc; + int error; + + sc = ifp->if_softc; + error = 0; + + switch (cmd) { + case SIOCSIFFLAGS: + if ((ifp->if_flags & IFF_UP) == 0 && + (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { + SMC_LOCK(sc); + smc_stop(sc); + SMC_UNLOCK(sc); + } else { + smc_init(sc); + if (sc->smc_mii_mediachg != NULL) + sc->smc_mii_mediachg(sc); + } + break; + + case SIOCADDMULTI: + case SIOCDELMULTI: + /* XXX + SMC_LOCK(sc); + smc_setmcast(sc); + SMC_UNLOCK(sc); + */ + error = EINVAL; + break; + + case SIOCGIFMEDIA: + case SIOCSIFMEDIA: + if (sc->smc_mii_mediaioctl == NULL) { + error = EINVAL; + break; + } + sc->smc_mii_mediaioctl(sc, (struct ifreq *)data, cmd); + break; + + default: + error = ether_ioctl(ifp, cmd, data); + break; + } + + return (error); +} diff --git a/freebsd/dev/smc/if_smcreg.h b/freebsd/dev/smc/if_smcreg.h new file mode 100644 index 00000000..50af8077 --- /dev/null +++ b/freebsd/dev/smc/if_smcreg.h @@ -0,0 +1,261 @@ +/*- + * Copyright (c) 2006 Benno Rice. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + * + */ + +#ifndef _IF_SMCREG_HH_ +#define _IF_SMCREG_HH_ + +/* All Banks, Offset 0xe: Bank Select Register */ +#define BSR 0xe +#define BSR_BANK_MASK 0x0007 /* Which bank is currently selected */ +#define BSR_IDENTIFY 0x3300 /* Static value for identification */ +#define BSR_IDENTIFY_MASK 0xff00 + +/* Bank 0, Offset 0x0: Transmit Control Register */ +#define TCR 0x0 +#define TCR_TXENA 0x0001 /* Enable/disable transmitter */ +#define TCR_LOOP 0x0002 /* Put the PHY into loopback mode */ +#define TCR_FORCOL 0x0004 /* Force a collision */ +#define TCR_PAD_EN 0x0080 /* Pad TX frames to 64 bytes */ +#define TCR_NOCRC 0x0100 /* Disable/enable CRC */ +#define TCR_MON_CSN 0x0400 /* Monitor carrier signal */ +#define TCR_FDUPLX 0x0800 /* Enable/disable full duplex */ +#define TCR_STP_SQET 0x1000 /* Stop TX on signal quality error */ +#define TCR_EPH_LOOP 0x2000 /* Internal loopback */ +#define TCR_SWFDUP 0x8000 /* Switched full duplex */ + +/* Bank 0, Offset 0x2: EPH Status Register */ +#define EPHSR 0x2 +#define EPHSR_TX_SUC 0x0001 /* Last TX was successful */ +#define EPHSR_SNGLCOL 0x0002 /* Single collision on last TX */ +#define EPHSR_MULCOL 0x0004 /* Multiple collisions on last TX */ +#define EPHSR_LTX_MULT 0x0008 /* Last TX was multicast */ +#define EPHSR_16COL 0x0010 /* 16 collisions on last TX */ +#define EPHSR_SQET 0x0020 /* Signal quality error test */ +#define EPHSR_LTX_BRD 0x0040 /* Last TX was broadcast */ +#define EPHSR_TX_DEFR 0x0080 /* Transmit deferred */ +#define EPHSR_LATCOL 0x0200 /* Late collision on last TX */ +#define EPHSR_LOST_CARR 0x0400 /* Lost carrier sense */ +#define EPHSR_EXC_DEF 0x0800 /* Excessive deferral */ +#define EPHSR_CTR_ROL 0x1000 /* Counter rollover */ +#define EPHSR_LINK_OK 0x4000 /* Inverse of nLNK pin */ +#define EPHSR_TXUNRN 0x8000 /* Transmit underrun */ + +/* Bank 0, Offset 0x4: Receive Control Register */ +#define RCR 0x4 +#define RCR_RX_ABORT 0x0001 /* RX aborted */ +#define RCR_PRMS 0x0002 /* Enable/disable promiscuous mode */ +#define RCR_ALMUL 0x0004 /* Accept all multicast frames */ +#define RCR_RXEN 0x0100 /* Enable/disable receiver */ +#define RCR_STRIP_CRC 0x0200 /* Strip CRC from RX packets */ +#define RCR_ABORT_ENB 0x2000 /* Abort RX on collision */ +#define RCR_FILT_CAR 0x4000 /* Filter leading 12 bits of carrier */ +#define RCR_SOFT_RST 0x8000 /* Software reset */ + +/* Bank 0, Offset 0x6: Counter Register */ +#define ECR 0x6 +#define ECR_SNGLCOL_MASK 0x000f /* Single collisions */ +#define ECR_SNGLCOL_SHIFT 0 +#define ECR_MULCOL_MASK 0x00f0 /* Multiple collisions */ +#define ECR_MULCOL_SHIFT 4 +#define ECR_TX_DEFR_MASK 0x0f00 /* Transmit deferrals */ +#define ECR_TX_DEFR_SHIFT 8 +#define ECR_EXC_DEF_MASK 0xf000 /* Excessive deferrals */ +#define ECR_EXC_DEF_SHIFT 12 + +/* Bank 0, Offset 0x8: Memory Information Register */ +#define MIR 0x8 +#define MIR_SIZE_MASK 0x00ff /* Memory size (2k pages) */ +#define MIR_SIZE_SHIFT 0 +#define MIR_FREE_MASK 0xff00 /* Memory free (2k pages) */ +#define MIR_FREE_SHIFT 8 +#define MIR_PAGE_SIZE 2048 + +/* Bank 0, Offset 0xa: Receive/PHY Control Reigster */ +#define RPCR 0xa +#define RPCR_ANEG 0x0800 /* Put PHY in autonegotiation mode */ +#define RPCR_DPLX 0x1000 /* Put PHY in full-duplex mode */ +#define RPCR_SPEED 0x2000 /* Manual speed selection */ +#define RPCR_LSA_MASK 0x00e0 /* Select LED A function */ +#define RPCR_LSA_SHIFT 5 +#define RPCR_LSB_MASK 0x001c /* Select LED B function */ +#define RPCR_LSB_SHIFT 2 +#define RPCR_LED_LINK_ANY 0x0 /* 10baseT or 100baseTX link detected */ +#define RPCR_LED_LINK_10 0x2 /* 10baseT link detected */ +#define RPCR_LED_LINK_FDX 0x3 /* Full-duplex link detected */ +#define RPCR_LED_LINK_100 0x5 /* 100baseTX link detected */ +#define RPCR_LED_ACT_ANY 0x4 /* TX or RX activity detected */ +#define RPCR_LED_ACT_RX 0x6 /* RX activity detected */ +#define RPCR_LED_ACT_TX 0x7 /* TX activity detected */ + +/* Bank 1, Offset 0x0: Configuration Register */ +#define CR 0x0 +#define CR_EXT_PHY 0x0200 /* Enable/disable external PHY */ +#define CR_GPCNTRL 0x0400 /* Inverse drives nCNTRL pin */ +#define CR_NO_WAIT 0x1000 /* Do not request additional waits */ +#define CR_EPH_POWER_EN 0x8000 /* Disable/enable low power mode */ + +/* Bank 1, Offset 0x2: Base Address Register */ +#define BAR 0x2 +#define BAR_HIGH_MASK 0xe000 +#define BAR_LOW_MASK 0x1f00 +#define BAR_LOW_SHIFT 4 +#define BAR_ADDRESS(val) \ + ((val & BAR_HIGH_MASK) | ((val & BAR_LOW_MASK) >> BAR_LOW_SHIFT)) + +/* Bank 1, Offsets 0x4: Individual Address Registers */ +#define IAR0 0x4 +#define IAR1 0x5 +#define IAR2 0x6 +#define IAR3 0x7 +#define IAR4 0x8 +#define IAR5 0x9 + +/* Bank 1, Offset 0xa: General Purpose Register */ +#define GPR 0xa + +/* Bank 1, Offset 0xc: Control Register */ +#define CTR 0xa +#define CTR_STORE 0x0001 /* Store registers to EEPROM */ +#define CTR_RELOAD 0x0002 /* Reload registers from EEPROM */ +#define CTR_EEPROM_SELECT 0x0004 /* Select registers to store/reload */ +#define CTR_TE_ENABLE 0x0020 /* TX error causes EPH interrupt */ +#define CTR_CR_ENABLE 0x0040 /* Ctr rollover causes EPH interrupt */ +#define CTR_LE_ENABLE 0x0080 /* Link error causes EPH interrupt */ +#define CTR_AUTO_RELEASE 0x0800 /* Automatically release TX packets */ +#define CTR_RCV_BAD 0x4000 /* Receive/discard bad CRC packets */ + +/* Bank 2, Offset 0x0: MMU Command Register */ +#define MMUCR 0x0 +#define MMUCR_BUSY 0x0001 /* MMU is busy */ +#define MMUCR_CMD_NOOP (0<<5) /* No operation */ +#define MMUCR_CMD_TX_ALLOC (1<<5) /* Alloc TX memory (256b chunks) */ +#define MMUCR_CMD_MMU_RESET (2<<5) /* Reset MMU */ +#define MMUCR_CMD_REMOVE (3<<5) /* Remove frame from RX FIFO */ +#define MMUCR_CMD_RELEASE (4<<5) /* Remove and release from RX FIFO */ +#define MMUCR_CMD_RELEASE_PKT (5<<5) /* Release packet specified in PNR */ +#define MMUCR_CMD_ENQUEUE (6<<5) /* Enqueue packet for TX */ +#define MMUCR_CMD_TX_RESET (7<<5) /* Reset TX FIFOs */ + +/* Bank 2, Offset 0x2: Packet Number Register */ +#define PNR 0x2 +#define PNR_MASK 0x3fff + +/* Bank 2, Offset 0x3: Allocation Result Register */ +#define ARR 0x3 +#define ARR_FAILED 0x8000 /* Last allocation request failed */ +#define ARR_MASK 0x3000 + +/* Bank 2, Offset 0x4: FIFO Ports Register */ +#define FIFO_TX 0x4 +#define FIFO_RX 0x5 +#define FIFO_EMPTY 0x80 /* FIFO empty */ +#define FIFO_PACKET_MASK 0x3f /* Packet number mask */ + +/* Bank 2, Offset 0x6: Pointer Register */ +#define PTR 0x6 +#define PTR_MASK 0x07ff /* Address accessible within TX/RX */ +#define PTR_NOT_EMPTY 0x0800 /* Write Data FIFO not empty */ +#define PTR_ETEN 0x1000 /* Enable early TX underrun detection */ +#define PTR_READ 0x2000 /* Set read/write */ +#define PTR_AUTO_INCR 0x4000 /* Auto increment on read/write */ +#define PTR_RCV 0x8000 /* Read/write to/from RX/TX */ + +/* Bank 2, Offset 0x8: Data Registers */ +#define DATA0 0x8 +#define DATA1 0xa + +/* Bank 2, Offset 0xc: Interrupt Status Registers */ +#define IST 0xc /* read only */ +#define ACK 0xc /* write only */ +#define MSK 0xd + +#define RCV_INT 0x0001 /* RX */ +#define TX_INT 0x0002 /* TX */ +#define TX_EMPTY_INT 0x0004 /* TX empty */ +#define ALLOC_INT 0x0008 /* Allocation complete */ +#define RX_OVRN_INT 0x0010 /* RX overrun */ +#define EPH_INT 0x0020 /* EPH interrupt */ +#define ERCV_INT 0x0040 /* Early RX */ +#define MD_INT 0x0080 /* MII */ + +#define IST_PRINTF "\20\01RCV\02TX\03TX_EMPTY\04ALLOC" \ + "\05RX_OVRN\06EPH\07ERCV\10MD" + +/* Bank 3, Offset 0x0: Multicast Table Registers */ +#define MT 0x0 + +/* Bank 3, Offset 0x8: Management Interface */ +#define MGMT 0x8 +#define MGMT_MDO 0x0001 /* MII management output */ +#define MGMT_MDI 0x0002 /* MII management input */ +#define MGMT_MCLK 0x0004 /* MII management clock */ +#define MGMT_MDOE 0x0008 /* MII management output enable */ +#define MGMT_MSK_CRS100 0x4000 /* Disable CRS100 detection during TX */ + +/* Bank 3, Offset 0xa: Revision Register */ +#define REV 0xa +#define REV_CHIP_MASK 0x00f0 /* Chip ID */ +#define REV_CHIP_SHIFT 4 +#define REV_REV_MASK 0x000f /* Revision ID */ +#define REV_REV_SHIFT 0 + +#define REV_CHIP_9192 3 +#define REV_CHIP_9194 4 +#define REV_CHIP_9195 5 +#define REV_CHIP_9196 6 +#define REV_CHIP_91100 7 +#define REV_CHIP_91100FD 8 +#define REV_CHIP_91110FD 9 + +/* Bank 3, Offset 0xc: Early RCV Register */ +#define ERCV 0xc +#define ERCV_THRESHOLD_MASK 0x001f /* ERCV int threshold (64b chunks) */ +#define ERCV_RCV_DISCARD 0x0080 /* Discard packet being received */ + +/* Control Byte */ +#define CTRL_CRC 0x10 /* Frame has CRC */ +#define CTRL_ODD 0x20 /* Frame has odd byte count */ + +/* Receive Frame Status */ +#define RX_MULTCAST 0x0001 /* Frame was multicast */ +#define RX_HASH_MASK 0x007e /* Hash value for multicast */ +#define RX_HASH_SHIFT 1 +#define RX_TOOSHORT 0x0400 /* Frame was too short */ +#define RX_TOOLNG 0x0800 /* Frame was too long */ +#define RX_ODDFRM 0x1000 /* Frame has odd number of bytes */ +#define RX_BADCRC 0x2000 /* Frame failed CRC */ +#define RX_BROADCAST 0x4000 /* Frame was broadcast */ +#define RX_ALGNERR 0x8000 /* Frame had alignment error */ +#define RX_LEN_MASK 0x07ff + +/* Length of status word + byte count + control bytes for packets */ +#define PKT_CTRL_DATA_LEN 6 + +/* Number of times to spin on TX allocations */ +#define TX_ALLOC_WAIT_TIME 1000 + +#endif /* IF_SMCREG_HH_ */ diff --git a/freebsd/dev/smc/if_smcvar.h b/freebsd/dev/smc/if_smcvar.h new file mode 100644 index 00000000..a9e4a668 --- /dev/null +++ b/freebsd/dev/smc/if_smcvar.h @@ -0,0 +1,77 @@ +/*- + * Copyright (c) 2008 Benno Rice. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + * + */ + +#ifndef _IF_SMCVAR_HH_ +#define _IF_SMCVAR_HH_ + +struct smc_softc { + struct ifnet *smc_ifp; + device_t smc_dev; + struct mtx smc_mtx; + u_int smc_chip; + u_int smc_rev; + u_int smc_mask; + + /* Resources */ + int smc_usemem; + int smc_reg_rid; + int smc_irq_rid; + struct resource *smc_reg; + struct resource *smc_irq; + void *smc_ih; + + /* Tasks */ + struct taskqueue *smc_tq; + struct task smc_intr; + struct task smc_rx; + struct task smc_tx; + struct mbuf *smc_pending; + struct callout smc_watchdog; + + /* MII support */ + device_t smc_miibus; + struct callout smc_mii_tick_ch; + void (*smc_mii_tick)(void *); + void (*smc_mii_mediachg)(struct smc_softc *); + int (*smc_mii_mediaioctl)(struct smc_softc *, + struct ifreq *, u_long); + + /* DMA support */ + void (*smc_read_packet)(struct smc_softc *, + bus_addr_t, uint8_t *, bus_size_t); + void *smc_read_arg; +}; + +int smc_probe(device_t); +int smc_attach(device_t); +int smc_detach(device_t); + +int smc_miibus_readreg(device_t, int, int); +int smc_miibus_writereg(device_t, int, int, int); +void smc_miibus_statchg(device_t); + +#endif /* _IF_SMCVAR_HH_ */ diff --git a/freebsd/local/opt_bce.h b/freebsd/local/opt_bce.h new file mode 100644 index 00000000..936ffd88 --- /dev/null +++ b/freebsd/local/opt_bce.h @@ -0,0 +1 @@ +/* EMPTY */