mirror of
https://git.rtems.org/rtems-libbsd/
synced 2025-05-13 06:44:44 +08:00
if_atsam: Optimize transmit
Use the transmit interface handler to avoid a transmit task/interrupt. Use a compile-time constant for the transmit DMA descriptor count to simplify calculations. Update #4652.
This commit is contained in:
Sebastian Huber
parent
3150b37022
commit
6be24bd16a
@ -99,17 +99,11 @@
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#define GMAC_RX_SET_USED_WRAP ((1u << 1) | (1u << 0))
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#define GMAC_RX_SET_WRAP (1u << 1)
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#define GMAC_RX_SET_USED (1u << 0)
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/** TX Defines */
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#define GMAC_TX_SET_EOF (1u << 15)
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#define GMAC_TX_SET_WRAP (1u << 30)
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#define GMAC_TX_SET_USED (1u << 31)
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#define GMAC_DESCRIPTOR_ALIGNMENT 8
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/** Events */
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#define ATSAMV7_ETH_RX_EVENT_INTERRUPT RTEMS_EVENT_1
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#define ATSAMV7_ETH_TX_EVENT_INTERRUPT RTEMS_EVENT_2
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#define ATSAMV7_ETH_START_TRANSMIT_EVENT RTEMS_EVENT_3
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#define ATSAMV7_ETH_RX_DATA_OFFSET 2
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@ -119,9 +113,17 @@
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#define MDIO_RETRIES 10
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#define MDIO_PHY MII_PHY_ANY
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#define RXBUF_COUNT 8
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#define TXBUF_COUNT 64
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#define IGNORE_RX_ERR false
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#define TX_DESC_LOG2 6
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#define TX_DESC_COUNT (1U << TX_DESC_LOG2)
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#define TX_DESC_WRAP(idx) \
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((((idx) + 1) & TX_DESC_COUNT) << (30 - TX_DESC_LOG2))
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RTEMS_STATIC_ASSERT(TX_DESC_WRAP(TX_DESC_COUNT - 1) ==
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GMAC_TX_WRAP_BIT, tx_desc_wrap);
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RTEMS_STATIC_ASSERT(TX_DESC_WRAP(TX_DESC_COUNT - 2) ==
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0, tx_desc_no_wrap);
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/** The PINs for GMAC */
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static const Pin gmacPins[] = { BOARD_GMAC_RUN_PINS };
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@ -131,11 +133,9 @@ typedef struct if_atsam_gmac {
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uint32_t retries;
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} if_atsam_gmac;
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typedef struct ring_buffer {
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unsigned tx_bd_used;
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unsigned tx_bd_free;
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size_t length;
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} ring_buffer;
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struct if_atsam_tx_bds {
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volatile sGmacTxDescriptor bds[TX_DESC_COUNT];
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};
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/*
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* Per-device data
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@ -148,17 +148,16 @@ typedef struct if_atsam_softc {
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struct ifnet *ifp;
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struct mtx mtx;
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if_atsam_gmac Gmac_inst;
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size_t tx_idx_head;
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size_t tx_idx_tail;
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struct if_atsam_tx_bds *tx;
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struct mbuf *tx_mbufs[TX_DESC_COUNT];
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uint8_t GMacAddress[6];
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rtems_id rx_daemon_tid;
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rtems_id tx_daemon_tid;
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rtems_vector_number interrupt_number;
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struct mbuf **rx_mbuf;
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struct mbuf **tx_mbuf;
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volatile sGmacTxDescriptor *tx_bd_base;
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size_t rx_bd_fill_idx;
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size_t amount_rx_buf;
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size_t amount_tx_buf;
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ring_buffer tx_ring;
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struct callout tick_ch;
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/*
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@ -183,12 +182,10 @@ typedef struct if_atsam_softc {
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/* Software */
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uint32_t rx_overrun_errors;
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uint32_t rx_interrupts;
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uint32_t tx_complete_int;
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uint32_t tx_tur_errors;
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uint32_t tx_rlex_errors;
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uint32_t tx_tfc_errors;
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uint32_t tx_hresp_errors;
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uint32_t tx_interrupts;
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/* Hardware */
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uint64_t octets_transm;
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@ -396,55 +393,40 @@ if_atsam_init_phy(if_atsam_gmac *gmac_inst, uint32_t mck,
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static void if_atsam_interrupt_handler(void *arg)
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{
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if_atsam_softc *sc = (if_atsam_softc *)arg;
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uint32_t irq_status_val;
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rtems_event_set rx_event = 0;
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rtems_event_set tx_event = 0;
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Gmac *pHw = sc->Gmac_inst.gGmacd.pHw;
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uint32_t is;
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/* Get interrupt status */
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irq_status_val = GMAC_GetItStatus(pHw, 0);
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is = pHw->GMAC_ISR;
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if (__predict_false((is & GMAC_TX_ERR_BIT) != 0)) {
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if ((is & GMAC_IER_TUR) != 0) {
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++sc->stats.tx_tur_errors;
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}
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if ((is & GMAC_IER_RLEX) != 0) {
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++sc->stats.tx_rlex_errors;
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}
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if ((is & GMAC_IER_TFC) != 0) {
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++sc->stats.tx_tfc_errors;
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}
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if ((is & GMAC_IER_HRESP) != 0) {
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++sc->stats.tx_hresp_errors;
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}
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}
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/* Check receive interrupts */
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if ((irq_status_val & GMAC_IER_ROVR) != 0) {
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++sc->stats.rx_overrun_errors;
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rx_event = ATSAMV7_ETH_RX_EVENT_INTERRUPT;
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}
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if ((irq_status_val & GMAC_IER_RCOMP) != 0) {
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rx_event = ATSAMV7_ETH_RX_EVENT_INTERRUPT;
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}
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/* Send events to receive task and switch off rx interrupts */
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if (rx_event != 0) {
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if (__predict_true((is & (GMAC_IER_ROVR | GMAC_IER_RCOMP)) != 0)) {
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if (__predict_false((is & GMAC_IER_ROVR) != 0)) {
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++sc->stats.rx_overrun_errors;
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}
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++sc->stats.rx_interrupts;
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/* Erase the interrupts for RX completion and errors */
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GMAC_DisableIt(pHw, GMAC_IER_RCOMP | GMAC_IER_ROVR, 0);
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(void)if_atsam_event_send(sc->rx_daemon_tid, rx_event);
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}
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if ((irq_status_val & GMAC_IER_TUR) != 0) {
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++sc->stats.tx_tur_errors;
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tx_event = ATSAMV7_ETH_TX_EVENT_INTERRUPT;
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}
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if ((irq_status_val & GMAC_IER_RLEX) != 0) {
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++sc->stats.tx_rlex_errors;
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tx_event = ATSAMV7_ETH_TX_EVENT_INTERRUPT;
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}
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if ((irq_status_val & GMAC_IER_TFC) != 0) {
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++sc->stats.tx_tfc_errors;
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tx_event = ATSAMV7_ETH_TX_EVENT_INTERRUPT;
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}
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if ((irq_status_val & GMAC_IER_HRESP) != 0) {
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++sc->stats.tx_hresp_errors;
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tx_event = ATSAMV7_ETH_TX_EVENT_INTERRUPT;
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}
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if ((irq_status_val & GMAC_IER_TCOMP) != 0) {
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++sc->stats.tx_complete_int;
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tx_event = ATSAMV7_ETH_TX_EVENT_INTERRUPT;
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}
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/* Send events to transmit task and switch off tx interrupts */
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if (tx_event != 0) {
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++sc->stats.tx_interrupts;
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/* Erase the interrupts for TX completion and errors */
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GMAC_DisableIt(pHw, GMAC_INT_TX_BITS, 0);
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(void)if_atsam_event_send(sc->tx_daemon_tid, tx_event);
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pHw->GMAC_IDR = GMAC_IER_RCOMP | GMAC_IER_ROVR;
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(void)if_atsam_event_send(sc->rx_daemon_tid,
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ATSAMV7_ETH_RX_EVENT_INTERRUPT);
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}
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}
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@ -571,9 +553,6 @@ static void if_atsam_rx_daemon(void *arg)
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sc->ifp->if_input(ifp, m);
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IF_ATSAM_LOCK(sc);
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m = n;
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} else {
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(void)if_atsam_event_send(
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sc->tx_daemon_tid, ATSAMV7_ETH_START_TRANSMIT_EVENT);
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}
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sc->rx_mbuf[sc->rx_bd_fill_idx] = m;
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tmp_rx_bd_address = (uint32_t)m->m_data &
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@ -604,241 +583,169 @@ static void if_atsam_rx_daemon(void *arg)
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}
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}
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/*
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* Update of current transmit buffer position.
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*/
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static void if_atsam_tx_bd_pos_update(size_t *pos, size_t amount_tx_buf)
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static void
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if_atsam_tx_reclaim(struct if_atsam_softc *sc, struct ifnet *ifp)
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{
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*pos = (*pos + 1) % amount_tx_buf;
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}
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uint32_t head_idx;
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uint32_t tail_idx;
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volatile sGmacTxDescriptor *base;
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/*
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* Is RingBuffer empty
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*/
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static bool if_atsam_ring_buffer_empty(ring_buffer *ring_buffer)
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{
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return (ring_buffer->tx_bd_used == ring_buffer->tx_bd_free);
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}
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head_idx = sc->tx_idx_head;
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tail_idx = sc->tx_idx_tail;
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base = &sc->tx->bds[0];
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/*
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* Is RingBuffer full
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*/
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static bool if_atsam_ring_buffer_full(ring_buffer *ring_buffer)
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{
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size_t tx_bd_used_next = ring_buffer->tx_bd_used;
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while (head_idx != tail_idx) {
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uint32_t status;
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ift_counter cnt;
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struct mbuf *m;
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if_atsam_tx_bd_pos_update(&tx_bd_used_next, ring_buffer->length);
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return (tx_bd_used_next == ring_buffer->tx_bd_free);
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}
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status = base[tail_idx].status.val;
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/*
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* Cleanup transmit file descriptors by freeing mbufs which are not needed any
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* longer due to correct transmission.
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*/
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static void if_atsam_tx_bd_cleanup(if_atsam_softc *sc)
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{
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struct mbuf *m;
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volatile sGmacTxDescriptor *cur;
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bool eof_needed = false;
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while (!if_atsam_ring_buffer_empty(&sc->tx_ring)){
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cur = sc->tx_bd_base + sc->tx_ring.tx_bd_free;
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if (((cur->status.bm.bUsed == 1) && !eof_needed) || eof_needed) {
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eof_needed = true;
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cur->status.val |= GMAC_TX_SET_USED;
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m = sc->tx_mbuf[sc->tx_ring.tx_bd_free];
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m_free(m);
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sc->tx_mbuf[sc->tx_ring.tx_bd_free] = 0;
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if_atsam_tx_bd_pos_update(&sc->tx_ring.tx_bd_free,
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sc->tx_ring.length);
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if (cur->status.bm.bLastBuffer) {
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eof_needed = false;
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}
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} else {
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if ((status & GMAC_TX_USED_BIT) == 0) {
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break;
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}
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if (__predict_true((status & GMAC_TX_ERR_BITS) == 0)) {
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cnt = IFCOUNTER_OPACKETS;
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} else {
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cnt = IFCOUNTER_OERRORS;
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}
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while ((m = sc->tx_mbufs[tail_idx]) == NULL ) {
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base[tail_idx].status.val = status | GMAC_TX_USED_BIT;
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tail_idx = (tail_idx + 1) % TX_DESC_COUNT;
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status = base[tail_idx].status.val;
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if (__predict_false((status & GMAC_TX_ERR_BITS) != 0)) {
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cnt = IFCOUNTER_OERRORS;
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}
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}
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base[tail_idx].status.val = status | GMAC_TX_USED_BIT;
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if_inc_counter(ifp, cnt, 1);
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sc->tx_mbufs[tail_idx] = NULL;
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m_freem(m);
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tail_idx = (tail_idx + 1) % TX_DESC_COUNT;
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}
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sc->tx_idx_tail = tail_idx;
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}
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/*
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* Prepare Ethernet frame to start transmission.
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*/
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static bool if_atsam_send_packet(if_atsam_softc *sc, struct mbuf *m)
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static void
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if_atsam_cache_flush(uintptr_t begin, uintptr_t size)
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{
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volatile sGmacTxDescriptor *cur;
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volatile sGmacTxDescriptor *start_packet_tx_bd = 0;
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int pos = 0;
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uint32_t tmp_val = 0;
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Gmac *pHw = sc->Gmac_inst.gGmacd.pHw;
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bool success;
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uintptr_t end;
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uintptr_t mask;
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if_atsam_tx_bd_cleanup(sc);
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/* Wait for interrupt in case no buffer descriptors are available */
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/* Wait for events */
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while (true) {
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if (if_atsam_ring_buffer_full(&sc->tx_ring)) {
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/* Setup the interrupts for TX completion and errors */
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GMAC_EnableIt(pHw, GMAC_INT_TX_BITS, 0);
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success = false;
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break;
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/* Align begin and end of the data to a cache line */
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end = begin + size;
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mask = CPU_CACHE_LINE_BYTES - 1;
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begin &= ~mask;
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end = (end + mask) & ~mask;
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rtems_cache_flush_multiple_data_lines((void *)begin, end - begin);
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}
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static int
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if_atsam_tx_enqueue(struct if_atsam_softc *sc, struct ifnet *ifp, struct mbuf *m)
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{
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size_t head_idx;
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size_t tail_idx;
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size_t capacity;
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size_t idx;
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volatile sGmacTxDescriptor *base;
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volatile sGmacTxDescriptor *desc;
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size_t bufs;
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uint32_t status;
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struct mbuf *n;
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head_idx = sc->tx_idx_head;
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tail_idx = sc->tx_idx_tail;
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capacity = (tail_idx - head_idx - 1) % TX_DESC_COUNT;
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idx = head_idx;
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base = &sc->tx->bds[0];
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bufs = 0;
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n = m;
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do {
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uint32_t size;
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desc = &base[idx];
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size = (uint32_t)n->m_len;
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if (__predict_true(size > 0)) {
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uintptr_t begin;
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++bufs;
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if (__predict_false(bufs > capacity)) {
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return (ENOBUFS);
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}
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begin = mtod(n, uintptr_t);
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desc->addr = (uint32_t)begin;
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status = GMAC_TX_USED_BIT | TX_DESC_WRAP(idx) | size;
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desc->status.val = status;
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if_atsam_cache_flush(begin, size);
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idx = (idx + 1) % TX_DESC_COUNT;
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}
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/*
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* Get current mbuf for data fill
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*/
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cur = &sc->tx_bd_base[sc->tx_ring.tx_bd_used];
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/* Set the transfer data */
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if (m->m_len) {
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uintptr_t cache_adjustment = mtod(m, uintptr_t) % 32;
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n = n->m_next;
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} while (n != NULL);
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rtems_cache_flush_multiple_data_lines(
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mtod(m, const char *) - cache_adjustment,
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(size_t)(m->m_len + cache_adjustment));
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sc->tx_idx_head = idx;
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cur->addr = mtod(m, uint32_t);
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tmp_val = (uint32_t)m->m_len | GMAC_TX_SET_USED;
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if (sc->tx_ring.tx_bd_used == (sc->tx_ring.length - 1)) {
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tmp_val |= GMAC_TX_SET_WRAP;
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}
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if (pos == 0) {
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start_packet_tx_bd = cur;
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}
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sc->tx_mbuf[sc->tx_ring.tx_bd_used] = m;
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m = m->m_next;
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if_atsam_tx_bd_pos_update(&sc->tx_ring.tx_bd_used,
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sc->tx_ring.length);
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} else {
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/* Discard empty mbufs */
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m = m_free(m);
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}
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idx = (idx - 1) % TX_DESC_COUNT;
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desc = &base[idx];
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sc->tx_mbufs[idx] = m;
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status = GMAC_TX_LAST_BUFFER_BIT;
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/*
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* Send out the buffer once the complete mbuf_chain has been
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* processed
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*/
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if (m == NULL) {
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_ARM_Data_synchronization_barrier();
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tmp_val |= GMAC_TX_SET_EOF;
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tmp_val &= ~GMAC_TX_SET_USED;
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cur->status.val = tmp_val;
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start_packet_tx_bd->status.val &= ~GMAC_TX_SET_USED;
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_ARM_Data_synchronization_barrier();
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GMAC_TransmissionStart(pHw);
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success = true;
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break;
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} else {
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if (pos > 0) {
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tmp_val &= ~GMAC_TX_SET_USED;
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}
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pos++;
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cur->status.val = tmp_val;
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}
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while (idx != head_idx) {
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desc->status.val = (desc->status.val & ~GMAC_TX_USED_BIT) |
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status;
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status = 0;
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idx = (idx - 1) % TX_DESC_COUNT;
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desc = &base[idx];
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}
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return success;
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desc->status.val = (desc->status.val & ~GMAC_TX_USED_BIT) | status;
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_ARM_Data_synchronization_barrier();
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sc->Gmac_inst.gGmacd.pHw->GMAC_NCR |= GMAC_NCR_TSTART;
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return (0);
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}
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/*
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* Transmit daemon
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*/
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static void if_atsam_tx_daemon(void *arg)
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static int
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if_atsam_transmit(struct ifnet *ifp, struct mbuf *m)
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{
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||||
if_atsam_softc *sc = (if_atsam_softc *)arg;
|
||||
sGmacTxDescriptor *buffer_desc;
|
||||
int bd_number;
|
||||
void *tx_bd_base;
|
||||
struct mbuf *m;
|
||||
bool success;
|
||||
struct if_atsam_softc *sc;
|
||||
int error;
|
||||
|
||||
sc = ifp->if_softc;
|
||||
IF_ATSAM_LOCK(sc);
|
||||
|
||||
Gmac *pHw = sc->Gmac_inst.gGmacd.pHw;
|
||||
struct ifnet *ifp = sc->ifp;
|
||||
error = if_atsam_tx_enqueue(sc, ifp, m);
|
||||
if_atsam_tx_reclaim(sc, ifp);
|
||||
|
||||
GMAC_TransmitEnable(pHw, 0);
|
||||
if (__predict_false(error != 0)) {
|
||||
struct mbuf *n;
|
||||
|
||||
/* Allocate memory space for priority queue descriptor list */
|
||||
tx_bd_base = rtems_cache_coherent_allocate(sizeof(sGmacTxDescriptor),
|
||||
GMAC_DESCRIPTOR_ALIGNMENT, 0);
|
||||
assert(tx_bd_base != NULL);
|
||||
n = m_defrag(m, M_NOWAIT);
|
||||
if (n != NULL) {
|
||||
m = n;
|
||||
}
|
||||
|
||||
buffer_desc = (sGmacTxDescriptor *)tx_bd_base;
|
||||
buffer_desc->addr = 0;
|
||||
buffer_desc->status.val = GMAC_TX_SET_USED | GMAC_TX_SET_WRAP;
|
||||
|
||||
GMAC_SetTxQueue(pHw, (uint32_t)buffer_desc, 1);
|
||||
GMAC_SetTxQueue(pHw, (uint32_t)buffer_desc, 2);
|
||||
|
||||
/* Allocate memory space for buffer descriptor list */
|
||||
tx_bd_base = rtems_cache_coherent_allocate(
|
||||
sc->amount_tx_buf * sizeof(sGmacTxDescriptor),
|
||||
GMAC_DESCRIPTOR_ALIGNMENT, 0);
|
||||
assert(tx_bd_base != NULL);
|
||||
buffer_desc = (sGmacTxDescriptor *)tx_bd_base;
|
||||
|
||||
/* Create descriptor list and mark as empty */
|
||||
for (bd_number = 0; bd_number < sc->amount_tx_buf; bd_number++) {
|
||||
buffer_desc->addr = 0;
|
||||
buffer_desc->status.val = GMAC_TX_SET_USED;
|
||||
if (bd_number == (sc->amount_tx_buf - 1)) {
|
||||
buffer_desc->status.bm.bWrap = 1;
|
||||
} else {
|
||||
buffer_desc++;
|
||||
error = if_atsam_tx_enqueue(sc, ifp, m);
|
||||
if (error != 0) {
|
||||
m_freem(m);
|
||||
if_inc_counter(ifp, IFCOUNTER_OQDROPS, 1);
|
||||
}
|
||||
}
|
||||
buffer_desc = (sGmacTxDescriptor *)tx_bd_base;
|
||||
|
||||
/* Write Buffer Queue Base Address Register */
|
||||
GMAC_SetTxQueue(pHw, (uint32_t)buffer_desc, 0);
|
||||
|
||||
/* Enable Transmission of data */
|
||||
GMAC_TransmitEnable(pHw, 1);
|
||||
|
||||
/* Set variables in context */
|
||||
sc->tx_bd_base = tx_bd_base;
|
||||
|
||||
while (true) {
|
||||
/* Wait for events */
|
||||
if_atsam_event_receive(sc,
|
||||
ATSAMV7_ETH_START_TRANSMIT_EVENT |
|
||||
ATSAMV7_ETH_TX_EVENT_INTERRUPT);
|
||||
//printf("TX Transmit Event received\n");
|
||||
|
||||
/*
|
||||
* Send packets till queue is empty
|
||||
*/
|
||||
while (true) {
|
||||
/*
|
||||
* Get the mbuf chain to transmit
|
||||
*/
|
||||
if_atsam_tx_bd_cleanup(sc);
|
||||
IF_DEQUEUE(&ifp->if_snd, m);
|
||||
if (!m) {
|
||||
ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
|
||||
break;
|
||||
}
|
||||
success = if_atsam_send_packet(sc, m);
|
||||
if (!success){
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
IF_ATSAM_UNLOCK(sc);
|
||||
return (error);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Send packet (caller provides header).
|
||||
*/
|
||||
static void if_atsam_enet_start(struct ifnet *ifp)
|
||||
{
|
||||
if_atsam_softc *sc = (if_atsam_softc *)ifp->if_softc;
|
||||
|
||||
ifp->if_drv_flags |= IFF_DRV_OACTIVE;
|
||||
if_atsam_event_send(sc->tx_daemon_tid,
|
||||
ATSAMV7_ETH_START_TRANSMIT_EVENT);
|
||||
}
|
||||
|
||||
|
||||
static uint8_t if_atsam_get_gmac_linkspeed_from_media(uint32_t media_subtype)
|
||||
{
|
||||
switch (media_subtype) {
|
||||
@ -959,13 +866,53 @@ if_atsam_tick(void *context)
|
||||
callout_reset(&sc->tick_ch, hz, if_atsam_tick, sc);
|
||||
}
|
||||
|
||||
static void
|
||||
if_atsam_setup_tx(struct if_atsam_softc *sc)
|
||||
{
|
||||
sGmacTxDescriptor *base;
|
||||
struct if_atsam_tx_bds *tx;
|
||||
size_t i;
|
||||
Gmac *pHw;
|
||||
|
||||
pHw = sc->Gmac_inst.gGmacd.pHw;
|
||||
GMAC_TransmitEnable(pHw, 0);
|
||||
|
||||
/* Allocate memory space for priority queue descriptor list */
|
||||
base = rtems_cache_coherent_allocate(sizeof(base),
|
||||
GMAC_DESCRIPTOR_ALIGNMENT, 0);
|
||||
assert(base != NULL);
|
||||
|
||||
base->addr = 0;
|
||||
base->status.val = GMAC_TX_USED_BIT | GMAC_TX_WRAP_BIT;
|
||||
|
||||
GMAC_SetTxQueue(pHw, (uint32_t)base, 1);
|
||||
GMAC_SetTxQueue(pHw, (uint32_t)base, 2);
|
||||
|
||||
/* Allocate memory space for buffer descriptor list */
|
||||
tx = rtems_cache_coherent_allocate(sizeof(*sc->tx),
|
||||
GMAC_DESCRIPTOR_ALIGNMENT, 0);
|
||||
assert(tx != NULL);
|
||||
|
||||
/* Set variables in context */
|
||||
sc->tx = tx;
|
||||
|
||||
/* Create descriptor list and mark as empty */
|
||||
for (i = 0; i < TX_DESC_COUNT; ++i) {
|
||||
tx->bds[i].addr = 0;
|
||||
tx->bds[i].status.val = GMAC_TX_USED_BIT | TX_DESC_WRAP(i);
|
||||
}
|
||||
|
||||
/* Write Buffer Queue Base Address Register */
|
||||
GMAC_SetTxQueue(pHw, (uint32_t)&tx->bds[0], 0);
|
||||
|
||||
/* Enable Transmission of data */
|
||||
GMAC_TransmitEnable(pHw, 1);
|
||||
}
|
||||
|
||||
static void
|
||||
if_atsam_init(if_atsam_softc *sc)
|
||||
{
|
||||
rtems_status_code status;
|
||||
|
||||
struct ifnet *ifp = sc->ifp;
|
||||
uint32_t dmac_cfg = 0;
|
||||
|
||||
sc->interrupt_number = GMAC_IRQn;
|
||||
@ -1001,9 +948,7 @@ if_atsam_init(if_atsam_softc *sc)
|
||||
* Allocate mbuf pointers
|
||||
*/
|
||||
sc->rx_mbuf = malloc(sc->amount_rx_buf * sizeof *sc->rx_mbuf,
|
||||
M_TEMP, M_NOWAIT);
|
||||
sc->tx_mbuf = malloc(sc->amount_tx_buf * sizeof *sc->tx_mbuf,
|
||||
M_TEMP, M_NOWAIT);
|
||||
M_TEMP, M_WAITOK | M_ZERO);
|
||||
|
||||
/* Install interrupt handler */
|
||||
status = rtems_interrupt_handler_install(sc->interrupt_number,
|
||||
@ -1018,10 +963,10 @@ if_atsam_init(if_atsam_softc *sc)
|
||||
*/
|
||||
sc->rx_daemon_tid = rtems_bsdnet_newproc("SCrx", 4096,
|
||||
if_atsam_rx_daemon, sc);
|
||||
sc->tx_daemon_tid = rtems_bsdnet_newproc("SCtx", 4096,
|
||||
if_atsam_tx_daemon, sc);
|
||||
|
||||
callout_reset(&sc->tick_ch, hz, if_atsam_tick, sc);
|
||||
|
||||
if_atsam_setup_tx(sc);
|
||||
}
|
||||
|
||||
static int
|
||||
@ -1221,9 +1166,6 @@ if_atsam_add_sysctls(device_t dev)
|
||||
SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_interrupts",
|
||||
CTLFLAG_RD, &sc->stats.rx_interrupts, 0,
|
||||
"Rx interrupts");
|
||||
SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_complete_int",
|
||||
CTLFLAG_RD, &sc->stats.tx_complete_int, 0,
|
||||
"Tx complete interrupts");
|
||||
SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_tur_errors",
|
||||
CTLFLAG_RD, &sc->stats.tx_tur_errors, 0,
|
||||
"Error Tur Tx interrupts");
|
||||
@ -1236,9 +1178,6 @@ if_atsam_add_sysctls(device_t dev)
|
||||
SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_hresp_errors",
|
||||
CTLFLAG_RD, &sc->stats.tx_hresp_errors, 0,
|
||||
"Error Hresp Tx interrupts");
|
||||
SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_interrupts",
|
||||
CTLFLAG_RD, &sc->stats.tx_interrupts, 0,
|
||||
"Tx interrupts");
|
||||
|
||||
tree = SYSCTL_ADD_NODE(ctx, statsnode, OID_AUTO, "hw", CTLFLAG_RD,
|
||||
NULL, "if_atsam hardware statistics");
|
||||
@ -1479,11 +1418,6 @@ static int if_atsam_driver_attach(device_t dev)
|
||||
memcpy(sc->GMacAddress, eaddr, ETHER_ADDR_LEN);
|
||||
|
||||
sc->amount_rx_buf = RXBUF_COUNT;
|
||||
sc->amount_tx_buf = TXBUF_COUNT;
|
||||
|
||||
sc->tx_ring.tx_bd_used = 0;
|
||||
sc->tx_ring.tx_bd_free = 0;
|
||||
sc->tx_ring.length = sc->amount_tx_buf;
|
||||
|
||||
/* Set Initial Link Speed */
|
||||
sc->link_speed = GMAC_SPEED_100M;
|
||||
@ -1529,16 +1463,18 @@ static int if_atsam_driver_attach(device_t dev)
|
||||
if_initname(ifp, device_get_name(dev), device_get_unit(dev));
|
||||
ifp->if_init = if_atsam_start;
|
||||
ifp->if_ioctl = if_atsam_ioctl;
|
||||
ifp->if_start = if_atsam_enet_start;
|
||||
ifp->if_transmit = if_atsam_transmit;
|
||||
ifp->if_qflush = if_qflush;
|
||||
ifp->if_flags = IFF_BROADCAST | IFF_MULTICAST | IFF_SIMPLEX;
|
||||
ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6 |
|
||||
IFCAP_VLAN_HWCSUM;
|
||||
ifp->if_capenable = ifp->if_capabilities;
|
||||
ifp->if_hwassist = CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP |
|
||||
CSUM_IP6_UDP | CSUM_IP6_TCP;
|
||||
IFQ_SET_MAXLEN(&ifp->if_snd, TXBUF_COUNT - 1);
|
||||
ifp->if_snd.ifq_drv_maxlen = TXBUF_COUNT - 1;
|
||||
IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1);
|
||||
ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1;
|
||||
IFQ_SET_READY(&ifp->if_snd);
|
||||
ifp->if_hdrlen = sizeof(struct ether_vlan_header);
|
||||
|
||||
/*
|
||||
* Attach the interface
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user