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freebsd/if_cpsw: Import.
This commit is contained in:
Christian Mauderer
committed by
Sebastian Huber
Sebastian Huber
parent
d7c7d6e256
commit
736d651892
2991
freebsd/sys/arm/ti/cpsw/if_cpsw.c
Normal file
2991
freebsd/sys/arm/ti/cpsw/if_cpsw.c
Normal file
File diff suppressed because it is too large
Load Diff
210
freebsd/sys/arm/ti/cpsw/if_cpswreg.h
Normal file
210
freebsd/sys/arm/ti/cpsw/if_cpswreg.h
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@@ -0,0 +1,210 @@
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
|
||||
* are met:
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||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
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||||
*
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||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _IF_CPSWREG_H
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#define _IF_CPSWREG_H
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#define CPSW_SS_OFFSET 0x0000
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#define CPSW_SS_IDVER (CPSW_SS_OFFSET + 0x00)
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#define CPSW_SS_SOFT_RESET (CPSW_SS_OFFSET + 0x08)
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#define CPSW_SS_STAT_PORT_EN (CPSW_SS_OFFSET + 0x0C)
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#define CPSW_SS_PTYPE (CPSW_SS_OFFSET + 0x10)
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#define CPSW_SS_FLOW_CONTROL (CPSW_SS_OFFSET + 0x24)
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#define CPSW_PORT_OFFSET 0x0100
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#define CPSW_PORT_P_MAX_BLKS(p) (CPSW_PORT_OFFSET + 0x08 + ((p) * 0x100))
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#define CPSW_PORT_P_BLK_CNT(p) (CPSW_PORT_OFFSET + 0x0C + ((p) * 0x100))
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#define CPSW_PORT_P_VLAN(p) (CPSW_PORT_OFFSET + 0x14 + ((p) * 0x100))
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#define CPSW_PORT_P_TX_PRI_MAP(p) (CPSW_PORT_OFFSET + 0x118 + ((p-1) * 0x100))
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#define CPSW_PORT_P0_CPDMA_TX_PRI_MAP (CPSW_PORT_OFFSET + 0x01C)
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#define CPSW_PORT_P0_CPDMA_RX_CH_MAP (CPSW_PORT_OFFSET + 0x020)
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#define CPSW_PORT_P_SA_LO(p) (CPSW_PORT_OFFSET + 0x120 + ((p-1) * 0x100))
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#define CPSW_PORT_P_SA_HI(p) (CPSW_PORT_OFFSET + 0x124 + ((p-1) * 0x100))
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#define CPSW_CPDMA_OFFSET 0x0800
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#define CPSW_CPDMA_TX_CONTROL (CPSW_CPDMA_OFFSET + 0x04)
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#define CPSW_CPDMA_TX_TEARDOWN (CPSW_CPDMA_OFFSET + 0x08)
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#define CPSW_CPDMA_RX_CONTROL (CPSW_CPDMA_OFFSET + 0x14)
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#define CPSW_CPDMA_RX_TEARDOWN (CPSW_CPDMA_OFFSET + 0x18)
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#define CPSW_CPDMA_SOFT_RESET (CPSW_CPDMA_OFFSET + 0x1c)
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#define CPSW_CPDMA_DMACONTROL (CPSW_CPDMA_OFFSET + 0x20)
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#define CPSW_CPDMA_DMASTATUS (CPSW_CPDMA_OFFSET + 0x24)
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#define CPSW_CPDMA_RX_BUFFER_OFFSET (CPSW_CPDMA_OFFSET + 0x28)
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#define CPSW_CPDMA_TX_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0x80)
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#define CPSW_CPDMA_TX_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0x84)
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#define CPSW_CPDMA_TX_INTMASK_SET (CPSW_CPDMA_OFFSET + 0x88)
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#define CPSW_CPDMA_TX_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0x8C)
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#define CPSW_CPDMA_CPDMA_EOI_VECTOR (CPSW_CPDMA_OFFSET + 0x94)
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#define CPSW_CPDMA_RX_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0xA0)
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#define CPSW_CPDMA_RX_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0xA4)
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#define CPSW_CPDMA_RX_INTMASK_SET (CPSW_CPDMA_OFFSET + 0xA8)
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#define CPSW_CPDMA_RX_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0xAc)
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#define CPSW_CPDMA_RX_INT_THRESH(_ch) (1 << (8 + ((_ch) & 7)))
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#define CPSW_CPDMA_RX_INT(_ch) (1 << (0 + ((_ch) & 7)))
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#define CPSW_CPDMA_DMA_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0xB0)
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#define CPSW_CPDMA_DMA_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0xB4)
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#define CPSW_CPDMA_DMA_INTMASK_SET (CPSW_CPDMA_OFFSET + 0xB8)
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#define CPSW_CPDMA_DMA_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0xBC)
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#define CPSW_CPDMA_RX_PENDTHRESH(p) (CPSW_CPDMA_OFFSET + 0x0c0 + ((p) * 0x04))
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#define CPSW_CPDMA_RX_FREEBUFFER(p) (CPSW_CPDMA_OFFSET + 0x0e0 + ((p) * 0x04))
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#define CPSW_STATS_OFFSET 0x0900
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#define CPSW_STATERAM_OFFSET 0x0A00
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#define CPSW_CPDMA_TX_HDP(p) (CPSW_STATERAM_OFFSET + 0x00 + ((p) * 0x04))
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#define CPSW_CPDMA_RX_HDP(p) (CPSW_STATERAM_OFFSET + 0x20 + ((p) * 0x04))
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#define CPSW_CPDMA_TX_CP(p) (CPSW_STATERAM_OFFSET + 0x40 + ((p) * 0x04))
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#define CPSW_CPDMA_RX_CP(p) (CPSW_STATERAM_OFFSET + 0x60 + ((p) * 0x04))
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#define CPSW_CPTS_OFFSET 0x0C00
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#define CPSW_ALE_OFFSET 0x0D00
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#define CPSW_ALE_CONTROL (CPSW_ALE_OFFSET + 0x08)
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#define CPSW_ALE_CTL_ENABLE (1U << 31)
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#define CPSW_ALE_CTL_CLEAR_TBL (1 << 30)
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#define CPSW_ALE_CTL_BYPASS (1 << 4)
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#define CPSW_ALE_CTL_VLAN_AWARE (1 << 2)
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#define CPSW_ALE_TBLCTL (CPSW_ALE_OFFSET + 0x20)
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#define CPSW_ALE_TBLW2 (CPSW_ALE_OFFSET + 0x34)
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#define CPSW_ALE_TBLW1 (CPSW_ALE_OFFSET + 0x38)
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#define CPSW_ALE_TBLW0 (CPSW_ALE_OFFSET + 0x3C)
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#define ALE_MCAST(_a) ((_a[1] >> 8) & 1)
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#define ALE_MCAST_FWD (3 << 30)
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#define ALE_PORTS(_a) ((_a[2] >> 2) & 7)
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#define ALE_TYPE(_a) ((_a[1] >> 28) & 3)
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#define ALE_TYPE_ADDR 1
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#define ALE_TYPE_VLAN 2
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#define ALE_TYPE_VLAN_ADDR 3
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#define ALE_VLAN(_a) ((_a[1] >> 16) & 0xfff)
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#define ALE_VLAN_UNREGFLOOD(_a) ((_a[0] >> 8) & 7)
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#define ALE_VLAN_REGFLOOD(_a) ((_a[0] >> 16) & 7)
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#define ALE_VLAN_UNTAG(_a) ((_a[0] >> 24) & 7)
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#define ALE_VLAN_MEMBERS(_a) (_a[0] & 7)
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#define CPSW_ALE_PORTCTL(p) (CPSW_ALE_OFFSET + 0x40 + ((p) * 0x04))
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#define ALE_PORTCTL_NO_SA_UPDATE (1 << 5)
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#define ALE_PORTCTL_NO_LEARN (1 << 4)
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#define ALE_PORTCTL_INGRESS (1 << 3)
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#define ALE_PORTCTL_DROP_UNTAGGED (1 << 2)
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#define ALE_PORTCTL_FORWARD 3
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#define ALE_PORTCTL_LEARN 2
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#define ALE_PORTCTL_BLOCKED 1
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#define ALE_PORTCTL_DISABLED 0
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/* SL1 is at 0x0D80, SL2 is at 0x0DC0 */
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#define CPSW_SL_OFFSET 0x0D80
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#define CPSW_SL_MACCONTROL(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x04)
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#define CPSW_SL_MACTL_IFCTL_B (1 << 16)
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#define CPSW_SL_MACTL_IFCTL_A (1 << 15)
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#define CPSW_SL_MACTL_GIG (1 << 7)
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#define CPSW_SL_MACTL_GMII_ENABLE (1 << 5)
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#define CPSW_SL_MACTL_FULLDUPLEX (1 << 0)
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#define CPSW_SL_MACSTATUS(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x08)
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#define CPSW_SL_SOFT_RESET(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x0C)
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#define CPSW_SL_RX_MAXLEN(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x10)
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#define CPSW_SL_RX_PAUSE(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x18)
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#define CPSW_SL_TX_PAUSE(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x1C)
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#define CPSW_SL_RX_PRI_MAP(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x24)
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#define MDIO_OFFSET 0x1000
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#define MDIOCONTROL (MDIO_OFFSET + 0x04)
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#define MDIOCTL_ENABLE (1 << 30)
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#define MDIOCTL_FAULTENB (1 << 18)
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#define MDIOLINKINTRAW (MDIO_OFFSET + 0x10)
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#define MDIOLINKINTMASKED (MDIO_OFFSET + 0x14)
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#define MDIOUSERACCESS0 (MDIO_OFFSET + 0x80)
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#define MDIOUSERPHYSEL0 (MDIO_OFFSET + 0x84)
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#define MDIOUSERACCESS1 (MDIO_OFFSET + 0x88)
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#define MDIOUSERPHYSEL1 (MDIO_OFFSET + 0x8C)
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#define MDIO_PHYSEL_LINKINTENB (1 << 6)
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#define MDIO_PHYACCESS_GO (1U << 31)
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#define MDIO_PHYACCESS_WRITE (1 << 30)
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#define MDIO_PHYACCESS_ACK (1 << 29)
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#define CPSW_WR_OFFSET 0x1200
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#define CPSW_WR_SOFT_RESET (CPSW_WR_OFFSET + 0x04)
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#define CPSW_WR_CONTROL (CPSW_WR_OFFSET + 0x08)
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#define CPSW_WR_INT_CONTROL (CPSW_WR_OFFSET + 0x0c)
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#define CPSW_WR_INT_C0_RX_PULSE (1 << 16)
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#define CPSW_WR_INT_C0_TX_PULSE (1 << 17)
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#define CPSW_WR_INT_C1_RX_PULSE (1 << 18)
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#define CPSW_WR_INT_C1_TX_PULSE (1 << 19)
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#define CPSW_WR_INT_C2_RX_PULSE (1 << 20)
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#define CPSW_WR_INT_C2_TX_PULSE (1 << 21)
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#define CPSW_WR_INT_PACE_EN \
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(CPSW_WR_INT_C0_RX_PULSE | CPSW_WR_INT_C0_TX_PULSE | \
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CPSW_WR_INT_C1_RX_PULSE | CPSW_WR_INT_C1_TX_PULSE | \
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CPSW_WR_INT_C2_RX_PULSE | CPSW_WR_INT_C2_TX_PULSE)
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#define CPSW_WR_INT_PRESCALE_MASK 0xfff
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#define CPSW_WR_C_RX_THRESH_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x10)
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#define CPSW_WR_C_RX_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x14)
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#define CPSW_WR_C_TX_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x18)
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#define CPSW_WR_C_MISC_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x1C)
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#define CPSW_WR_C_RX_THRESH_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x40)
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#define CPSW_WR_C_RX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x44)
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#define CPSW_WR_C_TX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x48)
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#define CPSW_WR_C_MISC_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x4C)
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#define CPSW_WR_C_MISC_EVNT_PEND (1 << 4)
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#define CPSW_WR_C_MISC_STAT_PEND (1 << 3)
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#define CPSW_WR_C_MISC_HOST_PEND (1 << 2)
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#define CPSW_WR_C_MISC_MDIOLINK (1 << 1)
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#define CPSW_WR_C_MISC_MDIOUSER (1 << 0)
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#define CPSW_WR_C_RX_IMAX(p) (CPSW_WR_OFFSET + (0x08 * (p)) + 0x70)
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#define CPSW_WR_C_TX_IMAX(p) (CPSW_WR_OFFSET + (0x08 * (p)) + 0x74)
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#define CPSW_WR_C_IMAX_MASK 0x3f
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#define CPSW_WR_C_IMAX_MAX 63
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#define CPSW_WR_C_IMAX_MIN 2
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#define CPSW_WR_C_IMAX_US_MAX 500
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#define CPSW_WR_C_IMAX_US_MIN 16
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#define CPSW_CPPI_RAM_OFFSET 0x2000
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#define CPSW_CPPI_RAM_SIZE 0x2000
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#define CPSW_MEMWINDOW_SIZE 0x4000
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#define CPDMA_BD_SOP (1 << 15)
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#define CPDMA_BD_EOP (1 << 14)
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#define CPDMA_BD_OWNER (1 << 13)
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#define CPDMA_BD_EOQ (1 << 12)
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#define CPDMA_BD_TDOWNCMPLT (1 << 11)
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#define CPDMA_BD_PASS_CRC (1 << 10)
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#define CPDMA_BD_PKT_ERR_MASK (3 << 4)
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#define CPDMA_BD_TO_PORT (1 << 4)
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#define CPDMA_BD_PORT_MASK 3
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struct cpsw_cpdma_bd {
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volatile uint32_t next;
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volatile uint32_t bufptr;
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volatile uint16_t buflen;
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volatile uint16_t bufoff;
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volatile uint16_t pktlen;
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volatile uint16_t flags;
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};
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#endif /*_IF_CPSWREG_H */
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151
freebsd/sys/arm/ti/cpsw/if_cpswvar.h
Normal file
151
freebsd/sys/arm/ti/cpsw/if_cpswvar.h
Normal file
@@ -0,0 +1,151 @@
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
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* All rights reserved.
|
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*
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
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* $FreeBSD$
|
||||
*/
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#ifndef _IF_CPSWVAR_H
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#define _IF_CPSWVAR_H
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#define CPSW_PORTS 2
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#define CPSW_INTR_COUNT 4
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/* MII BUS */
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#define CPSW_MIIBUS_RETRIES 20
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#define CPSW_MIIBUS_DELAY 100
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#define CPSW_MAX_ALE_ENTRIES 1024
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#define CPSW_SYSCTL_COUNT 34
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#ifdef CPSW_ETHERSWITCH
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#define CPSW_CPU_PORT 0
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#define CPSW_PORTS_MASK 0x7
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#define CPSW_VLANS 128 /* Arbitrary number. */
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struct cpsw_vlangroups {
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int vid;
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};
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#endif
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struct cpsw_slot {
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uint32_t bd_offset; /* Offset of corresponding BD within CPPI RAM. */
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bus_dmamap_t dmamap;
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struct ifnet *ifp;
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struct mbuf *mbuf;
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STAILQ_ENTRY(cpsw_slot) next;
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};
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STAILQ_HEAD(cpsw_slots, cpsw_slot);
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struct cpsw_queue {
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struct mtx lock;
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int running;
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int teardown;
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struct cpsw_slots active;
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struct cpsw_slots avail;
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uint32_t queue_adds; /* total bufs added */
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uint32_t queue_removes; /* total bufs removed */
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uint32_t queue_removes_at_last_tick; /* Used by watchdog */
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uint32_t queue_restart;
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int queue_slots;
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int active_queue_len;
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int max_active_queue_len;
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int avail_queue_len;
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int max_avail_queue_len;
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int longest_chain; /* Largest # segments in a single packet. */
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int hdp_offset;
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};
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struct cpsw_port {
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device_t dev;
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int phy;
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int vlan;
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};
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struct cpsw_softc {
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device_t dev;
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int active_slave;
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int debug;
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int dualemac;
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phandle_t node;
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struct bintime attach_uptime; /* system uptime when attach happened. */
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struct cpsw_port port[2];
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unsigned coal_us;
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/* RX and TX buffer tracking */
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struct cpsw_queue rx, tx;
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/* We expect 1 memory resource and 4 interrupts from the device tree. */
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int mem_rid;
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struct resource *mem_res;
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struct resource *irq_res[CPSW_INTR_COUNT];
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void *ih_cookie[CPSW_INTR_COUNT];
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/* A buffer full of nulls for TX padding. */
|
||||
void *nullpad;
|
||||
|
||||
bus_dma_tag_t mbuf_dtag;
|
||||
|
||||
struct {
|
||||
int resets;
|
||||
int timer;
|
||||
struct callout callout;
|
||||
} watchdog;
|
||||
|
||||
/* 64-bit versions of 32-bit hardware statistics counters */
|
||||
uint64_t shadow_stats[CPSW_SYSCTL_COUNT];
|
||||
|
||||
/* CPPI STATERAM has 512 slots for building TX/RX queues. */
|
||||
/* TODO: Size here supposedly varies with different versions
|
||||
of the controller. Check DaVinci specs and find a good
|
||||
way to adjust this. One option is to have a separate
|
||||
Device Tree parameter for number slots; another option
|
||||
is to calculate it from the memory size in the device tree. */
|
||||
struct cpsw_slot _slots[CPSW_CPPI_RAM_SIZE / sizeof(struct cpsw_cpdma_bd)];
|
||||
struct cpsw_slots avail;
|
||||
};
|
||||
|
||||
struct cpswp_softc {
|
||||
device_t dev;
|
||||
device_t miibus;
|
||||
device_t pdev;
|
||||
int media_status;
|
||||
int unit;
|
||||
int vlan;
|
||||
struct bintime init_uptime; /* system uptime when init happened. */
|
||||
struct callout mii_callout;
|
||||
struct cpsw_softc *swsc;
|
||||
struct ifnet *ifp;
|
||||
struct mii_data *mii;
|
||||
struct mtx lock;
|
||||
uint32_t if_flags;
|
||||
uint32_t phy;
|
||||
uint32_t phyaccess;
|
||||
uint32_t physel;
|
||||
};
|
||||
|
||||
#endif /*_IF_CPSWVAR_H */
|
||||
Reference in New Issue
Block a user