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imx6_ccm: Import from FreeBSD

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Update #3869.
This commit is contained in:
Sebastian Huber
2019-02-08 12:02:05 +01:00
committed by Christian Mauderer
parent bd7af5fcee
commit 7bafcafd9b
6 changed files with 969 additions and 0 deletions
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193
freebsd/sys/arm/freescale/imx/imx6_anatopreg.h Normal file
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/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef IMX6_ANATOPREG_H
#define IMX6_ANATOPREG_H
#define IMX6_ANALOG_CCM_PLL_ARM 0x000
#define IMX6_ANALOG_CCM_PLL_ARM_SET 0x004
#define IMX6_ANALOG_CCM_PLL_ARM_CLR 0x008
#define IMX6_ANALOG_CCM_PLL_ARM_TOG 0x00C
#define IMX6_ANALOG_CCM_PLL_ARM_DIV_MASK 0x7F
#define IMX6_ANALOG_CCM_PLL_ARM_LOCK (1U << 31)
#define IMX6_ANALOG_CCM_PLL_ARM_BYPASS (1 << 16)
#define IMX6_ANALOG_CCM_PLL_ARM_CLK_SRC_MASK (0x03 << 16)
#define IMX6_ANALOG_CCM_PLL_USB1 0x010
#define IMX6_ANALOG_CCM_PLL_USB1_SET 0x014
#define IMX6_ANALOG_CCM_PLL_USB1_CLR 0x018
#define IMX6_ANALOG_CCM_PLL_USB1_TOG 0x01C
#define IMX6_ANALOG_CCM_PLL_USB_LOCK (1U << 31)
#define IMX6_ANALOG_CCM_PLL_USB_BYPASS (1 << 16)
#define IMX6_ANALOG_CCM_PLL_USB_ENABLE (1 << 13)
#define IMX6_ANALOG_CCM_PLL_USB_POWER (1 << 12)
#define IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS (1 << 6)
#define IMX6_ANALOG_CCM_PLL_USB2 0x020
#define IMX6_ANALOG_CCM_PLL_USB2_SET 0x024
#define IMX6_ANALOG_CCM_PLL_USB2_CLR 0x028
#define IMX6_ANALOG_CCM_PLL_USB2_TOG 0x02C
#define IMX6_ANALOG_CCM_PLL_SYS 0x030
#define IMX6_ANALOG_CCM_PLL_SYS_SET 0x034
#define IMX6_ANALOG_CCM_PLL_SYS_CLR 0x038
#define IMX6_ANALOG_CCM_PLL_SYS_TOG 0x03C
#define IMX6_ANALOG_CCM_PLL_SYS_SS 0x040
#define IMX6_ANALOG_CCM_PLL_SYS_NUM 0x050
#define IMX6_ANALOG_CCM_PLL_SYS_DENOM 0x060
#define IMX6_ANALOG_CCM_PLL_AUDIO 0x070
#define IMX6_ANALOG_CCM_PLL_AUDIO_ENABLE (1 << 13)
#define IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_SHIFT 0
#define IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_MASK 0x7f
#define IMX6_ANALOG_CCM_PLL_AUDIO_SET 0x074
#define IMX6_ANALOG_CCM_PLL_AUDIO_CLR 0x078
#define IMX6_ANALOG_CCM_PLL_AUDIO_TOG 0x07C
#define IMX6_ANALOG_CCM_PLL_AUDIO_NUM 0x080
#define IMX6_ANALOG_CCM_PLL_AUDIO_DENOM 0x090
#define IMX6_ANALOG_CCM_PLL_VIDEO 0x0A0
#define IMX6_ANALOG_CCM_PLL_VIDEO_SET 0x0A4
#define IMX6_ANALOG_CCM_PLL_VIDEO_CLR 0x0A8
#define IMX6_ANALOG_CCM_PLL_VIDEO_TOG 0x0AC
#define IMX6_ANALOG_CCM_PLL_VIDEO_NUM 0x0B0
#define IMX6_ANALOG_CCM_PLL_VIDEO_DENOM 0x0C0
#define IMX6_ANALOG_CCM_PLL_MLB 0x0D0
#define IMX6_ANALOG_CCM_PLL_MLB_SET 0x0D4
#define IMX6_ANALOG_CCM_PLL_MLB_CLR 0x0D8
#define IMX6_ANALOG_CCM_PLL_MLB_TOG 0x0DC
#define IMX6_ANALOG_CCM_PLL_ENET 0x0E0
#define IMX6_ANALOG_CCM_PLL_ENET_SET 0x0E4
#define IMX6_ANALOG_CCM_PLL_ENET_CLR 0x0E8
#define IMX6_ANALOG_CCM_PLL_ENET_TOG 0x0EC
#define IMX6_ANALOG_CCM_PFD_480 0x0F0
#define IMX6_ANALOG_CCM_PFD_480_SET 0x0F4
#define IMX6_ANALOG_CCM_PFD_480_CLR 0x0F8
#define IMX6_ANALOG_CCM_PFD_480_TOG 0x0FC
#define IMX6_ANALOG_CCM_PFD_528 0x100
#define IMX6_ANALOG_CCM_PFD_528_SET 0x104
#define IMX6_ANALOG_CCM_PFD_528_CLR 0x108
#define IMX6_ANALOG_CCM_PFD_528_TOG 0x10C
#define IMX6_ANALOG_PMU_REG_CORE 0x140
#define IMX6_ANALOG_PMU_REG2_TARG_SHIFT 18
#define IMX6_ANALOG_PMU_REG2_TARG_MASK \
(0x1f << IMX6_ANALOG_PMU_REG2_TARG_SHIFT)
#define IMX6_ANALOG_PMU_REG1_TARG_SHIFT 9
#define IMX6_ANALOG_PMU_REG1_TARG_MASK \
(0x1f << IMX6_ANALOG_PMU_REG1_TARG_SHIFT)
#define IMX6_ANALOG_PMU_REG0_TARG_SHIFT 0
#define IMX6_ANALOG_PMU_REG0_TARG_MASK \
(0x1f << IMX6_ANALOG_PMU_REG0_TARG_SHIFT)
#define IMX6_ANALOG_PMU_MISC0 0x150
#define IMX6_ANALOG_PMU_MISC0_SET 0x154
#define IMX6_ANALOG_PMU_MISC0_CLR 0x158
#define IMX6_ANALOG_PMU_MISC0_TOG 0x15C
#define IMX6_ANALOG_PMU_MISC0_SELFBIASOFF (1 << 3)
#define IMX6_ANALOG_PMU_MISC1 0x160
#define IMX6_ANALOG_PMU_MISC1_SET 0x164
#define IMX6_ANALOG_PMU_MISC1_CLR 0x168
#define IMX6_ANALOG_PMU_MISC1_TOG 0x16C
#define IMX6_ANALOG_PMU_MISC1_IRQ_TEMPSENSE (1 << 29)
#define IMX6_ANALOG_PMU_MISC2 0x170
#define IMX6_ANALOG_PMU_MISC2_SET 0x174
#define IMX6_ANALOG_PMU_MISC2_CLR 0x178
#define IMX6_ANALOG_PMU_MISC2_TOG 0x17C
/*
* Note that the ANALOG_CCM_MISCn registers are the same as the PMU_MISCn
* registers; some bits conceptually belong to the PMU and some to the CCM.
*/
#define IMX6_ANALOG_CCM_MISC0 IMX6_ANALOG_PMU_MISC0
#define IMX6_ANALOG_CCM_MISC0_SET IMX6_ANALOG_PMU_MISC0_SET
#define IMX6_ANALOG_CCM_MISC0_CLR IMX6_ANALOG_PMU_MISC0_CLR
#define IMX6_ANALOG_CCM_MISC0_TOG IMX6_ANALOG_PMU_MISC0_TOG
#define IMX6_ANALOG_CCM_MISC2 IMX6_ANALOG_PMU_MISC2
#define IMX6_ANALOG_CCM_MISC2_SET IMX6_ANALOG_PMU_MISC2_SET
#define IMX6_ANALOG_CCM_MISC2_CLR IMX6_ANALOG_PMU_MISC2_CLR
#define IMX6_ANALOG_CCM_MISC2_TOG IMX6_ANALOG_PMU_MISC2_TOG
#define IMX6_ANALOG_TEMPMON_TEMPSENSE0 0x180
#define IMX6_ANALOG_TEMPMON_TEMPSENSE0_SET 0x184
#define IMX6_ANALOG_TEMPMON_TEMPSENSE0_CLR 0x188
#define IMX6_ANALOG_TEMPMON_TEMPSENSE0_TOG 0x18C
#define IMX6_ANALOG_TEMPMON_TEMPSENSE0_TOG 0x18C
#define IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_SHIFT 20
#define IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_MASK \
(0xfff << IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_SHIFT)
#define IMX6_ANALOG_TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT 8
#define IMX6_ANALOG_TEMPMON_TEMPSENSE0_TEMP_CNT_MASK \
(0xfff << IMX6_ANALOG_TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT)
#define IMX6_ANALOG_TEMPMON_TEMPSENSE0_VALID 0x4
#define IMX6_ANALOG_TEMPMON_TEMPSENSE0_MEASURE 0x2
#define IMX6_ANALOG_TEMPMON_TEMPSENSE0_POWER_DOWN 0x1
#define IMX6_ANALOG_TEMPMON_TEMPSENSE1 0x190
#define IMX6_ANALOG_TEMPMON_TEMPSENSE1_SET 0x194
#define IMX6_ANALOG_TEMPMON_TEMPSENSE1_CLR 0x198
#define IMX6_ANALOG_TEMPMON_TEMPSENSE1_TOG 0x19C
#define IMX6_ANALOG_USB1_VBUS_DETECT 0x1A0
#define IMX6_ANALOG_USB1_VBUS_DETECT_SET 0x1A4
#define IMX6_ANALOG_USB1_VBUS_DETECT_CLR 0x1A8
#define IMX6_ANALOG_USB1_VBUS_DETECT_TOG 0x1AC
#define IMX6_ANALOG_USB1_CHRG_DETECT 0x1B0
#define IMX6_ANALOG_USB1_CHRG_DETECT_SET 0x1B4
#define IMX6_ANALOG_USB1_CHRG_DETECT_CLR 0x1B8
#define IMX6_ANALOG_USB1_CHRG_DETECT_TOG 0x1BC
#define IMX6_ANALOG_USB_CHRG_DETECT_N_ENABLE (1 << 20) /* EN_B */
#define IMX6_ANALOG_USB_CHRG_DETECT_N_CHK_CHRG (1 << 19) /* CHK_CHRG_B */
#define IMX6_ANALOG_USB_CHRG_DETECT_CHK_CONTACT (1 << 18)
#define IMX6_ANALOG_USB1_VBUS_DETECT_STAT 0x1C0
#define IMX6_ANALOG_USB1_CHRG_DETECT_STAT 0x1D0
#define IMX6_ANALOG_USB1_MISC 0x1F0
#define IMX6_ANALOG_USB1_MISC_SET 0x1F4
#define IMX6_ANALOG_USB1_MISC_CLR 0x1F8
#define IMX6_ANALOG_USB1_MISC_TOG 0x1FC
#define IMX6_ANALOG_USB2_VBUS_DETECT 0x200
#define IMX6_ANALOG_USB2_VBUS_DETECT_SET 0x204
#define IMX6_ANALOG_USB2_VBUS_DETECT_CLR 0x208
#define IMX6_ANALOG_USB2_VBUS_DETECT_TOG 0x20C
#define IMX6_ANALOG_USB2_CHRG_DETECT 0x210
#define IMX6_ANALOG_USB2_CHRG_DETECT_SET 0x214
#define IMX6_ANALOG_USB2_CHRG_DETECT_CLR 0x218
#define IMX6_ANALOG_USB2_CHRG_DETECT_TOG 0x21C
#define IMX6_ANALOG_USB2_VBUS_DETECT_STAT 0x220
#define IMX6_ANALOG_USB2_CHRG_DETECT_STAT 0x230
#define IMX6_ANALOG_USB2_MISC 0x250
#define IMX6_ANALOG_USB2_MISC_SET 0x254
#define IMX6_ANALOG_USB2_MISC_CLR 0x258
#define IMX6_ANALOG_USB2_MISC_TOG 0x25C
#define IMX6_ANALOG_DIGPROG 0x260
#define IMX6_ANALOG_DIGPROG_SL 0x280
#define IMX6_ANALOG_DIGPROG_SOCTYPE_SHIFT 16
#define IMX6_ANALOG_DIGPROG_SOCTYPE_MASK \
(0xff << IMX6_ANALOG_DIGPROG_SOCTYPE_SHIFT)
#endif

49
freebsd/sys/arm/freescale/imx/imx6_anatopvar.h Normal file
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/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef IMX6_ANATOPVAR_H
#define IMX6_ANATOPVAR_H
/*
* All registers controlling various analog aspects of the SoC (such as PLLs or
* voltage regulators or USB VBUS detection) are gathered together under the
* anatop device (because of newbus hierarchical resource management), but other
* drivers such as CMM or USBPHY need access to these registers. These
* functions let them have at the hardware directly. No effort is made by these
* functions to mediate concurrent access.
*/
uint32_t imx6_anatop_read_4(bus_size_t _offset);
void imx6_anatop_write_4(bus_size_t _offset, uint32_t _value);
uint32_t imx6_get_cpu_clock(void);
uint32_t pll4_configure_output(uint32_t mfi, uint32_t mfn, uint32_t mfd);
#endif

468
freebsd/sys/arm/freescale/imx/imx6_ccm.c Normal file
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#include <machine/rtems-bsd-kernel-space.h>
/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
/*
* Clocks and power control driver for Freescale i.MX6 family of SoCs.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/bus.h>
#include <sys/rman.h>
#include <dev/ofw/ofw_bus.h>
#include <dev/ofw/ofw_bus_subr.h>
#include <machine/bus.h>
#include <arm/freescale/imx/imx6_anatopreg.h>
#include <arm/freescale/imx/imx6_anatopvar.h>
#include <arm/freescale/imx/imx6_ccmreg.h>
#include <arm/freescale/imx/imx_machdep.h>
#include <arm/freescale/imx/imx_ccmvar.h>
#ifndef CCGR_CLK_MODE_ALWAYS
#define CCGR_CLK_MODE_OFF 0
#define CCGR_CLK_MODE_RUNMODE 1
#define CCGR_CLK_MODE_ALWAYS 3
#endif
struct ccm_softc {
device_t dev;
struct resource *mem_res;
};
static struct ccm_softc *ccm_sc;
static inline uint32_t
RD4(struct ccm_softc *sc, bus_size_t off)
{
return (bus_read_4(sc->mem_res, off));
}
static inline void
WR4(struct ccm_softc *sc, bus_size_t off, uint32_t val)
{
bus_write_4(sc->mem_res, off, val);
}
/*
* Until we have a fully functional ccm driver which implements the fdt_clock
* interface, use the age-old workaround of unconditionally enabling the clocks
* for devices we might need to use. The SoC defaults to most clocks enabled,
* but the rom boot code and u-boot disable a few of them. We turn on only
* what's needed to run the chip plus devices we have drivers for, and turn off
* devices we don't yet have drivers for. (Note that USB is not turned on here
* because that is one we do when the driver asks for it.)
*/
static void
ccm_init_gates(struct ccm_softc *sc)
{
uint32_t reg;
/* ahpbdma, aipstz 1 & 2 buses */
reg = CCGR0_AIPS_TZ1 | CCGR0_AIPS_TZ2 | CCGR0_ABPHDMA;
WR4(sc, CCM_CCGR0, reg);
/* enet, epit, gpt, spi */
reg = CCGR1_ENET | CCGR1_EPIT1 | CCGR1_GPT | CCGR1_ECSPI1 |
CCGR1_ECSPI2 | CCGR1_ECSPI3 | CCGR1_ECSPI4 | CCGR1_ECSPI5;
WR4(sc, CCM_CCGR1, reg);
/* ipmux & ipsync (bridges), iomux, i2c */
reg = CCGR2_I2C1 | CCGR2_I2C2 | CCGR2_I2C3 | CCGR2_IIM |
CCGR2_IOMUX_IPT | CCGR2_IPMUX1 | CCGR2_IPMUX2 | CCGR2_IPMUX3 |
CCGR2_IPSYNC_IP2APB_TZASC1 | CCGR2_IPSYNC_IP2APB_TZASC2 |
CCGR2_IPSYNC_VDOA;
WR4(sc, CCM_CCGR2, reg);
/* DDR memory controller */
reg = CCGR3_OCRAM | CCGR3_MMDC_CORE_IPG |
CCGR3_MMDC_CORE_ACLK_FAST | CCGR3_CG11 | CCGR3_CG13;
WR4(sc, CCM_CCGR3, reg);
/* pl301 bus crossbar */
reg = CCGR4_PL301_MX6QFAST1_S133 |
CCGR4_PL301_MX6QPER1_BCH | CCGR4_PL301_MX6QPER2_MAIN;
WR4(sc, CCM_CCGR4, reg);
/* uarts, ssi, sdma */
reg = CCGR5_SDMA | CCGR5_SSI1 | CCGR5_SSI2 | CCGR5_SSI3 |
CCGR5_UART | CCGR5_UART_SERIAL;
WR4(sc, CCM_CCGR5, reg);
/* usdhc 1-4, usboh3 */
reg = CCGR6_USBOH3 | CCGR6_USDHC1 | CCGR6_USDHC2 |
CCGR6_USDHC3 | CCGR6_USDHC4;
WR4(sc, CCM_CCGR6, reg);
}
static int
ccm_detach(device_t dev)
{
struct ccm_softc *sc;
sc = device_get_softc(dev);
if (sc->mem_res != NULL)
bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
return (0);
}
static int
ccm_attach(device_t dev)
{
struct ccm_softc *sc;
int err, rid;
uint32_t reg;
sc = device_get_softc(dev);
err = 0;
/* Allocate bus_space resources. */
rid = 0;
sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
RF_ACTIVE);
if (sc->mem_res == NULL) {
device_printf(dev, "Cannot allocate memory resources\n");
err = ENXIO;
goto out;
}
ccm_sc = sc;
/*
* Configure the Low Power Mode setting to leave the ARM core power on
* when a WFI instruction is executed. This lets the MPCore timers and
* GIC continue to run, which is helpful when the only thing that can
* wake you up is an MPCore Private Timer interrupt delivered via GIC.
*
* XXX Based on the docs, setting CCM_CGPR_INT_MEM_CLK_LPM shouldn't be
* required when the LPM bits are set to LPM_RUN. But experimentally
* I've experienced a fairly rare lockup when not setting it. I was
* unable to prove conclusively that the lockup was related to power
* management or that this definitively fixes it. Revisit this.
*/
reg = RD4(sc, CCM_CGPR);
reg |= CCM_CGPR_INT_MEM_CLK_LPM;
WR4(sc, CCM_CGPR, reg);
reg = RD4(sc, CCM_CLPCR);
reg = (reg & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM_RUN;
WR4(sc, CCM_CLPCR, reg);
ccm_init_gates(sc);
err = 0;
out:
if (err != 0)
ccm_detach(dev);
return (err);
}
static int
ccm_probe(device_t dev)
{
if (!ofw_bus_status_okay(dev))
return (ENXIO);
if (ofw_bus_is_compatible(dev, "fsl,imx6q-ccm") == 0)
return (ENXIO);
device_set_desc(dev, "Freescale i.MX6 Clock Control Module");
return (BUS_PROBE_DEFAULT);
}
void
imx_ccm_ssi_configure(device_t _ssidev)
{
struct ccm_softc *sc;
uint32_t reg;
sc = ccm_sc;
/*
* Select PLL4 (Audio PLL) clock multiplexer as source.
* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM).
*/
reg = RD4(sc, CCM_CSCMR1);
reg &= ~(SSI_CLK_SEL_M << SSI1_CLK_SEL_S);
reg |= (SSI_CLK_SEL_PLL4 << SSI1_CLK_SEL_S);
reg &= ~(SSI_CLK_SEL_M << SSI2_CLK_SEL_S);
reg |= (SSI_CLK_SEL_PLL4 << SSI2_CLK_SEL_S);
reg &= ~(SSI_CLK_SEL_M << SSI3_CLK_SEL_S);
reg |= (SSI_CLK_SEL_PLL4 << SSI3_CLK_SEL_S);
WR4(sc, CCM_CSCMR1, reg);
/*
* Ensure we have set hardware-default values
* for pre and post dividers.
*/
/* SSI1 and SSI3 */
reg = RD4(sc, CCM_CS1CDR);
/* Divide by 2 */
reg &= ~(SSI_CLK_PODF_MASK << SSI1_CLK_PODF_SHIFT);
reg &= ~(SSI_CLK_PODF_MASK << SSI3_CLK_PODF_SHIFT);
reg |= (0x1 << SSI1_CLK_PODF_SHIFT);
reg |= (0x1 << SSI3_CLK_PODF_SHIFT);
/* Divide by 4 */
reg &= ~(SSI_CLK_PRED_MASK << SSI1_CLK_PRED_SHIFT);
reg &= ~(SSI_CLK_PRED_MASK << SSI3_CLK_PRED_SHIFT);
reg |= (0x3 << SSI1_CLK_PRED_SHIFT);
reg |= (0x3 << SSI3_CLK_PRED_SHIFT);
WR4(sc, CCM_CS1CDR, reg);
/* SSI2 */
reg = RD4(sc, CCM_CS2CDR);
/* Divide by 2 */
reg &= ~(SSI_CLK_PODF_MASK << SSI2_CLK_PODF_SHIFT);
reg |= (0x1 << SSI2_CLK_PODF_SHIFT);
/* Divide by 4 */
reg &= ~(SSI_CLK_PRED_MASK << SSI2_CLK_PRED_SHIFT);
reg |= (0x3 << SSI2_CLK_PRED_SHIFT);
WR4(sc, CCM_CS2CDR, reg);
}
void
imx_ccm_usb_enable(device_t _usbdev)
{
/*
* For imx6, the USBOH3 clock gate is bits 0-1 of CCGR6, so no need for
* shifting and masking here, just set the low-order two bits to ALWAYS.
*/
WR4(ccm_sc, CCM_CCGR6, RD4(ccm_sc, CCM_CCGR6) | CCGR_CLK_MODE_ALWAYS);
}
void
imx_ccm_usbphy_enable(device_t _phydev)
{
/*
* XXX Which unit?
* Right now it's not clear how to figure from fdt data which phy unit
* we're supposed to operate on. Until this is worked out, just enable
* both PHYs.
*/
#if 0
int phy_num, regoff;
phy_num = 0; /* XXX */
switch (phy_num) {
case 0:
regoff = 0;
break;
case 1:
regoff = 0x10;
break;
default:
device_printf(ccm_sc->dev, "Bad PHY number %u,\n",
phy_num);
return;
}
imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_USB1 + regoff,
IMX6_ANALOG_CCM_PLL_USB_ENABLE |
IMX6_ANALOG_CCM_PLL_USB_POWER |
IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS);
#else
imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_USB1 + 0,
IMX6_ANALOG_CCM_PLL_USB_ENABLE |
IMX6_ANALOG_CCM_PLL_USB_POWER |
IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS);
imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_USB1 + 0x10,
IMX6_ANALOG_CCM_PLL_USB_ENABLE |
IMX6_ANALOG_CCM_PLL_USB_POWER |
IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS);
#endif
}
int
imx6_ccm_sata_enable(void)
{
uint32_t v;
int timeout;
/* Un-gate the sata controller. */
WR4(ccm_sc, CCM_CCGR5, RD4(ccm_sc, CCM_CCGR5) | CCGR5_SATA);
/* Power up the PLL that feeds ENET/SATA/PCI phys, wait for lock. */
v = RD4(ccm_sc, CCM_ANALOG_PLL_ENET);
v &= ~CCM_ANALOG_PLL_ENET_POWERDOWN;
WR4(ccm_sc, CCM_ANALOG_PLL_ENET, v);
for (timeout = 100000; timeout > 0; timeout--) {
if (RD4(ccm_sc, CCM_ANALOG_PLL_ENET) &
CCM_ANALOG_PLL_ENET_LOCK) {
break;
}
}
if (timeout <= 0) {
return ETIMEDOUT;
}
/* Enable the PLL, and enable its 100mhz output. */
v |= CCM_ANALOG_PLL_ENET_ENABLE;
v &= ~CCM_ANALOG_PLL_ENET_BYPASS;
WR4(ccm_sc, CCM_ANALOG_PLL_ENET, v);
v |= CCM_ANALOG_PLL_ENET_ENABLE_100M;
WR4(ccm_sc, CCM_ANALOG_PLL_ENET, v);
return 0;
}
uint32_t
imx_ccm_ecspi_hz(void)
{
return (60000000);
}
uint32_t
imx_ccm_ipg_hz(void)
{
return (66000000);
}
uint32_t
imx_ccm_perclk_hz(void)
{
return (66000000);
}
uint32_t
imx_ccm_sdhci_hz(void)
{
return (200000000);
}
uint32_t
imx_ccm_uart_hz(void)
{
return (80000000);
}
uint32_t
imx_ccm_ahb_hz(void)
{
return (132000000);
}
void
imx_ccm_ipu_enable(int ipu)
{
struct ccm_softc *sc;
uint32_t reg;
sc = ccm_sc;
reg = RD4(sc, CCM_CCGR3);
if (ipu == 1)
reg |= CCGR3_IPU1_IPU | CCGR3_IPU1_DI0;
else
reg |= CCGR3_IPU2_IPU | CCGR3_IPU2_DI0;
WR4(sc, CCM_CCGR3, reg);
}
void
imx_ccm_hdmi_enable(void)
{
struct ccm_softc *sc;
uint32_t reg;
sc = ccm_sc;
reg = RD4(sc, CCM_CCGR2);
reg |= CCGR2_HDMI_TX | CCGR2_HDMI_TX_ISFR;
WR4(sc, CCM_CCGR2, reg);
/* Set HDMI clock to 280MHz */
reg = RD4(sc, CCM_CHSCCDR);
reg &= ~(CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
CHSCCDR_IPU1_DI0_PODF_MASK | CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
reg |= (CHSCCDR_PODF_DIVIDE_BY_3 << CHSCCDR_IPU1_DI0_PODF_SHIFT);
reg |= (CHSCCDR_IPU_PRE_CLK_540M_PFD << CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT);
WR4(sc, CCM_CHSCCDR, reg);
reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT);
WR4(sc, CCM_CHSCCDR, reg);
}
uint32_t
imx_ccm_get_cacrr(void)
{
return (RD4(ccm_sc, CCM_CACCR));
}
void
imx_ccm_set_cacrr(uint32_t divisor)
{
WR4(ccm_sc, CCM_CACCR, divisor);
}
static device_method_t ccm_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, ccm_probe),
DEVMETHOD(device_attach, ccm_attach),
DEVMETHOD(device_detach, ccm_detach),
DEVMETHOD_END
};
static driver_t ccm_driver = {
"ccm",
ccm_methods,
sizeof(struct ccm_softc)
};
static devclass_t ccm_devclass;
EARLY_DRIVER_MODULE(ccm, simplebus, ccm_driver, ccm_devclass, 0, 0,
BUS_PASS_CPU + BUS_PASS_ORDER_EARLY);

149
freebsd/sys/arm/freescale/imx/imx6_ccmreg.h Normal file
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/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef IMX6_CCMREG_H
#define IMX6_CCMREG_H
#define CCM_CACCR 0x010
#define CCM_CBCDR 0x014
#define CBCDR_MMDC_CH1_AXI_PODF_SHIFT 3
#define CBCDR_MMDC_CH1_AXI_PODF_MASK (7 << 3)
#define CCM_CSCMR1 0x01C
#define SSI1_CLK_SEL_S 10
#define SSI2_CLK_SEL_S 12
#define SSI3_CLK_SEL_S 14
#define SSI_CLK_SEL_M 0x3
#define SSI_CLK_SEL_508_PFD 0
#define SSI_CLK_SEL_454_PFD 1
#define SSI_CLK_SEL_PLL4 2
#define CCM_CSCMR2 0x020
#define CSCMR2_LDB_DI0_IPU_DIV_SHIFT 10
#define CCM_CS1CDR 0x028
#define SSI1_CLK_PODF_SHIFT 0
#define SSI1_CLK_PRED_SHIFT 6
#define SSI3_CLK_PODF_SHIFT 16
#define SSI3_CLK_PRED_SHIFT 22
#define SSI_CLK_PODF_MASK 0x3f
#define SSI_CLK_PRED_MASK 0x7
#define CCM_CS2CDR 0x02C
#define SSI2_CLK_PODF_SHIFT 0
#define SSI2_CLK_PRED_SHIFT 6
#define LDB_DI0_CLK_SEL_SHIFT 9
#define LDB_DI0_CLK_SEL_MASK (3 << LDB_DI0_CLK_SEL_SHIFT)
#define CCM_CHSCCDR 0x034
#define CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
#define CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT 6
#define CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3)
#define CHSCCDR_IPU1_DI0_PODF_SHIFT 3
#define CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7)
#define CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT 0
#define CHSCCDR_CLK_SEL_LDB_DI0 3
#define CHSCCDR_PODF_DIVIDE_BY_3 2
#define CHSCCDR_IPU_PRE_CLK_540M_PFD 5
#define CCM_CSCDR2 0x038
#define CCM_CLPCR 0x054
#define CCM_CLPCR_LPM_MASK 0x03
#define CCM_CLPCR_LPM_RUN 0x00
#define CCM_CLPCR_LPM_WAIT 0x01
#define CCM_CLPCR_LPM_STOP 0x02
#define CCM_CGPR 0x064
#define CCM_CGPR_INT_MEM_CLK_LPM (1 << 17)
#define CCM_CCGR0 0x068
#define CCGR0_AIPS_TZ1 (0x3 << 0)
#define CCGR0_AIPS_TZ2 (0x3 << 2)
#define CCGR0_ABPHDMA (0x3 << 4)
#define CCM_CCGR1 0x06C
#define CCGR1_ECSPI1 (0x3 << 0)
#define CCGR1_ECSPI2 (0x3 << 2)
#define CCGR1_ECSPI3 (0x3 << 4)
#define CCGR1_ECSPI4 (0x3 << 6)
#define CCGR1_ECSPI5 (0x3 << 8)
#define CCGR1_ENET (0x3 << 10)
#define CCGR1_EPIT1 (0x3 << 12)
#define CCGR1_EPIT2 (0x3 << 14)
#define CCGR1_ESAI (0x3 << 16)
#define CCGR1_GPT (0x3 << 20)
#define CCGR1_GPT_SERIAL (0x3 << 22)
#define CCM_CCGR2 0x070
#define CCGR2_HDMI_TX (0x3 << 0)
#define CCGR2_HDMI_TX_ISFR (0x3 << 4)
#define CCGR2_I2C1 (0x3 << 6)
#define CCGR2_I2C2 (0x3 << 8)
#define CCGR2_I2C3 (0x3 << 10)
#define CCGR2_IIM (0x3 << 12)
#define CCGR2_IOMUX_IPT (0x3 << 14)
#define CCGR2_IPMUX1 (0x3 << 16)
#define CCGR2_IPMUX2 (0x3 << 18)
#define CCGR2_IPMUX3 (0x3 << 20)
#define CCGR2_IPSYNC_IP2APB_TZASC1 (0x3 << 22)
#define CCGR2_IPSYNC_IP2APB_TZASC2 (0x3 << 24)
#define CCGR2_IPSYNC_VDOA (0x3 << 26)
#define CCM_CCGR3 0x074
#define CCGR3_IPU1_IPU (0x3 << 0)
#define CCGR3_IPU1_DI0 (0x3 << 2)
#define CCGR3_IPU1_DI1 (0x3 << 4)
#define CCGR3_IPU2_IPU (0x3 << 6)
#define CCGR3_IPU2_DI0 (0x3 << 8)
#define CCGR3_IPU2_DI1 (0x3 << 10)
#define CCGR3_LDB_DI0 (0x3 << 12)
#define CCGR3_LDB_DI1 (0x3 << 14)
#define CCGR3_MMDC_CORE_ACLK_FAST (0x3 << 20)
#define CCGR3_CG11 (0x3 << 22)
#define CCGR3_MMDC_CORE_IPG (0x3 << 24)
#define CCGR3_CG13 (0x3 << 26)
#define CCGR3_OCRAM (0x3 << 28)
#define CCM_CCGR4 0x078
#define CCGR4_PL301_MX6QFAST1_S133 (0x3 << 8)
#define CCGR4_PL301_MX6QPER1_BCH (0x3 << 12)
#define CCGR4_PL301_MX6QPER2_MAIN (0x3 << 14)
#define CCM_CCGR5 0x07C
#define CCGR5_SATA (0x3 << 4)
#define CCGR5_SDMA (0x3 << 6)
#define CCGR5_SSI1 (0x3 << 18)
#define CCGR5_SSI2 (0x3 << 20)
#define CCGR5_SSI3 (0x3 << 22)
#define CCGR5_UART (0x3 << 24)
#define CCGR5_UART_SERIAL (0x3 << 26)
#define CCM_CCGR6 0x080
#define CCGR6_USBOH3 (0x3 << 0)
#define CCGR6_USDHC1 (0x3 << 2)
#define CCGR6_USDHC2 (0x3 << 4)
#define CCGR6_USDHC3 (0x3 << 6)
#define CCGR6_USDHC4 (0x3 << 8)
#define CCM_CMEOR 0x088
#define CCM_ANALOG_PLL_ENET 0x000040e0
#define CCM_ANALOG_PLL_ENET_LOCK (1u << 31)
#define CCM_ANALOG_PLL_ENET_ENABLE_100M (1u << 20) /* SATA */
#define CCM_ANALOG_PLL_ENET_BYPASS (1u << 16)
#define CCM_ANALOG_PLL_ENET_ENABLE (1u << 13) /* Ether */
#define CCM_ANALOG_PLL_ENET_POWERDOWN (1u << 12)
#endif

38
freebsd/sys/arm/freescale/imx/imx6_machdep.h Normal file
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/*-
* Copyright (c) 2017 Andrew Turner
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef IMX6_MACHDEP_H
#define IMX6_MACHDEP_H
struct pl310_softc;
void imx6_mp_start_ap(platform_t);
void imx6_mp_setmaxid(platform_t);
void imx6_pl310_init(platform_t, struct pl310_softc *);
#endif /* IMX6_MACHDEP_H */

72
freebsd/sys/arm/freescale/imx/imx_machdep.h Normal file
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/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef IMX_MACHDEP_H
#define IMX_MACHDEP_H
#include <sys/types.h>
#include <sys/sysctl.h>
SYSCTL_DECL(_hw_imx);
/* Common functions, implemented in imx_machdep.c. */
void imx_wdog_cpu_reset(vm_offset_t _wdcr_phys) __attribute__((__noreturn__));
void imx_wdog_init_last_reset(vm_offset_t _wdsr_phys);
/* From here down, routines are implemented in imxNN_machdep.c. */
/*
* SoC identity.
* According to the documentation, there is such a thing as an i.MX6 Dual
* (non-lite flavor). However, Freescale doesn't seem to have assigned it a
* number in their code for determining the SoC type in u-boot.
*
* To-do: put silicon revision numbers into the low-order bits somewhere.
*/
#define IMXSOC_51 0x51000000
#define IMXSOC_53 0x53000000
#define IMXSOC_6SL 0x60000000
#define IMXSOC_6DL 0x61000000
#define IMXSOC_6S 0x62000000
#define IMXSOC_6Q 0x63000000
#define IMXSOC_6UL 0x64000000
#define IMXSOC_FAMSHIFT 28
u_int imx_soc_type(void);
static inline u_int
imx_soc_family(void)
{
return (imx_soc_type() >> IMXSOC_FAMSHIFT);
}
#endif