mirror of
https://git.rtems.org/rtems-libbsd/
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e1000phy: Import from FreeBSD
This commit is contained in:
Sebastian Huber
parent
6a73f64fe2
commit
946611a1af
1
Makefile
1
Makefile
@ -399,6 +399,7 @@ LIB_C_FILES += freebsd/sys/dev/mii/mii.c
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LIB_C_FILES += freebsd/sys/dev/mii/mii_bitbang.c
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LIB_C_FILES += freebsd/sys/dev/mii/mii_physubr.c
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LIB_C_FILES += freebsd/sys/dev/mii/icsphy.c
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LIB_C_FILES += freebsd/sys/dev/mii/e1000phy.c
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LIB_C_FILES += freebsd/sys/dev/mii/brgphy.c
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LIB_C_FILES += freebsd/sys/dev/tsec/if_tsec.c
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LIB_C_FILES += freebsd/sys/dev/cadence/if_cgem.c
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@ -1244,6 +1244,7 @@ devNet.addKernelSpaceHeaderFiles(
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'sys/dev/mii/mii_bitbang.h',
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'sys/dev/mii/miivar.h',
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'sys/dev/mii/brgphyreg.h',
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'sys/dev/mii/e1000phyreg.h',
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'sys/dev/mii/icsphyreg.h',
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'sys/dev/led/led.h',
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'sys/net/bpf.h',
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@ -1267,6 +1268,7 @@ devNet.addKernelSpaceSourceFiles(
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'sys/dev/mii/mii_bitbang.c',
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'sys/dev/mii/mii_physubr.c',
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'sys/dev/mii/icsphy.c',
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'sys/dev/mii/e1000phy.c',
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'sys/dev/mii/brgphy.c',
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'sys/dev/tsec/if_tsec.c',
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'sys/dev/cadence/if_cgem.c',
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503
freebsd/sys/dev/mii/e1000phy.c
Normal file
503
freebsd/sys/dev/mii/e1000phy.c
Normal file
@ -0,0 +1,503 @@
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#include <machine/rtems-bsd-kernel-space.h>
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/*-
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* Principal Author: Parag Patel
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* Copyright (c) 2001
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Additional Copyright (c) 2001 by Traakan Software under same licence.
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* Secondary Author: Matthew Jacob
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* driver for the Marvell 88E1000 series external 1000/100/10-BT PHY.
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*/
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/*
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* Support added for the Marvell 88E1011 (Alaska) 1000/100/10baseTX and
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* 1000baseSX PHY.
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* Nathan Binkert <nate@openbsd.org>
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* Jung-uk Kim <jkim@niksun.com>
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*/
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#include <rtems/bsd/sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/socket.h>
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#include <sys/bus.h>
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#include <net/if.h>
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#include <net/if_media.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include <rtems/bsd/local/miidevs.h>
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#include <dev/mii/e1000phyreg.h>
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#include <rtems/bsd/local/miibus_if.h>
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static int e1000phy_probe(device_t);
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static int e1000phy_attach(device_t);
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static device_method_t e1000phy_methods[] = {
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/* device interface */
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DEVMETHOD(device_probe, e1000phy_probe),
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DEVMETHOD(device_attach, e1000phy_attach),
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DEVMETHOD(device_detach, mii_phy_detach),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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DEVMETHOD_END
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};
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static devclass_t e1000phy_devclass;
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static driver_t e1000phy_driver = {
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"e1000phy",
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e1000phy_methods,
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sizeof(struct mii_softc)
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};
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DRIVER_MODULE(e1000phy, miibus, e1000phy_driver, e1000phy_devclass, 0, 0);
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static int e1000phy_service(struct mii_softc *, struct mii_data *, int);
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static void e1000phy_status(struct mii_softc *);
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static void e1000phy_reset(struct mii_softc *);
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static int e1000phy_mii_phy_auto(struct mii_softc *, int);
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static const struct mii_phydesc e1000phys[] = {
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MII_PHY_DESC(MARVELL, E1000),
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MII_PHY_DESC(MARVELL, E1011),
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MII_PHY_DESC(MARVELL, E1000_3),
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MII_PHY_DESC(MARVELL, E1000_5),
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MII_PHY_DESC(MARVELL, E1111),
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MII_PHY_DESC(xxMARVELL, E1000),
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MII_PHY_DESC(xxMARVELL, E1011),
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MII_PHY_DESC(xxMARVELL, E1000_3),
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MII_PHY_DESC(xxMARVELL, E1000S),
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MII_PHY_DESC(xxMARVELL, E1000_5),
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MII_PHY_DESC(xxMARVELL, E1101),
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MII_PHY_DESC(xxMARVELL, E3082),
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MII_PHY_DESC(xxMARVELL, E1112),
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MII_PHY_DESC(xxMARVELL, E1149),
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MII_PHY_DESC(xxMARVELL, E1111),
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MII_PHY_DESC(xxMARVELL, E1116),
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MII_PHY_DESC(xxMARVELL, E1116R),
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MII_PHY_DESC(xxMARVELL, E1118),
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MII_PHY_DESC(xxMARVELL, E1149R),
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MII_PHY_DESC(xxMARVELL, E3016),
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MII_PHY_DESC(xxMARVELL, PHYG65G),
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MII_PHY_END
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};
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static const struct mii_phy_funcs e1000phy_funcs = {
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e1000phy_service,
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e1000phy_status,
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e1000phy_reset
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};
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static int
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e1000phy_probe(device_t dev)
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{
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return (mii_phy_dev_probe(dev, e1000phys, BUS_PROBE_DEFAULT));
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}
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static int
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e1000phy_attach(device_t dev)
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{
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struct mii_softc *sc;
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struct ifnet *ifp;
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sc = device_get_softc(dev);
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mii_phy_dev_attach(dev, MIIF_NOMANPAUSE, &e1000phy_funcs, 0);
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ifp = sc->mii_pdata->mii_ifp;
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if (strcmp(ifp->if_dname, "msk") == 0 &&
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(sc->mii_flags & MIIF_MACPRIV0) != 0)
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sc->mii_flags |= MIIF_PHYPRIV0;
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switch (sc->mii_mpd_model) {
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case MII_MODEL_xxMARVELL_E1011:
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case MII_MODEL_xxMARVELL_E1112:
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if (PHY_READ(sc, E1000_ESSR) & E1000_ESSR_FIBER_LINK)
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sc->mii_flags |= MIIF_HAVEFIBER;
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break;
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case MII_MODEL_xxMARVELL_E1149:
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case MII_MODEL_xxMARVELL_E1149R:
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/*
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* Some 88E1149 PHY's page select is initialized to
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* point to other bank instead of copper/fiber bank
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* which in turn resulted in wrong registers were
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* accessed during PHY operation. It is believed that
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* page 0 should be used for copper PHY so reinitialize
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* E1000_EADR to select default copper PHY. If parent
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* device know the type of PHY(either copper or fiber),
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* that information should be used to select default
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* type of PHY.
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*/
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PHY_WRITE(sc, E1000_EADR, 0);
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break;
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}
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PHY_RESET(sc);
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sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask;
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if (sc->mii_capabilities & BMSR_EXTSTAT)
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sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
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device_printf(dev, " ");
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mii_phy_add_media(sc);
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printf("\n");
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MIIBUS_MEDIAINIT(sc->mii_dev);
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return (0);
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}
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static void
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e1000phy_reset(struct mii_softc *sc)
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{
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uint16_t reg, page;
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reg = PHY_READ(sc, E1000_SCR);
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if ((sc->mii_flags & MIIF_HAVEFIBER) != 0) {
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reg &= ~E1000_SCR_AUTO_X_MODE;
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PHY_WRITE(sc, E1000_SCR, reg);
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if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1112) {
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/* Select 1000BASE-X only mode. */
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page = PHY_READ(sc, E1000_EADR);
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PHY_WRITE(sc, E1000_EADR, 2);
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reg = PHY_READ(sc, E1000_SCR);
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reg &= ~E1000_SCR_MODE_MASK;
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reg |= E1000_SCR_MODE_1000BX;
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PHY_WRITE(sc, E1000_SCR, reg);
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if ((sc->mii_flags & MIIF_PHYPRIV0) != 0) {
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/* Set SIGDET polarity low for SFP module. */
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PHY_WRITE(sc, E1000_EADR, 1);
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reg = PHY_READ(sc, E1000_SCR);
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reg |= E1000_SCR_FIB_SIGDET_POLARITY;
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PHY_WRITE(sc, E1000_SCR, reg);
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}
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PHY_WRITE(sc, E1000_EADR, page);
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}
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} else {
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switch (sc->mii_mpd_model) {
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case MII_MODEL_xxMARVELL_E1111:
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case MII_MODEL_xxMARVELL_E1112:
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case MII_MODEL_xxMARVELL_E1116:
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case MII_MODEL_xxMARVELL_E1118:
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case MII_MODEL_xxMARVELL_E1149:
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case MII_MODEL_xxMARVELL_E1149R:
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case MII_MODEL_xxMARVELL_PHYG65G:
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/* Disable energy detect mode. */
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reg &= ~E1000_SCR_EN_DETECT_MASK;
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reg |= E1000_SCR_AUTO_X_MODE;
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if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116)
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reg &= ~E1000_SCR_POWER_DOWN;
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reg |= E1000_SCR_ASSERT_CRS_ON_TX;
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break;
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case MII_MODEL_xxMARVELL_E3082:
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reg |= (E1000_SCR_AUTO_X_MODE >> 1);
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reg |= E1000_SCR_ASSERT_CRS_ON_TX;
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break;
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case MII_MODEL_xxMARVELL_E3016:
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reg |= E1000_SCR_AUTO_MDIX;
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reg &= ~(E1000_SCR_EN_DETECT |
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E1000_SCR_SCRAMBLER_DISABLE);
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reg |= E1000_SCR_LPNP;
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/* XXX Enable class A driver for Yukon FE+ A0. */
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PHY_WRITE(sc, 0x1C, PHY_READ(sc, 0x1C) | 0x0001);
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break;
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default:
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reg &= ~E1000_SCR_AUTO_X_MODE;
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reg |= E1000_SCR_ASSERT_CRS_ON_TX;
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break;
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}
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if (sc->mii_mpd_model != MII_MODEL_xxMARVELL_E3016) {
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/* Auto correction for reversed cable polarity. */
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reg &= ~E1000_SCR_POLARITY_REVERSAL;
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}
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PHY_WRITE(sc, E1000_SCR, reg);
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if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116 ||
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sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1149 ||
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sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1149R) {
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PHY_WRITE(sc, E1000_EADR, 2);
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reg = PHY_READ(sc, E1000_SCR);
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reg |= E1000_SCR_RGMII_POWER_UP;
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PHY_WRITE(sc, E1000_SCR, reg);
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PHY_WRITE(sc, E1000_EADR, 0);
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}
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}
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switch (sc->mii_mpd_model) {
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case MII_MODEL_xxMARVELL_E3082:
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case MII_MODEL_xxMARVELL_E1112:
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case MII_MODEL_xxMARVELL_E1118:
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break;
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case MII_MODEL_xxMARVELL_E1116:
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page = PHY_READ(sc, E1000_EADR);
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/* Select page 3, LED control register. */
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PHY_WRITE(sc, E1000_EADR, 3);
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PHY_WRITE(sc, E1000_SCR,
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E1000_SCR_LED_LOS(1) | /* Link/Act */
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E1000_SCR_LED_INIT(8) | /* 10Mbps */
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E1000_SCR_LED_STAT1(7) | /* 100Mbps */
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E1000_SCR_LED_STAT0(7)); /* 1000Mbps */
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/* Set blink rate. */
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PHY_WRITE(sc, E1000_IER, E1000_PULSE_DUR(E1000_PULSE_170MS) |
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E1000_BLINK_RATE(E1000_BLINK_84MS));
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PHY_WRITE(sc, E1000_EADR, page);
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break;
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case MII_MODEL_xxMARVELL_E3016:
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/* LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED. */
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PHY_WRITE(sc, 0x16, 0x0B << 8 | 0x05 << 4 | 0x04);
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/* Integrated register calibration workaround. */
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PHY_WRITE(sc, 0x1D, 17);
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PHY_WRITE(sc, 0x1E, 0x3F60);
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break;
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default:
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/* Force TX_CLK to 25MHz clock. */
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reg = PHY_READ(sc, E1000_ESCR);
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reg |= E1000_ESCR_TX_CLK_25;
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PHY_WRITE(sc, E1000_ESCR, reg);
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break;
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}
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/* Reset the PHY so all changes take effect. */
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reg = PHY_READ(sc, E1000_CR);
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reg |= E1000_CR_RESET;
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PHY_WRITE(sc, E1000_CR, reg);
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}
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static int
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e1000phy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
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{
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struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
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uint16_t speed, gig;
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int reg;
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switch (cmd) {
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case MII_POLLSTAT:
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break;
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case MII_MEDIACHG:
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/*
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* If the interface is not up, don't do anything.
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*/
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if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
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break;
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if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
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e1000phy_mii_phy_auto(sc, ife->ifm_media);
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break;
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}
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speed = 0;
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switch (IFM_SUBTYPE(ife->ifm_media)) {
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case IFM_1000_T:
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if ((sc->mii_extcapabilities &
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(EXTSR_1000TFDX | EXTSR_1000THDX)) == 0)
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return (EINVAL);
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speed = E1000_CR_SPEED_1000;
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break;
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case IFM_1000_SX:
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if ((sc->mii_extcapabilities &
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(EXTSR_1000XFDX | EXTSR_1000XHDX)) == 0)
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return (EINVAL);
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speed = E1000_CR_SPEED_1000;
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break;
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case IFM_100_TX:
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speed = E1000_CR_SPEED_100;
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break;
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case IFM_10_T:
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speed = E1000_CR_SPEED_10;
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break;
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case IFM_NONE:
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reg = PHY_READ(sc, E1000_CR);
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PHY_WRITE(sc, E1000_CR,
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reg | E1000_CR_ISOLATE | E1000_CR_POWER_DOWN);
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goto done;
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default:
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return (EINVAL);
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}
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if ((ife->ifm_media & IFM_FDX) != 0) {
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speed |= E1000_CR_FULL_DUPLEX;
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gig = E1000_1GCR_1000T_FD;
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} else
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gig = E1000_1GCR_1000T;
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reg = PHY_READ(sc, E1000_CR);
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reg &= ~E1000_CR_AUTO_NEG_ENABLE;
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PHY_WRITE(sc, E1000_CR, reg | E1000_CR_RESET);
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if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) {
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gig |= E1000_1GCR_MS_ENABLE;
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if ((ife->ifm_media & IFM_ETH_MASTER) != 0)
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gig |= E1000_1GCR_MS_VALUE;
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} else if ((sc->mii_extcapabilities &
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(EXTSR_1000TFDX | EXTSR_1000THDX)) != 0)
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gig = 0;
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PHY_WRITE(sc, E1000_1GCR, gig);
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PHY_WRITE(sc, E1000_AR, E1000_AR_SELECTOR_FIELD);
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PHY_WRITE(sc, E1000_CR, speed | E1000_CR_RESET);
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done:
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break;
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case MII_TICK:
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/*
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* Is the interface even up?
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*/
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if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
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return (0);
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/*
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* Only used for autonegotiation.
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*/
|
||||
if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
|
||||
sc->mii_ticks = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
/*
|
||||
* check for link.
|
||||
* Read the status register twice; BMSR_LINK is latch-low.
|
||||
*/
|
||||
reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
|
||||
if (reg & BMSR_LINK) {
|
||||
sc->mii_ticks = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Announce link loss right after it happens. */
|
||||
if (sc->mii_ticks++ == 0)
|
||||
break;
|
||||
if (sc->mii_ticks <= sc->mii_anegticks)
|
||||
break;
|
||||
|
||||
sc->mii_ticks = 0;
|
||||
PHY_RESET(sc);
|
||||
e1000phy_mii_phy_auto(sc, ife->ifm_media);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Update the media status. */
|
||||
PHY_STATUS(sc);
|
||||
|
||||
/* Callback if something changed. */
|
||||
mii_phy_update(sc, cmd);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static void
|
||||
e1000phy_status(struct mii_softc *sc)
|
||||
{
|
||||
struct mii_data *mii = sc->mii_pdata;
|
||||
int bmcr, bmsr, ssr;
|
||||
|
||||
mii->mii_media_status = IFM_AVALID;
|
||||
mii->mii_media_active = IFM_ETHER;
|
||||
|
||||
bmsr = PHY_READ(sc, E1000_SR) | PHY_READ(sc, E1000_SR);
|
||||
bmcr = PHY_READ(sc, E1000_CR);
|
||||
ssr = PHY_READ(sc, E1000_SSR);
|
||||
|
||||
if (bmsr & E1000_SR_LINK_STATUS)
|
||||
mii->mii_media_status |= IFM_ACTIVE;
|
||||
|
||||
if (bmcr & E1000_CR_LOOPBACK)
|
||||
mii->mii_media_active |= IFM_LOOP;
|
||||
|
||||
if ((bmcr & E1000_CR_AUTO_NEG_ENABLE) != 0 &&
|
||||
(ssr & E1000_SSR_SPD_DPLX_RESOLVED) == 0) {
|
||||
/* Erg, still trying, I guess... */
|
||||
mii->mii_media_active |= IFM_NONE;
|
||||
return;
|
||||
}
|
||||
|
||||
if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
|
||||
switch (ssr & E1000_SSR_SPEED) {
|
||||
case E1000_SSR_1000MBS:
|
||||
mii->mii_media_active |= IFM_1000_T;
|
||||
break;
|
||||
case E1000_SSR_100MBS:
|
||||
mii->mii_media_active |= IFM_100_TX;
|
||||
break;
|
||||
case E1000_SSR_10MBS:
|
||||
mii->mii_media_active |= IFM_10_T;
|
||||
break;
|
||||
default:
|
||||
mii->mii_media_active |= IFM_NONE;
|
||||
return;
|
||||
}
|
||||
} else {
|
||||
/*
|
||||
* Some fiber PHY(88E1112) does not seem to set resolved
|
||||
* speed so always assume we've got IFM_1000_SX.
|
||||
*/
|
||||
mii->mii_media_active |= IFM_1000_SX;
|
||||
}
|
||||
|
||||
if (ssr & E1000_SSR_DUPLEX) {
|
||||
mii->mii_media_active |= IFM_FDX;
|
||||
if ((sc->mii_flags & MIIF_HAVEFIBER) == 0)
|
||||
mii->mii_media_active |= mii_phy_flowstatus(sc);
|
||||
} else
|
||||
mii->mii_media_active |= IFM_HDX;
|
||||
|
||||
if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
|
||||
if (((PHY_READ(sc, E1000_1GSR) | PHY_READ(sc, E1000_1GSR)) &
|
||||
E1000_1GSR_MS_CONFIG_RES) != 0)
|
||||
mii->mii_media_active |= IFM_ETH_MASTER;
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
e1000phy_mii_phy_auto(struct mii_softc *sc, int media)
|
||||
{
|
||||
uint16_t reg;
|
||||
|
||||
if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
|
||||
reg = PHY_READ(sc, E1000_AR);
|
||||
reg &= ~(E1000_AR_PAUSE | E1000_AR_ASM_DIR);
|
||||
reg |= E1000_AR_10T | E1000_AR_10T_FD |
|
||||
E1000_AR_100TX | E1000_AR_100TX_FD;
|
||||
if ((media & IFM_FLOW) != 0 ||
|
||||
(sc->mii_flags & MIIF_FORCEPAUSE) != 0)
|
||||
reg |= E1000_AR_PAUSE | E1000_AR_ASM_DIR;
|
||||
PHY_WRITE(sc, E1000_AR, reg | E1000_AR_SELECTOR_FIELD);
|
||||
} else
|
||||
PHY_WRITE(sc, E1000_AR, E1000_FA_1000X_FD | E1000_FA_1000X);
|
||||
if ((sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0)
|
||||
PHY_WRITE(sc, E1000_1GCR,
|
||||
E1000_1GCR_1000T_FD | E1000_1GCR_1000T);
|
||||
PHY_WRITE(sc, E1000_CR,
|
||||
E1000_CR_AUTO_NEG_ENABLE | E1000_CR_RESTART_AUTO_NEG);
|
||||
|
||||
return (EJUSTRETURN);
|
||||
}
|
||||
374
freebsd/sys/dev/mii/e1000phyreg.h
Normal file
374
freebsd/sys/dev/mii/e1000phyreg.h
Normal file
@ -0,0 +1,374 @@
|
||||
/* $FreeBSD$ */
|
||||
/*-
|
||||
* Principal Author: Parag Patel
|
||||
* Copyright (c) 2001
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice unmodified, this list of conditions, and the following
|
||||
* disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* Additional Copyright (c) 2001 by Traakan Software under same licence.
|
||||
* Secondary Author: Matthew Jacob
|
||||
*/
|
||||
|
||||
/*-
|
||||
* Derived by information released by Intel under the following license:
|
||||
*
|
||||
* Copyright (c) 1999 - 2001, Intel Corporation
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Intel Corporation nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* Marvell E1000 PHY registers
|
||||
*/
|
||||
|
||||
#define E1000_MAX_REG_ADDRESS 0x1F
|
||||
|
||||
#define E1000_CR 0x00 /* control register */
|
||||
#define E1000_CR_SPEED_SELECT_MSB 0x0040
|
||||
#define E1000_CR_COLL_TEST_ENABLE 0x0080
|
||||
#define E1000_CR_FULL_DUPLEX 0x0100
|
||||
#define E1000_CR_RESTART_AUTO_NEG 0x0200
|
||||
#define E1000_CR_ISOLATE 0x0400
|
||||
#define E1000_CR_POWER_DOWN 0x0800
|
||||
#define E1000_CR_AUTO_NEG_ENABLE 0x1000
|
||||
#define E1000_CR_SPEED_SELECT_LSB 0x2000
|
||||
#define E1000_CR_LOOPBACK 0x4000
|
||||
#define E1000_CR_RESET 0x8000
|
||||
|
||||
#define E1000_CR_SPEED_1000 0x0040
|
||||
#define E1000_CR_SPEED_100 0x2000
|
||||
#define E1000_CR_SPEED_10 0x0000
|
||||
|
||||
#define E1000_SR 0x01 /* status register */
|
||||
#define E1000_SR_EXTENDED 0x0001
|
||||
#define E1000_SR_JABBER_DETECT 0x0002
|
||||
#define E1000_SR_LINK_STATUS 0x0004
|
||||
#define E1000_SR_AUTO_NEG 0x0008
|
||||
#define E1000_SR_REMOTE_FAULT 0x0010
|
||||
#define E1000_SR_AUTO_NEG_COMPLETE 0x0020
|
||||
#define E1000_SR_PREAMBLE_SUPPRESS 0x0040
|
||||
#define E1000_SR_EXTENDED_STATUS 0x0100
|
||||
#define E1000_SR_100T2 0x0200
|
||||
#define E1000_SR_100T2_FD 0x0400
|
||||
#define E1000_SR_10T 0x0800
|
||||
#define E1000_SR_10T_FD 0x1000
|
||||
#define E1000_SR_100TX 0x2000
|
||||
#define E1000_SR_100TX_FD 0x4000
|
||||
#define E1000_SR_100T4 0x8000
|
||||
|
||||
#define E1000_ID1 0x02 /* ID register 1 */
|
||||
#define E1000_ID2 0x03 /* ID register 2 */
|
||||
#define E1000_ID_88E1000 0x01410C50
|
||||
#define E1000_ID_88E1000S 0x01410C40
|
||||
#define E1000_ID_88E1011 0x01410C20
|
||||
#define E1000_ID_MASK 0xFFFFFFF0
|
||||
|
||||
#define E1000_AR 0x04 /* autonegotiation advertise reg */
|
||||
#define E1000_AR_SELECTOR_FIELD 0x0001
|
||||
#define E1000_AR_10T 0x0020
|
||||
#define E1000_AR_10T_FD 0x0040
|
||||
#define E1000_AR_100TX 0x0080
|
||||
#define E1000_AR_100TX_FD 0x0100
|
||||
#define E1000_AR_100T4 0x0200
|
||||
#define E1000_AR_PAUSE 0x0400
|
||||
#define E1000_AR_ASM_DIR 0x0800
|
||||
#define E1000_AR_REMOTE_FAULT 0x2000
|
||||
#define E1000_AR_NEXT_PAGE 0x8000
|
||||
#define E1000_AR_SPEED_MASK 0x01E0
|
||||
|
||||
/* Autonegotiation register bits for fiber cards (Alaska Only!) */
|
||||
#define E1000_FA_1000X_FD 0x0020
|
||||
#define E1000_FA_1000X 0x0040
|
||||
#define E1000_FA_SYM_PAUSE 0x0080
|
||||
#define E1000_FA_ASYM_PAUSE 0x0100
|
||||
#define E1000_FA_FAULT1 0x1000
|
||||
#define E1000_FA_FAULT2 0x2000
|
||||
#define E1000_FA_NEXT_PAGE 0x8000
|
||||
|
||||
#define E1000_LPAR 0x05 /* autoneg link partner abilities reg */
|
||||
#define E1000_LPAR_SELECTOR_FIELD 0x0001
|
||||
#define E1000_LPAR_10T 0x0020
|
||||
#define E1000_LPAR_10T_FD 0x0040
|
||||
#define E1000_LPAR_100TX 0x0080
|
||||
#define E1000_LPAR_100TX_FD 0x0100
|
||||
#define E1000_LPAR_100T4 0x0200
|
||||
#define E1000_LPAR_PAUSE 0x0400
|
||||
#define E1000_LPAR_ASM_DIR 0x0800
|
||||
#define E1000_LPAR_REMOTE_FAULT 0x2000
|
||||
#define E1000_LPAR_ACKNOWLEDGE 0x4000
|
||||
#define E1000_LPAR_NEXT_PAGE 0x8000
|
||||
|
||||
/* autoneg link partner ability register bits for fiber cards (Alaska Only!) */
|
||||
#define E1000_FPAR_1000X_FD 0x0020
|
||||
#define E1000_FPAR_1000X 0x0040
|
||||
#define E1000_FPAR_SYM_PAUSE 0x0080
|
||||
#define E1000_FPAR_ASYM_PAUSE 0x0100
|
||||
#define E1000_FPAR_FAULT1 0x1000
|
||||
#define E1000_FPAR_FAULT2 0x2000
|
||||
#define E1000_FPAR_ACK 0x4000
|
||||
#define E1000_FPAR_NEXT_PAGE 0x8000
|
||||
|
||||
#define E1000_ER 0x06 /* autoneg expansion reg */
|
||||
#define E1000_ER_LP_NWAY 0x0001
|
||||
#define E1000_ER_PAGE_RXD 0x0002
|
||||
#define E1000_ER_NEXT_PAGE 0x0004
|
||||
#define E1000_ER_LP_NEXT_PAGE 0x0008
|
||||
#define E1000_ER_PAR_DETECT_FAULT 0x0100
|
||||
|
||||
#define E1000_NPTX 0x07 /* autoneg next page TX */
|
||||
#define E1000_NPTX_MSG_CODE_FIELD 0x0001
|
||||
#define E1000_NPTX_TOGGLE 0x0800
|
||||
#define E1000_NPTX_ACKNOWLDGE2 0x1000
|
||||
#define E1000_NPTX_MSG_PAGE 0x2000
|
||||
#define E1000_NPTX_NEXT_PAGE 0x8000
|
||||
|
||||
#define E1000_RNPR 0x08 /* autoneg link-partner (?) next page */
|
||||
#define E1000_RNPR_MSG_CODE_FIELD 0x0001
|
||||
#define E1000_RNPR_TOGGLE 0x0800
|
||||
#define E1000_RNPR_ACKNOWLDGE2 0x1000
|
||||
#define E1000_RNPR_MSG_PAGE 0x2000
|
||||
#define E1000_RNPR_ACKNOWLDGE 0x4000
|
||||
#define E1000_RNPR_NEXT_PAGE 0x8000
|
||||
|
||||
#define E1000_1GCR 0x09 /* 1000T (1G) control reg */
|
||||
#define E1000_1GCR_ASYM_PAUSE 0x0080
|
||||
#define E1000_1GCR_1000T 0x0100
|
||||
#define E1000_1GCR_1000T_FD 0x0200
|
||||
#define E1000_1GCR_REPEATER_DTE 0x0400
|
||||
#define E1000_1GCR_MS_VALUE 0x0800
|
||||
#define E1000_1GCR_MS_ENABLE 0x1000
|
||||
#define E1000_1GCR_TEST_MODE_NORMAL 0x0000
|
||||
#define E1000_1GCR_TEST_MODE_1 0x2000
|
||||
#define E1000_1GCR_TEST_MODE_2 0x4000
|
||||
#define E1000_1GCR_TEST_MODE_3 0x6000
|
||||
#define E1000_1GCR_TEST_MODE_4 0x8000
|
||||
#define E1000_1GCR_SPEED_MASK 0x0300
|
||||
|
||||
#define E1000_1GSR 0x0A /* 1000T (1G) status reg */
|
||||
#define E1000_1GSR_IDLE_ERROR_CNT 0x0000
|
||||
#define E1000_1GSR_ASYM_PAUSE_DIR 0x0100
|
||||
#define E1000_1GSR_LP 0x0400
|
||||
#define E1000_1GSR_LP_FD 0x0800
|
||||
#define E1000_1GSR_REMOTE_RX_STATUS 0x1000
|
||||
#define E1000_1GSR_LOCAL_RX_STATUS 0x2000
|
||||
#define E1000_1GSR_MS_CONFIG_RES 0x4000
|
||||
#define E1000_1GSR_MS_CONFIG_FAULT 0x8000
|
||||
|
||||
#define E1000_ESR 0x0F /* IEEE extended status reg */
|
||||
#define E1000_ESR_1000T 0x1000
|
||||
#define E1000_ESR_1000T_FD 0x2000
|
||||
#define E1000_ESR_1000X 0x4000
|
||||
#define E1000_ESR_1000X_FD 0x8000
|
||||
|
||||
#define E1000_TX_POLARITY_MASK 0x0100
|
||||
#define E1000_TX_NORMAL_POLARITY 0
|
||||
|
||||
#define E1000_AUTO_POLARITY_DISABLE 0x0010
|
||||
|
||||
#define E1000_SCR 0x10 /* special control register */
|
||||
#define E1000_SCR_JABBER_DISABLE 0x0001
|
||||
#define E1000_SCR_POLARITY_REVERSAL 0x0002
|
||||
#define E1000_SCR_SQE_TEST 0x0004
|
||||
#define E1000_SCR_INT_FIFO_DISABLE 0x0008
|
||||
#define E1000_SCR_CLK125_DISABLE 0x0010
|
||||
#define E1000_SCR_MDI_MANUAL_MODE 0x0000
|
||||
#define E1000_SCR_MDIX_MANUAL_MODE 0x0020
|
||||
#define E1000_SCR_AUTO_X_1000T 0x0040
|
||||
#define E1000_SCR_AUTO_X_MODE 0x0060
|
||||
#define E1000_SCR_10BT_EXT_ENABLE 0x0080
|
||||
#define E1000_SCR_MII_5BIT_ENABLE 0x0100
|
||||
#define E1000_SCR_SCRAMBLER_DISABLE 0x0200
|
||||
#define E1000_SCR_FORCE_LINK_GOOD 0x0400
|
||||
#define E1000_SCR_ASSERT_CRS_ON_TX 0x0800
|
||||
#define E1000_SCR_RX_FIFO_DEPTH_6 0x0000
|
||||
#define E1000_SCR_RX_FIFO_DEPTH_8 0x1000
|
||||
#define E1000_SCR_RX_FIFO_DEPTH_10 0x2000
|
||||
#define E1000_SCR_RX_FIFO_DEPTH_12 0x3000
|
||||
#define E1000_SCR_TX_FIFO_DEPTH_6 0x0000
|
||||
#define E1000_SCR_TX_FIFO_DEPTH_8 0x4000
|
||||
#define E1000_SCR_TX_FIFO_DEPTH_10 0x8000
|
||||
#define E1000_SCR_TX_FIFO_DEPTH_12 0xC000
|
||||
|
||||
/* 88E3016 only */
|
||||
#define E1000_SCR_AUTO_MDIX 0x0030
|
||||
#define E1000_SCR_SIGDET_POLARITY 0x0040
|
||||
#define E1000_SCR_EXT_DISTANCE 0x0080
|
||||
#define E1000_SCR_FEFI_DISABLE 0x0100
|
||||
#define E1000_SCR_NLP_GEN_DISABLE 0x0800
|
||||
#define E1000_SCR_LPNP 0x1000
|
||||
#define E1000_SCR_NLP_CHK_DISABLE 0x2000
|
||||
#define E1000_SCR_EN_DETECT 0x4000
|
||||
|
||||
#define E1000_SCR_EN_DETECT_MASK 0x0300
|
||||
|
||||
/* 88E1112 page 1 fiber specific control */
|
||||
#define E1000_SCR_FIB_TX_DIS 0x0008
|
||||
#define E1000_SCR_FIB_SIGDET_POLARITY 0x0200
|
||||
#define E1000_SCR_FIB_FORCE_LINK 0x0400
|
||||
|
||||
/* 88E1112 page 2 */
|
||||
#define E1000_SCR_MODE_MASK 0x0380
|
||||
#define E1000_SCR_MODE_AUTO 0x0180
|
||||
#define E1000_SCR_MODE_COPPER 0x0280
|
||||
#define E1000_SCR_MODE_1000BX 0x0380
|
||||
|
||||
/* 88E1116 page 0 */
|
||||
#define E1000_SCR_POWER_DOWN 0x0004
|
||||
/* 88E1116, 88E1149 page 2 */
|
||||
#define E1000_SCR_RGMII_POWER_UP 0x0008
|
||||
|
||||
/* 88E1116, 88E1149 page 3 */
|
||||
#define E1000_SCR_LED_STAT0_MASK 0x000F
|
||||
#define E1000_SCR_LED_STAT1_MASK 0x00F0
|
||||
#define E1000_SCR_LED_INIT_MASK 0x0F00
|
||||
#define E1000_SCR_LED_LOS_MASK 0xF000
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#define E1000_SCR_LED_STAT0(x) ((x) & E1000_SCR_LED_STAT0_MASK)
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#define E1000_SCR_LED_STAT1(x) ((x) & E1000_SCR_LED_STAT1_MASK)
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#define E1000_SCR_LED_INIT(x) ((x) & E1000_SCR_LED_INIT_MASK)
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#define E1000_SCR_LED_LOS(x) ((x) & E1000_SCR_LED_LOS_MASK)
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|
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#define E1000_SSR 0x11 /* special status register */
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#define E1000_SSR_JABBER 0x0001
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#define E1000_SSR_REV_POLARITY 0x0002
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#define E1000_SSR_MDIX 0x0020
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#define E1000_SSR_LINK 0x0400
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#define E1000_SSR_SPD_DPLX_RESOLVED 0x0800
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#define E1000_SSR_PAGE_RCVD 0x1000
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#define E1000_SSR_DUPLEX 0x2000
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#define E1000_SSR_SPEED 0xC000
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#define E1000_SSR_10MBS 0x0000
|
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#define E1000_SSR_100MBS 0x4000
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#define E1000_SSR_1000MBS 0x8000
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|
||||
#define E1000_IER 0x12 /* interrupt enable reg */
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||||
#define E1000_IER_JABBER 0x0001
|
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#define E1000_IER_POLARITY_CHANGE 0x0002
|
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#define E1000_IER_MDIX_CHANGE 0x0040
|
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#define E1000_IER_FIFO_OVER_UNDERUN 0x0080
|
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#define E1000_IER_FALSE_CARRIER 0x0100
|
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#define E1000_IER_SYMBOL_ERROR 0x0200
|
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#define E1000_IER_LINK_STAT_CHANGE 0x0400
|
||||
#define E1000_IER_AUTO_NEG_COMPLETE 0x0800
|
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#define E1000_IER_PAGE_RECEIVED 0x1000
|
||||
#define E1000_IER_DUPLEX_CHANGED 0x2000
|
||||
#define E1000_IER_SPEED_CHANGED 0x4000
|
||||
#define E1000_IER_AUTO_NEG_ERR 0x8000
|
||||
|
||||
/* 88E1116, 88E1149 page 3, LED timer control. */
|
||||
#define E1000_PULSE_MASK 0x7000
|
||||
#define E1000_PULSE_NO_STR 0 /* no pulse stretching */
|
||||
#define E1000_PULSE_21MS 1 /* 21 ms to 42 ms */
|
||||
#define E1000_PULSE_42MS 2 /* 42 ms to 84 ms */
|
||||
#define E1000_PULSE_84MS 3 /* 84 ms to 170 ms */
|
||||
#define E1000_PULSE_170MS 4 /* 170 ms to 340 ms */
|
||||
#define E1000_PULSE_340MS 5 /* 340 ms to 670 ms */
|
||||
#define E1000_PULSE_670MS 6 /* 670 ms to 1300 ms */
|
||||
#define E1000_PULSE_1300MS 7 /* 1300 ms to 2700 ms */
|
||||
#define E1000_PULSE_DUR(x) ((x) & E1000_PULSE_MASK)
|
||||
|
||||
#define E1000_BLINK_MASK 0x0700
|
||||
#define E1000_BLINK_42MS 0 /* 42 ms */
|
||||
#define E1000_BLINK_84MS 1 /* 84 ms */
|
||||
#define E1000_BLINK_170MS 2 /* 170 ms */
|
||||
#define E1000_BLINK_340MS 3 /* 340 ms */
|
||||
#define E1000_BLINK_670MS 4 /* 670 ms */
|
||||
#define E1000_BLINK_RATE(x) ((x) & E1000_BLINK_MASK)
|
||||
|
||||
#define E1000_ISR 0x13 /* interrupt status reg */
|
||||
#define E1000_ISR_JABBER 0x0001
|
||||
#define E1000_ISR_POLARITY_CHANGE 0x0002
|
||||
#define E1000_ISR_MDIX_CHANGE 0x0040
|
||||
#define E1000_ISR_FIFO_OVER_UNDERUN 0x0080
|
||||
#define E1000_ISR_FALSE_CARRIER 0x0100
|
||||
#define E1000_ISR_SYMBOL_ERROR 0x0200
|
||||
#define E1000_ISR_LINK_STAT_CHANGE 0x0400
|
||||
#define E1000_ISR_AUTO_NEG_COMPLETE 0x0800
|
||||
#define E1000_ISR_PAGE_RECEIVED 0x1000
|
||||
#define E1000_ISR_DUPLEX_CHANGED 0x2000
|
||||
#define E1000_ISR_SPEED_CHANGED 0x4000
|
||||
#define E1000_ISR_AUTO_NEG_ERR 0x8000
|
||||
|
||||
#define E1000_ESCR 0x14 /* extended special control reg */
|
||||
#define E1000_ESCR_FIBER_LOOPBACK 0x4000
|
||||
#define E1000_ESCR_DOWN_NO_IDLE 0x8000
|
||||
#define E1000_ESCR_TX_CLK_2_5 0x0060
|
||||
#define E1000_ESCR_TX_CLK_25 0x0070
|
||||
#define E1000_ESCR_TX_CLK_0 0x0000
|
||||
|
||||
#define E1000_RECR 0x15 /* RX error counter reg */
|
||||
|
||||
#define E1000_EADR 0x16 /* extended address reg */
|
||||
|
||||
#define E1000_LCR 0x18 /* LED control reg */
|
||||
#define E1000_LCR_LED_TX 0x0001
|
||||
#define E1000_LCR_LED_RX 0x0002
|
||||
#define E1000_LCR_LED_DUPLEX 0x0004
|
||||
#define E1000_LCR_LINK 0x0008
|
||||
#define E1000_LCR_BLINK_42MS 0x0000
|
||||
#define E1000_LCR_BLINK_84MS 0x0100
|
||||
#define E1000_LCR_BLINK_170MS 0x0200
|
||||
#define E1000_LCR_BLINK_340MS 0x0300
|
||||
#define E1000_LCR_BLINK_670MS 0x0400
|
||||
#define E1000_LCR_PULSE_OFF 0x0000
|
||||
#define E1000_LCR_PULSE_21_42MS 0x1000
|
||||
#define E1000_LCR_PULSE_42_84MS 0x2000
|
||||
#define E1000_LCR_PULSE_84_170MS 0x3000
|
||||
#define E1000_LCR_PULSE_170_340MS 0x4000
|
||||
#define E1000_LCR_PULSE_340_670MS 0x5000
|
||||
#define E1000_LCR_PULSE_670_13S 0x6000
|
||||
#define E1000_LCR_PULSE_13_26S 0x7000
|
||||
|
||||
/* The following register is found only on the 88E1011 Alaska PHY */
|
||||
#define E1000_ESSR 0x1B /* Extended PHY specific sts */
|
||||
#define E1000_ESSR_FIBER_LINK 0x2000
|
||||
#define E1000_ESSR_GMII_COPPER 0x000f
|
||||
#define E1000_ESSR_GMII_FIBER 0x0007
|
||||
#define E1000_ESSR_TBI_COPPER 0x000d
|
||||
#define E1000_ESSR_TBI_FIBER 0x0005
|
||||
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Reference in New Issue
Block a user