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Update to FreeBSD head 2019-09-24

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Git mirror commit 6b0307a0a5184339393f555d5d424190d8a8277a.
This commit is contained in:
Sebastian Huber
2019-09-24 11:05:03 +02:00
parent 83afe13399
commit a5ddb0ea69
903 changed files with 39332 additions and 17958 deletions
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37
freebsd/sys/powerpc/include/machine/cpufunc.h
View File

@@ -212,6 +212,43 @@ get_pcpu(void)
return (ret);
}
/* "NOP" operations to signify priorities to the kernel. */
static __inline void
nop_prio_vlow(void)
{
__asm __volatile("or 31,31,31");
}
static __inline void
nop_prio_low(void)
{
__asm __volatile("or 1,1,1");
}
static __inline void
nop_prio_mlow(void)
{
__asm __volatile("or 6,6,6");
}
static __inline void
nop_prio_medium(void)
{
__asm __volatile("or 2,2,2");
}
static __inline void
nop_prio_mhigh(void)
{
__asm __volatile("or 5,5,5");
}
static __inline void
nop_prio_high(void)
{
__asm __volatile("or 3,3,3");
}
#endif /* _KERNEL */
#endif /* !_MACHINE_CPUFUNC_H_ */

2
freebsd/sys/powerpc/include/machine/intr_machdep.h
View File

@@ -54,7 +54,7 @@ u_int powerpc_get_irq(uint32_t, u_int);
void powerpc_dispatch_intr(u_int, struct trapframe *);
int powerpc_enable_intr(void);
int powerpc_setup_intr(const char *, u_int, driver_filter_t, driver_intr_t,
void *, enum intr_type, void **);
void *, enum intr_type, void **, int);
int powerpc_teardown_intr(void *);
int powerpc_bind_intr(u_int irq, u_char cpu);
int powerpc_config_intr(int, enum intr_trigger, enum intr_polarity);

62
freebsd/sys/powerpc/include/machine/spr.h
View File

@@ -93,11 +93,12 @@
#define SPR_MQ 0x000 /* .6. 601 MQ register */
#define SPR_XER 0x001 /* 468 Fixed Point Exception Register */
#define SPR_DSCR 0x003 /* .6. Data Stream Control Register (Unprivileged) */
#define SPR_RTCU_R 0x004 /* .6. 601 RTC Upper - Read */
#define SPR_RTCL_R 0x005 /* .6. 601 RTC Lower - Read */
#define SPR_LR 0x008 /* 468 Link Register */
#define SPR_CTR 0x009 /* 468 Count Register */
#define SPR_DSCR 0x011 /* Data Stream Control Register */
#define SPR_DSCRP 0x011 /* Data Stream Control Register (Privileged) */
#define SPR_DSISR 0x012 /* .68 DSI exception source */
#define DSISR_DIRECT 0x80000000 /* Direct-store error exception */
#define DSISR_NOTFOUND 0x40000000 /* Translation not found */
@@ -122,19 +123,27 @@
#define SPR_EID 0x051 /* ..8 Exception Interrupt ??? */
#define SPR_NRI 0x052 /* ..8 Exception Interrupt ??? */
#define SPR_FSCR 0x099 /* Facility Status and Control Register */
#define FSCR_IC_MASK 0xFF00000000000000ULL /* FSCR[0:7] is Interrupt Cause */
#define FSCR_IC_FP 0x0000000000000000ULL /* FP unavailable */
#define FSCR_IC_VSX 0x0100000000000000ULL /* VSX unavailable */
#define FSCR_IC_DSCR 0x0200000000000000ULL /* Access to the DSCR at SPRs 3 or 17 */
#define FSCR_IC_PM 0x0300000000000000ULL /* Read or write access of a Performance Monitor SPR in group A */
#define FSCR_IC_BHRB 0x0400000000000000ULL /* Execution of a BHRB Instruction */
#define FSCR_IC_HTM 0x0500000000000000ULL /* Access to a Transactional Memory */
#define FSCR_IC_MASK 0xFF00000000000000ULL /* FSCR[0:7] is Interrupt Cause */
#define FSCR_IC_FP 0x0000000000000000ULL /* FP unavailable */
#define FSCR_IC_VSX 0x0100000000000000ULL /* VSX unavailable */
#define FSCR_IC_DSCR 0x0200000000000000ULL /* Access to the DSCR at SPRs 3 or 17 */
#define FSCR_IC_PM 0x0300000000000000ULL /* Read or write access of a Performance Monitor SPR in group A */
#define FSCR_IC_BHRB 0x0400000000000000ULL /* Execution of a BHRB Instruction */
#define FSCR_IC_HTM 0x0500000000000000ULL /* Access to a Transactional Memory */
/* Reserved 0x0600000000000000ULL */
#define FSCR_IC_EBB 0x0700000000000000ULL /* Access to Event-Based Branch */
#define FSCR_IC_TAR 0x0800000000000000ULL /* Access to Target Address Register */
#define FSCR_IC_STOP 0x0900000000000000ULL /* Access to the 'stop' instruction in privileged non-hypervisor state */
#define FSCR_IC_MSG 0x0A00000000000000ULL /* Access to 'msgsndp' or 'msgclrp' instructions */
#define FSCR_IC_SCV 0x0C00000000000000ULL /* Execution of a 'scv' instruction */
#define FSCR_IC_EBB 0x0700000000000000ULL /* Access to Event-Based Branch */
#define FSCR_IC_TAR 0x0800000000000000ULL /* Access to Target Address Register */
#define FSCR_IC_STOP 0x0900000000000000ULL /* Access to the 'stop' instruction in privileged non-hypervisor state */
#define FSCR_IC_MSG 0x0A00000000000000ULL /* Access to 'msgsndp' or 'msgclrp' instructions */
#define FSCR_IC_LM 0x0A00000000000000ULL /* Access to load monitored facility */
#define FSCR_IC_SCV 0x0C00000000000000ULL /* Execution of a 'scv' instruction */
#define FSCR_SCV 0x0000000000001000 /* scv instruction available */
#define FSCR_LM 0x0000000000000800 /* Load monitored facilities available */
#define FSCR_MSGP 0x0000000000000400 /* msgsndp and SPRs available */
#define FSCR_TAR 0x0000000000000100 /* TAR register available */
#define FSCR_EBB 0x0000000000000080 /* Event-based branch available */
#define FSCR_DSCR 0x0000000000000004 /* DSCR available in PR state */
#define SPR_DPDES 0x0b0 /* .6. Directed Privileged Doorbell Exception State Register */
#define SPR_USPRG0 0x100 /* 4.. User SPR General 0 */
#define SPR_VRSAVE 0x100 /* .6. AltiVec VRSAVE */
#define SPR_SPRG0 0x110 /* 468 SPR General 0 */
@@ -188,6 +197,7 @@
#define IBMPOWERPCA2 0x0049
#define IBMPOWER7PLUS 0x004a
#define IBMPOWER8E 0x004b
#define IBMPOWER8NVL 0x004c
#define IBMPOWER8 0x004d
#define IBMPOWER9 0x004e
#define MPC860 0x0050
@@ -242,7 +252,10 @@
#define LPCR_PECE_ME (1ULL << 12) /* Machine Check and Hypervisor */
/* Maintenance exceptions */
#define SPR_LPID 0x13f /* Logical Partitioning Control */
#define SPR_HMER 0x150 /* Hypervisor Maintenance Exception Register */
#define SPR_HMEER 0x151 /* Hypervisor Maintenance Exception Enable Register */
#define SPR_TIR 0x1be /* .6. Thread Identification Register */
#define SPR_PTCR 0x1d0 /* Partition Table Control Register */
#define SPR_SPEFSCR 0x200 /* ..8 Signal Processing Engine FSCR. */
#define SPEFSCR_SOVH 0x80000000
@@ -403,6 +416,16 @@
#define SPR_MD_TWC 0x31d /* ..8 DMMU tablewalk control */
#define SPR_MD_RPN 0x31e /* ..8 DMMU real (phys) page number */
#define SPR_MD_TW 0x31f /* ..8 MMU tablewalk scratch */
#define SPR_BESCRS 0x320 /* .6. Branch Event Status and Control Set Register */
#define SPR_BESCRSU 0x321 /* .6. Branch Event Status and Control Set Register (upper 32-bit) */
#define SPR_BESCRR 0x322 /* .6. Branch Event Status and Control Reset Register */
#define SPR_BESCRRU 0x323 /* .6. Branch Event Status and Control Register (upper 32-bit) */
#define SPR_EBBHR 0x324 /* .6. Event-based Branch Handler Register */
#define SPR_EBBRR 0x325 /* .6. Event-based Branch Return Register */
#define SPR_BESCR 0x326 /* .6. Branch Event Status and Control Register */
#define SPR_LMRR 0x32d /* .6. Load Monitored Region Register */
#define SPR_LMSER 0x32e /* .6. Load Monitored Section Enable Register */
#define SPR_TAR 0x32f /* .6. Branch Target Address Register */
#define SPR_MI_CAM 0x330 /* ..8 IMMU CAM entry read */
#define SPR_MI_RAM0 0x331 /* ..8 IMMU RAM entry read reg 0 */
#define SPR_MI_RAM1 0x332 /* ..8 IMMU RAM entry read reg 1 */
@@ -410,6 +433,19 @@
#define SPR_MD_RAM0 0x339 /* ..8 IMMU RAM entry read reg 0 */
#define SPR_MD_RAM1 0x33a /* ..8 IMMU RAM entry read reg 1 */
#define SPR_PSSCR 0x357 /* Processor Stop Status and Control Register (ISA 3.0) */
#define PSSCR_PLS_S 60
#define PSSCR_PLS_M (0xf << PSSCR_PLS_S)
#define PSSCR_SD (1 << 22)
#define PSSCR_ESL (1 << 21)
#define PSSCR_EC (1 << 20)
#define PSSCR_PSLL_S 16
#define PSSCR_PSLL_M (0xf << PSSCR_PSLL_S)
#define PSSCR_TR_S 8
#define PSSCR_TR_M (0x3 << PSSCR_TR_S)
#define PSSCR_MTL_S 4
#define PSSCR_MTL_M (0xf << PSSCR_MTL_S)
#define PSSCR_RL_S 0
#define PSSCR_RL_M (0xf << PSSCR_RL_S)
#define SPR_PMCR 0x374 /* Processor Management Control Register */
#define SPR_UMMCR2 0x3a0 /* .6. User Monitor Mode Control Register 2 */
#define SPR_UMMCR0 0x3a8 /* .6. User Monitor Mode Control Register 0 */