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https://git.rtems.org/rtems-libbsd/
synced 2025-06-28 17:49:33 +08:00
parent
0323c286e3
commit
a8a9cf1847
@ -81,6 +81,8 @@ __FBSDID("$FreeBSD$");
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#include <net/if_types.h>
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#include <net/if_var.h>
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#include <net/if_vlan_var.h>
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#include <netinet/in.h>
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#include <netinet/ip.h>
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#include <dev/ffec/if_ffecreg.h>
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#include <dev/ofw/ofw_bus.h>
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@ -620,7 +622,9 @@ ffec_encap(struct ifnet *ifp, struct ffec_softc *sc, struct mbuf *m0,
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int error, i, nsegs;
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struct ffec_bufmap *bmap;
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uint32_t tx_idx;
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int csum_flags;
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uint32_t flags;
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uint32_t flags2;
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FFEC_ASSERT_LOCKED(sc);
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@ -653,6 +657,27 @@ ffec_encap(struct ifnet *ifp, struct ffec_softc *sc, struct mbuf *m0,
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#endif /* __rtems__ */
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bmap->mbuf = m0;
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flags2 = FEC_TXDESC_INT;
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csum_flags = m0->m_pkthdr.csum_flags;
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if ((csum_flags & CSUM_IP) != 0) {
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struct mbuf *n;
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int off;
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int off2;
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struct ip *ip;
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flags2 |= FEC_TXDESC_IINS;
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n = m_getptr(m0, sizeof(struct ether_header), &off);
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ip = (struct ip *)mtodo(n, off);
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ip->ip_sum = 0;
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off2 = m0->m_pkthdr.csum_data;
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if ((csum_flags & (CSUM_TCP | CSUM_UDP)) != 0 && off2 != 0) {
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flags2 |= FEC_TXDESC_PINS;
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*(uint16_t *)((caddr_t)(ip + 1) + off2) = 0;
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}
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}
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/*
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* Fill in the TX descriptors back to front so that READY bit in first
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* descriptor is set last.
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@ -666,6 +691,7 @@ ffec_encap(struct ifnet *ifp, struct ffec_softc *sc, struct mbuf *m0,
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tx_idx = prev_txidx(tx_idx);;
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tx_desc = &sc->txdesc_ring[tx_idx];
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tx_desc->buf_paddr = segs[i].ds_addr;
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tx_desc->flags2 = flags2;
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#ifdef __rtems__
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rtems_cache_flush_multiple_data_lines((void *)segs[i].ds_addr,
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segs[i].ds_len);
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@ -793,6 +819,7 @@ ffec_setup_rxdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr)
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*/
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nidx = next_rxidx(idx);
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sc->rxdesc_ring[idx].buf_paddr = (uint32_t)paddr;
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sc->rxdesc_ring[idx].flags2 = FEC_RXDESC_INT;
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wmb();
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sc->rxdesc_ring[idx].flags_len = FEC_RXDESC_EMPTY |
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((nidx == 0) ? FEC_RXDESC_WRAP : 0);
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@ -851,7 +878,7 @@ ffec_alloc_mbufcl(struct ffec_softc *sc)
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}
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static void
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ffec_rxfinish_onebuf(struct ffec_softc *sc, int len)
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ffec_rxfinish_onebuf(struct ffec_softc *sc, int len, uint32_t flags2)
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{
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struct mbuf *m, *newmbuf;
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struct ffec_bufmap *bmap;
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@ -898,6 +925,12 @@ ffec_rxfinish_onebuf(struct ffec_softc *sc, int len)
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m->m_pkthdr.len = len;
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m->m_pkthdr.rcvif = sc->ifp;
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if ((flags2 & (FEC_RXDESC_ICE | FEC_RXDESC_PCR)) == 0) {
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m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID |
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CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
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m->m_pkthdr.csum_data = 0xffff;
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}
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if (sc->fectype & FECFLAG_RACC) {
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/* We use the RACC[SHIFT16] feature */
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m->m_data = mtod(m, uint8_t *) + 2;
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@ -973,7 +1006,7 @@ ffec_rxfinish_locked(struct ffec_softc *sc)
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/*
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* Normal case: a good frame all in one buffer.
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*/
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ffec_rxfinish_onebuf(sc, len);
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ffec_rxfinish_onebuf(sc, len, desc->flags2);
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}
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sc->rx_idx = next_rxidx(sc->rx_idx);
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}
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@ -1305,6 +1338,7 @@ ffec_init_locked(struct ffec_softc *sc)
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regval |= FEC_ECR_DBSWP;
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#endif
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regval |= FEC_ECR_ETHEREN;
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regval |= FEC_ECR_EN1588;
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WR4(sc, FEC_ECR_REG, regval);
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ifp->if_drv_flags |= IFF_DRV_RUNNING;
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@ -1962,8 +1996,10 @@ ffec_attach(device_t dev)
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ifp->if_softc = sc;
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if_initname(ifp, device_get_name(dev), device_get_unit(dev));
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ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
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ifp->if_capabilities = IFCAP_VLAN_MTU;
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ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6 |
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IFCAP_VLAN_MTU;
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ifp->if_capenable = ifp->if_capabilities;
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ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP;
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ifp->if_start = ffec_txstart;
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ifp->if_ioctl = ffec_ioctl;
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ifp->if_init = ffec_init;
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@ -295,6 +295,11 @@ struct ffec_hwdesc
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{
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uint32_t flags_len;
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uint32_t buf_paddr;
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uint32_t flags2;
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uint32_t hlen_proto;
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uint32_t bdu;
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uint32_t ts;
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uint32_t res[2];
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};
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#define FEC_TXDESC_READY (1U << 31)
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@ -306,6 +311,11 @@ struct ffec_hwdesc
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#define FEC_TXDESC_ABC (1 << 25)
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#define FEC_TXDESC_LEN_MASK (0xffff)
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#define FEC_TXDESC_INT (1 << 30)
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#define FEC_TXDESC_TS (1 << 29)
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#define FEC_TXDESC_PINS (1 << 28)
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#define FEC_TXDESC_IINS (1 << 27)
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#define FEC_RXDESC_EMPTY (1U << 31)
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#define FEC_RXDESC_R01 (1 << 30)
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#define FEC_RXDESC_WRAP (1 << 29)
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@ -321,6 +331,10 @@ struct ffec_hwdesc
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#define FEC_RXDESC_TR (1 << 16)
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#define FEC_RXDESC_LEN_MASK (0xffff)
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#define FEC_RXDESC_INT (1 << 23)
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#define FEC_RXDESC_ICE (1 << 5)
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#define FEC_RXDESC_PCR (1 << 4)
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#define FEC_RXDESC_ERROR_BITS (FEC_RXDESC_LG | FEC_RXDESC_NO | \
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FEC_RXDESC_OV | FEC_RXDESC_TR)
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