rtems/rtems-libbsd
1
0
Fork 0
mirror of https://git.rtems.org/rtems-libbsd/ synced 2025-10-16 08:02:13 +08:00
Code Issues Packages Projects Releases Wiki Activity

if_dwc: Add Altera Cyclone V support

Browse Source
This commit is contained in:
Sebastian Huber
2015-03-26 15:39:18 +01:00
parent 6b176ce668
commit aee6864330
3 changed files with 25 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
rtemsbsd/include/machine/rtems-bsd-cache.h
View File

@@ -44,7 +44,8 @@
#if defined(LIBBSP_ARM_LPC24XX_BSP_H)
/* No cache */
#elif defined(LIBBSP_ARM_XILINX_ZYNQ_BSP_H)
#elif defined(LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H) || \
defined(LIBBSP_ARM_XILINX_ZYNQ_BSP_H)
/* With cache, no coherency support in hardware */
#define CPU_DATA_CACHE_ALIGNMENT 32
#elif defined(LIBBSP_ARM_LPC32XX_BSP_H)