if_dwc: Add Altera Cyclone V support

This commit is contained in:
Sebastian Huber
2015-03-26 15:39:18 +01:00
parent 6b176ce668
commit aee6864330
3 changed files with 25 additions and 2 deletions

View File

@@ -90,6 +90,26 @@ SYSINIT_DRIVER_REFERENCE(e1000phy, miibus);
#elif defined(LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H)
#include <bsp/socal/hps.h>
#include <bsp/irq.h>
static const rtems_bsd_device_resource dwc0_res[] = {
{
.type = RTEMS_BSD_RES_MEMORY,
.start_request = 0,
.start_actual = (unsigned long)ALT_EMAC1_ADDR
}, {
.type = RTEMS_BSD_RES_IRQ,
.start_request = 0,
.start_actual = ALT_INT_INTERRUPT_EMAC1_IRQ
}
};
RTEMS_BSD_DEFINE_NEXUS_DEVICE(dwc, 0, RTEMS_ARRAY_SIZE(dwc0_res),
&dwc0_res[0]);
SYSINIT_DRIVER_REFERENCE(micphy, miibus);
RTEMS_BSD_DEFINE_NEXUS_DEVICE(dw_mmc, 0, 0, NULL);
SYSINIT_DRIVER_REFERENCE(mmc, dw_mmc);

View File

@@ -44,7 +44,8 @@
#if defined(LIBBSP_ARM_LPC24XX_BSP_H)
/* No cache */
#elif defined(LIBBSP_ARM_XILINX_ZYNQ_BSP_H)
#elif defined(LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H) || \
defined(LIBBSP_ARM_XILINX_ZYNQ_BSP_H)
/* With cache, no coherency support in hardware */
#define CPU_DATA_CACHE_ALIGNMENT 32
#elif defined(LIBBSP_ARM_LPC32XX_BSP_H)

View File

@@ -34,7 +34,9 @@
#include <bsp.h>
#if defined(LIBBSP_ARM_REALVIEW_PBX_A9_BSP_H)
#if defined(LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H)
#define NET_CFG_INTERFACE_0 "dwc0"
#elif defined(LIBBSP_ARM_REALVIEW_PBX_A9_BSP_H)
#define NET_CFG_INTERFACE_0 "smc0"
#elif defined(LIBBSP_ARM_XILINX_ZYNQ_BSP_H)
#define NET_CFG_INTERFACE_0 "cgem0"