Update to FreeBSD 8.4

This commit is contained in:
Sebastian Huber
2013-11-04 11:33:00 +01:00
parent 6779ce55bc
commit af5333e0a0
486 changed files with 66546 additions and 41281 deletions

View File

@@ -61,7 +61,9 @@ __FBSDID("$FreeBSD$");
static MALLOC_DEFINE(M_LEGACYDEV, "legacydrv", "legacy system device");
struct legacy_device {
int lg_pcibus;
int lg_pcibus;
int lg_pcislot;
int lg_pcifunc;
};
#define DEVTOAT(dev) ((struct legacy_device *)device_get_ivars(dev))
@@ -89,6 +91,7 @@ static device_method_t legacy_methods[] = {
DEVMETHOD(bus_read_ivar, legacy_read_ivar),
DEVMETHOD(bus_write_ivar, legacy_write_ivar),
DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
DEVMETHOD(bus_release_resource, bus_generic_release_resource),
DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
@@ -184,6 +187,8 @@ legacy_add_child(device_t bus, u_int order, const char *name, int unit)
if (atdev == NULL)
return(NULL);
atdev->lg_pcibus = -1;
atdev->lg_pcislot = -1;
atdev->lg_pcifunc = -1;
child = device_add_child_ordered(bus, order, name, unit);
if (child == NULL)
@@ -207,6 +212,12 @@ legacy_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
case LEGACY_IVAR_PCIBUS:
*result = atdev->lg_pcibus;
break;
case LEGACY_IVAR_PCISLOT:
*result = atdev->lg_pcislot;
break;
case LEGACY_IVAR_PCIFUNC:
*result = atdev->lg_pcifunc;
break;
default:
return ENOENT;
}
@@ -225,6 +236,12 @@ legacy_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
case LEGACY_IVAR_PCIBUS:
atdev->lg_pcibus = value;
break;
case LEGACY_IVAR_PCISLOT:
atdev->lg_pcislot = value;
break;
case LEGACY_IVAR_PCIFUNC:
atdev->lg_pcifunc = value;
break;
default:
return ENOENT;
}
@@ -260,19 +277,17 @@ static device_method_t cpu_methods[] = {
/* Bus interface */
DEVMETHOD(bus_add_child, cpu_add_child),
DEVMETHOD(bus_read_ivar, cpu_read_ivar),
DEVMETHOD(bus_print_child, bus_generic_print_child),
DEVMETHOD(bus_get_resource_list, cpu_get_rlist),
DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
DEVMETHOD(bus_alloc_resource, bus_generic_rl_alloc_resource),
DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
DEVMETHOD(bus_driver_added, bus_generic_driver_added),
DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
{ 0, 0 }
DEVMETHOD_END
};
static driver_t cpu_driver = {
@@ -294,12 +309,11 @@ cpu_identify(driver_t *driver, device_t parent)
* so that these devices are attached after the Host-PCI
* bridges (which are added at order 100).
*/
for (i = 0; i <= mp_maxid; i++)
if (!CPU_ABSENT(i)) {
child = BUS_ADD_CHILD(parent, 150, "cpu", i);
if (child == NULL)
panic("legacy_attach cpu");
}
CPU_FOREACH(i) {
child = BUS_ADD_CHILD(parent, 150, "cpu", i);
if (child == NULL)
panic("legacy_attach cpu");
}
}
static device_t

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@@ -147,6 +147,13 @@ cpu_mwait(int extensions, int hints)
__asm __volatile("mwait;" : :"a" (hints), "c" (extensions));
}
static __inline void
lfence(void)
{
__asm __volatile("lfence" : : : "memory");
}
static __inline void
mfence(void)
{

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@@ -60,10 +60,10 @@
* - 1 ??? dummy counter.
* - 2 counters for each I/O interrupt.
* - 1 counter for each CPU for lapic timer.
* - 7 counters for each CPU for IPI counters for SMP.
* - 9 counters for each CPU for IPI counters for SMP.
*/
#ifdef SMP
#define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + (1 + 7) * MAXCPU)
#define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + (1 + 9) * MAXCPU)
#else
#define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + 1)
#endif
@@ -94,7 +94,7 @@ struct pic {
int (*pic_config_intr)(struct intsrc *, enum intr_trigger,
enum intr_polarity);
int (*pic_assign_cpu)(struct intsrc *, u_int apic_id);
STAILQ_ENTRY(pic) pics;
TAILQ_ENTRY(pic) pics;
};
/* Flags for pic_disable_source() */

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@@ -31,7 +31,9 @@
enum legacy_device_ivars {
LEGACY_IVAR_PCIDOMAIN,
LEGACY_IVAR_PCIBUS
LEGACY_IVAR_PCIBUS,
LEGACY_IVAR_PCISLOT,
LEGACY_IVAR_PCIFUNC
};
#define LEGACY_ACCESSOR(var, ivar, type) \
@@ -39,6 +41,8 @@ enum legacy_device_ivars {
LEGACY_ACCESSOR(pcidomain, PCIDOMAIN, uint32_t)
LEGACY_ACCESSOR(pcibus, PCIBUS, uint32_t)
LEGACY_ACCESSOR(pcislot, PCISLOT, int)
LEGACY_ACCESSOR(pcifunc, PCIFUNC, int)
#undef LEGACY_ACCESSOR
@@ -53,5 +57,7 @@ int legacy_pcib_write_ivar(device_t dev, device_t child, int which,
uintptr_t value);
struct resource *legacy_pcib_alloc_resource(device_t dev, device_t child,
int type, int *rid, u_long start, u_long end, u_long count, u_int flags);
int legacy_pcib_map_msi(device_t pcib, device_t dev, int irq,
uint64_t *addr, uint32_t *data);
#endif /* !_MACHINE_LEGACYVAR_H_ */

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@@ -66,6 +66,7 @@
#define CR4_PCE 0x00000100 /* Performance monitoring counter enable */
#define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */
#define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */
#define CR4_XSAVE 0x00040000 /* XSETBV/XGETBV */
/*
* Bits in AMD64 special registers. EFER is 64 bits wide.
@@ -120,6 +121,7 @@
#define CPUID2_TM2 0x00000100
#define CPUID2_SSSE3 0x00000200
#define CPUID2_CNXTID 0x00000400
#define CPUID2_FMA 0x00001000
#define CPUID2_CX16 0x00002000
#define CPUID2_XTPR 0x00004000
#define CPUID2_PDCM 0x00008000
@@ -130,7 +132,23 @@
#define CPUID2_X2APIC 0x00200000
#define CPUID2_MOVBE 0x00400000
#define CPUID2_POPCNT 0x00800000
#define CPUID2_TSCDLT 0x01000000
#define CPUID2_AESNI 0x02000000
#define CPUID2_XSAVE 0x04000000
#define CPUID2_OSXSAVE 0x08000000
#define CPUID2_AVX 0x10000000
#define CPUID2_F16C 0x20000000
#define CPUID2_RDRAND 0x40000000
#define CPUID2_HV 0x80000000
/*
* Important bits in the Thermal and Power Management flags
* CPUID.6 EAX and ECX.
*/
#define CPUTPM1_SENSOR 0x00000001
#define CPUTPM1_TURBO 0x00000002
#define CPUTPM1_ARAT 0x00000004
#define CPUTPM2_EFFREQ 0x00000001
/*
* Important bits in the AMD extended cpuid flags
@@ -157,9 +175,14 @@
#define AMDID2_PREFETCH 0x00000100
#define AMDID2_OSVW 0x00000200
#define AMDID2_IBS 0x00000400
#define AMDID2_SSE5 0x00000800
#define AMDID2_XOP 0x00000800
#define AMDID2_SKINIT 0x00001000
#define AMDID2_WDT 0x00002000
#define AMDID2_LWP 0x00008000
#define AMDID2_FMA4 0x00010000
#define AMDID2_NODE_ID 0x00080000
#define AMDID2_TBM 0x00200000
#define AMDID2_TOPOLOGY 0x00400000
/*
* CPUID instruction 1 eax info
@@ -205,11 +228,14 @@
#define AMDPM_100MHZ_STEPS 0x00000040
#define AMDPM_HW_PSTATE 0x00000080
#define AMDPM_TSC_INVARIANT 0x00000100
#define AMDPM_CPB 0x00000200
/*
* AMD extended function 8000_0008h ecx info
*/
#define AMDID_CMP_CORES 0x000000ff
#define AMDID_COREID_SIZE 0x0000f000
#define AMDID_COREID_SIZE_SHIFT 12
/*
* CPUID manufacturers identifiers
@@ -245,6 +271,8 @@
#define MSR_BIOS_SIGN 0x08b
#define MSR_PERFCTR0 0x0c1
#define MSR_PERFCTR1 0x0c2
#define MSR_MPERF 0x0e7
#define MSR_APERF 0x0e8
#define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */
#define MSR_MTRRcap 0x0fe
#define MSR_BBL_CR_ADDR 0x116
@@ -553,7 +581,8 @@
#define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */
/* AMD64 MSR's */
#define MSR_EFER 0xc0000080 /* extended features */
#define MSR_EFER 0xc0000080 /* extended features */
#define MSR_HWCR 0xc0010015
#define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */
#define MSR_MC0_CTL_MASK 0xc0010044

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@@ -37,6 +37,7 @@ __FBSDID("$FreeBSD$");
#include <sys/kernel.h>
#include <sys/malloc.h>
#include <sys/module.h>
#include <sys/rman.h>
#include <sys/sysctl.h>
#include <dev/pci/pcivar.h>
@@ -112,14 +113,28 @@ legacy_pcib_alloc_msix(device_t pcib, device_t dev, int *irq)
return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq));
}
static int
int
legacy_pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
uint32_t *data)
{
device_t bus;
device_t bus, hostb;
int error, func, slot;
bus = device_get_parent(pcib);
return (PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data));
error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data);
if (error)
return (error);
slot = legacy_get_pcislot(pcib);
func = legacy_get_pcifunc(pcib);
if (slot == -1 || func == -1)
return (0);
hostb = pci_find_bsf(0, slot, func);
KASSERT(hostb != NULL, ("%s: missing hostb for 0:%d:%d", __func__,
slot, func));
pci_ht_map_msi(hostb, *addr);
return (0);
}
static const char *
@@ -444,6 +459,8 @@ legacy_pcib_identify(driver_t *driver, device_t parent)
"pcib", busnum);
device_set_desc(child, s);
legacy_set_pcibus(child, busnum);
legacy_set_pcislot(child, slot);
legacy_set_pcifunc(child, func);
found = 1;
if (id == 0x12258086)
@@ -577,10 +594,10 @@ static device_method_t legacy_pcib_methods[] = {
DEVMETHOD(device_resume, bus_generic_resume),
/* Bus interface */
DEVMETHOD(bus_print_child, bus_generic_print_child),
DEVMETHOD(bus_read_ivar, legacy_pcib_read_ivar),
DEVMETHOD(bus_write_ivar, legacy_pcib_write_ivar),
DEVMETHOD(bus_alloc_resource, legacy_pcib_alloc_resource),
DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
DEVMETHOD(bus_release_resource, bus_generic_release_resource),
DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
@@ -598,7 +615,7 @@ static device_method_t legacy_pcib_methods[] = {
DEVMETHOD(pcib_release_msix, pcib_release_msix),
DEVMETHOD(pcib_map_msi, legacy_pcib_map_msi),
{ 0, 0 }
DEVMETHOD_END
};
static devclass_t hostb_devclass;
@@ -673,7 +690,6 @@ static device_method_t pcibios_pcib_pci_methods[] = {
DEVMETHOD(device_resume, bus_generic_resume),
/* Bus interface */
DEVMETHOD(bus_print_child, bus_generic_print_child),
DEVMETHOD(bus_read_ivar, pcib_read_ivar),
DEVMETHOD(bus_write_ivar, pcib_write_ivar),
DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
@@ -694,7 +710,7 @@ static device_method_t pcibios_pcib_pci_methods[] = {
DEVMETHOD(pcib_release_msix, pcib_release_msix),
DEVMETHOD(pcib_map_msi, pcib_map_msi),
{0, 0}
DEVMETHOD_END
};
static devclass_t pcib_devclass;