mirror of
https://git.rtems.org/rtems-libbsd/
synced 2025-07-26 10:59:44 +08:00
if_cgem: Add support for ZynqMP CGEM
This is a port of the latest patch in FreeBSD that adds support for 64bit CGEMs as used in ZynqMP. This does not include the work necessary for support on RISC-V systems.
This commit is contained in:
Kinsey Moore
Joel Sherrill
parent
0c60fe524e
commit
b7a12cc8f9
@ -81,6 +81,10 @@ __FBSDID("$FreeBSD$");
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#if defined(__LP64__) || defined(__ILP32__)
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#define CGEM64
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#endif
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#include <dev/cadence/if_cgem_hw.h>
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#include <rtems/bsd/local/miibus_if.h>
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@ -127,8 +131,14 @@ struct cgem_softc {
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void *intrhand;
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struct callout tick_ch;
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uint32_t net_ctl_shadow;
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#ifdef __rtems__
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uint32_t net_cfg_shadow;
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int neednullqs;
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#endif /* __rtems__ */
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int ref_clk_num;
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#ifndef __rtems__
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u_char eaddr[6];
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#endif /* __rtems__ */
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bus_dma_tag_t desc_dma_tag;
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bus_dma_tag_t mbuf_dma_tag;
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@ -161,12 +171,18 @@ struct cgem_softc {
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int txring_hd_ptr; /* where to put next xmits */
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int txring_tl_ptr; /* next xmit mbuf to free */
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int txring_queued; /* num xmits segs queued */
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#ifndef __rtems__
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bus_dmamap_t txring_dma_map;
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#endif /* __rtems__ */
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u_int txfull; /* tx ring full events */
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u_int txdefrags; /* tx calls to m_defrag() */
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u_int txdefragfails; /* tx m_defrag() failures */
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u_int txdmamapfails; /* tx dmamap failures */
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/* null descriptor rings */
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void *null_qs;
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bus_addr_t null_qs_physaddr;
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/* hardware provided statistics */
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struct cgem_hw_stats {
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uint64_t tx_bytes;
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@ -337,7 +353,11 @@ cgem_rx_filter(struct cgem_softc *sc)
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hash_hi = 0;
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hash_lo = 0;
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#ifdef __rtems__
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net_cfg = sc->net_cfg_shadow;
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#else
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net_cfg = RD4(sc, CGEM_NET_CFG);
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#endif
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net_cfg &= ~(CGEM_NET_CFG_MULTI_HASH_EN |
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CGEM_NET_CFG_NO_BCAST |
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@ -379,6 +399,9 @@ cgem_rx_filter(struct cgem_softc *sc)
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WR4(sc, CGEM_HASH_TOP, hash_hi);
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WR4(sc, CGEM_HASH_BOT, hash_lo);
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#ifdef __rtems__
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sc->net_cfg_shadow = net_cfg;
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#endif /* __rtems__ */
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WR4(sc, CGEM_NET_CFG, net_cfg);
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}
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@ -392,24 +415,87 @@ cgem_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
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*(bus_addr_t *)arg = segs[0].ds_addr;
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}
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#ifdef __rtems__
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/* Set up null queues for priority queues we actually can't disable. */
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static void
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cgem_null_qs(struct cgem_softc *sc)
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{
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struct cgem_rx_desc *rx_desc;
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struct cgem_tx_desc *tx_desc;
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uint32_t queue_mask;
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int n;
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/* Read design config register 6 to determine number of queues. */
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queue_mask = (RD4(sc, CGEM_DESIGN_CFG6) &
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CGEM_DESIGN_CFG6_DMA_PRIO_Q_MASK) >> 1;
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if (queue_mask == 0)
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return;
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/* Create empty RX queue and empty TX buf queues. */
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memset(sc->null_qs, 0, sizeof(struct cgem_rx_desc) +
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sizeof(struct cgem_tx_desc));
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rx_desc = sc->null_qs;
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rx_desc->addr = CGEM_RXDESC_OWN | CGEM_RXDESC_WRAP;
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tx_desc = (struct cgem_tx_desc *)(rx_desc + 1);
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tx_desc->ctl = CGEM_TXDESC_USED | CGEM_TXDESC_WRAP;
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/* Point all valid ring base pointers to the null queues. */
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for (n = 1; (queue_mask & 1) != 0; n++, queue_mask >>= 1) {
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WR4(sc, CGEM_RX_QN_BAR(n), sc->null_qs_physaddr);
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WR4(sc, CGEM_TX_QN_BAR(n), sc->null_qs_physaddr +
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sizeof(struct cgem_rx_desc));
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}
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}
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#endif /* __rtems__ */
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/* Create DMA'able descriptor rings. */
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static int
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cgem_setup_descs(struct cgem_softc *sc)
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{
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int i, err;
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#ifdef __rtems__
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int desc_rings_size = CGEM_NUM_RX_DESCS * sizeof(struct cgem_rx_desc) +
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CGEM_NUM_TX_DESCS * sizeof(struct cgem_tx_desc);
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if (sc->neednullqs)
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desc_rings_size += sizeof(struct cgem_rx_desc) +
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sizeof(struct cgem_tx_desc);
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#endif /* __rtems__ */
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sc->txring = NULL;
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sc->rxring = NULL;
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/* Allocate non-cached DMA space for RX and TX descriptors.
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*/
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#ifndef __rtems__
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err = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0,
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BUS_SPACE_MAXADDR_32BIT,
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#else /* __rtems__ */
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err = bus_dma_tag_create(bus_get_dma_tag(sc->dev),
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#if defined(__LP64__)
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8,
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1ULL << 32, /* Do not cross a 4G boundary. */
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BUS_SPACE_MAXADDR,
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#elif defined(__ILP32__)
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8,
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0,
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BUS_SPACE_MAXADDR,
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#else /* ARMv7 */
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1,
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0,
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BUS_SPACE_MAXADDR_32BIT,
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#endif /* ARMv7 */
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#endif /* __rtems__ */
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BUS_SPACE_MAXADDR,
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NULL, NULL,
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#ifndef __rtems__
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MAX_DESC_RING_SIZE,
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1,
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MAX_DESC_RING_SIZE,
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#else /* __rtems__ */
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desc_rings_size,
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1,
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desc_rings_size,
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#endif /* __rtems__ */
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0,
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busdma_lock_mutex,
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&sc->sc_mtx,
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@ -418,8 +504,19 @@ cgem_setup_descs(struct cgem_softc *sc)
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return (err);
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/* Set up a bus_dma_tag for mbufs. */
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#ifndef __rtems__
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err = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0,
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BUS_SPACE_MAXADDR_32BIT,
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#else /* __rtems__ */
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err = bus_dma_tag_create(bus_get_dma_tag(sc->dev),
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#ifdef CGEM64
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8,
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#else
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1,
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#endif
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0,
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BUS_SPACE_MAXADDR,
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#endif /* __rtems__ */
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BUS_SPACE_MAXADDR,
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NULL, NULL,
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MCLBYTES,
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@ -435,7 +532,11 @@ cgem_setup_descs(struct cgem_softc *sc)
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/* Allocate DMA memory in non-cacheable space. */
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err = bus_dmamem_alloc(sc->desc_dma_tag,
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(void **)&sc->rxring,
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#ifndef __rtems__
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BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
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#else /* __rtems__ */
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BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO,
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#endif /* __rtems__ */
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&sc->rxring_dma_map);
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if (err)
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return (err);
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@ -443,7 +544,11 @@ cgem_setup_descs(struct cgem_softc *sc)
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/* Load descriptor DMA memory. */
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err = bus_dmamap_load(sc->desc_dma_tag, sc->rxring_dma_map,
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(void *)sc->rxring,
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#ifndef __rtems__
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CGEM_NUM_RX_DESCS*sizeof(struct cgem_rx_desc),
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#else /* __rtems__ */
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desc_rings_size,
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#endif /* __rtems__ */
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cgem_getaddr, &sc->rxring_physaddr,
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BUS_DMA_NOWAIT);
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if (err)
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@ -464,6 +569,7 @@ cgem_setup_descs(struct cgem_softc *sc)
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sc->rxring_tl_ptr = 0;
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sc->rxring_queued = 0;
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#ifndef __rtems__
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/* Allocate DMA memory for TX descriptors in non-cacheable space. */
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err = bus_dmamem_alloc(sc->desc_dma_tag,
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(void **)&sc->txring,
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@ -480,6 +586,11 @@ cgem_setup_descs(struct cgem_softc *sc)
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BUS_DMA_NOWAIT);
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if (err)
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return (err);
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#else /* __rtems__ */
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sc->txring = (struct cgem_tx_desc *)(sc->rxring + CGEM_NUM_RX_DESCS);
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sc->txring_physaddr = sc->rxring_physaddr + CGEM_NUM_RX_DESCS *
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sizeof(struct cgem_rx_desc);
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#endif /* __rtems__ */
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/* Initialize TX descriptor ring. */
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for (i = 0; i < CGEM_NUM_TX_DESCS; i++) {
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@ -496,6 +607,16 @@ cgem_setup_descs(struct cgem_softc *sc)
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sc->txring_tl_ptr = 0;
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sc->txring_queued = 0;
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#ifdef __rtems__
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if (sc->neednullqs) {
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sc->null_qs = (void *)(sc->txring + CGEM_NUM_TX_DESCS);
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sc->null_qs_physaddr = sc->txring_physaddr +
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CGEM_NUM_TX_DESCS * sizeof(struct cgem_tx_desc);
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cgem_null_qs(sc);
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}
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#endif /* __rtems__ */
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return (0);
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}
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@ -556,6 +677,13 @@ cgem_fill_rqueue(struct cgem_softc *sc)
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/* Write rx descriptor and increment head pointer. */
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sc->rxring[sc->rxring_hd_ptr].ctl = 0;
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#ifdef __rtems__
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#if defined(__LP64__)
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sc->rxring[sc->rxring_hd_ptr].addrhi = segs[0].ds_addr >> 32;
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#elif defined(__ILP32__)
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sc->rxring[sc->rxring_hd_ptr].addrhi = 0;
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#endif
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#endif /* __rtems__ */
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if (sc->rxring_hd_ptr == CGEM_NUM_RX_DESCS - 1) {
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sc->rxring[sc->rxring_hd_ptr].addr = segs[0].ds_addr |
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CGEM_RXDESC_WRAP;
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@ -709,9 +837,16 @@ cgem_clean_tx(struct cgem_softc *sc)
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/* Check the status. */
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if ((ctl & CGEM_TXDESC_AHB_ERR) != 0) {
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/* Serious bus error. log to console. */
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#if defined(__LP64__) && defined(__rtems__)
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device_printf(sc->dev,
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"cgem_clean_tx: AHB error, addr=0x%x%08x\n",
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sc->txring[sc->txring_tl_ptr].addrhi,
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sc->txring[sc->txring_tl_ptr].addr);
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#else
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device_printf(sc->dev, "cgem_clean_tx: Whoa! "
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"AHB error, addr=0x%x\n",
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sc->txring[sc->txring_tl_ptr].addr);
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#endif
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} else if ((ctl & (CGEM_TXDESC_RETRY_ERR |
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CGEM_TXDESC_LATE_COLL)) != 0) {
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if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, 1);
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@ -879,6 +1014,14 @@ cgem_start_locked(if_t ifp)
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/* Descriptor address. */
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sc->txring[sc->txring_hd_ptr + i].addr =
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segs[i].ds_addr;
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#ifdef __rtems__
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#ifdef defined(__LP64__)
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sc->txring[sc->txring_hd_ptr + i].addrhi =
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segs[i].ds_addr >> 32;
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#elif defined(__ILP32__)
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sc->txring[sc->txring_hd_ptr + i].addrhi = 0;
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#endif
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#endif /* __rtems__ */
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/* Descriptor control word. */
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ctl = segs[i].ds_len;
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@ -1081,7 +1224,11 @@ cgem_reset(struct cgem_softc *sc)
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CGEM_ASSERT_LOCKED(sc);
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WR4(sc, CGEM_NET_CTRL, 0);
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#ifndef __rtems__
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WR4(sc, CGEM_NET_CFG, 0);
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#else
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WR4(sc, CGEM_NET_CFG, sc->net_cfg_shadow);
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#endif
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WR4(sc, CGEM_NET_CTRL, CGEM_NET_CTRL_CLR_STAT_REGS);
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WR4(sc, CGEM_TX_STAT, CGEM_TX_STAT_ALL);
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WR4(sc, CGEM_RX_STAT, CGEM_RX_STAT_ALL);
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@ -1092,9 +1239,31 @@ cgem_reset(struct cgem_softc *sc)
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WR4(sc, CGEM_RX_QBAR, 0);
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/* Get management port running even if interface is down. */
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#ifndef __rtems__
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WR4(sc, CGEM_NET_CFG,
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CGEM_NET_CFG_DBUS_WIDTH_32 |
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CGEM_NET_CFG_MDC_CLK_DIV_64);
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#else
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/* Determine data bus width from design configuration register. */
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switch (RD4(sc, CGEM_DESIGN_CFG1) &
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CGEM_DESIGN_CFG1_DMA_BUS_WIDTH_MASK) {
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case CGEM_DESIGN_CFG1_DMA_BUS_WIDTH_64:
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sc->net_cfg_shadow = CGEM_NET_CFG_DBUS_WIDTH_64;
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break;
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case CGEM_DESIGN_CFG1_DMA_BUS_WIDTH_128:
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sc->net_cfg_shadow = CGEM_NET_CFG_DBUS_WIDTH_128;
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break;
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default:
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sc->net_cfg_shadow = CGEM_NET_CFG_DBUS_WIDTH_32;
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}
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#ifdef CGEM64
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sc->net_cfg_shadow |= CGEM_NET_CFG_MDC_CLK_DIV_48;
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#else
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sc->net_cfg_shadow |= CGEM_NET_CFG_MDC_CLK_DIV_64;
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#endif
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WR4(sc, CGEM_NET_CFG, sc->net_cfg_shadow);
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#endif /* __rtems__ */
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sc->net_ctl_shadow = CGEM_NET_CTRL_MGMT_PORT_EN;
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WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow);
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@ -1112,8 +1281,14 @@ cgem_config(struct cgem_softc *sc)
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CGEM_ASSERT_LOCKED(sc);
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/* Program Net Config Register. */
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#ifndef __rtems__
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net_cfg = CGEM_NET_CFG_DBUS_WIDTH_32 |
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CGEM_NET_CFG_MDC_CLK_DIV_64 |
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#else /* __rtems__ */
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sc->net_cfg_shadow &= (CGEM_NET_CFG_MDC_CLK_DIV_MASK |
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CGEM_NET_CFG_DBUS_WIDTH_MASK);
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net_cfg = sc->net_cfg_shadow |
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#endif /* __rtems__ */
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CGEM_NET_CFG_FCS_REMOVE |
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CGEM_NET_CFG_RX_BUF_OFFSET(ETHER_ALIGN) |
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CGEM_NET_CFG_GIGE_EN |
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@ -1125,6 +1300,9 @@ cgem_config(struct cgem_softc *sc)
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if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
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net_cfg |= CGEM_NET_CFG_RX_CHKSUM_OFFLD_EN;
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#ifdef __rtems__
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sc->net_cfg_shadow = net_cfg;
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#endif /* __rtems__ */
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WR4(sc, CGEM_NET_CFG, net_cfg);
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/* Program DMA Config Register. */
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@ -1132,6 +1310,9 @@ cgem_config(struct cgem_softc *sc)
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CGEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL_8K |
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CGEM_DMA_CFG_TX_PKTBUF_MEMSZ_SEL |
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CGEM_DMA_CFG_AHB_FIXED_BURST_LEN_16 |
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#if defined(CGEM64) && defined(__rtems__)
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CGEM_DMA_CFG_ADDR_BUS_64 |
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#endif
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CGEM_DMA_CFG_DISC_WHEN_NO_AHB;
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/* Enable transmit checksum offloading? */
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@ -1143,6 +1324,13 @@ cgem_config(struct cgem_softc *sc)
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/* Write the rx and tx descriptor ring addresses to the QBAR regs. */
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WR4(sc, CGEM_RX_QBAR, (uint32_t) sc->rxring_physaddr);
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WR4(sc, CGEM_TX_QBAR, (uint32_t) sc->txring_physaddr);
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#if defined(__LP64__) && defined(__rtems__)
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WR4(sc, CGEM_RX_QBAR_HI, (uint32_t)(sc->rxring_physaddr >> 32));
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WR4(sc, CGEM_TX_QBAR_HI, (uint32_t)(sc->txring_physaddr >> 32));
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#elif defined(__ILP32__) && defined(__rtems__)
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WR4(sc, CGEM_RX_QBAR_HI, 0);
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WR4(sc, CGEM_TX_QBAR_HI, 0);
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#endif
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/* Enable rx and tx. */
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sc->net_ctl_shadow |= (CGEM_NET_CTRL_TX_EN | CGEM_NET_CTRL_RX_EN);
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@ -1176,8 +1364,14 @@ cgem_init_locked(struct cgem_softc *sc)
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if_setdrvflagbits(sc->ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
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#ifdef __rtems__
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if (sc->miibus != NULL) {
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#endif /* __rtems__ */
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mii = device_get_softc(sc->miibus);
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mii_mediachg(mii);
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#ifdef __rtems__
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}
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#endif /* __rtems__ */
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callout_reset(&sc->tick_ch, hz, cgem_tick, sc);
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}
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@ -1297,6 +1491,10 @@ cgem_ioctl(if_t ifp, u_long cmd, caddr_t data)
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case SIOCSIFMEDIA:
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case SIOCGIFMEDIA:
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#ifdef __rtems__
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if (sc->miibus == NULL)
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return (ENXIO);
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#endif /* __rtems__ */
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mii = device_get_softc(sc->miibus);
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error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
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break;
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@ -1331,16 +1529,28 @@ cgem_ioctl(if_t ifp, u_long cmd, caddr_t data)
|
||||
/* Turn on RX checksumming. */
|
||||
if_setcapenablebit(ifp, IFCAP_RXCSUM |
|
||||
IFCAP_RXCSUM_IPV6, 0);
|
||||
#ifndef __rtems__
|
||||
WR4(sc, CGEM_NET_CFG,
|
||||
RD4(sc, CGEM_NET_CFG) |
|
||||
CGEM_NET_CFG_RX_CHKSUM_OFFLD_EN);
|
||||
#else /* __rtems__ */
|
||||
sc->net_cfg_shadow |=
|
||||
CGEM_NET_CFG_RX_CHKSUM_OFFLD_EN;
|
||||
WR4(sc, CGEM_NET_CFG, sc->net_cfg_shadow);
|
||||
#endif /* __rtems__ */
|
||||
} else {
|
||||
/* Turn off RX checksumming. */
|
||||
if_setcapenablebit(ifp, 0, IFCAP_RXCSUM |
|
||||
IFCAP_RXCSUM_IPV6);
|
||||
#ifndef __rtems__
|
||||
WR4(sc, CGEM_NET_CFG,
|
||||
RD4(sc, CGEM_NET_CFG) &
|
||||
~CGEM_NET_CFG_RX_CHKSUM_OFFLD_EN);
|
||||
#else /* __rtems__ */
|
||||
sc->net_cfg_shadow &=
|
||||
~CGEM_NET_CFG_RX_CHKSUM_OFFLD_EN;
|
||||
WR4(sc, CGEM_NET_CFG, sc->net_cfg_shadow);
|
||||
#endif /* __rtems__ */
|
||||
}
|
||||
}
|
||||
if ((if_getcapenable(ifp) & (IFCAP_RXCSUM | IFCAP_TXCSUM)) ==
|
||||
@ -1361,6 +1571,7 @@ cgem_ioctl(if_t ifp, u_long cmd, caddr_t data)
|
||||
|
||||
/* MII bus support routines.
|
||||
*/
|
||||
#ifndef __rtems__
|
||||
static void
|
||||
cgem_child_detached(device_t dev, device_t child)
|
||||
{
|
||||
@ -1369,6 +1580,7 @@ cgem_child_detached(device_t dev, device_t child)
|
||||
if (child == sc->miibus)
|
||||
sc->miibus = NULL;
|
||||
}
|
||||
#endif /* __rtems__ */
|
||||
|
||||
static int
|
||||
cgem_ifmedia_upd(if_t ifp)
|
||||
@ -1514,7 +1726,11 @@ cgem_mediachange(struct cgem_softc *sc, struct mii_data *mii)
|
||||
CGEM_ASSERT_LOCKED(sc);
|
||||
|
||||
/* Update hardware to reflect media. */
|
||||
#ifndef __rtems__
|
||||
net_cfg = RD4(sc, CGEM_NET_CFG);
|
||||
#else /* __rtems__ */
|
||||
net_cfg = sc->net_cfg_shadow;
|
||||
#endif /* __rtems__ */
|
||||
net_cfg &= ~(CGEM_NET_CFG_SPEED100 | CGEM_NET_CFG_GIGE_EN |
|
||||
CGEM_NET_CFG_FULL_DUPLEX);
|
||||
|
||||
@ -1535,6 +1751,9 @@ cgem_mediachange(struct cgem_softc *sc, struct mii_data *mii)
|
||||
if ((mii->mii_media_active & IFM_FDX) != 0)
|
||||
net_cfg |= CGEM_NET_CFG_FULL_DUPLEX;
|
||||
|
||||
#ifdef __rtems__
|
||||
sc->net_cfg_shadow = net_cfg;
|
||||
#endif /* __rtems__ */
|
||||
WR4(sc, CGEM_NET_CFG, net_cfg);
|
||||
|
||||
/* Set the reference clock if necessary. */
|
||||
@ -1809,7 +2028,17 @@ cgem_attach(device_t dev)
|
||||
|
||||
sc->if_old_flags = if_getflags(ifp);
|
||||
sc->rxbufs = DEFAULT_NUM_RX_BUFS;
|
||||
#if defined(CGEM64) && defined(__rtems__)
|
||||
uint32_t design_cfg6 = RD4(sc, CGEM_DESIGN_CFG6);
|
||||
/*
|
||||
* QEMU does not have PBUF_CUTTHRU defined and is broken when trying
|
||||
* to use nullqs
|
||||
*/
|
||||
if ((design_cfg6 & CGEM_DESIGN_CFG6_PBUF_CUTTHRU))
|
||||
sc->neednullqs = 1;
|
||||
#else
|
||||
sc->rxhangwar = 1;
|
||||
#endif
|
||||
|
||||
/* Reset hardware. */
|
||||
CGEM_LOCK(sc);
|
||||
@ -1901,10 +2130,18 @@ cgem_detach(device_t dev)
|
||||
bus_dmamap_unload(sc->desc_dma_tag,
|
||||
sc->rxring_dma_map);
|
||||
sc->rxring_physaddr = 0;
|
||||
#ifdef __rtems__
|
||||
sc->txring_physaddr = 0;
|
||||
sc->null_qs_physaddr = 0;
|
||||
#endif /* __rtems__ */
|
||||
}
|
||||
bus_dmamem_free(sc->desc_dma_tag, sc->rxring,
|
||||
sc->rxring_dma_map);
|
||||
sc->rxring = NULL;
|
||||
#ifdef __rtems__
|
||||
sc->txring = NULL;
|
||||
sc->null_qs = NULL;
|
||||
#endif /* __rtems__ */
|
||||
#ifndef __rtems__
|
||||
for (i = 0; i < CGEM_NUM_RX_DESCS; i++)
|
||||
if (sc->rxring_m_dmamap[i] != NULL) {
|
||||
@ -1912,7 +2149,6 @@ cgem_detach(device_t dev)
|
||||
sc->rxring_m_dmamap[i]);
|
||||
sc->rxring_m_dmamap[i] = NULL;
|
||||
}
|
||||
#endif /* __rtems__ */
|
||||
}
|
||||
if (sc->txring != NULL) {
|
||||
if (sc->txring_physaddr != 0) {
|
||||
@ -1923,7 +2159,6 @@ cgem_detach(device_t dev)
|
||||
bus_dmamem_free(sc->desc_dma_tag, sc->txring,
|
||||
sc->txring_dma_map);
|
||||
sc->txring = NULL;
|
||||
#ifndef __rtems__
|
||||
for (i = 0; i < CGEM_NUM_TX_DESCS; i++)
|
||||
if (sc->txring_m_dmamap[i] != NULL) {
|
||||
bus_dmamap_destroy(sc->mbuf_dma_tag,
|
||||
@ -1954,8 +2189,10 @@ static device_method_t cgem_methods[] = {
|
||||
DEVMETHOD(device_attach, cgem_attach),
|
||||
DEVMETHOD(device_detach, cgem_detach),
|
||||
|
||||
#ifndef __rtems__
|
||||
/* Bus interface */
|
||||
DEVMETHOD(bus_child_detached, cgem_child_detached),
|
||||
#endif /* __rtems__ */
|
||||
|
||||
/* MII interface */
|
||||
DEVMETHOD(miibus_readreg, cgem_miibus_readreg),
|
||||
|
||||
@ -77,6 +77,7 @@
|
||||
#define CGEM_NET_CFG_MDC_CLK_DIV_16 (1<<18)
|
||||
#define CGEM_NET_CFG_MDC_CLK_DIV_32 (2<<18)
|
||||
#define CGEM_NET_CFG_MDC_CLK_DIV_48 (3<<18)
|
||||
/* Higher MDC clock divs are reserved values on 64bit hardware */
|
||||
#define CGEM_NET_CFG_MDC_CLK_DIV_64 (4<<18)
|
||||
#define CGEM_NET_CFG_MDC_CLK_DIV_96 (5<<18)
|
||||
#define CGEM_NET_CFG_MDC_CLK_DIV_128 (6<<18)
|
||||
@ -113,6 +114,7 @@
|
||||
#define CGEM_USER_IO 0x00C /* User I/O */
|
||||
|
||||
#define CGEM_DMA_CFG 0x010 /* DMA Config */
|
||||
#define CGEM_DMA_CFG_ADDR_BUS_64 (1 << 30)
|
||||
#define CGEM_DMA_CFG_DISC_WHEN_NO_AHB (1<<24)
|
||||
#define CGEM_DMA_CFG_RX_BUF_SIZE_SHIFT 16
|
||||
#define CGEM_DMA_CFG_RX_BUF_SIZE_MASK (0xff<<16)
|
||||
@ -290,6 +292,29 @@
|
||||
#define CGEM_PTP_PEER_RX_S 0x1F8 /* PTP Peer Event rcv'd s */
|
||||
#define CGEM_PTP_PEER_RX_NS 0x1FC /* PTP Peer Event rcv'd ns */
|
||||
|
||||
#define CGEM_DESIGN_CFG1 0x280 /* Design Configuration 1 */
|
||||
#define CGEM_DESIGN_CFG1_AXI_CACHE_WIDTH_MASK (0xfU << 28)
|
||||
#define CGEM_DESIGN_CFG1_DMA_BUS_WIDTH_MASK (7 << 25)
|
||||
#define CGEM_DESIGN_CFG1_DMA_BUS_WIDTH_32 (1 << 25)
|
||||
#define CGEM_DESIGN_CFG1_DMA_BUS_WIDTH_64 (2 << 25)
|
||||
#define CGEM_DESIGN_CFG1_DMA_BUS_WIDTH_128 (4 << 25)
|
||||
#define CGEM_DESIGN_CFG1_IRQ_READ_CLR (1 << 23)
|
||||
#define CGEM_DESIGN_CFG1_NO_SNAPSHOT (1 << 22)
|
||||
#define CGEM_DESIGN_CFG1_NO_STATS (1 << 21)
|
||||
#define CGEM_DESIGN_CFG1_NO_SCAN_PINS (1 << 20)
|
||||
#define CGEM_DESIGN_CFG1_USER_IN_WIDTH_MASK (0x1f << 15)
|
||||
#define CGEM_DESIGN_CFG1_USER_OUT_WIDTH_MASK (0x1f << 10)
|
||||
#define CGEM_DESIGN_CFG1_USER_IO (1 << 9)
|
||||
#define CGEM_DESIGN_CFG1_APB_REV2 (1 << 8)
|
||||
#define CGEM_DESIGN_CFG1_APB_REV1 (1 << 7)
|
||||
#define CGEM_DESIGN_CFG1_EXT_FIFO_INTERFACE (1 << 6)
|
||||
#define CGEM_DESIGN_CFG1_NO_INT_LOOPBACK (1 << 5)
|
||||
#define CGEM_DESIGN_CFG1_INT_LOOPBACK (1 << 4)
|
||||
#define CGEM_DESIGN_CFG1_TDC_50 (1 << 3)
|
||||
#define CGEM_DESIGN_CFG1_RDC_50 (1 << 2)
|
||||
#define CGEM_DESIGN_CFG1_SERDES (1 << 1)
|
||||
#define CGEM_DESIGN_CFG1_NO_PCS (1 << 0)
|
||||
|
||||
#define CGEM_DESIGN_CFG2 0x284 /* Design Configuration 2 */
|
||||
#define CGEM_DESIGN_CFG2_TX_PBUF_ADDR_SHIFT 26
|
||||
#define CGEM_DESIGN_CFG2_TX_PBUF_ADDR_MASK (0xf<<26)
|
||||
@ -330,6 +355,18 @@
|
||||
#define CGEM_DESIGN_CFG5_TX_FIFO_CNT_WIDTH_MASK (0xf<<4)
|
||||
#define CGEM_DESIGN_CFG5_RX_FIFO_CNT_WIDTH_MASK 0xf
|
||||
|
||||
#define CGEM_DESIGN_CFG6 0x294 /* Design Configuration 6 */
|
||||
#define CGEM_DESIGN_CFG6_PBUF_CUTTHRU (1 << 25) /* 64-bit addr cap */
|
||||
#define CGEM_DESIGN_CFG6_ADDR_64B (1 << 23) /* 64-bit addr cap */
|
||||
#define CGEM_DESIGN_CFG6_DMA_PRIO_Q_MASK 0xfffe
|
||||
#define CGEM_DESIGN_CFG6_DMA_PRIO_Q(n) (1 << (n))
|
||||
|
||||
#define CGEM_TX_QN_BAR(n) (0x440 + ((n) - 1) * 4)
|
||||
#define CGEM_RX_QN_BAR(n) (0x480 + ((n) - 1) * 4)
|
||||
|
||||
#define CGEM_TX_QBAR_HI 0x4C8
|
||||
#define CGEM_RX_QBAR_HI 0x4D4
|
||||
|
||||
/* Transmit Descriptors */
|
||||
struct cgem_tx_desc {
|
||||
uint32_t addr;
|
||||
@ -350,6 +387,10 @@ struct cgem_tx_desc {
|
||||
#define CGEM_TXDESC_NO_CRC_APPENDED (1<<16)
|
||||
#define CGEM_TXDESC_LAST_BUF (1<<15) /* last buf in frame */
|
||||
#define CGEM_TXDESC_LENGTH_MASK 0x3fff
|
||||
#if defined(CGEM64) && defined(__rtems__)
|
||||
uint32_t addrhi;
|
||||
uint32_t unused;
|
||||
#endif
|
||||
};
|
||||
|
||||
struct cgem_rx_desc {
|
||||
@ -379,6 +420,10 @@ struct cgem_rx_desc {
|
||||
#define CGEM_RXDESC_SOF (1<<14) /* start of frame */
|
||||
#define CGEM_RXDESC_BAD_FCS (1<<13)
|
||||
#define CGEM_RXDESC_LENGTH_MASK 0x1fff
|
||||
#if defined(CGEM64) && defined(__rtems__)
|
||||
uint32_t addrhi;
|
||||
uint32_t unused;
|
||||
#endif
|
||||
};
|
||||
|
||||
#endif /* _IF_CGEM_HW_H_ */
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user