mirror of
https://git.rtems.org/rtems-libbsd/
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at91_mci: Import from FreeBSD
This commit is contained in:
Sebastian Huber
parent
589220752b
commit
ea5880a3cc
1408
freebsd/sys/arm/at91/at91_mci.c
Normal file
1408
freebsd/sys/arm/at91/at91_mci.c
Normal file
File diff suppressed because it is too large
Load Diff
156
freebsd/sys/arm/at91/at91_mcireg.h
Normal file
156
freebsd/sys/arm/at91/at91_mcireg.h
Normal file
@ -0,0 +1,156 @@
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/*-
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* Copyright (c) 2006 Berndt Walter. All rights reserved.
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* Copyright (c) 2006 M. Warner Losh. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* $FreeBSD$ */
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#ifndef ARM_AT91_AT91_MCIREG_H
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#define ARM_AT91_AT91_MCIREG_H
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#define MMC_MAX 30
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#define MCI_CR 0x00 /* MCI Control Register */
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#define MCI_MR 0x04 /* MCI Mode Register */
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#define MCI_DTOR 0x08 /* MCI Data Timeout Register */
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#define MCI_SDCR 0x0c /* MCI SD Card Register */
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#define MCI_ARGR 0x10 /* MCI Argument Register */
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#define MCI_CMDR 0x14 /* MCI Command Register */
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#define MCI_RSPR 0x20 /* MCI Response Registers - 4 of them */
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#define MCI_RDR 0x30 /* MCI Receive Data Register */
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#define MCI_TDR 0x34 /* MCI Transmit Data Register */
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#define MCI_SR 0x40 /* MCI Status Register */
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#define MCI_IER 0x44 /* MCI Interrupt Enable Register */
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#define MCI_IDR 0x48 /* MCI Interrupt Disable Register */
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#define MCI_IMR 0x4c /* MCI Interrupt Mask Register */
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/* -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- */
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#define MCI_CR_MCIEN (0x1u << 0) /* (MCI) Multimedia Interface Enable */
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#define MCI_CR_MCIDIS (0x1u << 1) /* (MCI) Multimedia Interface Disable */
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#define MCI_CR_PWSEN (0x1u << 2) /* (MCI) Power Save Mode Enable */
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#define MCI_CR_PWSDIS (0x1u << 3) /* (MCI) Power Save Mode Disable */
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#define MCI_CR_SWRST (0x1u << 7) /* (MCI) Software Reset */
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/* -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- */
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#define MCI_MR_CLKDIV (0xffu << 0) /* (MCI) Clock Divider */
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#define MCI_MR_PWSDIV (0x3fu << 8) /* (MCI) Power Saving Divider */
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#define MCI_MR_RDPROOF (0x1u << 11) /* (MCI) Read Proof Enable */
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#define MCI_MR_WRPROOF (0x1u << 12) /* (MCI) Write Proof Enable */
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#define MCI_MR_PDCFBYTE (0x1u << 13) /* (MCI) PDC Force Byte Transfer */
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#define MCI_MR_PDCPADV (0x1u << 14) /* (MCI) PDC Padding Value */
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#define MCI_MR_PDCMODE (0x1u << 15) /* (MCI) PDC Oriented Mode */
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#define MCI_MR_BLKLEN 0x3fff0000ul /* (MCI) Data Block Length */
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/* -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- */
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#define MCI_DTOR_DTOCYC (0xfu << 0) /* (MCI) Data Timeout Cycle Number */
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#define MCI_DTOR_DTOMUL (0x7u << 4) /* (MCI) Data Timeout Multiplier */
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#define MCI_DTOR_DTOMUL_1 (0x0u << 4) /* (MCI) DTOCYC x 1 */
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#define MCI_DTOR_DTOMUL_16 (0x1u << 4) /* (MCI) DTOCYC x 16 */
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#define MCI_DTOR_DTOMUL_128 (0x2u << 4) /* (MCI) DTOCYC x 128 */
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#define MCI_DTOR_DTOMUL_256 (0x3u << 4) /* (MCI) DTOCYC x 256 */
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#define MCI_DTOR_DTOMUL_1k (0x4u << 4) /* (MCI) DTOCYC x 1024 */
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#define MCI_DTOR_DTOMUL_4k (0x5u << 4) /* (MCI) DTOCYC x 4096 */
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#define MCI_DTOR_DTOMUL_64k (0x6u << 4) /* (MCI) DTOCYC x 65536 */
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#define MCI_DTOR_DTOMUL_1M (0x7u << 4) /* (MCI) DTOCYC x 1048576 */
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/* -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- */
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#define MCI_SDCR_SDCSEL (0x1u << 0) /* (MCI) SD Card Selector */
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#define MCI_SDCR_SDCBUS (0x1u << 7) /* (MCI) SD Card Bus Width */
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/* -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- */
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#define MCI_CMDR_CMDNB (0x1Fu << 0) /* (MCI) Command Number */
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#define MCI_CMDR_RSPTYP (0x3u << 6) /* (MCI) Response Type */
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#define MCI_CMDR_RSPTYP_NO (0x0u << 6) /* (MCI) No response */
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#define MCI_CMDR_RSPTYP_48 (0x1u << 6) /* (MCI) 48-bit response */
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#define MCI_CMDR_RSPTYP_136 (0x2u << 6) /* (MCI) 136-bit response */
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#define MCI_CMDR_SPCMD (0x7u << 8) /* (MCI) Special CMD */
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#define MCI_CMDR_SPCMD_NONE (0x0u << 8) /* (MCI) Not a special CMD */
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#define MCI_CMDR_SPCMD_INIT (0x1u << 8) /* (MCI) Initialization CMD */
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#define MCI_CMDR_SPCMD_SYNC (0x2u << 8) /* (MCI) Synchronized CMD */
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#define MCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /* (MCI) Interrupt command */
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#define MCI_CMDR_SPCMD_IT_REP (0x5u << 8) /* (MCI) Interrupt response */
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#define MCI_CMDR_OPDCMD (0x1u << 11) /* (MCI) Open Drain Command */
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#define MCI_CMDR_MAXLAT (0x1u << 12) /* (MCI) Maximum Latency for Command to respond */
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#define MCI_CMDR_TRCMD (0x3u << 16) /* (MCI) Transfer CMD */
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#define MCI_CMDR_TRCMD_NO (0x0u << 16) /* (MCI) No transfer */
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#define MCI_CMDR_TRCMD_START (0x1u << 16) /* (MCI) Start transfer */
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#define MCI_CMDR_TRCMD_STOP (0x2u << 16) /* (MCI) Stop transfer */
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#define MCI_CMDR_TRDIR (0x1u << 18) /* (MCI) Transfer Direction */
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#define MCI_CMDR_TRTYP (0x3u << 19) /* (MCI) Transfer Type */
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#define MCI_CMDR_TRTYP_BLOCK (0x0u << 19) /* (MCI) Block Transfer type */
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#define MCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /* (MCI) Multiple Block transfer type */
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#define MCI_CMDR_TRTYP_STREAM (0x2u << 19) /* (MCI) Stream transfer type */
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/* -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- */
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#define MCI_SR_CMDRDY (0x1u << 0) /* (MCI) Command Ready flag */
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#define MCI_SR_RXRDY (0x1u << 1) /* (MCI) RX Ready flag */
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#define MCI_SR_TXRDY (0x1u << 2) /* (MCI) TX Ready flag */
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#define MCI_SR_BLKE (0x1u << 3) /* (MCI) Data Block Transfer Ended flag */
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#define MCI_SR_DTIP (0x1u << 4) /* (MCI) Data Transfer in Progress flag */
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#define MCI_SR_NOTBUSY (0x1u << 5) /* (MCI) Data Line Not Busy flag */
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#define MCI_SR_ENDRX (0x1u << 6) /* (MCI) End of RX Buffer flag */
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#define MCI_SR_ENDTX (0x1u << 7) /* (MCI) End of TX Buffer flag */
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#define MCI_SR_RXBUFF (0x1u << 14) /* (MCI) RX Buffer Full flag */
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#define MCI_SR_TXBUFE (0x1u << 15) /* (MCI) TX Buffer Empty flag */
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#define MCI_SR_RINDE (0x1u << 16) /* (MCI) Response Index Error flag */
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#define MCI_SR_RDIRE (0x1u << 17) /* (MCI) Response Direction Error flag */
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#define MCI_SR_RCRCE (0x1u << 18) /* (MCI) Response CRC Error flag */
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#define MCI_SR_RENDE (0x1u << 19) /* (MCI) Response End Bit Error flag */
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#define MCI_SR_RTOE (0x1u << 20) /* (MCI) Response Time-out Error flag */
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#define MCI_SR_DCRCE (0x1u << 21) /* (MCI) data CRC Error flag */
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#define MCI_SR_DTOE (0x1u << 22) /* (MCI) Data timeout Error flag */
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#define MCI_SR_OVRE (0x1u << 30) /* (MCI) Overrun flag */
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#define MCI_SR_UNRE (0x1u << 31) /* (MCI) Underrun flag */
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/* TXRDY,DTIP,ENDTX,TXBUFE,RTOE */
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#define MCI_SR_BITSTRING \
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"\020" \
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"\001CMDRDY" \
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"\002RXRDY" \
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"\003TXRDY" \
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"\004BLKE" \
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"\005DTIP" \
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"\006NOTBUSY" \
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"\007ENDRX" \
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"\010ENDTX" \
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"\017RXBUFF" \
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"\020TXBUFE" \
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"\021RINDE" \
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"\022RDIRE" \
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"\023RCRCE" \
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"\024RENDE" \
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"\025RTOE" \
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"\026DCRCE" \
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"\027DTOE" \
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"\037OVRE" \
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"\040UNRE"
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/* -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- */
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/* -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- */
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/* -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- */
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#define MCI_SR_ERROR (MCI_SR_UNRE | MCI_SR_OVRE | MCI_SR_DTOE | \
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MCI_SR_DCRCE | MCI_SR_RTOE | MCI_SR_RENDE | \
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MCI_SR_RCRCE | MCI_SR_RDIRE | MCI_SR_RINDE)
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#define AT91C_BUS_WIDTH_1BIT 0x00
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#define AT91C_BUS_WIDTH_4BITS 0x02
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#endif /* ARM_AT91_AT91_MCIREG_H */
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48
freebsd/sys/arm/at91/at91_pdcreg.h
Normal file
48
freebsd/sys/arm/at91/at91_pdcreg.h
Normal file
@ -0,0 +1,48 @@
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/*-
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* Copyright (c) 2006 M. Warner Losh. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
|
||||
* are met:
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||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
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* SUCH DAMAGE.
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*/
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/* $FreeBSD$ */
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#ifndef ARM_AT91_AT91_PDCREG_H
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#define ARM_AT91_AT91_PDCREG_H
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#define PDC_RPR 0x100 /* PDC Receive Pointer Register */
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#define PDC_RCR 0x104 /* PDC Receive Counter Register */
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#define PDC_TPR 0x108 /* PDC Transmit Pointer Register */
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#define PDC_TCR 0x10c /* PDC Transmit Counter Register */
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#define PDC_RNPR 0x110 /* PDC Receive Next Pointer Register */
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#define PDC_RNCR 0x114 /* PDC Receive Next Counter Register */
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#define PDC_TNPR 0x118 /* PDC Transmit Next Pointer Reg */
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#define PDC_TNCR 0x11c /* PDC Transmit Next Counter Reg */
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#define PDC_PTCR 0x120 /* PDC Transfer Control Register */
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#define PDC_PTSR 0x124 /* PDC Transfer Status Register */
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/* PTCR/PTSR */
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#define PDC_PTCR_RXTEN (1UL << 0) /* RXTEN: Receiver Transfer Enable */
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#define PDC_PTCR_RXTDIS (1UL << 1) /* RXTDIS: Receiver Transfer Disable */
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#define PDC_PTCR_TXTEN (1UL << 8) /* TXTEN: Transmitter Transfer En */
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#define PDC_PTCR_TXTDIS (1UL << 9) /* TXTDIS: Transmitter Transmit Dis */
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#endif /* ARM_AT91_AT91_PDCREG_H */
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90
freebsd/sys/arm/at91/at91reg.h
Normal file
90
freebsd/sys/arm/at91/at91reg.h
Normal file
@ -0,0 +1,90 @@
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/*-
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* Copyright (c) 2009 Greg Ansley All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
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/*
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* $FreeBSD$
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*/
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#ifndef _AT91REG_H_
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#define _AT91REG_H_
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#include <rtems/bsd/local/opt_at91.h>
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/* Where builtin peripherals start in KVM */
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#define AT91_BASE 0xd0000000
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/* Where builtin peripherals start PA */
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#define AT91_PA_BASE 0xf0000000
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/* A few things that we count on being the same
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* throughout the whole family of SOCs */
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/* SYSC System Controller */
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/* System Registers */
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#define AT91_SYS_BASE 0xffff000
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#define AT91_SYS_SIZE 0x1000
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#define AT91_DBGU0 0x0ffff200 /* Most */
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#define AT91_DBGU1 0x0fffee00 /* SAM9263, CAP9, and SAM9G45 */
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#define AT91_DBGU_SIZE 0x200
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#define DBGU_C1R (64) /* Chip ID1 Register */
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#define DBGU_C2R (68) /* Chip ID2 Register */
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#define DBGU_FNTR (72) /* Force NTRST Register */
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#define AT91_CPU_VERSION_MASK 0x0000001f
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#define AT91_CPU_FAMILY_MASK 0x0ff00000
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#define AT91_CPU_RM9200 0x09290780
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#define AT91_CPU_SAM9260 0x019803a0
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#define AT91_CPU_SAM9261 0x019703a0
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#define AT91_CPU_SAM9263 0x019607a0
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#define AT91_CPU_SAM9G10 0x819903a0
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#define AT91_CPU_SAM9G20 0x019905a0
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#define AT91_CPU_SAM9G45 0x819b05a0
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#define AT91_CPU_SAM9N12 0x819a07a0
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#define AT91_CPU_SAM9RL64 0x019b03a0
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#define AT91_CPU_SAM9X5 0x819a05a0
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#define AT91_CPU_SAM9XE128 0x329973a0
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#define AT91_CPU_SAM9XE256 0x329a93a0
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#define AT91_CPU_SAM9XE512 0x329aa3a0
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#define AT91_CPU_CAP9 0x039a03a0
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|
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#define AT91_EXID_SAM9M11 0x00000001
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#define AT91_EXID_SAM9M10 0x00000002
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#define AT91_EXID_SAM9G46 0x00000003
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#define AT91_EXID_SAM9G45 0x00000004
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||||
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||||
#define AT91_EXID_SAM9G15 0x00000000
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#define AT91_EXID_SAM9G35 0x00000001
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||||
#define AT91_EXID_SAM9X35 0x00000002
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||||
#define AT91_EXID_SAM9G25 0x00000003
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||||
#define AT91_EXID_SAM9X25 0x00000004
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||||
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#define AT91_IRQ_SYSTEM 1
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#endif /* _AT91REG_H_ */
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173
freebsd/sys/arm/at91/at91var.h
Normal file
173
freebsd/sys/arm/at91/at91var.h
Normal file
@ -0,0 +1,173 @@
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/*-
|
||||
* Copyright (c) 2005 Olivier Houchard. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/* $FreeBSD$ */
|
||||
|
||||
#ifndef _AT91VAR_H_
|
||||
#define _AT91VAR_H_
|
||||
|
||||
#include <sys/bus.h>
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||||
#include <sys/rman.h>
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||||
|
||||
#include <arm/at91/at91reg.h>
|
||||
|
||||
struct at91_softc {
|
||||
device_t dev;
|
||||
bus_space_tag_t sc_st;
|
||||
bus_space_handle_t sc_sh;
|
||||
bus_space_handle_t sc_aic_sh;
|
||||
struct rman sc_irq_rman;
|
||||
struct rman sc_mem_rman;
|
||||
};
|
||||
|
||||
struct at91_ivar {
|
||||
struct resource_list resources;
|
||||
};
|
||||
|
||||
struct cpu_devs
|
||||
{
|
||||
const char *name;
|
||||
int unit;
|
||||
bus_addr_t mem_base;
|
||||
bus_size_t mem_len;
|
||||
int irq0;
|
||||
int irq1;
|
||||
int irq2;
|
||||
const char *parent_clk;
|
||||
};
|
||||
|
||||
enum at91_soc_type {
|
||||
AT91_T_NONE = 0,
|
||||
AT91_T_CAP9,
|
||||
AT91_T_RM9200,
|
||||
AT91_T_SAM9260,
|
||||
AT91_T_SAM9261,
|
||||
AT91_T_SAM9263,
|
||||
AT91_T_SAM9G10,
|
||||
AT91_T_SAM9G20,
|
||||
AT91_T_SAM9G45,
|
||||
AT91_T_SAM9N12,
|
||||
AT91_T_SAM9RL,
|
||||
AT91_T_SAM9X5,
|
||||
};
|
||||
|
||||
enum at91_soc_subtype {
|
||||
AT91_ST_ANY = -1, /* Match any type */
|
||||
AT91_ST_NONE = 0,
|
||||
/* AT91RM9200 */
|
||||
AT91_ST_RM9200_BGA,
|
||||
AT91_ST_RM9200_PQFP,
|
||||
/* AT91SAM9260 */
|
||||
AT91_ST_SAM9XE,
|
||||
/* AT91SAM9G45 */
|
||||
AT91_ST_SAM9G45,
|
||||
AT91_ST_SAM9M10,
|
||||
AT91_ST_SAM9G46,
|
||||
AT91_ST_SAM9M11,
|
||||
/* AT91SAM9X5 */
|
||||
AT91_ST_SAM9G15,
|
||||
AT91_ST_SAM9G25,
|
||||
AT91_ST_SAM9G35,
|
||||
AT91_ST_SAM9X25,
|
||||
AT91_ST_SAM9X35,
|
||||
};
|
||||
|
||||
enum at91_soc_family {
|
||||
AT91_FAMILY_SAM9 = 0x19,
|
||||
AT91_FAMILY_SAM9XE = 0x29,
|
||||
AT91_FAMILY_RM92 = 0x92,
|
||||
};
|
||||
|
||||
#define AT91_SOC_NAME_MAX 50
|
||||
|
||||
typedef void (*DELAY_t)(int);
|
||||
typedef void (*cpu_reset_t)(void);
|
||||
typedef void (*clk_init_t)(void);
|
||||
|
||||
struct at91_soc_data {
|
||||
DELAY_t soc_delay; /* SoC specific delay function */
|
||||
cpu_reset_t soc_reset; /* SoC specific reset function */
|
||||
clk_init_t soc_clock_init; /* SoC specific clock init function */
|
||||
const int *soc_irq_prio; /* SoC specific IRQ priorities */
|
||||
const struct cpu_devs *soc_children; /* SoC specific children list */
|
||||
const uint32_t *soc_pio_base; /* SoC specific PIO base registers */
|
||||
size_t soc_pio_count; /* Count of PIO units (not pins) in SoC */
|
||||
};
|
||||
|
||||
struct at91_soc_info {
|
||||
enum at91_soc_type type;
|
||||
enum at91_soc_subtype subtype;
|
||||
enum at91_soc_family family;
|
||||
uint32_t cidr;
|
||||
uint32_t exid;
|
||||
char name[AT91_SOC_NAME_MAX];
|
||||
uint32_t dbgu_base;
|
||||
struct at91_soc_data *soc_data;
|
||||
};
|
||||
|
||||
extern struct at91_soc_info soc_info;
|
||||
|
||||
static inline int at91_is_rm92(void);
|
||||
static inline int at91_is_sam9(void);
|
||||
static inline int at91_is_sam9xe(void);
|
||||
static inline int at91_cpu_is(u_int cpu);
|
||||
|
||||
static inline int
|
||||
at91_is_rm92(void)
|
||||
{
|
||||
|
||||
return (soc_info.type == AT91_T_RM9200);
|
||||
}
|
||||
|
||||
static inline int
|
||||
at91_is_sam9(void)
|
||||
{
|
||||
|
||||
return (soc_info.family == AT91_FAMILY_SAM9);
|
||||
}
|
||||
|
||||
static inline int
|
||||
at91_is_sam9xe(void)
|
||||
{
|
||||
|
||||
return (soc_info.family == AT91_FAMILY_SAM9XE);
|
||||
}
|
||||
|
||||
static inline int
|
||||
at91_cpu_is(u_int cpu)
|
||||
{
|
||||
|
||||
return (soc_info.type == cpu);
|
||||
}
|
||||
|
||||
void at91_add_child(device_t dev, int prio, const char *name, int unit,
|
||||
bus_addr_t addr, bus_size_t size, int irq0, int irq1, int irq2);
|
||||
|
||||
extern uint32_t at91_irq_system;
|
||||
extern uint32_t at91_master_clock;
|
||||
void at91_pmc_init_clock(void);
|
||||
void at91_soc_id(void);
|
||||
|
||||
#endif /* _AT91VAR_H_ */
|
||||
Loading…
x
Reference in New Issue
Block a user