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87 lines
3.6 KiB
C
87 lines
3.6 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2021 Chris Johns <chrisj@rtems.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Defines for Xilinx Versal ACAP SLCR registers.
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*
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* Reference:
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* https://www.xilinx.com/html_docs/registers/am012/mod___crl.html
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*/
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#ifndef _VERSAL_SLCR_H_
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#define _VERSAL_SLCR_H_
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#define VERSAL_SLCR_CRF_OFFSET 0x01260000
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#define VERSAL_SLCR_CRL_OFFSET 0x0f5e0000
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/*
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* PLL controls
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*
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* P = PPLL = PMCPLL = PMCPLL_CTRL : PMC PLL Clock
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* N = NPLL = NOCPLL = NOCPLL_CTRL : NOC PLL Clock
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* R = RPLL = RPLL_CTRL : Low Power Domain clock
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*/
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#define VERSAL_SLCR_P_PLL_CTRL (VERSAL_SLCR_CRF_OFFSET + 0x40)
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#define VERSAL_SLCR_N_PLL_CTRL (VERSAL_SLCR_CRF_OFFSET + 0x50)
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#define VERSAL_SLCR_R_PLL_CTRL (VERSAL_SLCR_CRL_OFFSET + 0x40)
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#define VERSAL_SLCR_PLL_CTRL_RESET (1<<0)
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#define VERSAL_SLCR_PLL_CTRL_BYPASS (1<<3)
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#define VERSAL_SLCR_PLL_CTRL_FBDIV_SHIFT 8
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#define VERSAL_SLCR_PLL_CTRL_FBDIV_MAX 0xff
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#define VERSAL_SLCR_PLL_CTRL_FBDIV_MASK (VERSAL_SLCR_PLL_CTRL_FBDIV_MAX<<8)
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#define VERSAL_SLCR_PLL_CTRL_DIV_SHIFT (16)
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#define VERSAL_SLCR_PLL_CTRL_DIV_MASK (0x3<<16)
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#define VERSAL_SLCR_PLL_CTRL_PRE_SRC_SHIFT 20
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#define VERSAL_SLCR_PLL_CTRL_PRE_SRC_MASK (0x7<<20)
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#define VERSAL_SLCR_PLL_CTRL_POST_SRC_SHIFT 24
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#define VERSAL_SLCR_PLL_CTRL_POST_SRC_MASK (0x7<<24)
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#define VERSAL_SLCR_PLL_CTRL_SRC_REF_CLK 0x0
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#define VERSAL_SLCR_PLL_CTRL_SRC_REF_CLK_MASK 0x2
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#define VERSAL_SLCR_PLL_CTRL_SRC_PL_PMC_ALT_REF_CLK_MASK 0x3
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/* Clock controls. */
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#define VERSAL_SLCR_GEM0_CLK_CTRL (VERSAL_SLCR_CRL_OFFSET + 0x118)
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#define VERSAL_SLCR_GEM1_CLK_CTRL (VERSAL_SLCR_CRL_OFFSET + 0x11c)
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#define VERSAL_SLCR_GEM_CLK_CTRL_CLKACT_RX (1<<27)
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#define VERSAL_SLCR_GEM_CLK_CTRL_CLKACT_TX (1<<26)
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#define VERSAL_SLCR_GEM_CLK_CTRL_CLKACT (1<<25)
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#define VERSAL_SLCR_GEM_CLK_CTRL_DIVISOR_MAX 0x3ff
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#define VERSAL_SLCR_GEM_CLK_CTRL_DIVISOR_MASK (VERSAL_SLCR_GEM_CLK_CTRL_DIVISOR_MAX<<8)
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#define VERSAL_SLCR_GEM_CLK_CTRL_DIVISOR_SHIFT 8
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#define VERSAL_SLCR_GEM_CLK_CTRL_SRCSEL_MASK (7<<0)
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#define VERSAL_SLCR_GEM_CLK_CTRL_SRCSEL_P_PLL (0<<0)
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#define VERSAL_SLCR_GEM_CLK_CTRL_SRCSEL_R_PLL (1<<0)
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#define VERSAL_SLCR_GEM_CLK_CTRL_SRCSEL_N_PLL (3<<0)
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#define VERSAL_DEFAULT_PS_CLK_FREQUENCY 33333333
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#ifdef _KERNEL
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extern int cgem_set_ref_clk(int unit, int frequency);
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#endif
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#endif /* _VERSAL_SLCR_H_ */
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