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4820ccecc9
Some targets support only flushing or invalidating complete cache lines. In this cases misaligned buffers might lead to unexpected results. This patch adds a flag that allows drivers to signal to the bus dma driver that it is OK to round a buffer to the next full cache line. That's for example necessary if a driver wants to send out 14 byte via a USB DMA. Only the driver knows whether these 14 bytes are located in an otherwise unused cache line aligned buffer.