mirror of
https://git.rtems.org/rtems-tools/
synced 2025-05-13 23:19:22 +08:00
142 lines
3.5 KiB
Python
142 lines
3.5 KiB
Python
#
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# RTEMS gdb extensions
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# sparc archetecture specific abstractions
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from helper import test_bit
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class register:
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'''SPARC Registers'''
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class psr:
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'''status register'''
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sv_table = {
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0 : 'user',
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1 : 'superviser'
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}
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def __init__(self, psr):
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self.psr = psr
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def current_window(self):
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return int(self.psr & 0xf)
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def traps(self):
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return test_bit(self.psr, 5)
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def prev_superviser(self):
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return int(test_bit(self.psr,6))
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def superviser(self):
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return int(test_bit(self.psr,7))
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def interrupt_level(self):
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# bits 8 to 11
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return (self.spr & 0x780) >> 7
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def floating_point_status(self):
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return test_bit(self.psr, 12)
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def coproc_status(self):
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return test_bit(self.psr,13)
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def carry(self):
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return test_bit(self.psr, 20)
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def overflow(self):
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return test_bit(self.psr, 21)
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def zero(self):
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return test_bit(self.psr, 22)
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def icc(self):
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n = test_bit(self.psr,23)
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z = test_bit(self.psr,22)
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v = test_bit(self.psr,21)
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c = test_bit(self.psr,20)
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return (n,z,v,c)
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def to_string(self):
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val = " Status Register"
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val += "\n R Window : " + str(self.current_window())
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val += "\n Traps Enabled : " + str(self.traps())
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val += "\n Flaoting Point : " + str(self.floating_point_status())
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val += "\n Coprocessor : " + str(self.coproc_status())
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val += "\n Processor Mode : " + self.sv_table[self.superviser()]
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val += "\n Prev. Mode : " + self.sv_table[self.superviser()]
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val += "\n Carry : " + str(int(self.carry()))
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val += "\n Overflow : " + str(int(self.overflow()))
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val += "\n Zero : " + str(int(self.zero()))
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return val
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def __init__(self,reg):
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self.reg = reg
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def global_regs(self):
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val = [self.reg['g0_g1']]
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for i in range(2,7):
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val.append(int(self.reg['g'+str(i)]))
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return val
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def local_regs(self):
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val = []
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for i in range(0,8):
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val.append(self.reg['l'+str(i)])
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return val
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def in_regs(self):
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val = []
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for i in range(0,8):
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if i==6:
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val.append(self.reg['i6_fp'])
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else:
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val.append(self.reg['i'+str(i)])
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return val
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def out_regs(self):
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val = []
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for i in range(0,8):
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if i==6:
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val.append(self.reg['o6_sp'])
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else:
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val.append(self.reg['o'+str(i)])
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return val
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def status(self):
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return self.psr(self.reg['psr'])
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def show(self):
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print ' Global Regs:',
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print ' [',
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for i in self.global_regs():
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print str(i)+',',
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print '\b\b ]'
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print ' Local Regs:',
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print ' [',
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for i in self.local_regs():
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print str(i)+',',
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print '\b\b ]'
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print ' In Regs:',
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print ' [',
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for i in self.in_regs():
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print str(i)+',',
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print '\b\b ]'
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print ' Out Regs:',
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print ' [',
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for i in self.out_regs():
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print str(i)+',',
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print '\b\b ]'
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sr = self.status()
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print sr.to_string() |