mirror of
https://github.com/sakumisu/CherryUSB.git
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feat(port/dwc2/usb_glue_st): implement low level api for device and host
Signed-off-by: sakumisu <1203593632@qq.com>
This commit is contained in:
sakumisu
parent
a838edb3e6
commit
166795bd72
@ -68,7 +68,7 @@
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- F103 使用 fsdev ip
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- F429 主从使用 USB1, 引脚 pb14/pb15, 并且都使用 dma 模式
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- H7 设备使用 USB0, 引脚 pa11/pa12，主机使用 USB_OTG_HS ,引脚 pb14/pb15，并且需要做 nocache 处理
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- H7 设备使用 USB0, 引脚 pa11/pa12，没有开DMA 模式。主机使用 USB1 ,引脚 pb14/pb15，并且需要做 nocache 处理
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demo 底下提供了 **stm32xxx.ioc** 文件，双击打开，点击 **Generate Code** 即可。
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@ -166,6 +166,8 @@ USB Device 移植要点
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.. figure:: img/stm32_10.png
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.. figure:: img/stm32_11.png
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.. note :: 如果使用的是 dwc2，以下两个步骤从 V1.4.4 开始不再需要，**usb_glue_st.c** 文件中已经实现
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- 拷贝 **xxx_msp.c** 中的 **HAL_PCD_MspInit** 函数中的内容到 **usb_dc_low_level_init** 函数中，屏蔽 st 生成的 usb 初始化
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.. figure:: img/stm32_12.png
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@ -206,6 +208,8 @@ USB Host 移植要点
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#define CONFIG_USB_DWC2_PTX_FIFO_SIZE (1024 / 4)
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#define CONFIG_USB_DWC2_RX_FIFO_SIZE ((1012 - CONFIG_USB_DWC2_NPTX_FIFO_SIZE - CONFIG_USB_DWC2_PTX_FIFO_SIZE) / 4)
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.. note :: 如果使用的是 dwc2，以下两个步骤从 V1.4.4 开始不再需要，**usb_glue_st.c** 文件中已经实现
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- 拷贝 **xxx_msp.c** 中的 `HAL_HCD_MspInit` 函数中的内容到 `usb_hc_low_level_init` 函数中，屏蔽 st 生成的 usb 初始化
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- 在中断函数中调用 `USBH_IRQHandler`，并传入 `busid`
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- 调用 `usbh_initialize` 并填入 `busid` 和 USB IP 的 `reg base`， `busid` 从 0 开始，不能超过 `CONFIG_USBHOST_MAX_BUS`
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@ -3,10 +3,98 @@
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "usb_config.h"
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#include "stdint.h"
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#include "usb_dwc2_reg.h"
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#include "usbd_core.h"
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#include "usbh_core.h"
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#if __has_include("stm32f1xx_hal.h")
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#include "stm32f1xx_hal.h"
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#elif __has_include("stm32f2xx_hal.h")
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#include "stm32f2xx_hal.h"
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#elif __has_include("stm32f4xx_hal.h")
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#include "stm32f4xx_hal.h"
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#elif __has_include("stm32f7xx_hal.h")
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#include "stm32f7xx_hal.h"
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#elif __has_include("stm32h7xx_hal.h")
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#include "stm32h7xx_hal.h"
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#elif __has_include("stm32h7rsxx_hal.h")
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#include "stm32h7rsxx_hal.h"
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#elif __has_include("stm32l4xx_hal.h")
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#include "stm32l4xx_hal.h"
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#endif
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#if !defined(HAL_HCD_MODULE_ENABLED) && !defined(HAL_PCD_MODULE_ENABLED)
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#error please define HAL_HCD_MODULE_ENABLED or HAL_PCD_MODULE_ENABLED in stm32xxx_hal_conf.h
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#endif
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typedef void (*usb_dwc2_irq)(uint8_t busid);
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struct dwc2_instance {
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USB_OTG_GlobalTypeDef *Instance;
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};
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static usb_dwc2_irq g_usb_dwc2_irq[2];
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static volatile uint8_t g_usb_dwc2_busid[2] = { 0, 0 };
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static struct dwc2_instance g_dwc2_instance;
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#ifdef HAL_PCD_MODULE_ENABLED
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void usb_dc_low_level_init(uint8_t busid)
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{
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if (g_usbdev_bus[busid].reg_base == USB_OTG_HS_PERIPH_BASE) {
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g_usb_dwc2_busid[1] = busid;
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g_usb_dwc2_irq[1] = USBD_IRQHandler;
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} else {
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g_usb_dwc2_busid[0] = busid;
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g_usb_dwc2_irq[0] = USBD_IRQHandler;
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}
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g_dwc2_instance.Instance = (USB_OTG_GlobalTypeDef *)g_usbdev_bus[busid].reg_base;
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HAL_PCD_MspInit((PCD_HandleTypeDef *)&g_dwc2_instance);
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}
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void usb_dc_low_level_deinit(uint8_t busid)
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{
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if (g_usbdev_bus[busid].reg_base == USB_OTG_HS_PERIPH_BASE) {
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g_usb_dwc2_busid[1] = 0;
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g_usb_dwc2_irq[1] = NULL;
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} else {
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g_usb_dwc2_busid[0] = 0;
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g_usb_dwc2_irq[0] = NULL;
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}
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g_dwc2_instance.Instance = (USB_OTG_GlobalTypeDef *)g_usbdev_bus[busid].reg_base;
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HAL_PCD_MspDeInit((PCD_HandleTypeDef *)&g_dwc2_instance);
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}
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#endif
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#ifdef HAL_HCD_MODULE_ENABLED
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void usb_hc_low_level_init(struct usbh_bus *bus)
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{
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if (bus->hcd.reg_base == USB_OTG_HS_PERIPH_BASE) {
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g_usb_dwc2_busid[1] = bus->hcd.hcd_id;
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g_usb_dwc2_irq[1] = USBH_IRQHandler;
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} else {
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g_usb_dwc2_busid[0] = bus->hcd.hcd_id;
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g_usb_dwc2_irq[0] = USBH_IRQHandler;
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}
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g_dwc2_instance.Instance = (USB_OTG_GlobalTypeDef *)bus->hcd.reg_base;
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HAL_HCD_MspInit((HCD_HandleTypeDef *)&g_dwc2_instance);
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}
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void usb_hc_low_level_deinit(struct usbh_bus *bus)
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{
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if (bus->hcd.reg_base == USB_OTG_HS_PERIPH_BASE) {
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g_usb_dwc2_busid[1] = 0;
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g_usb_dwc2_irq[1] = NULL;
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} else {
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g_usb_dwc2_busid[0] = 0;
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g_usb_dwc2_irq[0] = NULL;
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}
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g_dwc2_instance.Instance = (USB_OTG_GlobalTypeDef *)bus->hcd.reg_base;
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HAL_HCD_MspDeInit((HCD_HandleTypeDef *)&g_dwc2_instance);
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}
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#endif
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/* you can find this config in function: USB_DevInit, file:stm32xxx_ll_usb.c, for example:
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*
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* USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
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@ -16,73 +104,7 @@
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*
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*/
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extern void HAL_Delay(uint32_t Delay);
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#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F730xx) || defined(STM32F732xx) || defined(STM32F733xx)
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/**
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* @brief USB_HS_PHY_Registers
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*/
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typedef struct
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{
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__IO uint32_t USB_HS_PHYC_PLL; /*!< This register is used to control the PLL of the HS PHY. 000h */
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__IO uint32_t Reserved04; /*!< Reserved 004h */
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__IO uint32_t Reserved08; /*!< Reserved 008h */
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__IO uint32_t USB_HS_PHYC_TUNE; /*!< This register is used to control the tuning interface of the High Speed PHY. 00Ch */
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__IO uint32_t Reserved10; /*!< Reserved 010h */
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__IO uint32_t Reserved14; /*!< Reserved 014h */
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__IO uint32_t USB_HS_PHYC_LDO; /*!< This register is used to control the regulator (LDO). 018h */
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} USB_HS_PHYC_GlobalTypeDef;
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#define USB_HS_PHYC_CONTROLLER_BASE 0x40017C00UL
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#define USB_HS_PHYC ((USB_HS_PHYC_GlobalTypeDef *) USB_HS_PHYC_CONTROLLER_BASE)
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/******************** Bit definition for USBPHYC_PLL1 register ********************/
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#define USB_HS_PHYC_PLL1_PLLEN_Pos (0U)
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#define USB_HS_PHYC_PLL1_PLLEN_Msk (0x1UL << USB_HS_PHYC_PLL1_PLLEN_Pos) /*!< 0x00000001 */
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#define USB_HS_PHYC_PLL1_PLLEN USB_HS_PHYC_PLL1_PLLEN_Msk /*!< Enable PLL */
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#define USB_HS_PHYC_PLL1_PLLSEL_Pos (1U)
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#define USB_HS_PHYC_PLL1_PLLSEL_Msk (0x7UL << USB_HS_PHYC_PLL1_PLLSEL_Pos) /*!< 0x0000000E */
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#define USB_HS_PHYC_PLL1_PLLSEL USB_HS_PHYC_PLL1_PLLSEL_Msk /*!< Controls PHY frequency operation selection */
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#define USB_HS_PHYC_PLL1_PLLSEL_1 (0x1UL << USB_HS_PHYC_PLL1_PLLSEL_Pos) /*!< 0x00000002 */
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#define USB_HS_PHYC_PLL1_PLLSEL_2 (0x2UL << USB_HS_PHYC_PLL1_PLLSEL_Pos) /*!< 0x00000004 */
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#define USB_HS_PHYC_PLL1_PLLSEL_3 (0x4UL << USB_HS_PHYC_PLL1_PLLSEL_Pos) /*!< 0x00000008 */
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#define USB_HS_PHYC_PLL1_PLLSEL_12MHZ 0x00000000U /*!< PHY PLL1 input clock frequency 12 MHz */
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#define USB_HS_PHYC_PLL1_PLLSEL_12_5MHZ USB_HS_PHYC_PLL1_PLLSEL_1 /*!< PHY PLL1 input clock frequency 12.5 MHz */
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#define USB_HS_PHYC_PLL1_PLLSEL_16MHZ (uint32_t)(USB_HS_PHYC_PLL1_PLLSEL_1 | USB_HS_PHYC_PLL1_PLLSEL_2) /*!< PHY PLL1 input clock frequency 16 MHz */
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#define USB_HS_PHYC_PLL1_PLLSEL_24MHZ USB_HS_PHYC_PLL1_PLLSEL_3 /*!< PHY PLL1 input clock frequency 24 MHz */
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#define USB_HS_PHYC_PLL1_PLLSEL_25MHZ (uint32_t)(USB_HS_PHYC_PLL1_PLLSEL_2 | USB_HS_PHYC_PLL1_PLLSEL_3) /*!< PHY PLL1 input clock frequency 25 MHz */
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/******************** Bit definition for USBPHYC_LDO register ********************/
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#define USB_HS_PHYC_LDO_USED_Pos (0U)
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#define USB_HS_PHYC_LDO_USED_Msk (0x1UL << USB_HS_PHYC_LDO_USED_Pos) /*!< 0x00000001 */
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#define USB_HS_PHYC_LDO_USED USB_HS_PHYC_LDO_USED_Msk /*!< Monitors the usage status of the PHY's LDO */
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#define USB_HS_PHYC_LDO_STATUS_Pos (1U)
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#define USB_HS_PHYC_LDO_STATUS_Msk (0x1UL << USB_HS_PHYC_LDO_STATUS_Pos) /*!< 0x00000002 */
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#define USB_HS_PHYC_LDO_STATUS USB_HS_PHYC_LDO_STATUS_Msk /*!< Monitors the status of the PHY's LDO. */
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#define USB_HS_PHYC_LDO_DISABLE_Pos (2U)
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#define USB_HS_PHYC_LDO_DISABLE_Msk (0x1UL << USB_HS_PHYC_LDO_DISABLE_Pos) /*!< 0x00000004 */
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#define USB_HS_PHYC_LDO_DISABLE USB_HS_PHYC_LDO_DISABLE_Msk /*!< Controls disable of the High Speed PHY's LDO */
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/* Legacy */
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#define USB_HS_PHYC_PLL_PLLEN_Pos USB_HS_PHYC_PLL1_PLLEN_Pos
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#define USB_HS_PHYC_PLL_PLLEN_Msk USB_HS_PHYC_PLL1_PLLEN_Msk
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#define USB_HS_PHYC_PLL_PLLEN USB_HS_PHYC_PLL1_PLLEN
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#define USB_HS_PHYC_PLL_PLLSEL_Pos USB_HS_PHYC_PLL1_PLLSEL_Pos
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#define USB_HS_PHYC_PLL_PLLSEL_Msk USB_HS_PHYC_PLL1_PLLSEL_Msk
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#define USB_HS_PHYC_PLL_PLLSEL USB_HS_PHYC_PLL1_PLLSEL
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#define USB_HS_PHYC_PLL_PLLSEL_1 USB_HS_PHYC_PLL1_PLLSEL_1
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#define USB_HS_PHYC_PLL_PLLSEL_2 USB_HS_PHYC_PLL1_PLLSEL_2
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#define USB_HS_PHYC_PLL_PLLSEL_3 USB_HS_PHYC_PLL1_PLLSEL_3
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#define USB_HS_PHYC_LDO_ENABLE_Pos USB_HS_PHYC_LDO_DISABLE_Pos
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#define USB_HS_PHYC_LDO_ENABLE_Msk USB_HS_PHYC_LDO_DISABLE_Msk
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#define USB_HS_PHYC_LDO_ENABLE USB_HS_PHYC_LDO_DISABLE
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#if !defined (USB_HS_PHYC_TUNE_VALUE)
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#define USB_HS_PHYC_TUNE_VALUE 0x00000F13U /*!< Value of USB HS PHY Tune */
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#endif /* USB_HS_PHYC_TUNE_VALUE */
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/**
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* @brief Enables control of a High Speed USB PHY
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* Init the low level hardware : GPIO, CLOCK, NVIC...
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@ -91,71 +113,60 @@ __IO uint32_t USB_HS_PHYC_LDO; /*!< This register is used to control the
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*/
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static int usb_hsphy_init(uint32_t hse_value)
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{
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__IO uint32_t count = 0U;
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__IO uint32_t count = 0U;
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/* Enable LDO */
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USB_HS_PHYC->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE;
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/* Enable LDO */
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USB_HS_PHYC->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE;
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/* wait for LDO Ready */
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while ((USB_HS_PHYC->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) == 0U)
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{
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count++;
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/* wait for LDO Ready */
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while ((USB_HS_PHYC->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) == 0U) {
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count++;
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if (count > 200000U)
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{
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return -1;
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if (count > 200000U) {
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return -1;
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}
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}
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}
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/* Controls PHY frequency operation selection */
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if (hse_value == 12000000U) /* HSE = 12MHz */
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{
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USB_HS_PHYC->USB_HS_PHYC_PLL = (0x0U << 1);
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}
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else if (hse_value == 12500000U) /* HSE = 12.5MHz */
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{
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USB_HS_PHYC->USB_HS_PHYC_PLL = (0x2U << 1);
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}
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else if (hse_value == 16000000U) /* HSE = 16MHz */
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{
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USB_HS_PHYC->USB_HS_PHYC_PLL = (0x3U << 1);
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}
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else if (hse_value == 24000000U) /* HSE = 24MHz */
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{
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USB_HS_PHYC->USB_HS_PHYC_PLL = (0x4U << 1);
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}
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else if (hse_value == 25000000U) /* HSE = 25MHz */
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{
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USB_HS_PHYC->USB_HS_PHYC_PLL = (0x5U << 1);
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}
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else if (hse_value == 32000000U) /* HSE = 32MHz */
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{
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USB_HS_PHYC->USB_HS_PHYC_PLL = (0x7U << 1);
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}
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else
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{
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/* ... */
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}
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/* Controls PHY frequency operation selection */
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if (hse_value == 12000000U) /* HSE = 12MHz */
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{
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USB_HS_PHYC->USB_HS_PHYC_PLL = (0x0U << 1);
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} else if (hse_value == 12500000U) /* HSE = 12.5MHz */
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{
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USB_HS_PHYC->USB_HS_PHYC_PLL = (0x2U << 1);
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} else if (hse_value == 16000000U) /* HSE = 16MHz */
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{
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USB_HS_PHYC->USB_HS_PHYC_PLL = (0x3U << 1);
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} else if (hse_value == 24000000U) /* HSE = 24MHz */
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{
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USB_HS_PHYC->USB_HS_PHYC_PLL = (0x4U << 1);
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} else if (hse_value == 25000000U) /* HSE = 25MHz */
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{
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USB_HS_PHYC->USB_HS_PHYC_PLL = (0x5U << 1);
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} else if (hse_value == 32000000U) /* HSE = 32MHz */
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{
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USB_HS_PHYC->USB_HS_PHYC_PLL = (0x7U << 1);
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} else {
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/* ... */
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}
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/* Control the tuning interface of the High Speed PHY */
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USB_HS_PHYC->USB_HS_PHYC_TUNE |= USB_HS_PHYC_TUNE_VALUE;
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/* Control the tuning interface of the High Speed PHY */
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USB_HS_PHYC->USB_HS_PHYC_TUNE |= USB_HS_PHYC_TUNE_VALUE;
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/* Enable PLL internal PHY */
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USB_HS_PHYC->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN;
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/* Enable PLL internal PHY */
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USB_HS_PHYC->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN;
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/* 2ms Delay required to get internal phy clock stable */
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HAL_Delay(2U);
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/* 2ms Delay required to get internal phy clock stable */
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HAL_Delay(2U);
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return 0;
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return 0;
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}
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#endif
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uint32_t usbd_get_dwc2_gccfg_conf(uint32_t reg_base)
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{
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#if __has_include("stm32h7xx.h") || __has_include("stm32f7xx.h") || __has_include("stm32l4xx.h")
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#define USB_OTG_GLB ((DWC2_GlobalTypeDef *)(reg_base))
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#define USB_OTG_GLB ((USB_OTG_GlobalTypeDef *)(reg_base))
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/* B-peripheral session valid override enable */
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USB_OTG_GLB->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
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USB_OTG_GLB->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
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@ -165,7 +176,7 @@ uint32_t usbd_get_dwc2_gccfg_conf(uint32_t reg_base)
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#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F730xx) || defined(STM32F732xx) || defined(STM32F733xx)
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USB_OTG_GLB->GCCFG = (1 << 23);
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usb_hsphy_init(25000000U);
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return (1 << 23); /* Enable USB HS PHY USBx->GCCFG |= USB_OTG_GCCFG_PHYHSEN;*/
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return (1 << 23); /* Enable USB HS PHY USBx->GCCFG |= USB_OTG_GCCFG_PHYHSEN;*/
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#elif __has_include("stm32h7rsxx.h")
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return (1 << 21);
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#else
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@ -183,7 +194,7 @@ uint32_t usbd_get_dwc2_gccfg_conf(uint32_t reg_base)
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uint32_t usbh_get_dwc2_gccfg_conf(uint32_t reg_base)
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{
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#if __has_include("stm32h7xx.h") || __has_include("stm32f7xx.h") || __has_include("stm32l4xx.h")
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#define USB_OTG_GLB ((DWC2_GlobalTypeDef *)(reg_base))
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||||
#define USB_OTG_GLB ((USB_OTG_GlobalTypeDef *)(reg_base))
|
||||
/* B-peripheral session valid override enable */
|
||||
USB_OTG_GLB->GOTGCTL &= ~USB_OTG_GOTGCTL_BVALOEN;
|
||||
USB_OTG_GLB->GOTGCTL &= ~USB_OTG_GOTGCTL_BVALOVAL;
|
||||
@ -210,3 +221,13 @@ void usbd_dwc2_delay_ms(uint8_t ms)
|
||||
{
|
||||
HAL_Delay(ms);
|
||||
}
|
||||
|
||||
void OTG_FS_IRQHandler(void)
|
||||
{
|
||||
g_usb_dwc2_irq[0](g_usb_dwc2_busid[0]);
|
||||
}
|
||||
|
||||
void OTG_HS_IRQHandler(void)
|
||||
{
|
||||
g_usb_dwc2_irq[1](g_usb_dwc2_busid[1]);
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user