mirror of
https://github.com/sakumisu/CherryUSB.git
synced 2025-05-09 00:21:44 +08:00
user must define some configs in usb_config.h when use fsdev/musb/dwc2
This commit is contained in:
sakumisu
parent
44e9c1cf4f
commit
8a831cdaa5
@ -64,10 +64,6 @@ if GetDepend(['PKG_CHERRYUSB_DEVICE']):
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src += Glob('port/dwc2/usb_dc_dwc2.c')
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if GetDepend(['PKG_CHERRYUSB_DEVICE_DWC2_STM32']):
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src += Glob('port/dwc2/usb_glue_st.c')
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if GetDepend(['PKG_CHERRYUSB_DEVICE_DWC2_PORT_FS']):
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CPPDEFINES += ['CONFIG_USB_DWC2_PORT=FS_PORT']
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elif GetDepend(['PKG_CHERRYUSB_DEVICE_DWC2_PORT_HS']):
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CPPDEFINES += ['CONFIG_USB_DWC2_PORT=HS_PORT']
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if GetDepend(['PKG_CHERRYUSB_DEVICE_MUSB']):
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src += Glob('port/musb/usb_dc_musb.c')
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@ -130,13 +130,15 @@
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/* ================ USB Device Port Configuration ================*/
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//#define USBD_IRQHandler USBD_IRQHandler
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//#define USB_BASE (0x40080000UL)
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//#define USB_NUM_BIDIR_ENDPOINTS 4
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#define USBD_IRQHandler USBD_IRQHandler
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#define USBD_BASE (0)
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#define CONFIG_USBDEV_EP_NUM 4
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/* ================ USB Host Port Configuration ==================*/
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#define CONFIG_USBHOST_PIPE_NUM 10
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// #define USBH_IRQHandler USBH_IRQHandler
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// #define USBH_BASE (0)
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// #define CONFIG_USBHOST_PIPE_NUM 10
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/* ================ EHCI Configuration ================ */
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@ -35,7 +35,6 @@
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- usb ip 区别：F1使用 fsdev，F4/H7使用 dwc2
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- dwc2 ip 区别： fs port(引脚是 PA11/PA12) 和 hs port(引脚是 PB14/PB15), 其中 hs port 默认全速，可以接外部PHY 形成高速主机，并且带 dma 功能
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- F4 无cache，H7 有 cache
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- H7 的 USB_BASE 与其他系列有区别，需要在 usb_config.h 中配置
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如果是 STM32F7/STM32H7 这种带 cache 功能，需要将 usb 使用到的 ram 定位到 no cache ram 区域。举例如下
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@ -77,8 +76,6 @@ USB Device 移植要点
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.. figure:: img/stm32_3_1.png
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.. figure:: img/stm32_3.png
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.. caution :: 如果使用 STM32H7 FS PORT, 请修改 USB_BASE 为 0x40080000UL
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- 配置 usb clock 为 48M
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.. figure:: img/stm32_4_1.png
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@ -7,21 +7,25 @@ USB Device 移植要点
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-----------------------
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- 拷贝 CherryUSB 源码到工程目录下，并按需添加源文件和头文件路径，其中 `usbd_core.c` 和 `usb_dc_xxx.c` 为必须添加项。而 `usb_dc_xxx.c` 是芯片所对应的 USB IP dcd 部分驱动，如果不知道自己芯片属于那个 USB IP，参考 **port** 目录下的不同 USB IP 的 readme。如果使用的 USB IP 没有支持，只能自己实现了
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- 添加 `USBD_IRQHandler=xxxx` 、 `USB_NUM_BIDIR_ENDPOINTS=x` 以及 `USB_BASE=0xxxxx` 三个 cflag 编译选项，如果没有添加则使用 `usb_dc_xxx.c` 中默认配置
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- 拷贝 `cherryusb_config_template.h` 文件到自己工程目录下，命名为 `usb_config.h`，并添加相应的目录头文件路径。
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- 拷贝 `cherryusb_config_template.h` 文件到自己工程目录下，命名为 `usb_config.h`，并添加相应的目录头文件路径
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- 在 `usb_config.h` 中添加 `USBD_IRQHandler=xxxx` 、 `CONFIG_USBDEV_EP_NUM=x` 以及 `USBD_BASE=0xxxxx` 三个常规 porting 需要的宏
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.. note:: 上述三个宏仅对 fsdev、musb、dwc2 有效，因为这 3 个是通用 IP
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- 实现 `usb_dc_low_level_init` 函数（该函数主要负责 USB 时钟、引脚、中断的初始化）。该函数可以放在你想要放的任何参与编译的 c 文件中。如何进行 USB 的时钟、引脚、中断等初始化，请自行根据你使用的芯片原厂提供的源码中进行添加。
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- 描述符的注册、class的注册、接口的注册、端点中断的注册。不会的参考 demo 下的 template
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- 调用 `usbd_initialize` 初始化 usb 硬件
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- 编译使用。各个 class 如何使用，参考 demo 下的 template
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.. note:: device 移植要点其实就三个，实现 `usb_dc_low_level_init` ;改 `USBD_IRQHandler=xxxx` 、`USB_BASE=0xxxxx` 、 `USB_NUM_BIDIR_ENDPOINTS=x`;改 `usb_config.h` 中的内容。其中前面说到的3个宏也可以在 `usb_config.h` 添加
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USB Host 移植要点
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-----------------------
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- 拷贝 CherryUSB 源码到工程目录下，并按需添加源文件和头文件路径，其中 `usbh_core.c` 、 `usb_hc_xxx.c` 以及 **osal** 目录下源文件（根据不同的 os 选择对应的源文件）为必须添加项。而 `usb_hc_xxx.c` 是芯片所对应的 USB IP dcd 部分驱动，如果不知道自己芯片属于那个 USB IP，参考 **port** 目录下的不同 USB IP 的 readme。如果使用的 USB IP 没有支持，只能自己实现了
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- 添加 `USBH_IRQHandler=xxxx` 以及 `USB_BASE=0xxxxx` 两个 cflag 编译选项，如果没有添加则使用 `usb_hc_xxx.c` 中默认配置
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- 拷贝 `cherryusb_config_template.h` 文件到自己工程目录下，命名为 `usb_config.h`，并添加相应的目录头文件路径。
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- 拷贝 `cherryusb_config_template.h` 文件到自己工程目录下，命名为 `usb_config.h`，并添加相应的目录头文件路径
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- 在 `usb_config.h` 中添加 `USBH_IRQHandler=xxxx` 、 `CONFIG_USBHOST_PIPE_NUM=x` 以及 `USBH_BASE=0xxxxx` 三个常规 porting 需要的宏
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.. note:: 上述三个宏仅对 musb、dwc2 有效，因为这 2 个是通用 IP
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- 实现 `usb_hc_low_level_init` 函数（该函数主要负责 USB 时钟、引脚、中断的初始化）。该函数可以放在你想要放的任何参与编译的 c 文件中。如何进行 USB 的时钟、引脚、中断等初始化，请自行根据你使用的芯片原厂提供的源码中进行添加。
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- 调用 `usbh_initialize` 初始化 usb 硬件
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- 如果使用的是 GCC ，需要在链接脚本(ld)中添加如下代码：
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@ -51,24 +51,19 @@
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#endif
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// clang-format on
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#define FS_PORT 0
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#define HS_PORT 1
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#ifndef CONFIG_USB_DWC2_PORT
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#error "please select CONFIG_USB_DWC2_PORT with FS_PORT or HS_PORT"
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#endif
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#if CONFIG_USB_DWC2_PORT == FS_PORT
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#ifndef USBD_IRQHandler
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#define USBD_IRQHandler OTG_FS_IRQHandler
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#error "please define USBD_IRQHandler in usb_config.h"
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#endif
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#ifndef USB_BASE
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#define USB_BASE (0x50000000UL)
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#ifndef USBD_BASE
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#error "please define USBD_BASE in usb_config.h"
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#endif
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#define USB_RAM_SIZE 1280 /* define with minimum value*/
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#ifndef CONFIG_USB_DWC2_RAM_SIZE
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#error "please define CONFIG_USB_DWC2_RAM_SIZE in usb_config.h, only support 1280 or 4096"
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#endif
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#if CONFIG_USB_DWC2_RAM_SIZE == 1280
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/*FIFO sizes in bytes (total available memory for FIFOs is 1.25KB )*/
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#ifndef CONFIG_USB_DWC2_RX_FIFO_SIZE
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#define CONFIG_USB_DWC2_RX_FIFO_SIZE (512)
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@ -98,21 +93,11 @@
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#define CONFIG_USB_DWC2_TX5_FIFO_SIZE (128)
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#endif
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#ifndef USB_NUM_BIDIR_ENDPOINTS
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#define USB_NUM_BIDIR_ENDPOINTS 4 /* define with minimum value*/
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#ifndef CONFIG_USBDEV_EP_NUM
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#define CONFIG_USBDEV_EP_NUM 4 /* define with minimum value*/
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#endif
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#else
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#ifndef USBD_IRQHandler
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#define USBD_IRQHandler OTG_HS_IRQHandler
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#endif
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#ifndef USB_BASE
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#define USB_BASE (0x40040000UL)
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#endif
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#define USB_RAM_SIZE 4096 /* define with minimum value*/
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#elif CONFIG_USB_DWC2_RAM_SIZE == 4096
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#define CONFIG_USB_DWC2_DMA_ENABLE
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@ -149,18 +134,20 @@
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#define CONFIG_USB_DWC2_TX5_FIFO_SIZE (256)
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#endif
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#ifndef USB_NUM_BIDIR_ENDPOINTS
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#define USB_NUM_BIDIR_ENDPOINTS 6 /* define with minimum value*/
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#ifndef CONFIG_USBDEV_EP_NUM
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#define CONFIG_USBDEV_EP_NUM 6 /* define with minimum value*/
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#endif
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#else
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#error "Unsupported CONFIG_USB_DWC2_RAM_SIZE value"
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#endif
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#define USB_OTG_GLB ((USB_OTG_GlobalTypeDef *)(USB_BASE))
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#define USB_OTG_DEV ((USB_OTG_DeviceTypeDef *)(USB_BASE + USB_OTG_DEVICE_BASE))
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#define USB_OTG_PCGCCTL *(__IO uint32_t *)((uint32_t)USB_BASE + USB_OTG_PCGCCTL_BASE)
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#define USB_OTG_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USB_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i)*USB_OTG_EP_REG_SIZE)))
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#define USB_OTG_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USB_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i)*USB_OTG_EP_REG_SIZE)))
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#define USB_OTG_FIFO(i) *(__IO uint32_t *)(USB_BASE + USB_OTG_FIFO_BASE + ((i)*USB_OTG_FIFO_SIZE))
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#define USB_OTG_GLB ((USB_OTG_GlobalTypeDef *)(USBD_BASE))
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#define USB_OTG_DEV ((USB_OTG_DeviceTypeDef *)(USBD_BASE + USB_OTG_DEVICE_BASE))
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#define USB_OTG_PCGCCTL *(__IO uint32_t *)((uint32_t)USBD_BASE + USB_OTG_PCGCCTL_BASE)
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#define USB_OTG_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBD_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i)*USB_OTG_EP_REG_SIZE)))
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#define USB_OTG_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBD_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i)*USB_OTG_EP_REG_SIZE)))
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#define USB_OTG_FIFO(i) *(__IO uint32_t *)(USBD_BASE + USB_OTG_FIFO_BASE + ((i)*USB_OTG_FIFO_SIZE))
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extern uint32_t SystemCoreClock;
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@ -177,8 +164,8 @@ struct dwc2_ep_state {
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/* Driver state */
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USB_NOCACHE_RAM_SECTION struct dwc2_udc {
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__attribute__((aligned(32))) struct usb_setup_packet setup;
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struct dwc2_ep_state in_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< IN endpoint parameters*/
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struct dwc2_ep_state out_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< OUT endpoint parameters */
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struct dwc2_ep_state in_ep[CONFIG_USBDEV_EP_NUM]; /*!< IN endpoint parameters*/
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struct dwc2_ep_state out_ep[CONFIG_USBDEV_EP_NUM]; /*!< OUT endpoint parameters */
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} g_dwc2_udc;
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static inline int dwc2_reset(void)
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@ -574,7 +561,7 @@ int usb_dc_init(void)
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USB_LOG_INFO("GHWCFG4:%08x\r\n", USB_OTG_GLB->GHWCFG4);
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USB_LOG_INFO("dwc2 fsphy type:%d, hsphy type:%d, dma support:%d\r\n", fsphy_type, hsphy_type, dma_support);
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USB_LOG_INFO("dwc2 has %d endpoints, default config: %d endpoints\r\n", endpoints, USB_NUM_BIDIR_ENDPOINTS);
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USB_LOG_INFO("dwc2 has %d endpoints, default config: %d endpoints\r\n", endpoints, CONFIG_USBDEV_EP_NUM);
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USB_LOG_INFO("=================================\r\n");
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USB_OTG_DEV->DCTL |= USB_OTG_DCTL_SDIS;
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@ -659,19 +646,19 @@ int usb_dc_init(void)
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dwc2_set_txfifo(1, CONFIG_USB_DWC2_TX1_FIFO_SIZE / 4);
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dwc2_set_txfifo(2, CONFIG_USB_DWC2_TX2_FIFO_SIZE / 4);
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dwc2_set_txfifo(3, CONFIG_USB_DWC2_TX3_FIFO_SIZE / 4);
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#if USB_NUM_BIDIR_ENDPOINTS > 4
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#if CONFIG_USBDEV_EP_NUM > 4
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dwc2_set_txfifo(4, CONFIG_USB_DWC2_TX4_FIFO_SIZE / 4);
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#endif
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#if USB_NUM_BIDIR_ENDPOINTS > 5
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#if CONFIG_USBDEV_EP_NUM > 5
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dwc2_set_txfifo(5, CONFIG_USB_DWC2_TX5_FIFO_SIZE / 4);
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#endif
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#if USB_NUM_BIDIR_ENDPOINTS > 6
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#if CONFIG_USBDEV_EP_NUM > 6
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dwc2_set_txfifo(6, CONFIG_USB_DWC2_TX6_FIFO_SIZE / 4);
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#endif
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#if USB_NUM_BIDIR_ENDPOINTS > 7
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#if CONFIG_USBDEV_EP_NUM > 7
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dwc2_set_txfifo(7, CONFIG_USB_DWC2_TX7_FIFO_SIZE / 4);
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#endif
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#if USB_NUM_BIDIR_ENDPOINTS > 8
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#if CONFIG_USBDEV_EP_NUM > 8
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dwc2_set_txfifo(8, CONFIG_USB_DWC2_TX8_FIFO_SIZE / 4);
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#endif
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USB_OTG_GLB->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
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@ -731,7 +718,7 @@ int usbd_ep_open(const struct usb_endpoint_descriptor *ep)
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{
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uint8_t ep_idx = USB_EP_GET_IDX(ep->bEndpointAddress);
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if (ep_idx > (USB_NUM_BIDIR_ENDPOINTS - 1)) {
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if (ep_idx > (CONFIG_USBDEV_EP_NUM - 1)) {
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USB_LOG_ERR("Ep addr %02x overflow\r\n", ep->bEndpointAddress);
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return -1;
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}
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@ -1112,7 +1099,7 @@ void USBD_IRQHandler(void)
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dwc2_flush_txfifo(0x10U);
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dwc2_flush_rxfifo();
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for (uint8_t i = 0U; i < USB_NUM_BIDIR_ENDPOINTS; i++) {
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for (uint8_t i = 0U; i < CONFIG_USBDEV_EP_NUM; i++) {
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if (i == 0U) {
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USB_OTG_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;
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USB_OTG_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;
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@ -1156,7 +1143,7 @@ void USBD_IRQHandler(void)
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daintmask = USB_OTG_DEV->DAINTMSK;
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daintmask >>= 16;
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for (ep_idx = 1; ep_idx < USB_NUM_BIDIR_ENDPOINTS; ep_idx++) {
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for (ep_idx = 1; ep_idx < CONFIG_USBDEV_EP_NUM; ep_idx++) {
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if ((BIT(ep_idx) & ~daintmask) || (g_dwc2_udc.out_ep[ep_idx].ep_type != USB_ENDPOINT_TYPE_ISOCHRONOUS))
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continue;
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if (!(USB_OTG_OUTEP(ep_idx)->DOEPCTL & USB_OTG_DOEPCTL_USBAEP))
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@ -1178,7 +1165,7 @@ void USBD_IRQHandler(void)
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daintmask = USB_OTG_DEV->DAINTMSK;
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daintmask >>= 16;
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for (ep_idx = 1; ep_idx < USB_NUM_BIDIR_ENDPOINTS; ep_idx++) {
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for (ep_idx = 1; ep_idx < CONFIG_USBDEV_EP_NUM; ep_idx++) {
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if (((BIT(ep_idx) & ~daintmask)) || (g_dwc2_udc.in_ep[ep_idx].ep_type != USB_ENDPOINT_TYPE_ISOCHRONOUS))
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continue;
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@ -8,27 +8,23 @@
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#include "usb_dwc2_reg.h"
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#ifndef USBH_IRQHandler
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#define USBH_IRQHandler OTG_HS_IRQHandler
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#error "please define USBH_IRQHandler in usb_config.h"
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#endif
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#ifndef USB_BASE
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#define USB_BASE (0x40040000UL)
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#ifndef USBH_BASE
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#error "please define USBH_BASE in usb_config.h"
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#endif
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#ifndef CONFIG_USBHOST_PIPE_NUM
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#define CONFIG_USBHOST_PIPE_NUM 12
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#endif
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#if defined(STM32F7) || defined(STM32H7)
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#warning please check your buf addr is not in tcm and use nocache ram.
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#endif
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#define USB_OTG_GLB ((USB_OTG_GlobalTypeDef *)(USB_BASE))
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#define USB_OTG_PCGCCTL *(__IO uint32_t *)((uint32_t)USB_BASE + USB_OTG_PCGCCTL_BASE)
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#define USB_OTG_HPRT *(__IO uint32_t *)((uint32_t)USB_BASE + USB_OTG_HOST_PORT_BASE)
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#define USB_OTG_HOST ((USB_OTG_HostTypeDef *)(USB_BASE + USB_OTG_HOST_BASE))
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#define USB_OTG_HC(i) ((USB_OTG_HostChannelTypeDef *)(USB_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i)*USB_OTG_HOST_CHANNEL_SIZE)))
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#define USB_OTG_FIFO(i) *(__IO uint32_t *)(USB_BASE + USB_OTG_FIFO_BASE + ((i)*USB_OTG_FIFO_SIZE))
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#define USB_OTG_GLB ((USB_OTG_GlobalTypeDef *)(USBH_BASE))
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#define USB_OTG_PCGCCTL *(__IO uint32_t *)((uint32_t)USBH_BASE + USB_OTG_PCGCCTL_BASE)
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#define USB_OTG_HPRT *(__IO uint32_t *)((uint32_t)USBH_BASE + USB_OTG_HOST_PORT_BASE)
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#define USB_OTG_HOST ((USB_OTG_HostTypeDef *)(USBH_BASE + USB_OTG_HOST_BASE))
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#define USB_OTG_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBH_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i)*USB_OTG_HOST_CHANNEL_SIZE)))
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#define USB_OTG_FIFO(i) *(__IO uint32_t *)(USBH_BASE + USB_OTG_FIFO_BASE + ((i)*USB_OTG_FIFO_SIZE))
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struct dwc2_chan {
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uint8_t ep0_state;
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@ -483,7 +479,7 @@ int usb_hc_init(void)
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USB_OTG_GLB->GCCFG = usbh_get_dwc2_gccfg_conf();
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ret = dwc2_core_init();
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/* Force Host Mode*/
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dwc2_set_mode(USB_OTG_MODE_HOST);
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usb_osal_msleep(50);
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@ -1,27 +1,31 @@
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#include "usbd_core.h"
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#ifndef CONFIG_USBDEV_FSDEV_PMA_ACCESS
|
||||
#error "please define USBD_BASE in usb_config.h"
|
||||
#endif
|
||||
|
||||
#define PMA_ACCESS CONFIG_USBDEV_FSDEV_PMA_ACCESS
|
||||
#include "usb_fsdev_reg.h"
|
||||
|
||||
#ifndef USBD_IRQHandler
|
||||
#define USBD_IRQHandler USB_LP_CAN1_RX0_IRQHandler //use actual usb irq name instead
|
||||
#error "please define USBD_IRQHandler in usb_config.h"
|
||||
#endif
|
||||
|
||||
#ifndef USB_BASE
|
||||
#define USB_BASE (0x40005C00UL) /*!< USB_IP Peripheral Registers base address */
|
||||
#ifndef USBD_BASE
|
||||
#error "please define USBD_BASE in usb_config.h"
|
||||
#endif
|
||||
|
||||
#ifndef USB_NUM_BIDIR_ENDPOINTS
|
||||
#define USB_NUM_BIDIR_ENDPOINTS 8
|
||||
#ifndef CONFIG_USB_FSDEV_RAM_SIZE
|
||||
#define CONFIG_USB_FSDEV_RAM_SIZE 512
|
||||
#endif
|
||||
|
||||
#ifndef USB_RAM_SIZE
|
||||
#define USB_RAM_SIZE 512
|
||||
#ifndef CONFIG_USBDEV_EP_NUM
|
||||
#define CONFIG_USBDEV_EP_NUM 8
|
||||
#endif
|
||||
|
||||
#warning please check your PMA_ACCESS is 1 or 2
|
||||
#define USB ((USB_TypeDef *)USBD_BASE)
|
||||
|
||||
#define USB ((USB_TypeDef *)USB_BASE)
|
||||
|
||||
#define USB_BTABLE_SIZE (8 * USB_NUM_BIDIR_ENDPOINTS)
|
||||
#define USB_BTABLE_SIZE (8 * CONFIG_USBDEV_EP_NUM)
|
||||
|
||||
static void fsdev_write_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
|
||||
static void fsdev_read_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
|
||||
@ -42,10 +46,10 @@ struct fsdev_ep_state {
|
||||
/* Driver state */
|
||||
struct fsdev_udc {
|
||||
struct usb_setup_packet setup;
|
||||
volatile uint8_t dev_addr; /*!< USB Address */
|
||||
volatile uint32_t pma_offset; /*!< pma offset */
|
||||
struct fsdev_ep_state in_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< IN endpoint parameters*/
|
||||
struct fsdev_ep_state out_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< OUT endpoint parameters */
|
||||
volatile uint8_t dev_addr; /*!< USB Address */
|
||||
volatile uint32_t pma_offset; /*!< pma offset */
|
||||
struct fsdev_ep_state in_ep[CONFIG_USBDEV_EP_NUM]; /*!< IN endpoint parameters*/
|
||||
struct fsdev_ep_state out_ep[CONFIG_USBDEV_EP_NUM]; /*!< OUT endpoint parameters */
|
||||
} g_fsdev_udc;
|
||||
|
||||
__WEAK void usb_dc_low_level_init(void)
|
||||
@ -125,7 +129,7 @@ int usbd_ep_open(const struct usb_endpoint_descriptor *ep)
|
||||
{
|
||||
uint8_t ep_idx = USB_EP_GET_IDX(ep->bEndpointAddress);
|
||||
|
||||
if (ep_idx > (USB_NUM_BIDIR_ENDPOINTS - 1)) {
|
||||
if (ep_idx > (CONFIG_USBDEV_EP_NUM - 1)) {
|
||||
USB_LOG_ERR("Ep addr %02x overflow\r\n", ep->bEndpointAddress);
|
||||
return -1;
|
||||
}
|
||||
@ -162,7 +166,7 @@ int usbd_ep_open(const struct usb_endpoint_descriptor *ep)
|
||||
g_fsdev_udc.out_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes);
|
||||
g_fsdev_udc.out_ep[ep_idx].ep_enable = true;
|
||||
if (g_fsdev_udc.out_ep[ep_idx].ep_mps > g_fsdev_udc.out_ep[ep_idx].ep_pma_buf_len) {
|
||||
if (g_fsdev_udc.pma_offset + g_fsdev_udc.out_ep[ep_idx].ep_mps > USB_RAM_SIZE) {
|
||||
if (g_fsdev_udc.pma_offset + g_fsdev_udc.out_ep[ep_idx].ep_mps > CONFIG_USB_FSDEV_RAM_SIZE) {
|
||||
USB_LOG_ERR("Ep pma %02x overflow\r\n", ep->bEndpointAddress);
|
||||
return -1;
|
||||
}
|
||||
@ -180,7 +184,7 @@ int usbd_ep_open(const struct usb_endpoint_descriptor *ep)
|
||||
g_fsdev_udc.in_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes);
|
||||
g_fsdev_udc.in_ep[ep_idx].ep_enable = true;
|
||||
if (g_fsdev_udc.in_ep[ep_idx].ep_mps > g_fsdev_udc.in_ep[ep_idx].ep_pma_buf_len) {
|
||||
if (g_fsdev_udc.pma_offset + g_fsdev_udc.in_ep[ep_idx].ep_mps > USB_RAM_SIZE) {
|
||||
if (g_fsdev_udc.pma_offset + g_fsdev_udc.in_ep[ep_idx].ep_mps > CONFIG_USB_FSDEV_RAM_SIZE) {
|
||||
USB_LOG_ERR("Ep pma %02x overflow\r\n", ep->bEndpointAddress);
|
||||
return -1;
|
||||
}
|
||||
|
||||
@ -13,16 +13,17 @@
|
||||
#define HWREGB(x) \
|
||||
(*((volatile uint8_t *)(x)))
|
||||
|
||||
#if defined(CONFIG_USB_MUSB_SUNXI)
|
||||
|
||||
#ifndef USB_BASE
|
||||
#define USB_BASE (0x01c13000)
|
||||
#endif
|
||||
|
||||
#ifndef USBD_IRQHandler
|
||||
#define USBD_IRQHandler USBD_IRQHandler //use actual usb irq name instead
|
||||
#error "please define USBD_IRQHandler in usb_config.h"
|
||||
#endif
|
||||
|
||||
#ifndef USBD_BASE
|
||||
#error "please define USBD_BASE in usb_config.h"
|
||||
#endif
|
||||
|
||||
#define USB_BASE USBD_BASE
|
||||
|
||||
#if defined(CONFIG_USB_MUSB_SUNXI)
|
||||
#define MUSB_FADDR_OFFSET 0x98
|
||||
#define MUSB_POWER_OFFSET 0x40
|
||||
#define MUSB_TXIS_OFFSET 0x44
|
||||
@ -51,17 +52,8 @@
|
||||
#define MUSB_RXFIFOADD_OFFSET 0x96
|
||||
|
||||
#elif defined(CONFIG_USB_MUSB_CUSTOM)
|
||||
|
||||
#include "musb_custom.h"
|
||||
#else
|
||||
|
||||
#ifndef USBD_IRQHandler
|
||||
#define USBD_IRQHandler USB_INT_Handler //use actual usb irq name instead
|
||||
#endif
|
||||
|
||||
#ifndef USB_BASE
|
||||
#define USB_BASE (0x40086400UL)
|
||||
#endif
|
||||
|
||||
#define MUSB_FADDR_OFFSET 0x00
|
||||
#define MUSB_POWER_OFFSET 0x01
|
||||
#define MUSB_TXIS_OFFSET 0x02
|
||||
@ -94,8 +86,8 @@
|
||||
|
||||
#define USB_FIFO_BASE(ep_idx) (USB_BASE + MUSB_FIFO_OFFSET + 0x4 * ep_idx)
|
||||
|
||||
#ifndef USB_NUM_BIDIR_ENDPOINTS
|
||||
#define USB_NUM_BIDIR_ENDPOINTS 8
|
||||
#ifndef CONFIG_USBDEV_EP_NUM
|
||||
#define CONFIG_USBDEV_EP_NUM 8
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
@ -124,8 +116,8 @@ struct musb_udc {
|
||||
volatile uint8_t dev_addr;
|
||||
volatile uint32_t fifo_size_offset;
|
||||
__attribute__((aligned(32))) struct usb_setup_packet setup;
|
||||
struct musb_ep_state in_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< IN endpoint parameters*/
|
||||
struct musb_ep_state out_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< OUT endpoint parameters */
|
||||
struct musb_ep_state in_ep[CONFIG_USBDEV_EP_NUM]; /*!< IN endpoint parameters*/
|
||||
struct musb_ep_state out_ep[CONFIG_USBDEV_EP_NUM]; /*!< OUT endpoint parameters */
|
||||
} g_musb_udc;
|
||||
|
||||
static volatile uint8_t usb_ep0_state = USB_EP0_STATE_SETUP;
|
||||
@ -307,7 +299,7 @@ int usbd_ep_open(const struct usb_endpoint_descriptor *ep)
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (ep_idx > (USB_NUM_BIDIR_ENDPOINTS - 1)) {
|
||||
if (ep_idx > (CONFIG_USBDEV_EP_NUM - 1)) {
|
||||
USB_LOG_ERR("Ep addr %02x overflow\r\n", ep->bEndpointAddress);
|
||||
return -1;
|
||||
}
|
||||
@ -492,21 +484,20 @@ int usb_ep_out_data_avail(uint8_t ep_addr)
|
||||
{
|
||||
uint16_t old_ep_idx, length;
|
||||
uint8_t ep_idx = USB_EP_GET_IDX(ep_addr);
|
||||
|
||||
|
||||
old_ep_idx = musb_get_active_ep();
|
||||
musb_set_active_ep(ep_idx);
|
||||
|
||||
if (ep_idx == 0){
|
||||
if (!(HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & USB_CSRL0_RXRDY)){
|
||||
|
||||
if (ep_idx == 0) {
|
||||
if (!(HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & USB_CSRL0_RXRDY)) {
|
||||
musb_set_active_ep(old_ep_idx);
|
||||
return 0;
|
||||
}
|
||||
length = HWREGH(USB_BASE + MUSB_IND_RXCOUNT_OFFSET);
|
||||
musb_set_active_ep(old_ep_idx);
|
||||
return length;
|
||||
}
|
||||
else{
|
||||
if (!(HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) & USB_RXCSRL1_RXRDY)){
|
||||
} else {
|
||||
if (!(HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) & USB_RXCSRL1_RXRDY)) {
|
||||
musb_set_active_ep(old_ep_idx);
|
||||
return 0;
|
||||
}
|
||||
@ -520,18 +511,17 @@ int usb_ep_in_data_avail(uint8_t ep_addr)
|
||||
{
|
||||
uint16_t old_ep_idx, length;
|
||||
uint8_t ep_idx = USB_EP_GET_IDX(ep_addr);
|
||||
|
||||
|
||||
old_ep_idx = musb_get_active_ep();
|
||||
musb_set_active_ep(ep_idx);
|
||||
|
||||
if (ep_idx == 0){
|
||||
if (HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & USB_CSRL0_TXRDY){
|
||||
|
||||
if (ep_idx == 0) {
|
||||
if (HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & USB_CSRL0_TXRDY) {
|
||||
musb_set_active_ep(old_ep_idx);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
else{
|
||||
if (HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & USB_TXCSRL1_TXRDY){
|
||||
} else {
|
||||
if (HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & USB_TXCSRL1_TXRDY) {
|
||||
musb_set_active_ep(old_ep_idx);
|
||||
return 0;
|
||||
}
|
||||
@ -544,8 +534,8 @@ int usb_ep_in_data_avail(uint8_t ep_addr)
|
||||
int usb_ep_wait_in_data_avail(uint8_t ep_addr)
|
||||
{
|
||||
uint32_t cnt;
|
||||
|
||||
for (cnt = 0; cnt < 3000; cnt++){
|
||||
|
||||
for (cnt = 0; cnt < 3000; cnt++) {
|
||||
if (usb_ep_in_data_avail(ep_addr))
|
||||
return cnt;
|
||||
}
|
||||
@ -556,25 +546,24 @@ int usbd_read_packet(uint8_t ep_addr, uint8_t *buffer, uint16_t len)
|
||||
{
|
||||
uint16_t old_ep_idx, cnt;
|
||||
uint8_t ep_idx = USB_EP_GET_IDX(ep_addr);
|
||||
|
||||
|
||||
old_ep_idx = musb_get_active_ep();
|
||||
musb_set_active_ep(ep_idx);
|
||||
if (ep_idx == 0){
|
||||
if (!(HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & USB_CSRL0_RXRDY)){
|
||||
if (ep_idx == 0) {
|
||||
if (!(HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & USB_CSRL0_RXRDY)) {
|
||||
musb_set_active_ep(old_ep_idx);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
else{
|
||||
if (!(HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) & USB_RXCSRL1_RXRDY)){
|
||||
} else {
|
||||
if (!(HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) & USB_RXCSRL1_RXRDY)) {
|
||||
musb_set_active_ep(old_ep_idx);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
cnt = usb_ep_out_data_avail(ep_idx);
|
||||
if (cnt){
|
||||
if (cnt) {
|
||||
musb_read_packet(ep_idx, buffer, cnt);
|
||||
HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) &= ~(USB_RXCSRL1_OVER | USB_RXCSRL1_ERROR | USB_RXCSRL1_STALL| USB_RXCSRL1_STALLED);
|
||||
HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) &= ~(USB_RXCSRL1_OVER | USB_RXCSRL1_ERROR | USB_RXCSRL1_STALL | USB_RXCSRL1_STALLED);
|
||||
HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) &= ~(USB_RXCSRL1_RXRDY);
|
||||
musb_set_active_ep(old_ep_idx);
|
||||
}
|
||||
@ -585,28 +574,28 @@ int usbd_write_packet(uint8_t ep_addr, uint8_t *buffer, uint16_t len)
|
||||
{
|
||||
uint16_t old_ep_idx, cnt;
|
||||
uint8_t ep_idx = USB_EP_GET_IDX(ep_addr);
|
||||
|
||||
|
||||
old_ep_idx = musb_get_active_ep();
|
||||
musb_set_active_ep(ep_idx);
|
||||
if (HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & USB_TXCSRL1_UNDRN){
|
||||
if (HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & USB_TXCSRL1_UNDRN) {
|
||||
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~USB_TXCSRL1_UNDRN;
|
||||
}
|
||||
if (HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & USB_TXCSRL1_TXRDY){
|
||||
if (HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & USB_TXCSRL1_TXRDY) {
|
||||
musb_set_active_ep(old_ep_idx);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (!buffer && len){
|
||||
}
|
||||
|
||||
if (!buffer && len) {
|
||||
return -2;
|
||||
}
|
||||
|
||||
if (!len){
|
||||
|
||||
if (!len) {
|
||||
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) |= USB_TXCSRL1_TXRDY;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
cnt = usb_ep_in_data_avail(ep_idx);
|
||||
if (cnt){
|
||||
if (cnt) {
|
||||
cnt = MIN(cnt, len);
|
||||
musb_write_packet(ep_idx, buffer, cnt);
|
||||
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) |= USB_TXCSRL1_TXRDY;
|
||||
@ -811,7 +800,7 @@ void USBD_IRQHandler(void)
|
||||
HWREGH(USB_BASE + MUSB_TXIE_OFFSET) = USB_TXIE_EP0;
|
||||
HWREGH(USB_BASE + MUSB_RXIE_OFFSET) = 0;
|
||||
|
||||
for (uint8_t i = 1; i < USB_NUM_BIDIR_ENDPOINTS; i++) {
|
||||
for (uint8_t i = 1; i < CONFIG_USBDEV_EP_NUM; i++) {
|
||||
musb_set_active_ep(i);
|
||||
HWREGB(USB_BASE + MUSB_TXFIFOSZ_OFFSET) = 0;
|
||||
HWREGH(USB_BASE + MUSB_TXFIFOADD_OFFSET) = 0;
|
||||
|
||||
@ -14,19 +14,21 @@
|
||||
#define HWREGB(x) \
|
||||
(*((volatile uint8_t *)(x)))
|
||||
|
||||
#ifndef USBH_IRQHandler
|
||||
#error "please define USBH_IRQHandler in usb_config.h"
|
||||
#endif
|
||||
|
||||
#ifndef USBH_BASE
|
||||
#error "please define USBH_BASE in usb_config.h"
|
||||
#endif
|
||||
|
||||
#define USB_BASE USBH_BASE
|
||||
|
||||
#if CONFIG_USBHOST_PIPE_NUM != 4
|
||||
#error musb host ip only supports 4 pipe num
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_MUSB_SUNXI
|
||||
|
||||
#ifndef USB_BASE
|
||||
#define USB_BASE (0x01c13000)
|
||||
#endif
|
||||
|
||||
#ifndef USBH_IRQHandler
|
||||
#define USBH_IRQHandler USBH_IRQHandler //use actual usb irq name instead
|
||||
#endif
|
||||
|
||||
#define MUSB_FADDR_OFFSET 0x98
|
||||
#define MUSB_POWER_OFFSET 0x40
|
||||
#define MUSB_TXIS_OFFSET 0x44
|
||||
@ -76,16 +78,8 @@
|
||||
#define USB_RXHUBPORT_BASE(ep_idx) (USB_BASE + MUSB_RXHUBPORTx_OFFSET)
|
||||
|
||||
#elif defined(CONFIG_USB_MUSB_CUSTOM)
|
||||
|
||||
#include "musb_custom.h"
|
||||
#else
|
||||
#ifndef USBH_IRQHandler
|
||||
#define USBH_IRQHandler USB_INT_Handler
|
||||
#endif
|
||||
|
||||
#ifndef USB_BASE
|
||||
#define USB_BASE (0x40086400UL)
|
||||
#endif
|
||||
|
||||
#define MUSB_FADDR_OFFSET 0x00
|
||||
#define MUSB_POWER_OFFSET 0x01
|
||||
#define MUSB_TXIS_OFFSET 0x02
|
||||
@ -632,8 +626,6 @@ int usbh_submit_urb(struct usbh_urb *urb)
|
||||
urb->errorcode = -USB_ERR_BUSY;
|
||||
urb->actual_length = 0;
|
||||
|
||||
usb_osal_leave_critical_section(flags);
|
||||
|
||||
switch (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes)) {
|
||||
case USB_ENDPOINT_TYPE_CONTROL:
|
||||
usb_ep0_state = USB_EP0_STATE_SETUP;
|
||||
@ -650,6 +642,8 @@ int usbh_submit_urb(struct usbh_urb *urb)
|
||||
default:
|
||||
break;
|
||||
}
|
||||
usb_osal_leave_critical_section(flags);
|
||||
|
||||
if (urb->timeout > 0) {
|
||||
/* wait until timeout or sem give */
|
||||
ret = usb_osal_sem_take(pipe->waitsem, urb->timeout);
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user