espressif/esptool
1
0
Fork 0
mirror of https://github.com/espressif/esptool.git synced 2025-10-14 02:43:11 +08:00
Code Issues Packages Projects Releases Wiki Activity

fix(espefuse): Fix calibration efuses for ESP32-P4 ECO5

Browse Source
This commit is contained in:
Konstantin Kondrashov
2025-09-25 13:06:29 +03:00
committed by Radim Karniš
parent ae23ab254d
commit a1ca6c9c4a
1 changed files with 56 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

70
espefuse/efuse_defs/esp32p4_v3.0.yaml
View File

@@ -1,4 +1,4 @@
VER_NO: 8f99219081b5ec5521595bf60ed8b331
VER_NO: 0b11fcae5408d9e48251cefb10178c11
EFUSES:
WR_DIS : {show: y, blk : 0, word: 0, pos : 0, len : 32, start : 0, type : 'uint:32', wr_dis: null, rd_dis: null, alt : '', dict : '', desc: Disable programming of individual eFuses, rloc: EFUSE_RD_WR_DIS_REG, bloc: 'B0,B1,B2,B3'}
RD_DIS : {show: y, blk : 0, word: 1, pos : 0, len : 7, start : 32, type : 'uint:7', wr_dis : 0, rd_dis: null, alt : '', dict : '', desc: Disable reading from BlOCK4-10, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[6:0]', bloc: 'B4[6:0]'}
@@ -92,16 +92,42 @@ EFUSES:
PSRAM_VENDOR : {show: y, blk : 1, word: 2, pos: 18, len : 2, start : 82, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: PSRAM vendor, rloc: 'EFUSE_RD_MAC_SYS2_REG[19:18]', bloc: 'B10[3:2]'}
PKG_VERSION : {show: y, blk : 1, word: 2, pos: 20, len : 3, start : 84, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Package version, rloc: 'EFUSE_RD_MAC_SYS2_REG[22:20]', bloc: 'B10[6:4]'}
WAFER_VERSION_MAJOR_HI : {show: y, blk : 1, word: 2, pos: 23, len : 1, start : 87, type : bool, wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Major chip version (MSB), rloc: 'EFUSE_RD_MAC_SYS2_REG[23]', bloc: 'B10[7]'}
RESERVED_1_88 : {show: n, blk : 1, word: 2, pos: 24, len : 8, start : 88, type : 'uint:8', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SYS2_REG[31:24]', bloc: B11}
MAC_RESERVED_2 : {show: n, blk : 1, word: 3, pos : 0, len : 18, start : 96, type : 'uint:18', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Reserved, rloc: 'EFUSE_RD_MAC_SYS3_REG[17:0]', bloc: 'B12,B13,B14[1:0]'}
SYS_DATA_PART0_0 : {show: n, blk : 1, word: 3, pos: 18, len : 14, start: 114, type : 'uint:14', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Represents the first 14-bit of zeroth part of system data, rloc: 'EFUSE_RD_MAC_SYS3_REG[31:18]', bloc: 'B14[7:2],B15'}
SYS_DATA_PART0_1 : {show: n, blk : 1, word: 4, pos : 0, len : 32, start: 128, type : 'uint:32', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Represents the second 32-bit of zeroth part of system data, rloc: EFUSE_RD_MAC_SYS4_REG, bloc: 'B16,B17,B18,B19'}
SYS_DATA_PART0_2 : {show: n, blk : 1, word: 5, pos : 0, len : 32, start: 160, type : 'uint:32', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Represents the third 32-bit of zeroth part of system data, rloc: EFUSE_RD_MAC_SYS5_REG, bloc: 'B20,B21,B22,B23'}
LDO_VO1_DREF : {show: y, blk : 1, word: 2, pos: 24, len : 4, start : 88, type : 'uint:4', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Output VO1 parameter, rloc: 'EFUSE_RD_MAC_SYS2_REG[27:24]', bloc: 'B11[3:0]'}
LDO_VO2_DREF : {show: y, blk : 1, word: 2, pos: 28, len : 4, start : 92, type : 'uint:4', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Output VO2 parameter, rloc: 'EFUSE_RD_MAC_SYS2_REG[31:28]', bloc: 'B11[7:4]'}
LDO_VO1_MUL : {show: y, blk : 1, word: 3, pos : 0, len : 3, start : 96, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Output VO1 parameter, rloc: 'EFUSE_RD_MAC_SYS3_REG[2:0]', bloc: 'B12[2:0]'}
LDO_VO2_MUL : {show: y, blk : 1, word: 3, pos : 3, len : 3, start : 99, type : 'uint:3', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Output VO2 parameter, rloc: 'EFUSE_RD_MAC_SYS3_REG[5:3]', bloc: 'B12[5:3]'}
LDO_VO3_K : {show: y, blk : 1, word: 3, pos : 6, len : 8, start: 102, type : 'uint:8', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Output VO3 calibration parameter, rloc: 'EFUSE_RD_MAC_SYS3_REG[13:6]', bloc: 'B12[7:6],B13[5:0]'}
LDO_VO3_VOS : {show: y, blk : 1, word: 3, pos: 14, len : 6, start: 110, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Output VO3 calibration parameter, rloc: 'EFUSE_RD_MAC_SYS3_REG[19:14]', bloc: 'B13[7:6],B14[3:0]'}
LDO_VO3_C : {show: y, blk : 1, word: 3, pos: 20, len : 6, start: 116, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Output VO3 calibration parameter, rloc: 'EFUSE_RD_MAC_SYS3_REG[25:20]', bloc: 'B14[7:4],B15[1:0]'}
LDO_VO4_K : {show: y, blk : 1, word: 3, pos: 26, len : 8, start: 122, type : 'uint:8', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Output VO4 calibration parameter, rloc: 'EFUSE_RD_MAC_SYS3_REG[31:26]', bloc: 'B15[7:2],B16[1:0]'}
LDO_VO4_VOS : {show: y, blk : 1, word: 4, pos : 2, len : 6, start: 130, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Output VO4 calibration parameter, rloc: 'EFUSE_RD_MAC_SYS4_REG[7:2]', bloc: 'B16[7:2]'}
LDO_VO4_C : {show: y, blk : 1, word: 4, pos : 8, len : 6, start: 136, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Output VO4 calibration parameter, rloc: 'EFUSE_RD_MAC_SYS4_REG[13:8]', bloc: 'B17[5:0]'}
RESERVED_1_142 : {show: n, blk : 1, word: 4, pos: 14, len : 2, start: 142, type : 'uint:2', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SYS4_REG[15:14]', bloc: 'B17[7:6]'}
ACTIVE_HP_DBIAS : {show: y, blk : 1, word: 4, pos: 16, len : 4, start: 144, type : 'uint:4', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Active HP DBIAS of fixed voltage, rloc: 'EFUSE_RD_MAC_SYS4_REG[19:16]', bloc: 'B18[3:0]'}
ACTIVE_LP_DBIAS : {show: y, blk : 1, word: 4, pos: 20, len : 4, start: 148, type : 'uint:4', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: Active LP DBIAS of fixed voltage, rloc: 'EFUSE_RD_MAC_SYS4_REG[23:20]', bloc: 'B18[7:4]'}
RESERVED_1_152 : {show: n, blk : 1, word: 4, pos: 24, len : 4, start: 152, type : 'uint:4', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SYS4_REG[27:24]', bloc: 'B19[3:0]'}
DSLP_DBG : {show: y, blk : 1, word: 4, pos: 28, len : 4, start: 156, type : 'uint:4', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: DSLP BDG of fixed voltage, rloc: 'EFUSE_RD_MAC_SYS4_REG[31:28]', bloc: 'B19[7:4]'}
DSLP_LP_DBIAS : {show: y, blk : 1, word: 5, pos : 0, len : 5, start: 160, type : 'uint:5', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: DSLP LP DBIAS of fixed voltage, rloc: 'EFUSE_RD_MAC_SYS5_REG[4:0]', bloc: 'B20[4:0]'}
LP_DCDC_DBIAS_VOL_GAP : {show: y, blk : 1, word: 5, pos : 5, len : 5, start: 165, type : 'uint:5', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: DBIAS gap between LP and DCDC, rloc: 'EFUSE_RD_MAC_SYS5_REG[9:5]', bloc: 'B20[7:5],B21[1:0]'}
RESERVED_1_170 : {show: n, blk : 1, word: 5, pos: 10, len : 1, start: 170, type : bool, wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SYS5_REG[10]', bloc: 'B21[2]'}
PVT_400M_BIAS : {show: y, blk : 1, word: 5, pos: 11, len : 5, start: 171, type : 'uint:5', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: PVT_DCM_VSET when the CPU is at 400M, rloc: 'EFUSE_RD_MAC_SYS5_REG[15:11]', bloc: 'B21[7:3]'}
PVT_40M_BIAS : {show: y, blk : 1, word: 5, pos: 16, len : 5, start: 176, type : 'uint:5', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: PVT_DCM_VSET corresponding to about 0.9V fixed voltage when the CPU is at 40M, rloc: 'EFUSE_RD_MAC_SYS5_REG[20:16]', bloc: 'B22[4:0]'}
PVT_100M_BIAS : {show: y, blk : 1, word: 5, pos: 21, len : 5, start: 181, type : 'uint:5', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: PVT_DCM_VSET corresponding to about 1.0V fixed voltage when the CPU is at 100M, rloc: 'EFUSE_RD_MAC_SYS5_REG[25:21]', bloc: 'B22[7:5],B23[1:0]'}
RESERVED_1_186 : {show: n, blk : 1, word: 5, pos: 26, len : 6, start: 186, type : 'uint:6', wr_dis : 20, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SYS5_REG[31:26]', bloc: 'B23[7:2]'}
OPTIONAL_UNIQUE_ID : {show: y, blk : 2, word: 0, pos : 0, len: 128, start : 0, type: 'bytes:16', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Optional unique 128-bit ID, rloc: EFUSE_RD_SYS_PART1_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15'}
SYS_DATA_PART1_4 : {show: n, blk : 2, word: 4, pos : 0, len : 32, start: 128, type : 'uint:32', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Represents the zeroth 32-bit of first part of system data, rloc: EFUSE_RD_SYS_PART1_DATA4_REG, bloc: 'B16,B17,B18,B19'}
SYS_DATA_PART1_5 : {show: n, blk : 2, word: 5, pos : 0, len : 32, start: 160, type : 'uint:32', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Represents the zeroth 32-bit of first part of system data, rloc: EFUSE_RD_SYS_PART1_DATA5_REG, bloc: 'B20,B21,B22,B23'}
SYS_DATA_PART1_6 : {show: n, blk : 2, word: 6, pos : 0, len : 32, start: 192, type : 'uint:32', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Represents the zeroth 32-bit of first part of system data, rloc: EFUSE_RD_SYS_PART1_DATA6_REG, bloc: 'B24,B25,B26,B27'}
SYS_DATA_PART1_7 : {show: n, blk : 2, word: 7, pos : 0, len : 32, start: 224, type : 'uint:32', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Represents the zeroth 32-bit of first part of system data, rloc: EFUSE_RD_SYS_PART1_DATA7_REG, bloc: 'B28,B29,B30,B31'}
ADC1_AVE_INITCODE_ATTEN0 : {show: y, blk : 2, word: 4, pos : 0, len : 10, start: 128, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Average initcode of ADC1 atten0, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[9:0]', bloc: 'B16,B17[1:0]'}
ADC1_AVE_INITCODE_ATTEN1 : {show: y, blk : 2, word: 4, pos: 10, len : 10, start: 138, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Average initcode of ADC1 atten1, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[19:10]', bloc: 'B17[7:2],B18[3:0]'}
ADC1_AVE_INITCODE_ATTEN2 : {show: y, blk : 2, word: 4, pos: 20, len : 10, start: 148, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Average initcode of ADC1 atten2, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[29:20]', bloc: 'B18[7:4],B19[5:0]'}
ADC1_AVE_INITCODE_ATTEN3 : {show: y, blk : 2, word: 4, pos: 30, len : 10, start: 158, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Average initcode of ADC1 atten3, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[31:30]', bloc: 'B19[7:6],B20'}
ADC2_AVE_INITCODE_ATTEN0 : {show: y, blk : 2, word: 5, pos : 8, len : 10, start: 168, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Average initcode of ADC2 atten0, rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[17:8]', bloc: 'B21,B22[1:0]'}
ADC2_AVE_INITCODE_ATTEN1 : {show: y, blk : 2, word: 5, pos: 18, len : 10, start: 178, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Average initcode of ADC2 atten1, rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[27:18]', bloc: 'B22[7:2],B23[3:0]'}
ADC2_AVE_INITCODE_ATTEN2 : {show: y, blk : 2, word: 5, pos: 28, len : 10, start: 188, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Average initcode of ADC2 atten2, rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[31:28]', bloc: 'B23[7:4],B24[5:0]'}
ADC2_AVE_INITCODE_ATTEN3 : {show: y, blk : 2, word: 6, pos : 6, len : 10, start: 198, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: Average initcode of ADC2 atten3, rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[15:6]', bloc: 'B24[7:6],B25'}
ADC1_HI_DOUT_ATTEN0 : {show: y, blk : 2, word: 6, pos: 16, len : 10, start: 208, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: HI_DOUT of ADC1 atten0, rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[25:16]', bloc: 'B26,B27[1:0]'}
ADC1_HI_DOUT_ATTEN1 : {show: y, blk : 2, word: 6, pos: 26, len : 10, start: 218, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: HI_DOUT of ADC1 atten1, rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[31:26]', bloc: 'B27[7:2],B28[3:0]'}
ADC1_HI_DOUT_ATTEN2 : {show: y, blk : 2, word: 7, pos : 4, len : 10, start: 228, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: HI_DOUT of ADC1 atten2, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[13:4]', bloc: 'B28[7:4],B29[5:0]'}
ADC1_HI_DOUT_ATTEN3 : {show: y, blk : 2, word: 7, pos: 14, len : 10, start: 238, type : 'uint:10', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: HI_DOUT of ADC1 atten3, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[23:14]', bloc: 'B29[7:6],B30'}
RESERVED_2_248 : {show: n, blk : 2, word: 7, pos: 24, len : 8, start: 248, type : 'uint:8', wr_dis : 21, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[31:24]', bloc: B31}
BLOCK_USR_DATA : {show: y, blk : 3, word: 0, pos : 0, len: 192, start : 0, type: 'bytes:24', wr_dis : 22, rd_dis: null, alt : USER_DATA, dict : '', desc: User data, rloc: EFUSE_RD_USR_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23'}
RESERVED_3_192 : {show: n, blk : 3, word: 6, pos : 0, len : 8, start: 192, type : 'uint:8', wr_dis : 22, rd_dis: null, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_USR_DATA6_REG[7:0]', bloc: B24}
CUSTOM_MAC : {show: y, blk : 3, word: 6, pos : 8, len : 48, start: 200, type : 'bytes:6', wr_dis : 22, rd_dis: null, alt: MAC_CUSTOM USER_DATA_MAC_CUSTOM, dict : '', desc: Custom MAC, rloc: 'EFUSE_RD_USR_DATA6_REG[31:8]', bloc: 'B25,B26,B27,B28,B29,B30'}
@@ -112,10 +138,26 @@ EFUSES:
BLOCK_KEY3 : {show: y, blk : 7, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 26, rd_dis : 3, alt : KEY3, dict : '', desc: Key3 or user data, rloc: EFUSE_RD_KEY3_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'}
BLOCK_KEY4 : {show: y, blk : 8, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 27, rd_dis : 4, alt : KEY4, dict : '', desc: Key4 or user data, rloc: EFUSE_RD_KEY4_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'}
BLOCK_KEY5 : {show: y, blk : 9, word: 0, pos : 0, len: 256, start : 0, type: 'bytes:32', wr_dis : 28, rd_dis : 5, alt : KEY5, dict : '', desc: Key5 or user data, rloc: EFUSE_RD_KEY5_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'}
SYS_DATA_PART2_0 : {show: n, blk: 10, word: 0, pos : 0, len : 32, start : 0, type : 'uint:32', wr_dis : 29, rd_dis : 6, alt : '', dict : '', desc: Represents the first 32-bit of second part of system data, rloc: EFUSE_RD_SYS_PART2_DATA0_REG, bloc: 'B0,B1,B2,B3'}
SYS_DATA_PART2_1 : {show: n, blk: 10, word: 1, pos : 0, len : 32, start : 32, type : 'uint:32', wr_dis : 29, rd_dis : 6, alt : '', dict : '', desc: Represents the first 32-bit of second part of system data, rloc: EFUSE_RD_SYS_PART2_DATA1_REG, bloc: 'B4,B5,B6,B7'}
SYS_DATA_PART2_2 : {show: n, blk: 10, word: 2, pos : 0, len : 32, start : 64, type : 'uint:32', wr_dis : 29, rd_dis : 6, alt : '', dict : '', desc: Represents the second 32-bit of second part of system data, rloc: EFUSE_RD_SYS_PART2_DATA2_REG, bloc: 'B8,B9,B10,B11'}
SYS_DATA_PART2_3 : {show: n, blk: 10, word: 3, pos : 0, len : 32, start : 96, type : 'uint:32', wr_dis : 29, rd_dis : 6, alt : '', dict : '', desc: Represents the third 32-bit of second part of system data, rloc: EFUSE_RD_SYS_PART2_DATA3_REG, bloc: 'B12,B13,B14,B15'}
ADC2_HI_DOUT_ATTEN0 : {show: y, blk: 10, word: 0, pos : 0, len : 10, start : 0, type : 'uint:10', wr_dis : 29, rd_dis : 6, alt : '', dict : '', desc: HI_DOUT of ADC2 atten0, rloc: 'EFUSE_RD_SYS_PART2_DATA0_REG[9:0]', bloc: 'B0,B1[1:0]'}
ADC2_HI_DOUT_ATTEN1 : {show: y, blk: 10, word: 0, pos: 10, len : 10, start : 10, type : 'uint:10', wr_dis : 29, rd_dis : 6, alt : '', dict : '', desc: HI_DOUT of ADC2 atten1, rloc: 'EFUSE_RD_SYS_PART2_DATA0_REG[19:10]', bloc: 'B1[7:2],B2[3:0]'}
ADC2_HI_DOUT_ATTEN2 : {show: y, blk: 10, word: 0, pos: 20, len : 10, start : 20, type : 'uint:10', wr_dis : 29, rd_dis : 6, alt : '', dict : '', desc: HI_DOUT of ADC2 atten2, rloc: 'EFUSE_RD_SYS_PART2_DATA0_REG[29:20]', bloc: 'B2[7:4],B3[5:0]'}
ADC2_HI_DOUT_ATTEN3 : {show: y, blk: 10, word: 0, pos: 30, len : 10, start : 30, type : 'uint:10', wr_dis : 29, rd_dis : 6, alt : '', dict : '', desc: HI_DOUT of ADC2 atten3, rloc: 'EFUSE_RD_SYS_PART2_DATA0_REG[31:30]', bloc: 'B3[7:6],B4'}
ADC1_CH0_ATTEN0_INITCODE_DIFF : {show: y, blk: 10, word: 1, pos : 8, len : 4, start : 40, type : 'uint:4', wr_dis : 29, rd_dis : 6, alt : '', dict : '', desc: Gap between ADC1_ch0 and average initcode, rloc: 'EFUSE_RD_SYS_PART2_DATA1_REG[11:8]', bloc: 'B5[3:0]'}
ADC1_CH1_ATTEN0_INITCODE_DIFF : {show: y, blk: 10, word: 1, pos: 12, len : 4, start : 44, type : 'uint:4', wr_dis : 29, rd_dis : 6, alt : '', dict : '', desc: Gap between ADC1_ch1 and average initcode, rloc: 'EFUSE_RD_SYS_PART2_DATA1_REG[15:12]', bloc: 'B5[7:4]'}
ADC1_CH2_ATTEN0_INITCODE_DIFF : {show: y, blk: 10, word: 1, pos: 16, len : 4, start : 48, type : 'uint:4', wr_dis : 29, rd_dis : 6, alt : '', dict : '', desc: Gap between ADC1_ch2 and average initcode, rloc: 'EFUSE_RD_SYS_PART2_DATA1_REG[19:16]', bloc: 'B6[3:0]'}
ADC1_CH3_ATTEN0_INITCODE_DIFF : {show: y, blk: 10, word: 1, pos: 20, len : 4, start : 52, type : 'uint:4', wr_dis : 29, rd_dis : 6, alt : '', dict : '', desc: Gap between ADC1_ch3 and average initcode, rloc: 'EFUSE_RD_SYS_PART2_DATA1_REG[23:20]', bloc: 'B6[7:4]'}
ADC1_CH4_ATTEN0_INITCODE_DIFF : {show: y, blk: 10, word: 1, pos: 24, len : 4, start : 56, type : 'uint:4', wr_dis : 29, rd_dis : 6, alt : '', dict : '', desc: Gap between ADC1_ch4 and average initcode, rloc: 'EFUSE_RD_SYS_PART2_DATA1_REG[27:24]', bloc: 'B7[3:0]'}
ADC1_CH5_ATTEN0_INITCODE_DIFF : {show: y, blk: 10, word: 1, pos: 28, len : 4, start : 60, type : 'uint:4', wr_dis : 29, rd_dis : 6, alt : '', dict : '', desc: Gap between ADC1_ch5 and average initcode, rloc: 'EFUSE_RD_SYS_PART2_DATA1_REG[31:28]', bloc: 'B7[7:4]'}
ADC1_CH6_ATTEN0_INITCODE_DIFF : {show: y, blk: 10, word: 2, pos : 0, len : 4, start : 64, type : 'uint:4', wr_dis : 29, rd_dis : 6, alt : '', dict : '', desc: Gap between ADC1_ch6 and average initcode, rloc: 'EFUSE_RD_SYS_PART2_DATA2_REG[3:0]', bloc: 'B8[3:0]'}
ADC1_CH7_ATTEN0_INITCODE_DIFF : {show: y, blk: 10, word: 2, pos : 4, len : 4, start : 68, type : 'uint:4', wr_dis : 29, rd_dis : 6, alt : '', dict : '', desc: Gap between ADC1_ch7 and average initcode, rloc: 'EFUSE_RD_SYS_PART2_DATA2_REG[7:4]', bloc: 'B8[7:4]'}
ADC2_CH0_ATTEN0_INITCODE_DIFF : {show: y, blk: 10, word: 2, pos : 8, len : 4, start : 72, type : 'uint:4', wr_dis : 29, rd_dis : 6, alt : '', dict : '', desc: Gap between ADC2_ch0 and average initcode, rloc: 'EFUSE_RD_SYS_PART2_DATA2_REG[11:8]', bloc: 'B9[3:0]'}
ADC2_CH1_ATTEN0_INITCODE_DIFF : {show: y, blk: 10, word: 2, pos: 12, len : 4, start : 76, type : 'uint:4', wr_dis : 29, rd_dis : 6, alt : '', dict : '', desc: Gap between ADC2_ch1 and average initcode, rloc: 'EFUSE_RD_SYS_PART2_DATA2_REG[15:12]', bloc: 'B9[7:4]'}
ADC2_CH2_ATTEN0_INITCODE_DIFF : {show: y, blk: 10, word: 2, pos: 16, len : 4, start : 80, type : 'uint:4', wr_dis : 29, rd_dis : 6, alt : '', dict : '', desc: Gap between ADC2_ch2 and average initcode, rloc: 'EFUSE_RD_SYS_PART2_DATA2_REG[19:16]', bloc: 'B10[3:0]'}
ADC2_CH3_ATTEN0_INITCODE_DIFF : {show: y, blk: 10, word: 2, pos: 20, len : 4, start : 84, type : 'uint:4', wr_dis : 29, rd_dis : 6, alt : '', dict : '', desc: Gap between ADC2_ch3 and average initcode, rloc: 'EFUSE_RD_SYS_PART2_DATA2_REG[23:20]', bloc: 'B10[7:4]'}
ADC2_CH4_ATTEN0_INITCODE_DIFF : {show: y, blk: 10, word: 2, pos: 24, len : 4, start : 88, type : 'uint:4', wr_dis : 29, rd_dis : 6, alt : '', dict : '', desc: Gap between ADC2_ch4 and average initcode, rloc: 'EFUSE_RD_SYS_PART2_DATA2_REG[27:24]', bloc: 'B11[3:0]'}
ADC2_CH5_ATTEN0_INITCODE_DIFF : {show: y, blk: 10, word: 2, pos: 28, len : 4, start : 92, type : 'uint:4', wr_dis : 29, rd_dis : 6, alt : '', dict : '', desc: Gap between ADC2_ch5 and average initcode, rloc: 'EFUSE_RD_SYS_PART2_DATA2_REG[31:28]', bloc: 'B11[7:4]'}
TEMPERATURE_SENSOR : {show: y, blk: 10, word: 3, pos : 0, len : 10, start : 96, type : 'uint:10', wr_dis : 29, rd_dis : 6, alt : '', dict : '', desc: Temperature calibration data, rloc: 'EFUSE_RD_SYS_PART2_DATA3_REG[9:0]', bloc: 'B12,B13[1:0]'}
RESERVED_10_106 : {show: n, blk: 10, word: 3, pos: 10, len : 22, start: 106, type : 'uint:22', wr_dis : 29, rd_dis : 6, alt : '', dict : '', desc: reserved, rloc: 'EFUSE_RD_SYS_PART2_DATA3_REG[31:10]', bloc: 'B13[7:2],B14,B15'}
SYS_DATA_PART2_4 : {show: n, blk: 10, word: 4, pos : 0, len : 32, start: 128, type : 'uint:32', wr_dis : 29, rd_dis : 6, alt : '', dict : '', desc: Represents the fourth 32-bit of second part of system data, rloc: EFUSE_RD_SYS_PART2_DATA4_REG, bloc: 'B16,B17,B18,B19'}
SYS_DATA_PART2_5 : {show: n, blk: 10, word: 5, pos : 0, len : 32, start: 160, type : 'uint:32', wr_dis : 29, rd_dis : 6, alt : '', dict : '', desc: Represents the fifth 32-bit of second part of system data, rloc: EFUSE_RD_SYS_PART2_DATA5_REG, bloc: 'B20,B21,B22,B23'}
PVT_LIMIT : {show: n, blk: 10, word: 6, pos : 0, len : 16, start: 192, type : 'uint:16', wr_dis : 29, rd_dis : 6, alt : '', dict : '', desc: Power glitch monitor threthold, rloc: 'EFUSE_RD_SYS_PART2_DATA6_REG[15:0]', bloc: 'B24,B25'}