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dcd/dwc2: fix enumration when EP0 size=8

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Signed-off-by: Mengsk <admin@hifiphile.com>
This commit is contained in:
Mengsk
2025-10-06 17:12:05 +02:00
parent 54fffd0de2
commit 5ac0bed779
2 changed files with 23 additions and 6 deletions
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23
src/portable/synopsys/dwc2/dcd_dwc2.c
View File

@@ -168,7 +168,7 @@ static void dma_setup_prepare(uint8_t rhport) {
- All EP OUT shared a unique OUT FIFO which uses (for Slave or Buffer DMA, Scatt/Gather DMA use different formula):
- 13 for setup packets + control words (up to 3 setup packets).
- 1 for global NAK (not required/used here).
- Largest-EPsize/4 + 1. ( FS: 64 bytes, HS: 512 bytes). Recommended is "2 x (Largest-EPsize/4 + 1)"
- Largest-EPsize/4 + 1. (FS: 64 bytes, HS: 512 bytes). Recommended is "2 x (Largest-EPsize/4 + 1)"
- 2 for each used OUT endpoint
Therefore GRXFSIZ = 13 + 1 + 2 x (Largest-EPsize/4 + 1) + 2 x EPOUTnum
@@ -701,12 +701,23 @@ static void handle_bus_reset(uint8_t rhport) {
dcfg.address = 0;
dwc2->dcfg = dcfg.value;
// Fixed both control EP0 size to 64 bytes
dwc2->epin[0].ctl &= ~(0x03 << DIEPCTL_MPSIZ_Pos);
dwc2->epout[0].ctl &= ~(0x03 << DOEPCTL_MPSIZ_Pos);
// 6. Configure maximum packet size for EP0
uint8_t mps = 0;
switch (CFG_TUD_ENDPOINT0_SIZE) {
case 8: mps = 3; break;
case 16: mps = 2; break;
case 32: mps = 1; break;
case 64: mps = 0; break;
default: mps = 0; break;
}
xfer_status[0][TUSB_DIR_OUT].max_size = 64;
xfer_status[0][TUSB_DIR_IN].max_size = 64;
dwc2->epin[0].ctl &= ~DIEPCTL0_MPSIZ_Msk;
dwc2->epout[0].ctl &= ~DOEPCTL0_MPSIZ_Msk;
dwc2->epin[0].ctl |= mps << DIEPCTL0_MPSIZ_Pos;
dwc2->epout[0].ctl |= mps << DOEPCTL0_MPSIZ_Pos;
xfer_status[0][TUSB_DIR_OUT].max_size = CFG_TUD_ENDPOINT0_SIZE;
xfer_status[0][TUSB_DIR_IN].max_size = CFG_TUD_ENDPOINT0_SIZE;
if(dma_device_enabled(dwc2)) {
dma_setup_prepare(rhport);

6
src/portable/synopsys/dwc2/dwc2_type.h
View File

@@ -1847,6 +1847,9 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size");
#define HPTXFSIZ_PTXFD HPTXFSIZ_PTXFD_Msk // Host periodic TxFIFO depth
/******************** Bit definition for DIEPCTL register ********************/
#define DIEPCTL0_MPSIZ_Pos (0U)
#define DIEPCTL0_MPSIZ_Msk (0x3UL << DIEPCTL0_MPSIZ_Pos) // 0x00000003
#define DIEPCTL0_MPSIZ DIEPCTL0_MPSIZ_Msk // Maximum packet size(endpoint 0)
#define DIEPCTL_MPSIZ_Pos (0U)
#define DIEPCTL_MPSIZ_Msk (0x7FFUL << DIEPCTL_MPSIZ_Pos) // 0x000007FF
#define DIEPCTL_MPSIZ DIEPCTL_MPSIZ_Msk // Maximum packet size
@@ -2155,6 +2158,9 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size");
#define EPCTL_EPENA EPCTL_EPENA_Msk // Endpoint enable
/******************** Bit definition for DOEPCTL register ********************/
#define DOEPCTL0_MPSIZ_Pos (0U)
#define DOEPCTL0_MPSIZ_Msk (0x3UL << DOEPCTL0_MPSIZ_Pos) // 0x00000003
#define DOEPCTL0_MPSIZ DOEPCTL0_MPSIZ_Msk // Maximum packet size(endpoint 0)
#define DOEPCTL_MPSIZ_Pos (0U)
#define DOEPCTL_MPSIZ_Msk (0x7FFUL << DOEPCTL_MPSIZ_Pos) // 0x000007FF
#define DOEPCTL_MPSIZ DOEPCTL_MPSIZ_Msk // Maximum packet size //Bit 1