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SYSENTER: Correct CS SS segment values

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Jonathan Campbell
2021-11-22 10:43:24 -08:00
parent bf515da36c
commit 253304ee99
1 changed files with 3 additions and 3 deletions
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6
src/cpu/cpu.cpp
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@@ -4153,7 +4153,7 @@ bool CPU_SYSENTER() {
cpu.code.big = true;
cpu.cpl = 0;
Segs.val[ss] = (cpu_sep_cs & 0xFFFC) + 8; /* Yes, really. Look it up in Intel's documentation */
Segs.val[ss] = (cpu_sep_cs & 0xFFFC) + 0x8; /* Yes, really. Look it up in Intel's documentation */
Segs.phys[ss] = 0;
Segs.limit[ss] = 0xFFFFFFFF;
Segs.expanddown[ss] = false;
@@ -4181,14 +4181,14 @@ bool CPU_SYSEXIT() {
/* NTS: Do NOT use SetSegGeneral, SYSENTER is documented to set CS and SS based on what was given to the MSR,
* but with fixed and very specific descriptor cache values that represent 32-bit flat segments with
* base == 0 and limit == 4GB. */
Segs.val[cs] = (cpu_sep_cs | 3);
Segs.val[cs] = (cpu_sep_cs | 3) + 0x10; /* Yes, really. Look it up in Intel's documentation */
Segs.phys[cs] = 0;
Segs.limit[cs] = 0xFFFFFFFF;
Segs.expanddown[cs] = false;
cpu.code.big = true;
cpu.cpl = 3;
Segs.val[ss] = (cpu_sep_cs | 3) + 8; /* Yes, really. Look it up in Intel's documentation */
Segs.val[ss] = (cpu_sep_cs | 3) + 0x8; /* Yes, really. Look it up in Intel's documentation */
Segs.phys[ss] = 0;
Segs.limit[ss] = 0xFFFFFFFF;
Segs.expanddown[ss] = false;