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Jonathan Campbell
@@ -3,388 +3,59 @@ arch "x86";
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description "Machine-parsable list of opcodes";
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charset_encoding "UTF-8"; /* default */
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define segment reference "segref" {
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description "data segment reference, or segment referenced by override";
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type segment reference;
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on start of instruction set to null;
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/* predefined variables:
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codesize == 16 || codesize == 32 || codesize == 64: word code access size (affects code handling)
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datasize == 16 || datasize == 32 || datasize == 64: word data access size (affects data handling)
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dsreg: default segment OR segment override
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CS, DS, ES, FS, GS, SS: segment registers
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reg: general register, operand (regw if word, regb if byte)
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regb: general register, byte operand (AH, AL, etc)
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regw: general register, word operand (AX, BX, CX, etc if 16-bit, EAX, EBX, etc if 32-bit)
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sreg: segment register, operand
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rm: register/memory operand, word operand
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rmb: register/memory operand, byte operand
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rmw: register/memory operand, byte operand
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mrm: mod/reg/rm (with optional scalar/index/byte if 32-bit addressing with the right combination)
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accum: AX/EAX
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immb: 8-bit immediate
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immw: word immediate
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sib: scalar/index/byte
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flags: flags register (FLAGS if 16-bit, EFLAGS if 32-bit)
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flags(...): specific flags (bitmask)
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stackp: stack pointer (SP/ESP)
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basep: base pointer (BP/EBP)
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ip: instruction pointer (IP/EIP) */
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/* avoid copy-pasta */
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common opcode "ADD" param(dst,src) {
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modifies flags(CF,PF,AF,ZF,SF,OF);
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/* dst += src */
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input dst,src; /* reads dst, src */
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output dst; /* writes dst */
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}
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define modeflag "mode64" {
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description "64-bit long mode";
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type boolean;
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opcode sequence(0x00 mrm) name "ADD" { /* ADD r/m, reg */
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common opcode "ADD" param(rmb,regb);
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}
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define modeflag "data32" {
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description "32-bit data encoding";
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type boolean;
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opcode sequence(0x01 mrm) name "ADD" { /* ADD r/m, reg */
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common opcode "ADD" param(rmw,regw);
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}
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define modeflag "addr32" {
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description "32-bit address encoding";
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type boolean;
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opcode sequence(0x02 mrm) name "ADD" { /* ADD reg, r/m */
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common opcode "ADD" param(regb,rmb);
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}
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define tempflag "dec_data32" {
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description "32-bit data encoding mode";
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on start of instruction set to modeflag "data32";
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type boolean;
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opcode sequence(0x03 mrm) name "ADD" { /* ADD reg, r/m */
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common opcode "ADD" param(regw,rmw);
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}
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define tempflag "dec_addr32" {
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description "32-bit address encoding mode";
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on start of instruction set to modeflag "addr32";
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type boolean;
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opcode sequence(0x04 immb) name "ADD" { /* ADD AL, imm */
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common opcode "ADD" param(AL,immb);
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}
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define register type "general" {
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type uint64_t;
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subset "qw" bit range(63:0);
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subset "dw" bit range(31:0);
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subset "w" bit range(15:0);
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subset "bh" bit range(15:8);
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subset "b" bit range( 7:0);
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}
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define register type "cpu flags" {
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type register type "general";
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}
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define register type "segment" {
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type uint16_t;
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subset "selector_index" bit range(15:3);
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subset "ldt_select" bit value 2;
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subset "priv_level" bit range(1:0);
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}
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define register "RAX" {
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type register type "general";
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}
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define register "RBX" {
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type register type "general";
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}
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define register "RCX" {
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type register type "general";
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}
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define register "RDX" {
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type register type "general";
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}
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define register "RSI" {
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type register type "general";
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}
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define register "RDI" {
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type register type "general";
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}
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define register "RBP" {
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type register type "general";
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}
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define register "RSP" {
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type register type "general";
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}
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define register "RIP" {
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type register type "general";
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}
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define register "RFLAGS" {
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type register type "cpu flags";
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subset "cf" bit value 0 description "carry";
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subset "pf" bit value 2 description "parity";
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subset "af" bit value 4 description "aux";
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subset "zf" bit value 6 description "zero";
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subset "sf" bit value 7 description "sign";
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subset "tf" bit value 8 description "trap";
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subset "if" bit value 9 description "interrupt enable";
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subset "df" bit value 10 description "direction";
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subset "of" bit value 11 description "overflow";
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subset "iopl" bit range(13:12) description "I/O privilege level";
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subset "nt" bit value 14 description "nested task";
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subset "rf" bit value 16 description "resume";
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subset "vm" bit value 17 description "virtual 8086 mode";
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subset "ac" bit value 18 description "alignment check";
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subset "vif" bit value 19 description "virtual interrupt";
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subset "vip" bit value 20 description "virtual interrupt pending";
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subset "id"; bit value 21 description "identification (CPUID)";
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subset "common results" bitmask("cf","pf","af","zf",sf","of");
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subset "popf" eval(subset("common results") | bitmask("tf","if","df"));
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}
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define register "EAX" {
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subset "dw" of register "RAX";
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}
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define register "EBX" {
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subset "dw" of register "RBX";
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}
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define register "ECX" {
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subset "dw" of register "RCX";
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}
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define register "EDX" {
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subset "dw" of register "RDX";
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}
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define register "ESI" {
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subset "dw" of register "RSI";
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}
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define register "EDI" {
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subset "dw" of register "RDI";
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}
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define register "EBP" {
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subset "dw" of register "RBP";
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}
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define register "ESP" {
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subset "dw" of register "RSP";
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}
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define register "EIP" {
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subset "dw" of register "RIP";
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}
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define register "EFLAGS" {
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subset "dw" of register "RFLAGS";
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}
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define register "AX" {
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subset "w" of register "EAX";
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}
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define register "BX" {
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subset "w" of register "EBX";
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}
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define register "CX" {
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subset "w" of register "ECX";
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}
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define register "DX" {
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subset "w" of register "EDX";
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}
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define register "SI" {
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subset "w" of register "ESI";
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}
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define register "DI" {
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subset "w" of register "EDI";
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}
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define register "BP" {
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subset "w" of register "EBP";
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}
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define register "SP" {
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subset "w" of register "ESP";
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}
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define register "IP" {
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subset "w" of register "EIP";
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}
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define register "FLAGS" {
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subset "w" of register "EFLAGS";
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}
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define register "AL" {
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subset "b" of register "AX";
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}
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define register "BL" {
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subset "b" of register "BX";
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}
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define register "CL" {
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subset "b" of register "CX";
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}
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define register "DL" {
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subset "b" of register "DX";
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}
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define register "AH" {
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subset "bh" of register "AX";
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}
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define register "BH" {
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subset "bh" of register "BX";
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}
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define register "CH" {
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subset "bh" of register "CX";
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}
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define register "DH" {
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subset "bh" of register "DX";
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}
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define register "CS" {
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type register type "segment";
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}
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define register "DS" {
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type register type "segment";
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}
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define register "ES" {
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type register type "segment";
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}
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define register "FS" {
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type register type "segment";
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}
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define register "GS" {
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type register type "segment";
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}
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define register "SS" {
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type register type "segment";
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}
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define register map "genregw" {
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index 0 register "RAX";
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index 1 register "RCX";
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index 2 register "RDX";
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index 3 register "RBX";
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index 4 register "RSP";
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index 5 register "RBP";
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index 6 register "RSI";
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index 7 register "RDI";
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}
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define register map "genregb" {
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index 0 register "AL";
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index 1 register "CL";
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index 2 register "DL";
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index 3 register "BL";
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index 4 register "AH";
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index 5 register "CH";
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index 6 register "DH";
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index 7 register "BH";
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}
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define register map "genreg" {
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input param "w" type boolean;
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if w == true {
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return register map "genregw";
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}
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else {
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return register map "genregb";
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}
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}
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define register map "sreg" {
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index 0 register "ES";
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index 1 register "CS";
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index 2 register "SS";
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index 3 register "DS";
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index 4 register "FS";
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index 5 register "GS";
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/* no index 6 */
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/* no index 7 */
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}
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define encoding "mrm" {
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description "mod/reg/rm field as encoded in instruction";
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type uint8_t;
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subset "mod" bit range(7:6);
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subset "reg" bit range(5:3);
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subset "rm" bit range(2:0);
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}
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define encoding "sib" {
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description "scale/index/base field as encoded in instruction";
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type uint8_t;
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subset "scale" bit range(7:6);
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subset "index" bit range(5:3);
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subset "base" bit range(2:0);
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}
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define register "mrm_dataseg" {
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if segref != null {
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return segref;
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}
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return register "DS";
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}
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define expression map "mrm16_eaofs" {
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input "mrm" encoding "mrm";
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index mrm.rm == 0 return eval(register "BX" + register "SI");
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index mrm.rm == 1 return eval(register "BX" + register "DI");
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index mrm.rm == 2 return eval(register "BP" + register "SI");
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index mrm.rm == 3 return eval(register "BP" + register "DI");
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index mrm.rm == 4 return eval(register "SI");
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index mrm.rm == 5 return eval(register "DI");
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index mrm.rm == 6 return eval(register "BP");
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index mrm.rm == 7 return eval(register "BX");
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return null;
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}
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define effective address "mrm16_eadisp" {
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return type memory reference;
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input "mrm" encoding "mrm";
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input "disp" type int16_t;
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require !(mrm.mod == 0 && mrm.rm == 6); /* make sure it's not [offset] */
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require mrm.mod != 3; /* mod == 3 means r/m is register */
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define var "ofs" description "offset" type uint16_t;
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define var "seg" description "segment" type segment reference;
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if segref != null {
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seg = segref;
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}
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else if mrm.rm == 2 || mrm.rm == 3 || mrm.rm == 6 {
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/* anything involving BP refers by default to the stack segment */
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seg = segment reference "SS";
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}
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else {
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seg = segment reference "DS";
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}
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ofs = eval((expression map "mrm16_eaofs" with param "mrm") + disp);
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return memory reference segment seg offset ofs;
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}
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define effective address "mrm16" {
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input "mrm" encoding "mrm";
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input "w" type boolean;
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if x.mod == 3 {
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return register map "genreg" with param "w" = w;
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}
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else if x.mod == 0 && x.rm == 6 {
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define var "disp" description "offset" type uint16_t;
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disp = cpu instruction fetch uint16_t;
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return memory reference offset "mrm_dataseg" offset disp;
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}
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else {
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define var "disp" description "displacement" type int16_t; /* signed two's complement */
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if x.mod == 1 {
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disp = cpu instruction fetch int8_t;
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}
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else if x.mod == 2 {
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disp = cpu instruction fetch int16_t;
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}
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else {
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disp = 0;
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}
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return effective address "mem16_eadisp" with param "mrm" = mrm with param "disp" = disp;
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}
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opcode sequence(0x05 immw) name "ADD" { /* ADD [E]AX, imm */
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common opcode "ADD" param(accum,immw);
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}
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