mirror of
https://github.com/joncampbell123/dosbox-x.git
synced 2025-10-14 02:17:36 +08:00
246 lines
8.1 KiB
C
246 lines
8.1 KiB
C
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#include "dos_inc.h"
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#define PC98_GDC_FIFO_SIZE 32 /* taken from Neko Project II, but what is it really? */
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#define GDC_COMMAND_BYTE 0x100
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enum {
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GDC_MASTER=0,
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GDC_SLAVE=1
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};
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// VOPBIT_* source: Neko Project II
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// operate: bit0 access page
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// bit1 egc enable
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// bit2 grcg bit6
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// bit3 grcg bit7
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// bit4 analog enable (16/256-color mode). 8-color mode if not.
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// bit5 pc9821 vga
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enum {
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VOPBIT_ACCESS = 0,
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VOPBIT_EGC = 1,
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VOPBIT_GRCG = 2,
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VOPBIT_ANALOG = 4,
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VOPBIT_VGA = 5,
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VOPBIT_PEGC_PLANAR = 6
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};
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union pc98_tile {
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uint8_t b[2];
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uint16_t w;
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};
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struct PC98_GDC_state {
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PC98_GDC_state();
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void reset_fifo(void);
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void reset_rfifo(void);
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void flush_fifo_old(void);
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bool write_fifo(const uint16_t c);
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bool write_rfifo(const uint8_t c);
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bool write_fifo_command(const unsigned char c);
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bool write_fifo_param(const unsigned char c);
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bool rfifo_has_content(void);
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uint8_t read_status(void);
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uint8_t rfifo_read_data(void);
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void idle_proc(void);
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void force_fifo_complete(void);
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void take_cursor_char_setup(unsigned char bi);
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void take_cursor_pos(unsigned char bi);
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void take_reset_sync_parameters(void);
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void cursor_advance(void);
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void draw_reset(void);
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void vectw(unsigned char bi);
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void set_vectw(uint8_t ope, uint8_t dir, uint16_t dc, uint16_t d, uint16_t d2, uint16_t d1, uint16_t dm);
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void exec(uint8_t command);
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void prepare(void);
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void draw_dot(uint16_t x, uint16_t y);
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void pset(void);
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void line(void);
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void text(void);
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void circle(void);
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void box(void);
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void set_vectl(int x1, int y1, int x2, int y2);
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void set_mode(uint8_t mode);
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void set_csrw(uint32_t ead, uint8_t dad);
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void set_textw(uint16_t pattern);
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void set_textw(uint8_t *tile, uint8_t len);
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void begin_frame(void);
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void next_line(void);
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void load_display_partition(void);
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void next_display_partition(void);
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size_t fifo_can_read(void);
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bool fifo_empty(void);
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uint16_t read_fifo(void);
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enum {
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RT_MULBIT = 15,
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RT_TABLEBIT = 12,
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RT_TABLEMAX = (1 << RT_TABLEBIT)
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};
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struct VECTDIR {
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int16_t x;
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int16_t y;
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int16_t x2;
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int16_t y2;
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};
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static const VECTDIR vectdir[16];
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static const PhysPt gram_base[4];
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static uint16_t gdc_rt[RT_TABLEMAX + 1];
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struct GDC_DRAW {
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PhysPt base;
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uint32_t ead;
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uint16_t dc;
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uint16_t d;
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uint16_t d1;
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uint16_t d2;
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uint16_t dm;
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uint16_t pattern;
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uint16_t x;
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uint16_t y;
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uint8_t tx[8];
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uint8_t dad;
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uint8_t ope;
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uint8_t dir;
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uint8_t dgd;
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uint8_t wg;
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uint8_t dots;
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uint8_t mode;
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uint8_t zoom;
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} draw;
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/* NTS:
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*
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* We're following the Neko Project II method of FIFO emulation BUT
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* I wonder if the GDC maintains two FIFOs and allows stacking params
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* in one and commands in another....? */
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uint8_t cmd_parm_tmp[11]; /* temp storage before accepting params */
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uint8_t rfifo[PC98_GDC_FIFO_SIZE];
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uint8_t rfifo_read,rfifo_write;
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uint16_t fifo[PC98_GDC_FIFO_SIZE]; /* NTS: Neko Project II uses one big FIFO for command and data, which makes sense to me */
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uint8_t fifo_read,fifo_write;
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uint8_t param_ram[16];
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uint8_t param_ram_wptr;
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uint16_t scan_address;
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uint8_t row_height;
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uint8_t row_line;
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uint8_t display_partition;
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uint16_t display_partition_rem_lines;
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uint8_t display_partition_mask;
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uint16_t active_display_lines; /* AL (translated) */
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uint16_t active_display_words_per_line;/* AW bits (translated) */
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uint16_t display_pitch;
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uint8_t horizontal_sync_width; /* HS (translated) */
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uint8_t vertical_sync_width; /* VS (translated) */
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uint8_t horizontal_front_porch_width;/* HFP (translated) */
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uint8_t horizontal_back_porch_width;/* HBP (translated) */
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uint8_t vertical_front_porch_width; /* VFP (translated) */
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uint8_t vertical_back_porch_width; /* VBP (translated) */
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uint8_t display_mode; /* CG bits */
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/* CG = 00 = mixed graphics & character
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* CG = 01 = graphics mode
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* CG = 10 = character mode
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* CG = 11 = invalid */
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uint8_t video_framing; /* IS bits */
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/* IS = 00 = non-interlaced
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* IS = 01 = invalid
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* IS = 10 = interlaced repeat field for character displays
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* IS = 11 = interlaced */
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uint8_t current_command;
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uint8_t proc_step;
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uint8_t cursor_blink_state;
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uint8_t cursor_blink_count; /* count from 0 to BR - 1 */
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uint8_t cursor_blink_rate; /* BR */
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bool draw_only_during_retrace; /* F bits */
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bool dynamic_ram_refresh; /* D bits */
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bool master_sync; /* master source generation */
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bool display_enable;
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bool cursor_enable;
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bool cursor_blink;
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bool IM_bit; /* display partition, IM bit */
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bool idle;
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bool doublescan; /* 200-line as 400-line */
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bool dbg_ev_partition;
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double drawing_end;
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int dot_count;
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uint8_t drawing_status;
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};
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typedef union pc98_tile egc_quad[4];
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extern bool gdc_analog;
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extern uint32_t pc98_text_palette[8];
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extern struct PC98_GDC_state pc98_gdc[2];
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extern egc_quad pc98_gdc_tiles;
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extern uint8_t pc98_gdc_vramop;
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extern uint8_t pc98_gdc_modereg;
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extern uint8_t pc98_gdc_tile_counter;
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extern uint8_t pc98_gdc_modereg;
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extern uint8_t pc98_gdc_vramop;
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extern egc_quad pc98_gdc_tiles;
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extern uint8_t pc98_egc_srcmask[2]; /* host given (Neko: egc.srcmask) */
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extern uint8_t pc98_egc_maskef[2]; /* effective (Neko: egc.mask2) */
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extern uint8_t pc98_egc_mask[2]; /* host given (Neko: egc.mask) */
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extern bool pc98_timestamp5c;
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extern uint8_t GDC_display_plane_wait_for_vsync;
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Bitu pc98_read_9a8(Bitu /*port*/,Bitu /*iolen*/);
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void pc98_write_9a8(Bitu port,Bitu val,Bitu iolen);
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void gdc_5mhz_mode_update_vars(void);
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void pc98_port6A_command_write(unsigned char b);
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void pc98_wait_write(Bitu port,Bitu val,Bitu iolen);
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void pc98_crtc_write(Bitu port,Bitu val,Bitu iolen);
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void pc98_port68_command_write(unsigned char b);
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Bitu pc98_read_9a0(Bitu /*port*/,Bitu /*iolen*/);
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void pc98_write_9a0(Bitu port,Bitu val,Bitu iolen);
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Bitu pc98_crtc_read(Bitu port,Bitu iolen);
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Bitu pc98_a1_read(Bitu port,Bitu iolen);
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void pc98_a1_write(Bitu port,Bitu val,Bitu iolen);
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void pc98_gdc_write(Bitu port,Bitu val,Bitu iolen);
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Bitu pc98_gdc_read(Bitu port,Bitu iolen);
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Bitu pc98_egc4a0_read(Bitu port,Bitu iolen);
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void pc98_egc4a0_write(Bitu port,Bitu val,Bitu iolen);
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Bitu pc98_egc4a0_read_warning(Bitu port,Bitu iolen);
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void pc98_egc4a0_write_warning(Bitu port,Bitu val,Bitu iolen);
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extern const UINT8 gdc_defsyncm15[8];
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extern const UINT8 gdc_defsyncs15[8];
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extern const UINT8 gdc_defsyncm24[8];
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extern const UINT8 gdc_defsyncs24[8];
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extern const UINT8 gdc_defsyncm31[8];
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extern const UINT8 gdc_defsyncs31[8];
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extern const UINT8 gdc_defsyncm31_480[8];
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extern const UINT8 gdc_defsyncs31_480[8];
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void PC98_Set24KHz(void);
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void PC98_Set31KHz(void);
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void PC98_Set31KHz_480line(void);
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