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tcl: add microchip's pic64gx curiosity config

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Microchip's PIC64GX Curiosity Board has a RISC-V core complex with 4
application processors and one monitor processor. The Curiosity kit also
has an on-board debug interface based around an FTDI 4232H device.

This patch adds basic target, interface and board support for PIC64GX
Curiosity Kit.

Change-Id: I2234d8725744fbae00b3909773b370e5c18debd8
Signed-off-by: Liam Fletcher <liam.fletcher@microchip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8878
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
This commit is contained in:
Liam Fletcher
2025-05-26 10:42:56 +01:00
committed by Antonio Borneo
parent 6e87864dfc
commit 1f56ea647d
2 changed files with 79 additions and 0 deletions
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10
tcl/board/microchip/pic64gx-curiosity-kit.cfg Normal file
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# SPDX-License-Identifier: GPL-2.0-or-later
#
# Microchip RISC-V board
#
# https://www.microchip.com/en-us/products/microprocessors/64-bit-mpus/pic64gx
#
adapter speed 6000
source [find interface/microchip/embedded_flashpro5.cfg]
source [find target/microchip/pic64gx.cfg]

69
tcl/target/microchip/pic64gx.cfg Normal file
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# SPDX-License-Identifier: GPL-2.0-or-later
#
# Target: Pic64gx processor by Microchip Technologies
#
# https://www.microchip.com/en-us/products/microprocessors/64-bit-mpus/pic64gx
#
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME pic64gx
}
# Process COREID variable
if {![exists COREID]} {
set COREID -1
}
transport select jtag
# PIC64GX hart id to name lookup table
array set hart_names {
0 e51
1 u54_1
2 u54_2
3 u54_3
4 u54_4
}
# PIC64GX table
set pic64gx_tap_info {
PIC64GX1000 0x0f8531cf
}
proc expected_ids {tap_list} {
set str ""
dict for {key value} $tap_list {
append str "-expected-id" " " $value " "
}
return $str
}
set irlen 8
set expected_ids [expected_ids $pic64gx_tap_info]
eval jtag newtap $_CHIPNAME cpu -irlen $irlen $expected_ids -ignore-version
if {$COREID == -1} {
# Single debug connection to all harts
set _TARGETNAME_0 $_CHIPNAME.$hart_names(0)
set _TARGETNAME_1 $_CHIPNAME.$hart_names(1)
set _TARGETNAME_2 $_CHIPNAME.$hart_names(2)
set _TARGETNAME_3 $_CHIPNAME.$hart_names(3)
set _TARGETNAME_4 $_CHIPNAME.$hart_names(4)
target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -coreid 0 -rtos hwthread
target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1 -rtos hwthread
target create $_TARGETNAME_2 riscv -chain-position $_CHIPNAME.cpu -coreid 2 -rtos hwthread
target create $_TARGETNAME_3 riscv -chain-position $_CHIPNAME.cpu -coreid 3 -rtos hwthread
target create $_TARGETNAME_4 riscv -chain-position $_CHIPNAME.cpu -coreid 4 -rtos hwthread
target smp $_TARGETNAME_0 $_TARGETNAME_1 $_TARGETNAME_2 $_TARGETNAME_3 $_TARGETNAME_4
} else {
# Debug connection to a specific hart
set _TARGETNAME_0 $_CHIPNAME.$hart_names($COREID)
target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -coreid $COREID
}
# Only TRSTn supported
reset_config trst_only