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contrib/firmware/angie: add new spartan6 VHDL code
This new code implement two FIFOs for handling TX and RX JTAG data transfers, its simply receives data and send it OUT to target chip in respect of JTAG protocol timing constraints. The IN FIFO receives data from target chip and send it back to openocd. Change-Id: I17c1231e7f4b0a6b510359fe147b609922e0809e Signed-off-by: Ahmed BOUDJELIDA <aboudjelida@nanoxplore.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8715 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Ahmed BOUDJELIDA
committed by
Antonio Borneo
Antonio Borneo
parent
2f1a0ab35f
commit
ceaa47a2aa
@@ -1,8 +1,8 @@
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## SPDX-License-Identifier: BSD-3-Clause
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##--------------------------------------------------------------------------
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## Project Context: nanoXplore USB-JTAG Adapter Board, Spartan6
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## Design Name: NJTAG USB-JTAG Adapter FPGA source code
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## Module Name: _angie_openocd.ucf
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## Project Context: nanoXplore USB to JTAG/I2C Adapter Board, Spartan6
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## Design Name: ANGIE USB to JTAG/I2C Adapter FPGA source code
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## Module Name: angie_bitstream.ucf
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## Target Device: XC6SLX9-2 TQ144
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## Tool versions: ISE Webpack 13.2 -> 14.2
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## Author: Ahmed BOUDJELIDA nanoXplore SAS
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@@ -10,41 +10,65 @@
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# WARNING: PullUps on JTAG inputs should be enabled after configuration
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# (bitgen option) since the pins are not connected.
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net TRST LOC = 'P48' ;
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net TMS LOC = 'P43' ;
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net TCK LOC = 'P44' ;
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net TDI LOC = 'P45' ;
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net TDO LOC = 'P46' ;
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net SRST LOC = 'P61' ;
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CONFIG VCCAUX = "3.3";
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net SDA LOC = 'P50' ;
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net SCL LOC = 'P51' ;
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net SDA_DIR LOC = 'P56' ;
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net SCL_DIR LOC = 'P57' ;
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# Timing
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# net IH24 period = 40; # Constrain at 25MHz
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# net IH40 period = 25; # Constrain at 40MHz
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# DCMs placement on Spartan6
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# INST S6MOD_CKMUL.H48_DCM LOC = DCM0;
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net SI_TDO LOC = 'P16' ;
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net SO_TRST LOC = 'P32' ;
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net SO_TMS LOC = 'P27' ;
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net SO_TCK LOC = 'P30' ;
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net SO_TDI LOC = 'P26' ;
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net SO_SRST LOC = 'P12' ;
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# Clock 48MHz
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net IFCLK_I LOC = 'P123' ;
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net SO_SDA_OUT LOC = 'P140' ;
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net SO_SDA_IN LOC = 'P1' ;
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net SO_SCL LOC = 'P137';
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net GD_IO<0> LOC = 'P48' ;
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net GD_IO<1> LOC = 'P43' ;
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net GD_IO<2> LOC = 'P44' ;
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net GD_IO<3> LOC = 'P45' ;
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net GD_IO<4> LOC = 'P46' ;
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net GD_IO<5> LOC = 'P61' ;
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net GD_IO<6> LOC = 'P62' ;
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net GD_IO<7> LOC = 'P65' ;
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net ST_0 LOC = 'P29' ;
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net ST_1 LOC = 'P21' ;
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net ST_2 LOC = 'P11' ;
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net PA2_I LOC = 'P47' ;
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#net PA3_I LOC = 'P64' ;
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net JPW_I LOC = 'P14' ;
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net ST_4 LOC = 'P134' ;
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net ST_5 LOC = 'P139' ;
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net GCTL0_I LOC = 'P70' ;
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#net GCTL1_I LOC = 'P55' ;
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#net GCTL2_I LOC = 'P67' ;
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net GRDY1_I LOC = 'P118' ;
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net FTP<0> LOC = 'P121' ;
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net FTP<1> LOC = 'P120' ;
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net FTP<2> LOC = 'P119' ;
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net FTP<3> LOC = 'P116' ;
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net FTP<4> LOC = 'P111' ;
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net FTP<5> LOC = 'P112' ;
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net FTP<6> LOC = 'P115' ;
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net FTP<7> LOC = 'P114' ;
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#net SDA_IO LOC = 'P50' ;
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net SDA_IO LOC = 'P64' ; #PA3
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#net SCL_I LOC = 'P51' ;
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net SCL_I LOC = 'P39' ; #PA4 switch
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net SDA_DIR_I LOC = 'P66' ; #PA0 switch
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#net SCL_DIR_I LOC = 'P57' ;
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net SO_SDA_OUT_O LOC = 'P140' ;
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net SO_SDA_IN_I LOC = 'P1' ;
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net SO_SCL_O LOC = 'P137' ;
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net SO_TRST_O LOC = 'P32' ;
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net SO_TMS_O LOC = 'P27' ;
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net SO_TCK_O LOC = 'P30' ;
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net SO_TDI_O LOC = 'P26' ;
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net SO_SRST_O LOC = 'P12' ;
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net SI_TDO_I LOC = 'P16' ;
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net ST_0_O LOC = 'P29' ;
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net ST_1_O LOC = 'P21' ;
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net ST_2_O LOC = 'P11' ;
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net ST_3_O LOC = 'P7' ;
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net ST_4_O LOC = 'P134' ;
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net ST_5_O LOC = 'P139' ;
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net FTP_O<0> LOC = 'P121' ;
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net FTP_O<1> LOC = 'P120' ;
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net FTP_O<2> LOC = 'P119' ;
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net FTP_O<3> LOC = 'P116' ;
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net FTP_O<4> LOC = 'P111' ;
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net FTP_O<5> LOC = 'P112' ;
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net FTP_O<6> LOC = 'P115' ;
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net FTP_O<7> LOC = 'P114' ;
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@@ -1,103 +1,428 @@
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-- SPDX-License-Identifier: BSD-3-Clause
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----------------------------------------------------------------------------
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-- Project Context: nanoXplore USB-JTAG Adapter Board, Spartan6
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-- Design Name: NJTAG USB-JTAG Adapter FPGA source code
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-- Module Name: _angie_openocd.vhd
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-- Project Context: nanoXplore USB to JTAG/I2C Adapter Board, Spartan6
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-- Design Name: ANGIE USB to JTAG/I2C Adapter FPGA source code
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-- Module Name: angie_bitstream.vhd
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-- Target Device: XC6SLX9-2 TQ144
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-- Tool versions: ISE Webpack 13.2 -> 14.2
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-- Author: Ahmed BOUDJELIDA nanoXplore SAS
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----------------------------------------------------------------------------
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library work;
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use work.all;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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library UNISIM;
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use UNISIM.VComponents.all;
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entity S609 is port(
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TRST : in std_logic;
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TMS : in std_logic;
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TCK : in std_logic;
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TDI : in std_logic;
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TDO : out std_logic;
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SRST : in std_logic;
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entity angie_bitstream is port(
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SDA_IO : inout std_logic;
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SDA_DIR_I : in std_logic;
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SCL_I : in std_logic;
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SDA : inout std_logic;
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SDA_DIR : in std_logic;
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SCL : in std_logic;
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SCL_DIR : in std_logic;
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JPW_I : in std_logic; --Devkit power
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FTP : out std_logic_vector(7 downto 0); -- Test points
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SI_TDO : in std_logic;
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ST_0 : out std_logic;
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ST_1 : out std_logic;
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ST_2 : out std_logic;
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SO_SDA_OUT_O : out std_logic;
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SO_SDA_IN_I : in std_logic;
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SO_SCL_O : out std_logic;
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ST_4 : out std_logic;
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ST_5 : out std_logic;
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ST_0_O : out std_logic;
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ST_1_O : out std_logic;
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ST_2_O : out std_logic;
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ST_3_O : out std_logic;
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ST_4_O : out std_logic;
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ST_5_O : out std_logic;
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SO_SDA_OUT : out std_logic;
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SO_SDA_IN : in std_logic;
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SO_SCL : out std_logic;
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SO_TRST_O : out std_logic;
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SO_TMS_O : out std_logic;
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SO_TCK_O : out std_logic;
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SO_TDI_O : out std_logic;
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SO_SRST_O : out std_logic;
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SI_TDO_I : in std_logic;
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SO_TRST : out std_logic;
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SO_TMS : out std_logic;
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SO_TCK : out std_logic;
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SO_TDI : out std_logic;
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SO_SRST : out std_logic
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PA2_I : in std_logic; -- GPIF IN
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-- Clock 48MHz
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IFCLK_I : in std_logic;
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GCTL0_I : in std_logic;
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GRDY1_I : out std_logic;
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GD_IO : inout std_logic_vector(7 downto 0);
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FTP_O : out std_logic_vector(15 downto 0)
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);
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end S609;
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end angie_bitstream;
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architecture A_angie_bitstream of angie_bitstream is
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----------------------------------------Fifo out (PC to devkit)
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signal rst_o, clk_wr_o, clk_rd_o : std_logic;
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signal write_en_o, read_en_o : std_logic;
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signal data_in_o, data_out_o : std_logic_vector(7 downto 0);
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signal empty_o, full_o : std_logic;
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----------------------------------------Fifo in (devkit to PC)
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signal rst_i, clk_wr_i, clk_rd_i : std_logic;
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signal write_en_i, read_en_i : std_logic;
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signal data_in_i, data_out_i : std_logic_vector(7 downto 0);
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signal empty_i, full_i : std_logic;
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signal wr_o, rd_i : std_logic;
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----------------------------------------MAE
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signal transit1, transit2 : std_logic;
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----------------------------------------DFF
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signal pa2_dff_clk, pa2_dff_rst, pa2_dff_d, pa2_dff_q : std_logic;
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signal trst_clk, trst_rst, trst_d, trst_q : std_logic;
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signal tms_clk, tms_rst, tms_d, tms_q : std_logic;
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signal tdi_clk, tdi_rst, tdi_d, tdi_q : std_logic;
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signal tdo_clk, tdo_rst, tdo_d, tdo_q : std_logic;
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signal srst_clk, srst_rst, srst_d, srst_q : std_logic;
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----------------------------------------clk_div
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signal clk_div_in, clk_div_out, reset_clk_div : std_logic;
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signal clk_div2_in, clk_div2_out, reset_clk_div2 : std_logic;
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----------------------------------------MAE
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type State_Type is (IDLE, WRITE_OUT, WRITE_IN, DELAY, READ_IN);
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signal state, state2 : State_Type;
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signal reset_mae, reset_mae2 : std_logic;
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-- Add Component DFF
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component DFF
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Port (
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clk : in std_logic;
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reset : in std_logic;
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d : in std_logic;
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q : out std_logic
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);
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end component;
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-- Add Component Clk_div
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component clk_div
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Port (
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clk_in : in std_logic;
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reset : in std_logic;
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clk_out : out std_logic
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);
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end component;
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-- Add component FIFO 64B
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component fifo_generator_v9_3
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PORT (
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rst : IN STD_LOGIC;
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wr_clk : IN STD_LOGIC;
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rd_clk : IN STD_LOGIC;
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din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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wr_en : IN STD_LOGIC;
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rd_en : IN STD_LOGIC;
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dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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full : OUT STD_LOGIC;
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empty : OUT STD_LOGIC
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);
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end component;
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signal state1_debug, state2_debug : std_logic;
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architecture A_S609 of S609 is
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begin
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-------------------------------------------------------------I2C :
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SDA_IO <= not(SO_SDA_IN_I) when (SDA_DIR_I = '1') else 'Z';
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SO_SDA_OUT_O <= SDA_IO;
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ST_5_O <= SDA_DIR_I;
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--Directions:
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ST_0 <= '0';
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ST_1 <= '1';
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SO_SCL_O <= SCL_I when (JPW_I = '1') else '0';
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ST_4_O <= '0';
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--TDO:
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TDO <= not SI_TDO;
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------------------------------------------------------------JTAG :
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-- Instantiate the Clk div by 10
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clk_div_inst : clk_div
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port map (
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clk_in => clk_div_in,
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reset => reset_clk_div,
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clk_out => clk_div_out
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);
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-- Instantiate the Clk div by 10
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clk_div2_inst : clk_div
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port map (
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clk_in => clk_div2_in,
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reset => reset_clk_div2,
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clk_out => clk_div2_out
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);
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--TRST - TCK - TMS - TDI:
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SO_TRST <= TRST;
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SO_TMS <= TMS;
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SO_TCK <= TCK;
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SO_TDI <= TDI;
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ST_2 <= SRST;
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SO_SRST <= '0';
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-- Instantiate DFFs
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DFF_inst_PA2 : DFF
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port map (
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clk => pa2_dff_clk,
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reset => pa2_dff_rst,
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d => pa2_dff_d,
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q => pa2_dff_q
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);
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SO_SCL <= SCL;
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DFF_inst_TRST : DFF
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port map (
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clk => trst_clk,
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reset => trst_rst,
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d => trst_d,
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q => trst_q
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);
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SDA <= not(SO_SDA_IN) when (SDA_DIR = '1') else 'Z';
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SO_SDA_OUT <= SDA;
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DFF_inst_TMS : DFF
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port map (
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clk => tms_clk,
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reset => tms_rst,
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d => tms_d,
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q => tms_q
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);
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process(SDA_DIR)
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begin
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if(SDA_DIR = '0') then
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ST_5 <= '0';
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else
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ST_5 <= '1';
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end if;
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end process;
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DFF_inst_TDI : DFF
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port map (
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clk => tdi_clk,
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reset => tdi_rst,
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d => tdi_d,
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q => tdi_q
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);
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process(SCL_DIR)
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begin
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if(SCL_DIR = '0') then
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ST_4 <= '0';
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else
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ST_4 <= '1';
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end if;
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end process;
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DFF_inst_TDO : DFF
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port map (
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clk => tdo_clk,
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reset => tdo_rst,
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d => tdo_d,
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q => tdo_q
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);
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DFF_inst_SRST : DFF
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port map (
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clk => srst_clk,
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reset => srst_rst,
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d => srst_d,
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q => srst_q
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);
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-- Instantiate the FIFO OUT
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U0 : fifo_generator_v9_3
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port map (
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rst => rst_o,
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wr_clk => clk_wr_o,
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rd_clk => clk_rd_o,
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din => data_in_o,
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wr_en => write_en_o,
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rd_en => read_en_o,
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dout => data_out_o,
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full => full_o,
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empty => empty_o
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);
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-- Instantiate the FIFO IN
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U1 : fifo_generator_v9_3
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port map (
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rst => rst_i,
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wr_clk => clk_wr_i,
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rd_clk => clk_rd_i,
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din => data_in_i,
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wr_en => write_en_i,
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rd_en => read_en_i,
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dout => data_out_i,
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full => full_i,
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empty => empty_i
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);
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--------------- clock dividers
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clk_div_in <= IFCLK_I; -- 48Mhz
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clk_div2_in <= clk_div_out; -- 24Mhz
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--------------- DFFs
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pa2_dff_clk <= IFCLK_I;
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trst_clk <= IFCLK_I;
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tms_clk <= IFCLK_I;
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tdi_clk <= IFCLK_I;
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tdo_clk <= IFCLK_I;
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srst_clk <= IFCLK_I;
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--------------- FIFOs
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clk_wr_o <= IFCLK_I;
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clk_rd_o <= clk_div2_out;
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clk_wr_i <= clk_div2_out;
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clk_rd_i <= IFCLK_I;
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--------------------------- GPIF ready :
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GRDY1_I <= '1';
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-------------------------------PA2 DFF :
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pa2_dff_rst <= '0';
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pa2_dff_d <= PA2_I;
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-------------------- FX2<->Fifo Enable pins :
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write_en_o <= not(wr_o) and not(GCTL0_I);
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read_en_i <= not(rd_i) and not(GCTL0_I);
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---------------- FX2->Fifo Data :
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data_in_o <= GD_IO;
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------------ FIFO_OUT->Devkit :
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SO_TRST_O <= trst_q;
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trst_d <= data_out_o(4);
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SO_TMS_O <= tms_q;
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||||
tms_d <= data_out_o(3);
|
||||
SO_TDI_O <= tdi_q;
|
||||
tdi_d <= data_out_o(1);
|
||||
------------
|
||||
SO_TCK_O <= data_out_o(0);
|
||||
|
||||
-------------------- FIFO_OUT->FIFO_IN :
|
||||
--data_in_i <= data_out_o;
|
||||
|
||||
-------------------- FIFO_IN<-Devkit :
|
||||
data_in_i(0) <= '0';
|
||||
data_in_i(1) <= '0';
|
||||
data_in_i(2) <= tdo_q;
|
||||
tdo_d <= not SI_TDO_I;
|
||||
data_in_i(3) <= '0';
|
||||
data_in_i(4) <= '0';
|
||||
data_in_i(5) <= '0';
|
||||
data_in_i(6) <= '0';
|
||||
data_in_i(7) <= '0';
|
||||
|
||||
-------------------- FX2<-FIFO_IN :
|
||||
GD_IO <= data_out_i when (state = READ_IN) else "ZZZZZZZZ";
|
||||
|
||||
state1_debug <= '1' when state = READ_IN else '0';
|
||||
state2_debug <= '1' when state2 = WRITE_IN else '0';
|
||||
|
||||
--Points de test:
|
||||
FTP(0) <= SDA;
|
||||
FTP(1) <= SCL;
|
||||
FTP(2) <= not(SO_SDA_IN);
|
||||
FTP(3) <= SDA_DIR;
|
||||
FTP(5) <= SRST;
|
||||
FTP(4) <= SI_TDO;
|
||||
FTP(6) <= '1';
|
||||
FTP(7) <= '1';
|
||||
FTP_O(0) <= IFCLK_I;
|
||||
FTP_O(1) <= GCTL0_I;
|
||||
FTP_O(2) <= GD_IO(0);
|
||||
FTP_O(3) <= GD_IO(1);
|
||||
FTP_O(4) <= JPW_I;
|
||||
FTP_O(5) <= PA2_I;
|
||||
FTP_O(6) <= empty_o;
|
||||
FTP_O(7) <= not SI_TDO_I;
|
||||
|
||||
end A_S609;
|
||||
process(pa2_dff_d, pa2_dff_q)
|
||||
begin
|
||||
if pa2_dff_d = '0' and pa2_dff_q = '1' then
|
||||
reset_mae <= '1'; -- Reset State Machine
|
||||
reset_mae2 <= '1'; -- Reset State Machine
|
||||
rst_o <= '1'; -- Reset OUT
|
||||
rst_i <= '1'; -- Reset IN
|
||||
reset_clk_div <= '1';
|
||||
reset_clk_div2 <= '1';
|
||||
trst_rst <= '1';
|
||||
tms_rst <= '1';
|
||||
tdi_rst <= '1';
|
||||
tdo_rst <= '1';
|
||||
srst_rst <= '1';
|
||||
else
|
||||
reset_mae <= '0'; -- No Reset State Machine
|
||||
reset_mae2 <= '0'; -- Reset State Machine
|
||||
rst_o <= '0'; -- No Reset OUT
|
||||
rst_i <= '0'; -- No Reset IN
|
||||
reset_clk_div <= '0';
|
||||
reset_clk_div2 <= '0';
|
||||
trst_rst <= '0';
|
||||
tms_rst <= '0';
|
||||
tdi_rst <= '0';
|
||||
tdo_rst <= '0';
|
||||
srst_rst <= '0';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk_div2_out, reset_mae2)
|
||||
begin
|
||||
if reset_mae2 = '1' then
|
||||
state2 <= IDLE;
|
||||
elsif rising_edge(clk_div2_out) then
|
||||
case state2 is
|
||||
when IDLE =>
|
||||
read_en_o <= '0'; -- Disable read OUT
|
||||
write_en_i <= '0'; -- Disable write IN
|
||||
transit2 <= '1';
|
||||
if transit1 = '0' and PA2_I = '0' then
|
||||
state2 <= WRITE_IN;
|
||||
else
|
||||
state2 <= IDLE;
|
||||
end if;
|
||||
|
||||
when WRITE_IN =>
|
||||
read_en_o <= '1'; -- Enable read OUT
|
||||
write_en_i <= '1'; -- Enable write IN
|
||||
if PA2_I = '1' then
|
||||
state2 <= DELAY; -- Change state to DELAY
|
||||
else
|
||||
state2 <= WRITE_IN; -- Stay in WRITE_IN state
|
||||
end if;
|
||||
|
||||
when DELAY =>
|
||||
transit2 <= '0'; -- Enable READ IN
|
||||
if empty_o = '1' then
|
||||
read_en_o <= '0'; -- Disable read OUT
|
||||
write_en_i <= '0'; -- Disable write IN
|
||||
state2 <= IDLE; -- Change state to IDLE
|
||||
else
|
||||
state2 <= DELAY; -- Stay in READ_IN state
|
||||
end if;
|
||||
|
||||
when others =>
|
||||
state2 <= IDLE;
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(IFCLK_I, reset_mae)
|
||||
begin
|
||||
if reset_mae = '1' then
|
||||
state <= IDLE;
|
||||
elsif rising_edge(IFCLK_I) then
|
||||
case state is
|
||||
when IDLE =>
|
||||
wr_o <= '1'; -- Disable write OUT
|
||||
rd_i <= '1'; -- Disable read IN
|
||||
transit1 <= '1';
|
||||
if PA2_I = '0' then
|
||||
state <= WRITE_OUT; -- Change state to RESET
|
||||
else
|
||||
state <= IDLE; -- Stay in IDLE state
|
||||
end if;
|
||||
|
||||
when WRITE_OUT =>
|
||||
wr_o <= '0'; -- Enable write OUT
|
||||
if empty_o = '0' then
|
||||
transit1 <= '0'; -- Enable Rd OUT & Wr IN
|
||||
state <= DELAY; -- Change state to DELAY
|
||||
else
|
||||
state <= WRITE_OUT; -- Stay in WRITE_OUT state
|
||||
end if;
|
||||
|
||||
when DELAY =>
|
||||
if transit2 = '0' then
|
||||
wr_o <= '1'; -- Disable write OUT
|
||||
state <= READ_IN;
|
||||
else
|
||||
state <= DELAY;
|
||||
end if;
|
||||
|
||||
when READ_IN =>
|
||||
rd_i <= '0'; -- Enable read IN
|
||||
if empty_i = '1' then
|
||||
rd_i <= '1'; -- Enable read IN
|
||||
state <= IDLE; -- Change state to IDLE
|
||||
else
|
||||
state <= READ_IN; -- Stay in READ_IN state
|
||||
end if;
|
||||
|
||||
when others =>
|
||||
state <= IDLE;
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- OUT signals direction
|
||||
-- TRST, TMS, TCK and TDI : out
|
||||
ST_0_O <= '0';
|
||||
-- TDO : in
|
||||
ST_1_O <= '1';
|
||||
-- SRST : out
|
||||
ST_2_O <= srst_q;
|
||||
srst_d <= data_out_o(6);
|
||||
SO_SRST_O <= '0';
|
||||
-- MOD : in
|
||||
ST_3_O <= '1';
|
||||
|
||||
end A_angie_bitstream;
|
||||
|
||||
33
contrib/firmware/angie/hdl/src/clk_div.vhd
Normal file
33
contrib/firmware/angie/hdl/src/clk_div.vhd
Normal file
@@ -0,0 +1,33 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.ALL;
|
||||
use ieee.numeric_std.ALL;
|
||||
|
||||
entity clk_div is
|
||||
Port (
|
||||
clk_in : in std_logic;
|
||||
reset : in std_logic;
|
||||
clk_out : out std_logic
|
||||
);
|
||||
end clk_div;
|
||||
|
||||
architecture behavioral of clk_div is
|
||||
-- Division factor N = 4, so we need a 2-bit counter (2^2 = 4)
|
||||
-- signal counter : unsigned(1 downto 0) := (others => '0');
|
||||
signal tmp : std_logic;
|
||||
begin
|
||||
process(clk_in, reset)
|
||||
begin
|
||||
if reset = '1' then
|
||||
-- counter <= (others => '0');
|
||||
tmp <= '0';
|
||||
elsif rising_edge(clk_in) then
|
||||
-- if counter = (2**2 - 1) then
|
||||
-- counter <= (others => '0');
|
||||
tmp <= NOT tmp; -- Toggle the output clock
|
||||
-- else
|
||||
-- counter <= counter + 1;
|
||||
-- end if;
|
||||
end if;
|
||||
end process;
|
||||
clk_out <= tmp;
|
||||
end behavioral;
|
||||
23
contrib/firmware/angie/hdl/src/dff.vhd
Normal file
23
contrib/firmware/angie/hdl/src/dff.vhd
Normal file
@@ -0,0 +1,23 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.ALL;
|
||||
use ieee.std_logic_arith.ALL;
|
||||
use ieee.std_logic_unsigned.ALL;
|
||||
|
||||
entity DFF is
|
||||
port ( clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
d : in std_logic;
|
||||
q : out std_logic);
|
||||
end DFF;
|
||||
|
||||
architecture Behavioral of DFF is
|
||||
begin
|
||||
process(clk, reset)
|
||||
begin
|
||||
if reset = '1' then
|
||||
q <= '1'; -- Reset output to 0
|
||||
elsif rising_edge(clk) then
|
||||
q <= d; -- Capture D at the rising edge of the clock
|
||||
end if;
|
||||
end process;
|
||||
end Behavioral;
|
||||
Binary file not shown.
Reference in New Issue
Block a user