ptitSeb/box64
1
0
Fork 0
mirror of https://github.com/ptitSeb/box64.git synced 2025-10-14 02:38:54 +08:00
Code Issues Packages Projects Releases Wiki Activity
7,121 Commits 3 Branches 19 Tags
main
Commit Graph

7121 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Yang Liu
485447850c [RV64_DYNAREC] Added more scalar avx opcodes (#2974) 2025-08-26 14:25:44 +02:00
Yang Liu
709a526217 [RV64_DYNAREC] Added more scalar avx opcodes (#2973) 
* [RV64_DYNAREC] Added more scalar avx opcodes

* fix
 2025-08-26 10:19:51 +02:00
ptitSeb
1cddcad20a [WRAPPER] Improved pulse wrapping 2025-08-25 19:26:09 +02:00
ptitSeb
aa30e665ff [TRACE] Small change on commented code (left for debugging purpose) 2025-08-25 17:00:54 +02:00
ptitSeb
9effd3f711 [INTERP] Fixed a regression introduced with a17811f4a6 2025-08-25 16:44:42 +02:00
Yang Liu
d71200de69 [RV64_DYNAREC] Added more scalar avx opcodes (#2971) 2025-08-25 13:36:16 +02:00
Yang Liu
8579ef84bd [RV64_DYNAREC] Added more scalar avx opcodes (#2970) 2025-08-25 10:32:59 +02:00
ptitSeb
747882cb4e [BOX32][WRAPPER] Added one more wrapped function to libc 2025-08-24 12:00:58 +02:00
ptitSeb
e76570ad7b [BOX32] Sligtly safer handling of 32bits signals 2025-08-24 12:00:24 +02:00
ptitSeb
e964b45894 [BOX32][WRAPPER] Fixed some SIGBUS with 32bits smeaphores 2025-08-24 11:32:04 +02:00
ptitSeb
b8526c7920 [BOX32][WRAPPER] Added ftw wrapped function to libc 2025-08-24 11:32:04 +02:00
Yang Liu
2a525b4eb2 [RV64_DYNAREC] Added YMM0 placeholder for later optim (#2968) 2025-08-24 10:29:59 +02:00
ptitSeb
cb2c29c5f9 [INTERP] Refactored how 64/65/66/67 and F2/F3 prefixes are handled, removing some (mostly) duplicated code 2025-08-22 18:10:13 +02:00
Yang Liu
3b0977eee1 [RV64_DYNAREC] Fixed scalar avx VCMPPD non-ymm case (#2966) 2025-08-22 17:04:05 +02:00
Yang Liu
893ffe8205 [RV64_DYNAREC] Added more scalar avx opcodes (#2965) 2025-08-22 13:13:04 +02:00
Yang Liu
82a91e717a [ARM64_DYNAREC] Fixed an inst name typo (#2964) 2025-08-22 13:12:17 +02:00
Yang Liu
031d3def2d [RV64_DYNAREC] Added scalar SSE 66 0F 3A 60/61/62 opcodes (#2963) 
* [RV64_DYNAREC] Added scalar SSE 66 0F 3A 60/61/62 opcodes

* [CI] Bump timeout
 2025-08-22 13:11:51 +02:00
Yang Liu
7c32cb24a0 [RV64_DYNAREC] Added more scalar avx 66 0F opcodes (#2960) 2025-08-22 08:45:14 +02:00
Yang Liu
cea8f94358 [RV64_DYNAREC] Added more scalar avx opcodes (#2961) 2025-08-21 23:44:40 +02:00
Yang Liu
d476217f4c [RV64_DYNAREC] Fixed more scalar avx opcodes (#2959) 
* [RV64_DYNAREC] Fixed more scalar avx opcodes

* oops
 2025-08-21 19:15:59 +02:00
Yang Liu
34e789484a [CORE] Better trace_file logging (#2958) 2025-08-21 16:55:10 +02:00
Yang Liu
6a6af076dd [COSIM] Better memory diff printing (#2957) 2025-08-21 15:43:46 +02:00
Yang Liu
5327489f39 [RV64_DYNAREC] Fixed some scalar avx opcodes (#2956) 2025-08-21 15:25:42 +02:00
Yang Liu
392255594b [RV64_DYNAREC] Added more scalar avx 66 0F3A opcodes (#2955) 2025-08-21 13:19:56 +02:00
Yang Liu
8d94d21716 [RV64_DYNAREC] Added more scalar avx 66 0F38 opcodes (#2954) 
* [RV64_DYNAREC] Added more scalar avx 66 0F38 opcodes

* fix
 2025-08-21 13:18:38 +02:00
Yang Liu
44448774a7 [RV64_DYNAREC] Added more scaalr avx opcodes (#2952) 2025-08-19 14:17:10 +02:00
Yang Liu
a280884f09 [RV64_DYNAREC] Added more scalar avx opcodes (#2951) 2025-08-19 13:17:02 +02:00
Yang Liu
7435006b7c [RV64_DYNAREC] Added more avx scalar 66 0F38 opcodes (#2950) 
* [RV64_DYNAREC] Added more avx scalar 66 0F38 opcodes

* more
 2025-08-19 12:26:42 +02:00
Yang Liu
1c2e763ffb [RV64_DYNAREC] Added a few more scalar AVX 66 0F38 opcodes (#2949) 2025-08-18 14:12:24 +02:00
Yang Liu
5f144d8ddd [RV64_DYNAREC] Added scalar AVX VMOVDQA opcodes (#2948) 2025-08-18 12:42:28 +02:00
Yang Liu
0a53d2223a [DYNAREC] Bump ARCH_VERSION (#2947) 2025-08-18 12:41:47 +02:00
Yang Liu
fe2930cbe3 [LA64_DYNAREC] Enable AVX/AVX2 by default (#2946) 2025-08-18 12:41:10 +02:00
Yang Liu
bf6c1533b3 [RV64_DYNAREC] Added more scalar AVX opcodes (#2945) 2025-08-18 12:40:11 +02:00
Yang Liu
167217c76b [LA64_DYNAREC] Added more scalar AVX opcodes (#2943) 2025-08-15 21:09:44 +02:00
Yang Liu
f615a10fe1 [RV64_DYNAREC] Added more scalar AVX VMOV opcodes (#2942) 
* [RV64_DYNAREC] Added more scalar AVX VMOV opcodes

* more
 2025-08-15 20:13:04 +02:00
Yang Liu
2d60c8c5b9 [RV64_DYNAREC] Added scalar AVX VMOVSS opcodes (#2941) 2025-08-15 14:18:38 +02:00
phorcys
270ce3750e [LA64_DYNAREC] Add la64 BMI/BMI2 ops. (#2933) 
VEX.0F.38  BLSR, BLSMSK, BLSI, BZHI, BEXTR
VEX.F2.0F.38 PDEP, MULX
VEX.F3.0F.38 PEXT
 2025-08-15 14:16:58 +02:00
Yang Liu
83e2427bfe [RV64_DYNAREC] Fixed OF2 handling (#2937) 2025-08-15 00:17:31 +02:00
Yang Liu
3815c28bfe [DYNAREC] Fixed reading emu->df (#2936) 2025-08-15 00:16:34 +02:00
phorcys
5144a2e286 [LA64_DYNAREC] Fix VMOVNTDQA. (#2934) 2025-08-15 00:13:16 +02:00
phorcys
febaf31b93 [LA64_DYNAREC] Add la64 avx insts using helpers. (#2935) 
VEX.66.0F.38 VAESIMC, VAESENC, VAESENCLAST, VAESDEC, VAESDECLAST
VEX.66.0F.3a  VPCLMULQDQ, VAESKEYGENASSIST
 2025-08-15 00:09:27 +02:00
Yang Liu
af057e309a [RV64_DYNAREC] Removed a dispensable line from dump (#2932) 2025-08-13 20:37:39 +02:00
Yang Liu
db864b6aa6 [LA64_DYNAREC] Fixed a typo in CMPXCHG8B opcode (#2931) 2025-08-13 13:24:01 +02:00
Yang Liu
3793e595f0 [DYNAREC] Rearranged arch-specific AVX infra code (#2930) 2025-08-13 13:21:51 +02:00
phorcys
abe29cc0ba [LA64_DYNAREC] Fix B3 BTR eflags when cpuext.lbt == 1. Fix 16bits AND when cpuext.lbt == 1. (#2929) 2025-08-12 14:38:15 +02:00
Yang Liu
c4e50cdbb1 [RV64_DYNAREC] Added F0 08 LOCK OR opcode (#2928) 2025-08-12 00:05:22 +02:00
Yang Liu
dce81673af [RV64_DYNAREC] Fixed F0 10 LOCK ADC opcode (#2927) 2025-08-11 15:32:13 +02:00
Yang Liu
df2e4f941f [RV64_DYNAREC][LA64_DYNAREC] Fixed missing zeroup in geted_32() (#2921) 2025-08-08 14:40:42 +02:00
Yang Liu
efd01c1126 [LA64_DYNAREC] Fixed AVX VPMOVMSKB opcode (#2920) 2025-08-07 23:25:30 +02:00
Yang Liu
197e5e440d [LA64_DYNAREC] Fixed AVX VPERM2F128/VPERM2I128 opcodes (#2919) 2025-08-07 23:24:47 +02:00