6456 Commits

Author SHA1 Message Date
ptitSeb
b7ae6ebc27 [INTERP] More work on UD flags 2025-04-27 15:51:17 +02:00
ptitSeb
9b904c622a [INTERP] Fixed some potential issue with LOCK ADC/SBB on Dynarec build 2025-04-27 15:41:22 +02:00
ptitSeb
950371427d [INTERP] Added 66 F3 0F BC opcode 2025-04-27 14:15:29 +02:00
ptitSeb
be63129179 [WRAPPER] Reworked libssh2 wrapping, to make it more complete 2025-04-27 14:07:31 +02:00
ptitSeb
02423c2d7d [WRAPPERHELPER] Fixed a small issue with the parser 2025-04-27 14:07:01 +02:00
ptitSeb
4add55aa45 [ELFLOADER] Fixed an issue were fail to load a library might endup unloading used libraries 2025-04-27 12:38:32 +02:00
ptitSeb
7334bb46c6 [ELFLOADER] Added lib loading/unloading logs to DLSYM_ERROR 2025-04-27 11:53:33 +02:00
ptitSeb
9c962f8b2c [RCFILE] Fixed BOX64_ROLLING_LOG not being a boolean but an integer value 2025-04-27 11:06:40 +02:00
ptitSeb
1f73944603 [ARM64_DYNAREC] Refactored (V)PSHUFD opcodes 2025-04-26 15:57:38 +02:00
ptitSeb
e844c5baa3 [INTERP] Cosmetic change to VPSHUFD opocde 2025-04-26 15:43:56 +02:00
ptitSeb
c849178bf8 [WRAPPER] Fixed some potential sagfault on my_backtrace wrapped function 2025-04-26 15:43:01 +02:00
ptitSeb
ff4ae1f4d8 [ARM64_DYNAREC] Allow shift with saturation on (V)PMULH(U)W because it will never saturate 2025-04-26 10:46:11 +02:00
ptitSeb
f7acb78743 [ARM64_DYNAREC] Small fix for edge cases on (V)PMULHUW opcodes 2025-04-26 10:39:44 +02:00
ptitSeb
6796b9ca02 [WRAPPER] Added some missing function to wrapped libgio-2 (for #2575) 2025-04-26 10:12:28 +02:00
ptitSeb
e4da025dc0 [ARM64_DYNAREC] Fixed (rarely used) some edge case for (V)PMULHRSW opcode (and improved tests) 2025-04-25 20:03:58 +02:00
ptitSeb
b6b069cf8d [ARM64_DYNAREC] Small optim on some 256bits VPMOV[S/Z]X* opcodes 2025-04-25 17:28:28 +02:00
ptitSeb
f9475aa540 [ARM64_DYNAREC] Allow bigger block to be built 2025-04-25 16:43:23 +02:00
ptitSeb
c6f0872e50 [ARM64_DYNAREC] Minor change, (V)PMOVMSKB is only valid on register, not memory 2025-04-25 16:10:16 +02:00
ptitSeb
71dc02e06f [INTERP] Another fix for a opcode name in comment 2025-04-25 16:05:50 +02:00
ptitSeb
e9715e4f0f [INTERP] Fixed a small issue where VPCMP[E/I]STRM would not wipe upper 128bits of ymm0 2025-04-25 11:14:02 +02:00
ptitSeb
8f197a7c08 [ARM64_DYNAREC] Fixed a potential issue with PCMPEQQ opcodes, and many missing space in instruction name 2025-04-25 10:56:38 +02:00
ptitSeb
3542c88dc1 [ARM64_DYNAREC] Improved and fixed software fallback for (V)PCLMULQDQ opcodes 2025-04-24 19:50:32 +02:00
ptitSeb
4585b74310 [ARM64_DYNAREC] Some optimisation to some (V)(P)BLEND* opcodes 2025-04-24 19:04:42 +02:00
ptitSeb
768dfd37bb [INTERP] Yet another opcode name comment fix 2025-04-24 19:03:03 +02:00
Yang Liu
d8212fab48
[SIGNAL] Better signal logging when trace enabled (#2572)
* [SIGNAL] Better signal logging when trace enabled

* fix
2025-04-24 16:40:39 +02:00
Yang Liu
740f4a19dc
[RV64_DYNAREC] Fixed x87 cache swapping (#2571) 2025-04-24 16:07:43 +02:00
ptitSeb
c469ed867a [ARM64_DYNAREC] Small optim on (V)PACKUSDW opcodes 2025-04-24 15:38:30 +02:00
phorcys
37dcb1a77b
[LA64_DYNAREC] Add/Opt more mmx/sse ops (#2565)
* [LA64_DYNAREC] Add/Opt PEXTR{B,W,D,Q}/PINSR{B,W,D,Q} .
  * 0f.c4/c5 PINSRW/PEXTRW mmx ops.
  * 66.0f.3a.14/15/16 PEXTR{B,W,D/Q} SSE4 ops.
  * 66.0f.c4/c5 PINSRW/PEXTRW sse ops.

* [LA64_DYNAREC] Add more SSE3/SSE4 ops
66.0f.38.28 PMULDQ
66.0f.38.2a MOVNTDQA
66.0f.38.37 PCMPGTQ
66.0f.38.38/3b/3c/3f PMINSB/PMINUD/PMAXSB/PMAXUD
66.0f.3a.17 EXTRACTPS
66.0f.3a.41 DPPD
opt 66.0f.3a.40 DPPS
2025-04-24 13:26:57 +02:00
ptitSeb
2e90a5dbaf [INTERP] Cosmetic change to 0F 1C..1E opcodes 2025-04-24 12:07:45 +02:00
ptitSeb
d988a39456 [INTERP] Added nan handling on AVX.F3.0F 59 opcode 2025-04-24 11:54:55 +02:00
ptitSeb
fc381e744e [ARM64_DYNAREC] Simplified code for MOVS[H/L]DUP opcodes 2025-04-24 11:38:20 +02:00
ptitSeb
e52b24b615 [INTERP] Fixed another opcode name comment 2025-04-24 11:37:17 +02:00
phorcys
7158405b73
[LA64_DYNAREC] Add POPCNT/TZCNT/LZCNT ops. (#2566)
66.f3.0f.b8/bc/bd POPCNT/TZCNT/LZCNT 16bits ops
f3.0f.bd LZCNT
fix f3.0f.bc TZCNT (GETED/RESTORE_EFLAGS x1 conflict)
2025-04-24 11:28:42 +02:00
ptitSeb
e059506d5e [ARM64_DYNAREC] Small iùprovments to some (V)MOVQ opcodes 2025-04-24 11:15:06 +02:00
ptitSeb
6da3a1265d [INTERP] Fixed a comment 2025-04-24 11:14:28 +02:00
ptitSeb
d51997bc77 [ARM64_DYNAREC] Small change and optims to various (V)MOVNT* opcodes 2025-04-24 10:58:56 +02:00
ptitSeb
af555abb6f [INTERP] Small change to various (V)MOVNT* opcodes, forbidding reg -> reg form 2025-04-24 10:58:23 +02:00
Yang Liu
926e4b2da8
[DYNAREC] Added ranged Dynablock dump (#2570) 2025-04-24 10:37:24 +02:00
Yang Liu
4903177bab
[ARM64_DYNAREC] Minor optim to MOVNTDQA (#2568) 2025-04-24 09:17:52 +02:00
Yang Liu
d8a6fa0395
Added some missing newlines (#2567) 2025-04-24 09:16:49 +02:00
ptitSeb
69127efae9 [ARM64_DYNAREC] Small fixes and improvments to (V)MOVMSKP[S/D] opcodes 2025-04-23 18:43:13 +02:00
ptitSeb
6f0db360a4 [ARM64_DYNAREC] Few fixes and small cosmetic changes to some partial (V)MOV opcodes 2025-04-23 18:21:15 +02:00
ptitSeb
223de50ec9 [INTERP] Fex fixes and small cosmetic changes to some partial (V)MOV opcodes 2025-04-23 18:20:38 +02:00
ptitSeb
5cfad22165 [ARM64_DYNAREC] Made REP MOVSB optimisation flagless 2025-04-23 12:54:04 +02:00
ptitSeb
815836d285 [ARM64_DYNAREC] Optimized REP STOSB 2025-04-23 12:47:56 +02:00
ptitSeb
468a3c2165 [PERFMAP] Added x86 address of code when function name cannot be found, instead of ??? 2025-04-23 11:48:37 +02:00
ptitSeb
3afe87bcce [ARM64_DYNAREC] Various improvment to various SSE/AVX 128bits/256bits mov opcodes 2025-04-23 10:57:07 +02:00
ptitSeb
d79d6bd6c2 [INTERP] RaZ upper 128bits on vmov* Ex, Gx if Ex is a registry (unused?) 2025-04-23 10:55:17 +02:00
rajdakin
cc6500b7dd
[RBTREE] Fixed an edge case (#2562) 2025-04-22 13:52:01 +02:00
Yang Liu
ad494480ce
[DYNAREC] Added a x87pc test and some cosmetic changes too (#2561) 2025-04-22 13:31:04 +02:00