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Author SHA1 Message Date
ptitSeb
cb26a742ff [INTERP] Added missing opcode nae in comment 2025-05-01 11:43:15 +02:00
ptitSeb
4b44501d17 [ARM64_DYNAREC] Fixed edge-case for VPERM2[F/I]128 opcodes 2025-05-01 11:13:25 +02:00
ptitSeb
830cc8a498 [INTERP] Fixed edge-case for VPERM2[F/I]128 opcodes 2025-05-01 11:13:01 +02:00
ptitSeb
16b0922ec5 [ARM_DYNAREC] Small improvments to VMASKMOVP[S/D] opcodes 2025-05-01 10:45:00 +02:00
ptitSeb
9791016c74 [INTERP] VMASKMOVP[S/D] opcodes have no register only path 2025-05-01 10:42:41 +02:00
ptitSeb
ced1157132 [ARM64_DYNAREC] Cosmetic change to VGATHER[D/Q]P[D/S] opcodes 2025-04-30 18:35:22 +02:00
ptitSeb
56982e4c05 [ARM64_DYNAREC] Small rework on VFMAD*S[S/D] opcodes 2025-04-30 17:50:44 +02:00
ptitSeb
f5e93a14a2 [INTERP] Fixed another instruction name comment 2025-04-30 17:49:48 +02:00
ptitSeb
eae608f35c [ARM64_DYNAREC] Small improvment to VPBROADCAST[B/W] opcodes 2025-04-30 17:17:08 +02:00
ptitSeb
89dbd81f27 [INTERP] Improved NAN handling on VSUBPD opcode 2025-04-30 16:15:34 +02:00
ptitSeb
c835227b8b [ARM64_DYNAREC] Fixed a potential issue with (V)STMXCSR opcodes 2025-04-30 15:58:09 +02:00
ptitSeb
57f07446ea [ARM64_DYNAREC] Add fastnan=0 handling in (V)SQRTSS opcodes 2025-04-30 15:47:48 +02:00
ptitSeb
7b2e084170 [INTERP] Improved NAN handling for some (V)SQRTS[S/D] opcodes 2025-04-30 15:46:08 +02:00
ptitSeb
ab70523b39 [INTERP] Improve NAN handling on SQRTPS opcode 2025-04-30 15:22:01 +02:00
ptitSeb
f0859e6462 [ARM64_DYNAREC] Switched RSQRTPS to precise instead of aproximate 2025-04-29 18:03:15 +02:00
ptitSeb
737a93a77c [INTERP] Improved (V)RSQRTSS opcodes 2025-04-29 17:56:08 +02:00
ptitSeb
17cbeab0be [ARM64_DYNAREC] Switched RPCPS opcode to precise 1/A instead of approximate 2025-04-29 17:33:52 +02:00
ptitSeb
313e16d2bc [ARM64_DYNAREC] Small optim on PTEST opcode 2025-04-29 15:58:28 +02:00
ptitSeb
ae8b5b4239 [INTERP] Fixed some more instruction name comments 2025-04-29 15:54:00 +02:00
rajdakin
1aa29ec1d3
[WRAPPERHELPER] Fixed 02423c2 (#2584) 2025-04-28 20:33:47 +02:00
Yang Liu
f72d43b77e
[RV64_DYNAREC] Minor optim to 8 bit TEST opcode (#2583) 2025-04-28 20:32:54 +02:00
Yang Liu
25de8bd35c
[RV64_DYNAREC] Small optimization to LEA opcode (#2582) 2025-04-28 12:31:15 +02:00
ptitSeb
5c9dc159d2 [ARM64_DYNAREC] Mostly cosmetic changes to SSE/AVX packed shift opcodes 2025-04-28 11:37:35 +02:00
ptitSeb
5a4021d72b [INTERP] Fixes and improvments to SSE/AVX packed shift opcodes 2025-04-28 11:36:50 +02:00
Yang Liu
ebaea69204
[RV64_DYNAREC] Optimized rv64 printer for pseudo and jump instructions (#2581) 2025-04-28 09:40:47 +02:00
Yang Liu
a221d50c17
Show Dynarec architecture in version string (#2580) 2025-04-28 09:39:22 +02:00
Yang Liu
4441be7a02
[RV64_DYNAREC] Minor adjustment to dynarec_missing=2 (#2578) 2025-04-28 08:11:28 +02:00
ptitSeb
bb7dfd395f [ARM64_DYNAREC] Small optim for PSIGN[B/W/D] opcodes 2025-04-27 19:39:01 +02:00
ptitSeb
b552de33f9 [ARM64_DYNAREC] Some work on UD flags on (66) F3 0F BC/BD opcodes 2025-04-27 17:37:44 +02:00
ptitSeb
35c8beb15f [ARM64_DYNAREC] More work on UD flags for (66) F3 0F BC/BD opcodes 2025-04-27 16:18:57 +02:00
ptitSeb
e1fd56123c [ARM64_DYNAREC] Minor fox to F6 /7 opcode 2025-04-27 16:18:23 +02:00
ptitSeb
b7ae6ebc27 [INTERP] More work on UD flags 2025-04-27 15:51:17 +02:00
ptitSeb
9b904c622a [INTERP] Fixed some potential issue with LOCK ADC/SBB on Dynarec build 2025-04-27 15:41:22 +02:00
ptitSeb
950371427d [INTERP] Added 66 F3 0F BC opcode 2025-04-27 14:15:29 +02:00
ptitSeb
be63129179 [WRAPPER] Reworked libssh2 wrapping, to make it more complete 2025-04-27 14:07:31 +02:00
ptitSeb
02423c2d7d [WRAPPERHELPER] Fixed a small issue with the parser 2025-04-27 14:07:01 +02:00
ptitSeb
4add55aa45 [ELFLOADER] Fixed an issue were fail to load a library might endup unloading used libraries 2025-04-27 12:38:32 +02:00
ptitSeb
7334bb46c6 [ELFLOADER] Added lib loading/unloading logs to DLSYM_ERROR 2025-04-27 11:53:33 +02:00
ptitSeb
9c962f8b2c [RCFILE] Fixed BOX64_ROLLING_LOG not being a boolean but an integer value 2025-04-27 11:06:40 +02:00
ptitSeb
1f73944603 [ARM64_DYNAREC] Refactored (V)PSHUFD opcodes 2025-04-26 15:57:38 +02:00
ptitSeb
e844c5baa3 [INTERP] Cosmetic change to VPSHUFD opocde 2025-04-26 15:43:56 +02:00
ptitSeb
c849178bf8 [WRAPPER] Fixed some potential sagfault on my_backtrace wrapped function 2025-04-26 15:43:01 +02:00
ptitSeb
ff4ae1f4d8 [ARM64_DYNAREC] Allow shift with saturation on (V)PMULH(U)W because it will never saturate 2025-04-26 10:46:11 +02:00
ptitSeb
f7acb78743 [ARM64_DYNAREC] Small fix for edge cases on (V)PMULHUW opcodes 2025-04-26 10:39:44 +02:00
ptitSeb
6796b9ca02 [WRAPPER] Added some missing function to wrapped libgio-2 (for #2575) 2025-04-26 10:12:28 +02:00
ptitSeb
e4da025dc0 [ARM64_DYNAREC] Fixed (rarely used) some edge case for (V)PMULHRSW opcode (and improved tests) 2025-04-25 20:03:58 +02:00
ptitSeb
b6b069cf8d [ARM64_DYNAREC] Small optim on some 256bits VPMOV[S/Z]X* opcodes 2025-04-25 17:28:28 +02:00
ptitSeb
f9475aa540 [ARM64_DYNAREC] Allow bigger block to be built 2025-04-25 16:43:23 +02:00
ptitSeb
c6f0872e50 [ARM64_DYNAREC] Minor change, (V)PMOVMSKB is only valid on register, not memory 2025-04-25 16:10:16 +02:00
ptitSeb
71dc02e06f [INTERP] Another fix for a opcode name in comment 2025-04-25 16:05:50 +02:00