riscv-software-src/riscv-isa-sim
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Remove non-ISO compound literals (-Wpedantic)

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This commit is contained in:
Andrew Waterman
2025-04-16 14:24:03 -07:00
parent 8006a64768
commit 2c26357d0c
4 changed files with 38 additions and 46 deletions
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16
customext/cflush.cc
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@@ -24,18 +24,18 @@ class cflush_t : public extension_t
cflush_t() {}
std::vector<insn_desc_t> get_instructions(const processor_t &) override {
std::vector<insn_desc_t> insns;
insns.push_back((insn_desc_t){0xFC000073, 0xFFF07FFF, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush});
insns.push_back((insn_desc_t){0xFC200073, 0xFFF07FFF, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush});
insns.push_back((insn_desc_t){0xFC100073, 0xFFF07FFF, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush});
std::vector<insn_desc_t> insns = {
{0xFC000073, 0xFFF07FFF, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush},
{0xFC200073, 0xFFF07FFF, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush},
{0xFC100073, 0xFFF07FFF, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush}};
return insns;
}
std::vector<disasm_insn_t *> get_disasms(const processor_t *) override {
std::vector<disasm_insn_t*> insns;
insns.push_back(new disasm_insn_t("cflush.d.l1", 0xFC000073, 0xFFF07FFF, {&xrs1}));
insns.push_back(new disasm_insn_t("cdiscard.d.l1", 0xFC200073, 0xFFF07FFF, {&xrs1}));
insns.push_back(new disasm_insn_t("cflush.i.l1", 0xFC100073, 0xFFF07FFF, {&xrs1}));
std::vector<disasm_insn_t*> insns = {
new disasm_insn_t("cflush.d.l1", 0xFC000073, 0xFFF07FFF, {&xrs1}),
new disasm_insn_t("cdiscard.d.l1", 0xFC200073, 0xFFF07FFF, {&xrs1}),
new disasm_insn_t("cflush.i.l1", 0xFC100073, 0xFFF07FFF, {&xrs1})};
return insns;
}
};

9
fesvr/dtm.cc
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@@ -61,17 +61,20 @@ uint32_t dtm_t::do_command(dtm_t::req r)
uint32_t dtm_t::read(uint32_t addr)
{
return do_command((req){addr, 1, 0});
req r = {addr, 1, 0};
return do_command(r);
}
uint32_t dtm_t::write(uint32_t addr, uint32_t data)
{
return do_command((req){addr, 2, data});
req r = {addr, 2, data};
return do_command(r);
}
void dtm_t::nop()
{
do_command((req){0, 0, 0});
req r = {0, 0, 0};
do_command(r);
}
void dtm_t::select_hart(int hartsel) {

41
riscv/processor.cc
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@@ -705,21 +705,27 @@ void processor_t::register_base_instructions()
#include "insn_list.h"
#undef DEFINE_INSN
#define DEFINE_INSN_UNCOND(name) { \
insn_desc_t insn = { \
name##_match, \
name##_mask, \
fast_rv32i_##name, \
fast_rv64i_##name, \
fast_rv32e_##name, \
fast_rv64e_##name, \
logged_rv32i_##name, \
logged_rv64i_##name, \
logged_rv32e_##name, \
logged_rv64e_##name \
}; \
register_base_insn(insn); \
}
// add overlapping instructions first, in order
#define DECLARE_OVERLAP_INSN(name, ext) \
name##_overlapping = true; \
if (isa.extension_enabled(ext)) \
register_base_insn((insn_desc_t) { \
name##_match, \
name##_mask, \
fast_rv32i_##name, \
fast_rv64i_##name, \
fast_rv32e_##name, \
fast_rv64e_##name, \
logged_rv32i_##name, \
logged_rv64i_##name, \
logged_rv32e_##name, \
logged_rv64e_##name});
DEFINE_INSN_UNCOND(name);
#include "overlap_list.h"
#undef DECLARE_OVERLAP_INSN
@@ -728,19 +734,10 @@ void processor_t::register_base_instructions()
// appear earlier to improve search time on opcode_cache misses.
#define DEFINE_INSN(name) \
if (!name##_overlapping) \
register_base_insn((insn_desc_t) { \
name##_match, \
name##_mask, \
fast_rv32i_##name, \
fast_rv64i_##name, \
fast_rv32e_##name, \
fast_rv64e_##name, \
logged_rv32i_##name, \
logged_rv64i_##name, \
logged_rv32e_##name, \
logged_rv64e_##name});
DEFINE_INSN_UNCOND(name);
#include "insn_list.h"
#undef DEFINE_INSN
#undef DEFINE_INSN_UNCOND
// terminate instruction list with a catch-all
register_base_insn(insn_desc_t::illegal_instruction);

18
riscv/rocc.cc
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@@ -33,19 +33,11 @@ customX(3)
std::vector<insn_desc_t> rocc_t::get_instructions(const processor_t &)
{
std::vector<insn_desc_t> insns;
insns.push_back((insn_desc_t){0x0b, 0x7f,
&::illegal_instruction, c0, &::illegal_instruction, c0,
&::illegal_instruction, c0, &::illegal_instruction, c0});
insns.push_back((insn_desc_t){0x2b, 0x7f,
&::illegal_instruction, c1, &::illegal_instruction, c1,
&::illegal_instruction, c1, &::illegal_instruction, c1});
insns.push_back((insn_desc_t){0x5b, 0x7f,
&::illegal_instruction, c2, &::illegal_instruction, c2,
&::illegal_instruction, c2, &::illegal_instruction, c2});
insns.push_back((insn_desc_t){0x7b, 0x7f,
&::illegal_instruction, c3, &::illegal_instruction, c3,
&::illegal_instruction, c0, &::illegal_instruction, c3});
std::vector<insn_desc_t> insns = {
{0x0b, 0x7f, &::illegal_instruction, c0, &::illegal_instruction, c0, &::illegal_instruction, c0, &::illegal_instruction, c0},
{0x2b, 0x7f, &::illegal_instruction, c1, &::illegal_instruction, c1, &::illegal_instruction, c1, &::illegal_instruction, c1},
{0x5b, 0x7f, &::illegal_instruction, c2, &::illegal_instruction, c2, &::illegal_instruction, c2, &::illegal_instruction, c2},
{0x7b, 0x7f, &::illegal_instruction, c3, &::illegal_instruction, c3, &::illegal_instruction, c0, &::illegal_instruction, c3}};
return insns;
}