riscv-software-src/riscv-isa-sim
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Reduce perf impact of Ziccid

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Modifications are expected to be uncommon, so don't flush the I$
quite so often.
This commit is contained in:
Andrew Waterman
2025-06-12 17:09:13 -07:00
parent cce834e437
commit 833ab91894
2 changed files with 7 additions and 1 deletions
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5
riscv/execute.cc
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@@ -226,7 +226,10 @@ void processor_t::step(size_t n)
if (extension_enabled(EXT_ZICCID)) {
// Ziccid requires stores eventually become visible to instruction fetch,
// so periodically flush the I$
_mmu->flush_icache();
if (ziccid_flush_count-- == 0) {
ziccid_flush_count += ZICCID_FLUSH_PERIOD;
_mmu->flush_icache();
}
}
while (n > 0) {

3
riscv/processor.h
View File

@@ -412,6 +412,9 @@ private:
static const size_t OPCODE_CACHE_SIZE = 4095;
opcode_cache_entry_t opcode_cache[OPCODE_CACHE_SIZE];
unsigned ziccid_flush_count = 0;
static const unsigned ZICCID_FLUSH_PERIOD = 10;
bool is_handled_in_vs();
void take_pending_interrupt() { take_interrupt(state.mip->read() & state.mie->read()); }
void take_interrupt(reg_t mask); // take first enabled interrupt in mask