riscv/riscv-opcodes
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Add RNMI CSRs and instruction

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Don't merge yet; it's still early days for this extension.
This commit is contained in:
Andrew Waterman
2021-11-08 18:43:43 -08:00
parent 2497a8cc12
commit 71cd23ab5d
2 changed files with 6 additions and 1 deletions
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1
opcodes-system
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@@ -3,6 +3,7 @@ ecall 11..7=0 19..15=0 31..20=0x000 14..12=0 6..2=0x1C 1..0=3
ebreak 11..7=0 19..15=0 31..20=0x001 14..12=0 6..2=0x1C 1..0=3
sret 11..7=0 19..15=0 31..20=0x102 14..12=0 6..2=0x1C 1..0=3
mret 11..7=0 19..15=0 31..20=0x302 14..12=0 6..2=0x1C 1..0=3
mnret 11..7=0 19..15=0 31..20=0x702 14..12=0 6..2=0x1C 1..0=3
dret 11..7=0 19..15=0 31..20=0x7b2 14..12=0 6..2=0x1C 1..0=3
sfence.vma 11..7=0 rs1 rs2 31..25=0x09 14..12=0 6..2=0x1C 1..0=3
wfi 11..7=0 19..15=0 31..20=0x105 14..12=0 6..2=0x1C 1..0=3

6
parse_opcodes
View File

@@ -206,6 +206,10 @@ csrs = [
(0x344, 'mip'),
(0x34a, 'mtinst'),
(0x34b, 'mtval2'),
(0x350, 'mnscratch'),
(0x351, 'mnepc'),
(0x352, 'mncause'),
(0x353, 'mnstatus'),
(0x3a0, 'pmpcfg0'),
(0x3a1, 'pmpcfg1'),
(0x3a2, 'pmpcfg2'),
@@ -895,7 +899,7 @@ def print_insts(*names):
def make_supervisor_latex_table():
print_header('r', 'i')
print_subtitle('Trap-Return Instructions')
print_insts('sret', 'mret')
print_insts('sret', 'mret', 'mnret')
print_subtitle('Interrupt-Management Instructions')
print_insts('wfi')
print_subtitle('Supervisor Memory-Management Instructions')