mirror of
https://git.rtems.org/rtems-libbsd/
synced 2025-07-25 07:33:13 +08:00
ffec: Defragment transmit mbuf only if necessary
Use structure similar to TSEC (if_tsec) driver. The use of bus_dmamap_sync() differs these network interface drivers. This should not be the case. Update #3090.
This commit is contained in:
Sebastian Huber
parent
798d308be8
commit
0cb40755cc
@ -125,12 +125,13 @@ static struct ofw_compat_data compat_data[] = {
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};
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/*
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* Driver data and defines.
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* Driver data and defines. The descriptor counts must be a power of two.
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*/
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#define RX_DESC_COUNT 64
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#define RX_DESC_SIZE (sizeof(struct ffec_hwdesc) * RX_DESC_COUNT)
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#define TX_DESC_COUNT 64
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#define TX_DESC_SIZE (sizeof(struct ffec_hwdesc) * TX_DESC_COUNT)
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#define TX_MAX_DMA_SEGS 8
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#define WATCHDOG_TIMEOUT_SECS 5
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#define STATS_HARVEST_INTERVAL 3
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@ -187,7 +188,6 @@ struct ffec_softc {
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struct ffec_bufmap txbuf_map[TX_DESC_COUNT];
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uint32_t tx_idx_head;
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uint32_t tx_idx_tail;
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int txcount;
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};
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#define FFEC_LOCK(sc) mtx_lock(&(sc)->mtx)
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@ -200,6 +200,8 @@ struct ffec_softc {
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static void ffec_init_locked(struct ffec_softc *sc);
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static void ffec_stop_locked(struct ffec_softc *sc);
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static void ffec_encap(struct ifnet *ifp, struct ffec_softc *sc,
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struct mbuf *m0, int *start_tx);
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static void ffec_txstart_locked(struct ffec_softc *sc);
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static void ffec_txfinish_locked(struct ffec_softc *sc);
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@ -232,17 +234,39 @@ WR4(struct ffec_softc *sc, bus_size_t off, uint32_t val)
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}
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static inline uint32_t
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next_rxidx(struct ffec_softc *sc, uint32_t curidx)
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next_rxidx(uint32_t curidx)
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{
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return ((curidx == RX_DESC_COUNT - 1) ? 0 : curidx + 1);
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return ((curidx + 1) & (RX_DESC_COUNT - 1));
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}
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static inline uint32_t
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next_txidx(struct ffec_softc *sc, uint32_t curidx)
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next_txidx(uint32_t curidx)
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{
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return ((curidx == TX_DESC_COUNT - 1) ? 0 : curidx + 1);
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return ((curidx + 1) & (TX_DESC_COUNT - 1));
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}
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static inline uint32_t
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prev_txidx(uint32_t curidx)
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{
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return ((curidx - 1) & (TX_DESC_COUNT - 1));
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}
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static inline uint32_t
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inc_txidx(uint32_t curidx, uint32_t inc)
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{
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return ((curidx + inc) & (TX_DESC_COUNT - 1));
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}
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static inline uint32_t
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free_txdesc(struct ffec_softc *sc)
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{
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return (((sc)->tx_idx_tail - (sc)->tx_idx_head - 1) &
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(TX_DESC_COUNT - 1));
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}
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static void
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@ -569,105 +593,110 @@ ffec_tick(void *arg)
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callout_reset(&sc->ffec_callout, hz, ffec_tick, sc);
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}
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inline static uint32_t
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ffec_setup_txdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr,
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uint32_t len)
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static void
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ffec_encap(struct ifnet *ifp, struct ffec_softc *sc, struct mbuf *m0,
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int *start_tx)
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{
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uint32_t nidx;
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bus_dma_segment_t segs[TX_MAX_DMA_SEGS];
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int error, i, nsegs;
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struct ffec_bufmap *bmap;
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uint32_t tx_idx;
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uint32_t flags;
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nidx = next_txidx(sc, idx);
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FFEC_ASSERT_LOCKED(sc);
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/* Addr/len 0 means we're clearing the descriptor after xmit done. */
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if (paddr == 0 || len == 0) {
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flags = 0;
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--sc->txcount;
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} else {
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flags = FEC_TXDESC_READY | FEC_TXDESC_L | FEC_TXDESC_TC;
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++sc->txcount;
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tx_idx = sc->tx_idx_head;
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bmap = &sc->txbuf_map[tx_idx];
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/* Create mapping in DMA memory */
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error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, bmap->map, m0,
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segs, &nsegs, BUS_DMA_NOWAIT);
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if (error == EFBIG) {
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/* Too many segments! Defrag and try again. */
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struct mbuf *m = m_defrag(m0, M_NOWAIT);
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if (m == NULL) {
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m_freem(m0);
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return;
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}
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m0 = m;
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error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag,
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bmap->map, m0, segs, &nsegs, BUS_DMA_NOWAIT);
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}
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if (nidx == 0)
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flags |= FEC_TXDESC_WRAP;
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if (error != 0) {
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/* Give up. */
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m_freem(m0);
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return;
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}
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#ifndef __rtems__
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bus_dmamap_sync(sc->txbuf_tag, bmap->map, BUS_DMASYNC_PREWRITE);
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#endif /* __rtems__ */
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bmap->mbuf = m0;
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/*
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* The hardware requires 32-bit physical addresses. We set up the dma
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* tag to indicate that, so the cast to uint32_t should never lose
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* significant bits.
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* Fill in the TX descriptors back to front so that READY bit in first
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* descriptor is set last.
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*/
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sc->txdesc_ring[idx].buf_paddr = (uint32_t)paddr;
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wmb();
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sc->txdesc_ring[idx].flags_len = flags | len; /* Must be set last! */
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tx_idx = inc_txidx(tx_idx, (uint32_t)nsegs);
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sc->tx_idx_head = tx_idx;
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flags = FEC_TXDESC_L | FEC_TXDESC_READY | FEC_TXDESC_TC;
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for (i = nsegs - 1; i >= 0; i--) {
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struct ffec_hwdesc *tx_desc;
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return (nidx);
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}
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static int
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ffec_setup_txbuf(struct ffec_softc *sc, int idx, struct mbuf **mp)
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{
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struct mbuf * m;
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int error, nsegs;
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struct bus_dma_segment seg;
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if ((m = m_defrag(*mp, M_NOWAIT)) == NULL)
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return (ENOMEM);
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*mp = m;
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error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map,
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m, &seg, &nsegs, 0);
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if (error != 0) {
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return (ENOMEM);
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}
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#ifndef __rtems__
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bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map,
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BUS_DMASYNC_PREWRITE);
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#else /* __rtems__ */
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rtems_cache_flush_multiple_data_lines((void *)seg.ds_addr, seg.ds_len);
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tx_idx = prev_txidx(tx_idx);;
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tx_desc = &sc->txdesc_ring[tx_idx];
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tx_desc->buf_paddr = segs[i].ds_addr;
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#ifdef __rtems__
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rtems_cache_flush_multiple_data_lines((void *)segs[i].ds_addr,
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segs[i].ds_len);
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#endif /* __rtems__ */
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sc->txbuf_map[idx].mbuf = m;
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ffec_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len);
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if (i == 0) {
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wmb();
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}
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return (0);
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tx_desc->flags_len = (tx_idx == (TX_DESC_COUNT - 1) ?
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FEC_TXDESC_WRAP : 0) | flags | segs[i].ds_len;
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flags &= ~FEC_TXDESC_L;
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}
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BPF_MTAP(ifp, m0);
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*start_tx = 1;
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}
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static void
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ffec_txstart_locked(struct ffec_softc *sc)
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{
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struct ifnet *ifp;
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struct mbuf *m;
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int enqueued;
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struct mbuf *m0;
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int start_tx;
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FFEC_ASSERT_LOCKED(sc);
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ifp = sc->ifp;
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start_tx = 0;
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if (!sc->link_is_up)
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return;
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ifp = sc->ifp;
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if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
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return;
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enqueued = 0;
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for (;;) {
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if (sc->txcount == (TX_DESC_COUNT-1)) {
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if (free_txdesc(sc) < TX_MAX_DMA_SEGS) {
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/* No free descriptors */
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ifp->if_drv_flags |= IFF_DRV_OACTIVE;
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break;
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}
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IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
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if (m == NULL)
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/* Get packet from the queue */
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IFQ_DRV_DEQUEUE(&ifp->if_snd, m0);
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if (m0 == NULL)
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break;
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if (ffec_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) {
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IFQ_DRV_PREPEND(&ifp->if_snd, m);
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break;
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}
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BPF_MTAP(ifp, m);
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sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head);
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++enqueued;
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ffec_encap(ifp, sc, m0, &start_tx);
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}
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if (enqueued != 0) {
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if (start_tx ) {
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bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREWRITE);
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WR4(sc, FEC_TDAR_REG, FEC_TDAR_TDAR);
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bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTWRITE);
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@ -689,40 +718,43 @@ static void
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ffec_txfinish_locked(struct ffec_softc *sc)
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{
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struct ifnet *ifp;
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struct ffec_hwdesc *desc;
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struct ffec_bufmap *bmap;
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boolean_t retired_buffer;
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uint32_t tx_idx;
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FFEC_ASSERT_LOCKED(sc);
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ifp = sc->ifp;
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/* XXX Can't set PRE|POST right now, but we need both. */
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bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREREAD);
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bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTREAD);
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ifp = sc->ifp;
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retired_buffer = false;
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while (sc->tx_idx_tail != sc->tx_idx_head) {
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desc = &sc->txdesc_ring[sc->tx_idx_tail];
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tx_idx = sc->tx_idx_tail;
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while (tx_idx != sc->tx_idx_head) {
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struct ffec_hwdesc *desc;
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struct ffec_bufmap *bmap;
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desc = &sc->txdesc_ring[tx_idx];
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if (desc->flags_len & FEC_TXDESC_READY)
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break;
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retired_buffer = true;
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bmap = &sc->txbuf_map[sc->tx_idx_tail];
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bus_dmamap_sync(sc->txbuf_tag, bmap->map,
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bmap = &sc->txbuf_map[tx_idx];
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tx_idx = next_txidx(tx_idx);
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if (bmap->mbuf == NULL)
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continue;
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/*
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* This is the last buf in this packet, so unmap and free it.
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*/
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bus_dmamap_sync(sc->txbuf_tag, bmap->map,
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BUS_DMASYNC_POSTWRITE);
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bus_dmamap_unload(sc->txbuf_tag, bmap->map);
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m_freem(bmap->mbuf);
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bmap->mbuf = NULL;
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ffec_setup_txdesc(sc, sc->tx_idx_tail, 0, 0);
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sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail);
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}
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sc->tx_idx_tail = tx_idx;
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/*
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* If we retired any buffers, there will be open tx slots available in
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* the descriptor ring, go try to start some new output.
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*/
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if (retired_buffer) {
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ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
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ffec_txstart_locked(sc);
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}
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ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
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ffec_txstart_locked(sc);
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/* If there are no buffers outstanding, muzzle the watchdog. */
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if (sc->tx_idx_tail == sc->tx_idx_head) {
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@ -740,7 +772,7 @@ ffec_setup_rxdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr)
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* tag to indicate that, so the cast to uint32_t should never lose
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* significant bits.
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*/
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nidx = next_rxidx(sc, idx);
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nidx = next_rxidx(idx);
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sc->rxdesc_ring[idx].buf_paddr = (uint32_t)paddr;
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wmb();
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sc->rxdesc_ring[idx].flags_len = FEC_RXDESC_EMPTY |
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@ -924,7 +956,7 @@ ffec_rxfinish_locked(struct ffec_softc *sc)
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*/
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ffec_rxfinish_onebuf(sc, len);
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}
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sc->rx_idx = next_rxidx(sc, sc->rx_idx);
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sc->rx_idx = next_rxidx(sc->rx_idx);
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}
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if (produced_empty_buffer) {
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@ -1076,13 +1108,15 @@ ffec_stop_locked(struct ffec_softc *sc)
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while (idx != sc->tx_idx_head) {
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desc = &sc->txdesc_ring[idx];
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bmap = &sc->txbuf_map[idx];
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if (desc->buf_paddr != 0) {
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bus_dmamap_unload(sc->txbuf_tag, bmap->map);
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m_freem(bmap->mbuf);
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bmap->mbuf = NULL;
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ffec_setup_txdesc(sc, idx, 0, 0);
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}
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idx = next_txidx(sc, idx);
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idx = next_txidx(idx);
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if (bmap->mbuf == NULL)
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continue;
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bus_dmamap_sync(sc->txbuf_tag, bmap->map,
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BUS_DMASYNC_POSTWRITE);
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bus_dmamap_unload(sc->txbuf_tag, bmap->map);
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m_freem(bmap->mbuf);
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bmap->mbuf = NULL;
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}
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/*
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@ -1210,7 +1244,6 @@ ffec_init_locked(struct ffec_softc *sc)
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*/
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sc->rx_idx = 0;
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sc->tx_idx_head = sc->tx_idx_tail = 0;
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sc->txcount = 0;
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WR4(sc, FEC_RDSR_REG, sc->rxdesc_ring_paddr);
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WR4(sc, FEC_TDSR_REG, sc->txdesc_ring_paddr);
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@ -1593,7 +1626,7 @@ ffec_attach(device_t dev)
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BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
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BUS_SPACE_MAXADDR, /* highaddr */
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NULL, NULL, /* filter, filterarg */
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MCLBYTES, 1, /* maxsize, nsegments */
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MCLBYTES, TX_MAX_DMA_SEGS, /* maxsize, nsegments */
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MCLBYTES, /* maxsegsize */
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0, /* flags */
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NULL, NULL, /* lockfunc, lockarg */
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@ -1612,7 +1645,9 @@ ffec_attach(device_t dev)
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"could not create TX buffer DMA map.\n");
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goto out;
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}
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ffec_setup_txdesc(sc, idx, 0, 0);
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sc->txdesc_ring[idx].buf_paddr = 0;
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sc->txdesc_ring[idx].flags_len =
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((idx == TX_DESC_COUNT - 1) ? FEC_TXDESC_WRAP : 0);
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}
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/*
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