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Add DEC Tulip, Broadcomm (bce, bfe, bge), and SMC 9111x NICs

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This commit is contained in:
Joel Sherrill 2012-03-22 08:02:26 -05:00
parent 0f09b72726
commit 5ad09a161d
19 changed files with 52451 additions and 1 deletions
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10
Makefile
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@ -267,6 +267,7 @@ C_FILES = \
freebsd/dev/mii/mii.c \
freebsd/dev/mii/mii_physubr.c \
freebsd/dev/mii/icsphy.c \
freebsd/dev/mii/brgphy.c \
freebsd/local/usb_if.c \
freebsd/local/bus_if.c \
freebsd/local/device_if.c \
@ -328,7 +329,14 @@ C_FILES = \
freebsd/dev/e1000/e1000_ich8lan.c \
freebsd/dev/e1000/e1000_mbx.c \
freebsd/dev/e1000/e1000_phy.c \
freebsd/dev/e1000/if_igb.c
freebsd/dev/e1000/if_igb.c \
freebsd/dev/dc/dcphy.c \
freebsd/dev/dc/if_dc.c \
freebsd/dev/dc/pnphy.c \
freebsd/dev/smc/if_smc.c \
freebsd/dev/bce/if_bce.c \
freebsd/dev/bfe/if_bfe.c \
freebsd/dev/bge/if_bge.c
# RTEMS Project Owned Files
C_FILES += \
rtemsbsd/dev/usb/controller/ohci_lpc3250.c \

71
freebsd-to-rtems.py
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@ -1083,6 +1083,7 @@ devNet.addHeaderFiles(
[
'dev/mii/mii.h',
'dev/mii/miivar.h',
'dev/mii/brgphyreg.h',
'dev/mii/icsphyreg.h',
'net/bpf.h',
'net/ethernet.h',
@ -1100,6 +1101,7 @@ devNet.addSourceFiles(
'dev/mii/mii.c',
'dev/mii/mii_physubr.c',
'dev/mii/icsphy.c',
'dev/mii/brgphy.c',
]
)
@ -1190,6 +1192,69 @@ devNic_e1000.addSourceFiles(
]
)
# DEC Tulip aka Intel 21143
devNic_dc = Module('dev_nic_dc')
devNic_dc.addHeaderFiles(
[
'dev/dc/if_dcreg.h',
]
)
devNic_dc.addSourceFiles(
[
'dev/dc/dcphy.c',
'dev/dc/if_dc.c',
'dev/dc/pnphy.c',
]
)
# SMC9111x
devNic_smc = Module('dev_nic_smc')
devNic_smc.addHeaderFiles(
[
'dev/smc/if_smcreg.h',
'dev/smc/if_smcvar.h',
]
)
devNic_smc.addSourceFiles(
[
'dev/smc/if_smc.c',
]
)
# Crystal Semiconductor CS8900
devNic_cs = Module('dev_nic_cs')
devNic_cs.addHeaderFiles(
[
'dev/cs/if_csreg.h',
'dev/cs/if_csvar.h',
]
)
devNic_cs.addSourceFiles(
[
'dev/cs/if_cs.c',
'dev/cs/if_cs_isa.c',
'dev/cs/if_cs_pccard.c',
]
)
# Broadcomm BCE, BFE, BGE - MII is intertwined
devNic_broadcomm = Module('dev_nic_broadcomm')
devNic_broadcomm.addHeaderFiles(
[
'dev/bce/if_bcefw.h',
'dev/bce/if_bcereg.h',
'dev/bfe/if_bfereg.h',
'dev/bge/if_bgereg.h',
]
)
devNic_broadcomm.addSourceFiles(
[
'dev/bce/if_bce.c',
'dev/bfe/if_bfe.c',
'dev/bge/if_bge.c',
]
)
netDeps = Module('netDeps')
netDeps.addHeaderFiles(
[
@ -1883,6 +1948,7 @@ mm.addEmptyFiles(
'machine/sf_buf.h',
'machine/smp.h',
#'machine/vmparam.h',
'local/opt_bce.h',
'local/opt_ntp.h',
'local/pci_if.h',
'security/audit/audit.h',
@ -1958,6 +2024,11 @@ mm.addModule(devNic)
mm.addModule(devNic_re)
mm.addModule(devNic_fxp)
mm.addModule(devNic_e1000)
mm.addModule(devNic_dc)
mm.addModule(devNic_smc)
mm.addModule(devNic_broadcomm)
# TBD Requires ISA and PCCard Support to be pulled in.
# mm.addModule(devNic_cs)
# Now add CPU Architecture Dependent Modules
mm.addModule(armDependent)

10847
freebsd/dev/bce/if_bce.c Normal file
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14594
freebsd/dev/bce/if_bcefw.h Normal file
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6796
freebsd/dev/bce/if_bcereg.h Normal file
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1973
freebsd/dev/bfe/if_bfe.c Normal file
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626
freebsd/dev/bfe/if_bfereg.h Normal file
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@ -0,0 +1,626 @@
/*-
* Copyright (c) 2003 Stuart Walsh
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/* $FreeBSD$ */
#ifndef _BFE_H
#define _BFE_H
/* PCI registers */
#define BFE_PCI_MEMLO 0x10
#define BFE_PCI_MEMHIGH 0x14
#define BFE_PCI_INTLINE 0x3C
/* Register layout. */
#define BFE_DEVCTRL 0x00000000 /* Device Control */
#define BFE_PFE 0x00000080 /* Pattern Filtering Enable */
#define BFE_IPP 0x00000400 /* Internal EPHY Present */
#define BFE_EPR 0x00008000 /* EPHY Reset */
#define BFE_PME 0x00001000 /* PHY Mode Enable */
#define BFE_PMCE 0x00002000 /* PHY Mode Clocks Enable */
#define BFE_PADDR 0x0007c000 /* PHY Address */
#define BFE_PADDR_SHIFT 18
#define BFE_BIST_STAT 0x0000000C /* Built-In Self-Test Status */
#define BFE_WKUP_LEN 0x00000010 /* Wakeup Length */
#define BFE_ISTAT 0x00000020 /* Interrupt Status */
#define BFE_ISTAT_PME 0x00000040 /* Power Management Event */
#define BFE_ISTAT_TO 0x00000080 /* General Purpose Timeout */
#define BFE_ISTAT_DSCE 0x00000400 /* Descriptor Error */
#define BFE_ISTAT_DATAE 0x00000800 /* Data Error */
#define BFE_ISTAT_DPE 0x00001000 /* Descr. Protocol Error */
#define BFE_ISTAT_RDU 0x00002000 /* Receive Descr. Underflow */
#define BFE_ISTAT_RFO 0x00004000 /* Receive FIFO Overflow */
#define BFE_ISTAT_TFU 0x00008000 /* Transmit FIFO Underflow */
#define BFE_ISTAT_RX 0x00010000 /* RX Interrupt */
#define BFE_ISTAT_TX 0x01000000 /* TX Interrupt */
#define BFE_ISTAT_EMAC 0x04000000 /* EMAC Interrupt */
#define BFE_ISTAT_MII_WRITE 0x08000000 /* MII Write Interrupt */
#define BFE_ISTAT_MII_READ 0x10000000 /* MII Read Interrupt */
#define BFE_ISTAT_ERRORS (BFE_ISTAT_DSCE | BFE_ISTAT_DATAE | BFE_ISTAT_DPE |\
BFE_ISTAT_RDU | BFE_ISTAT_RFO | BFE_ISTAT_TFU)
#define BFE_IMASK 0x00000024 /* Interrupt Mask */
#define BFE_IMASK_DEF (BFE_ISTAT_ERRORS | BFE_ISTAT_TO | BFE_ISTAT_RX | \
BFE_ISTAT_TX)
#define BFE_MAC_CTRL 0x000000A8 /* MAC Control */
#define BFE_CTRL_CRC32_ENAB 0x00000001 /* CRC32 Generation Enable */
#define BFE_CTRL_PDOWN 0x00000004 /* Onchip EPHY Powerdown */
#define BFE_CTRL_EDET 0x00000008 /* Onchip EPHY Energy Detected */
#define BFE_CTRL_LED 0x000000e0 /* Onchip EPHY LED Control */
#define BFE_CTRL_LED_SHIFT 5
#define BFE_MAC_FLOW 0x000000AC /* MAC Flow Control */
#define BFE_FLOW_RX_HIWAT 0x000000ff /* Onchip FIFO HI Water Mark */
#define BFE_FLOW_PAUSE_ENAB 0x00008000 /* Enable Pause Frame Generation */
#define BFE_RCV_LAZY 0x00000100 /* Lazy Interrupt Control */
#define BFE_LAZY_TO_MASK 0x00ffffff /* Timeout */
#define BFE_LAZY_FC_MASK 0xff000000 /* Frame Count */
#define BFE_LAZY_FC_SHIFT 24
#define BFE_DMATX_CTRL 0x00000200 /* DMA TX Control */
#define BFE_TX_CTRL_ENABLE 0x00000001 /* Enable */
#define BFE_TX_CTRL_SUSPEND 0x00000002 /* Suepend Request */
#define BFE_TX_CTRL_LPBACK 0x00000004 /* Loopback Enable */
#define BFE_TX_CTRL_FAIRPRI 0x00000008 /* Fair Priority */
#define BFE_TX_CTRL_FLUSH 0x00000010 /* Flush Request */
#define BFE_DMATX_ADDR 0x00000204 /* DMA TX Descriptor Ring Address */
#define BFE_DMATX_PTR 0x00000208 /* DMA TX Last Posted Descriptor */
#define BFE_DMATX_STAT 0x0000020C /* DMA TX Current Active Desc. + Status */
#define BFE_STAT_CDMASK 0x00000fff /* Current Descriptor Mask */
#define BFE_STAT_SMASK 0x0000f000 /* State Mask */
#define BFE_STAT_DISABLE 0x00000000 /* State Disabled */
#define BFE_STAT_SACTIVE 0x00001000 /* State Active */
#define BFE_STAT_SIDLE 0x00002000 /* State Idle Wait */
#define BFE_STAT_STOPPED 0x00003000 /* State Stopped */
#define BFE_STAT_SSUSP 0x00004000 /* State Suspend Pending */
#define BFE_STAT_EMASK 0x000f0000 /* Error Mask */
#define BFE_STAT_ENONE 0x00000000 /* Error None */
#define BFE_STAT_EDPE 0x00010000 /* Error Desc. Protocol Error */
#define BFE_STAT_EDFU 0x00020000 /* Error Data FIFO Underrun */
#define BFE_STAT_EBEBR 0x00030000 /* Error Bus Error on Buffer Read */
#define BFE_STAT_EBEDA 0x00040000 /* Error Bus Error on Desc. Access */
#define BFE_STAT_FLUSHED 0x00100000 /* Flushed */
#define BFE_DMARX_CTRL 0x00000210 /* DMA RX Control */
#define BFE_RX_CTRL_ENABLE 0x00000001 /* Enable */
#define BFE_RX_CTRL_ROMASK 0x000000fe /* Receive Offset Mask */
#define BFE_RX_CTRL_ROSHIFT 1 /* Receive Offset Shift */
#define BFE_DMARX_ADDR 0x00000214 /* DMA RX Descriptor Ring Address */
#define BFE_DMARX_PTR 0x00000218 /* DMA RX Last Posted Descriptor */
#define BFE_DMARX_STAT 0x0000021C /* DMA RX Current Active Desc. + Status */
#define BFE_RXCONF 0x00000400 /* EMAC RX Config */
#define BFE_RXCONF_DBCAST 0x00000001 /* Disable Broadcast */
#define BFE_RXCONF_ALLMULTI 0x00000002 /* Accept All Multicast */
#define BFE_RXCONF_NORXTX 0x00000004 /* Receive Disable While Transmitting */
#define BFE_RXCONF_PROMISC 0x00000008 /* Promiscuous Enable */
#define BFE_RXCONF_LPBACK 0x00000010 /* Loopback Enable */
#define BFE_RXCONF_FLOW 0x00000020 /* Flow Control Enable */
#define BFE_RXCONF_ACCEPT 0x00000040 /* Accept Unicast Flow Control Frame */
#define BFE_RXCONF_RFILT 0x00000080 /* Reject Filter */
#define BFE_RXMAXLEN 0x00000404 /* EMAC RX Max Packet Length */
#define BFE_TXMAXLEN 0x00000408 /* EMAC TX Max Packet Length */
#define BFE_MDIO_CTRL 0x00000410 /* EMAC MDIO Control */
#define BFE_MDIO_MAXF_MASK 0x0000007f /* MDC Frequency */
#define BFE_MDIO_PREAMBLE 0x00000080 /* MII Preamble Enable */
#define BFE_MDIO_DATA 0x00000414 /* EMAC MDIO Data */
#define BFE_MDIO_DATA_DATA 0x0000ffff /* R/W Data */
#define BFE_MDIO_TA_MASK 0x00030000 /* Turnaround Value */
#define BFE_MDIO_TA_SHIFT 16
#define BFE_MDIO_TA_VALID 2
#define BFE_MDIO_RA_MASK 0x007c0000 /* Register Address */
#define BFE_MDIO_PMD_MASK 0x0f800000 /* Physical Media Device */
#define BFE_MDIO_OP_MASK 0x30000000 /* Opcode */
#define BFE_MDIO_SB_MASK 0xc0000000 /* Start Bits */
#define BFE_MDIO_SB_START 0x40000000 /* Start Of Frame */
#define BFE_MDIO_RA_SHIFT 18
#define BFE_MDIO_PMD_SHIFT 23
#define BFE_MDIO_OP_SHIFT 28
#define BFE_MDIO_OP_WRITE 1
#define BFE_MDIO_OP_READ 2
#define BFE_MDIO_SB_SHIFT 30
#define BFE_EMAC_IMASK 0x00000418 /* EMAC Interrupt Mask */
#define BFE_EMAC_ISTAT 0x0000041C /* EMAC Interrupt Status */
#define BFE_EMAC_INT_MII 0x00000001 /* MII MDIO Interrupt */
#define BFE_EMAC_INT_MIB 0x00000002 /* MIB Interrupt */
#define BFE_EMAC_INT_FLOW 0x00000003 /* Flow Control Interrupt */
#define BFE_CAM_DATA_LO 0x00000420 /* EMAC CAM Data Low */
#define BFE_CAM_DATA_HI 0x00000424 /* EMAC CAM Data High */
#define BFE_CAM_HI_VALID 0x00010000 /* Valid Bit */
#define BFE_CAM_CTRL 0x00000428 /* EMAC CAM Control */
#define BFE_CAM_ENABLE 0x00000001 /* CAM Enable */
#define BFE_CAM_MSEL 0x00000002 /* Mask Select */
#define BFE_CAM_READ 0x00000004 /* Read */
#define BFE_CAM_WRITE 0x00000008 /* Read */
#define BFE_CAM_INDEX_MASK 0x003f0000 /* Index Mask */
#define BFE_CAM_BUSY 0x80000000 /* CAM Busy */
#define BFE_CAM_INDEX_SHIFT 16
#define BFE_ENET_CTRL 0x0000042C /* EMAC ENET Control */
#define BFE_ENET_ENABLE 0x00000001 /* EMAC Enable */
#define BFE_ENET_DISABLE 0x00000002 /* EMAC Disable */
#define BFE_ENET_SRST 0x00000004 /* EMAC Soft Reset */
#define BFE_ENET_EPSEL 0x00000008 /* External PHY Select */
#define BFE_TX_CTRL 0x00000430 /* EMAC TX Control */
#define BFE_TX_DUPLEX 0x00000001 /* Full Duplex */
#define BFE_TX_FMODE 0x00000002 /* Flow Mode */
#define BFE_TX_SBENAB 0x00000004 /* Single Backoff Enable */
#define BFE_TX_SMALL_SLOT 0x00000008 /* Small Slottime */
#define BFE_TX_WMARK 0x00000434 /* EMAC TX Watermark */
#define BFE_MIB_CTRL 0x00000438 /* EMAC MIB Control */
#define BFE_MIB_CLR_ON_READ 0x00000001 /* Autoclear on Read */
/* Status registers */
#define BFE_TX_GOOD_O 0x00000500 /* MIB TX Good Octets */
#define BFE_TX_GOOD_P 0x00000504 /* MIB TX Good Packets */
#define BFE_TX_O 0x00000508 /* MIB TX Octets */
#define BFE_TX_P 0x0000050C /* MIB TX Packets */
#define BFE_TX_BCAST 0x00000510 /* MIB TX Broadcast Packets */
#define BFE_TX_MCAST 0x00000514 /* MIB TX Multicast Packets */
#define BFE_TX_64 0x00000518 /* MIB TX <= 64 byte Packets */
#define BFE_TX_65_127 0x0000051C /* MIB TX 65 to 127 byte Packets */
#define BFE_TX_128_255 0x00000520 /* MIB TX 128 to 255 byte Packets */
#define BFE_TX_256_511 0x00000524 /* MIB TX 256 to 511 byte Packets */
#define BFE_TX_512_1023 0x00000528 /* MIB TX 512 to 1023 byte Packets */
#define BFE_TX_1024_MAX 0x0000052C /* MIB TX 1024 to max byte Packets */
#define BFE_TX_JABBER 0x00000530 /* MIB TX Jabber Packets */
#define BFE_TX_OSIZE 0x00000534 /* MIB TX Oversize Packets */
#define BFE_TX_FRAG 0x00000538 /* MIB TX Fragment Packets */
#define BFE_TX_URUNS 0x0000053C /* MIB TX Underruns */
#define BFE_TX_TCOLS 0x00000540 /* MIB TX Total Collisions */
#define BFE_TX_SCOLS 0x00000544 /* MIB TX Single Collisions */
#define BFE_TX_MCOLS 0x00000548 /* MIB TX Multiple Collisions */
#define BFE_TX_ECOLS 0x0000054C /* MIB TX Excessive Collisions */
#define BFE_TX_LCOLS 0x00000550 /* MIB TX Late Collisions */
#define BFE_TX_DEFERED 0x00000554 /* MIB TX Defered Packets */
#define BFE_TX_CLOST 0x00000558 /* MIB TX Carrier Lost */
#define BFE_TX_PAUSE 0x0000055C /* MIB TX Pause Packets */
#define BFE_RX_GOOD_O 0x00000580 /* MIB RX Good Octets */
#define BFE_RX_GOOD_P 0x00000584 /* MIB RX Good Packets */
#define BFE_RX_O 0x00000588 /* MIB RX Octets */
#define BFE_RX_P 0x0000058C /* MIB RX Packets */
#define BFE_RX_BCAST 0x00000590 /* MIB RX Broadcast Packets */
#define BFE_RX_MCAST 0x00000594 /* MIB RX Multicast Packets */
#define BFE_RX_64 0x00000598 /* MIB RX <= 64 byte Packets */
#define BFE_RX_65_127 0x0000059C /* MIB RX 65 to 127 byte Packets */
#define BFE_RX_128_255 0x000005A0 /* MIB RX 128 to 255 byte Packets */
#define BFE_RX_256_511 0x000005A4 /* MIB RX 256 to 511 byte Packets */
#define BFE_RX_512_1023 0x000005A8 /* MIB RX 512 to 1023 byte Packets */
#define BFE_RX_1024_MAX 0x000005AC /* MIB RX 1024 to max byte Packets */
#define BFE_RX_JABBER 0x000005B0 /* MIB RX Jabber Packets */
#define BFE_RX_OSIZE 0x000005B4 /* MIB RX Oversize Packets */
#define BFE_RX_FRAG 0x000005B8 /* MIB RX Fragment Packets */
#define BFE_RX_MISS 0x000005BC /* MIB RX Missed Packets */
#define BFE_RX_CRCA 0x000005C0 /* MIB RX CRC Align Errors */
#define BFE_RX_USIZE 0x000005C4 /* MIB RX Undersize Packets */
#define BFE_RX_CRC 0x000005C8 /* MIB RX CRC Errors */
#define BFE_RX_ALIGN 0x000005CC /* MIB RX Align Errors */
#define BFE_RX_SYM 0x000005D0 /* MIB RX Symbol Errors */
#define BFE_RX_PAUSE 0x000005D4 /* MIB RX Pause Packets */
#define BFE_RX_NPAUSE 0x000005D8 /* MIB RX Non-Pause Packets */
#define BFE_SBIMSTATE 0x00000F90 /* BFE_SB Initiator Agent State */
#define BFE_PC 0x0000000f /* Pipe Count */
#define BFE_AP_MASK 0x00000030 /* Arbitration Priority */
#define BFE_AP_BOTH 0x00000000 /* Use both timeslices and token */
#define BFE_AP_TS 0x00000010 /* Use timeslices only */
#define BFE_AP_TK 0x00000020 /* Use token only */
#define BFE_AP_RSV 0x00000030 /* Reserved */
#define BFE_IBE 0x00020000 /* In Band Error */
#define BFE_TO 0x00040000 /* Timeout */
/* Seems the bcm440x has a fairly generic core, we only need be concerned with
* a couple of these
*/
#define BFE_SBINTVEC 0x00000F94 /* BFE_SB Interrupt Mask */
#define BFE_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */
#define BFE_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */
#define BFE_INTVEC_ILINE20 0x00000004 /* Enable interrupts for iline20 */
#define BFE_INTVEC_CODEC 0x00000008 /* Enable interrupts for v90 codec */
#define BFE_INTVEC_USB 0x00000010 /* Enable interrupts for usb */
#define BFE_INTVEC_EXTIF 0x00000020 /* Enable interrupts for external i/f */
#define BFE_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */
#define BFE_SBTMSLOW 0x00000F98 /* BFE_SB Target State Low */
#define BFE_RESET 0x00000001 /* Reset */
#define BFE_REJECT 0x00000002 /* Reject */
#define BFE_CLOCK 0x00010000 /* Clock Enable */
#define BFE_FGC 0x00020000 /* Force Gated Clocks On */
#define BFE_PE 0x40000000 /* Power Management Enable */
#define BFE_BE 0x80000000 /* BIST Enable */
#define BFE_SBTMSHIGH 0x00000F9C /* BFE_SB Target State High */
#define BFE_SERR 0x00000001 /* S-error */
#define BFE_INT 0x00000002 /* Interrupt */
#define BFE_BUSY 0x00000004 /* Busy */
#define BFE_GCR 0x20000000 /* Gated Clock Request */
#define BFE_BISTF 0x40000000 /* BIST Failed */
#define BFE_BISTD 0x80000000 /* BIST Done */
#define BFE_SBBWA0 0x00000FA0 /* BFE_SB Bandwidth Allocation Table 0 */
#define BFE_TAB0_MASK 0x0000ffff /* Lookup Table 0 */
#define BFE_TAB1_MASK 0xffff0000 /* Lookup Table 0 */
#define BFE_TAB0_SHIFT 0
#define BFE_TAB1_SHIFT 16
#define BFE_SBIMCFGLOW 0x00000FA8 /* BFE_SB Initiator Configuration Low */
#define BFE_STO_MASK 0x00000003 /* Service Timeout */
#define BFE_RTO_MASK 0x00000030 /* Request Timeout */
#define BFE_CID_MASK 0x00ff0000 /* Connection ID */
#define BFE_RTO_SHIFT 4
#define BFE_CID_SHIFT 16
#define BFE_SBIMCFGHIGH 0x00000FAC /* BFE_SB Initiator Configuration High */
#define BFE_IEM_MASK 0x0000000c /* Inband Error Mode */
#define BFE_TEM_MASK 0x00000030 /* Timeout Error Mode */
#define BFE_BEM_MASK 0x000000c0 /* Bus Error Mode */
#define BFE_TEM_SHIFT 4
#define BFE_BEM_SHIFT 6
#define BFE_SBTMCFGLOW 0x00000FB8 /* BFE_SB Target Configuration Low */
#define BFE_LOW_CD_MASK 0x000000ff /* Clock Divide Mask */
#define BFE_LOW_CO_MASK 0x0000f800 /* Clock Offset Mask */
#define BFE_LOW_IF_MASK 0x00fc0000 /* Interrupt Flags Mask */
#define BFE_LOW_IM_MASK 0x03000000 /* Interrupt Mode Mask */
#define BFE_LOW_CO_SHIFT 11
#define BFE_LOW_IF_SHIFT 18
#define BFE_LOW_IM_SHIFT 24
#define BFE_SBTMCFGHIGH 0x00000FBC /* BFE_SB Target Configuration High */
#define BFE_HIGH_BM_MASK 0x00000003 /* Busy Mode */
#define BFE_HIGH_RM_MASK 0x0000000C /* Retry Mode */
#define BFE_HIGH_SM_MASK 0x00000030 /* Stop Mode */
#define BFE_HIGH_EM_MASK 0x00000300 /* Error Mode */
#define BFE_HIGH_IM_MASK 0x00000c00 /* Interrupt Mode */
#define BFE_HIGH_RM_SHIFT 2
#define BFE_HIGH_SM_SHIFT 4
#define BFE_HIGH_EM_SHIFT 8
#define BFE_HIGH_IM_SHIFT 10
#define BFE_SBBCFG 0x00000FC0 /* BFE_SB Broadcast Configuration */
#define BFE_LAT_MASK 0x00000003 /* BFE_SB Latency */
#define BFE_MAX0_MASK 0x000f0000 /* MAX Counter 0 */
#define BFE_MAX1_MASK 0x00f00000 /* MAX Counter 1 */
#define BFE_MAX0_SHIFT 16
#define BFE_MAX1_SHIFT 20
#define BFE_SBBSTATE 0x00000FC8 /* BFE_SB Broadcast State */
#define BFE_SBBSTATE_SRD 0x00000001 /* ST Reg Disable */
#define BFE_SBBSTATE_HRD 0x00000002 /* Hold Reg Disable */
#define BFE_SBACTCNFG 0x00000FD8 /* BFE_SB Activate Configuration */
#define BFE_SBFLAGST 0x00000FE8 /* BFE_SB Current BFE_SBFLAGS */
#define BFE_SBIDLOW 0x00000FF8 /* BFE_SB Identification Low */
#define BFE_CS_MASK 0x00000003 /* Config Space Mask */
#define BFE_AR_MASK 0x00000038 /* Num Address Ranges Supported */
#define BFE_SYNCH 0x00000040 /* Sync */
#define BFE_INIT 0x00000080 /* Initiator */
#define BFE_MINLAT_MASK 0x00000f00 /* Minimum Backplane Latency */
#define BFE_MAXLAT_MASK 0x0000f000 /* Maximum Backplane Latency */
#define BFE_FIRST 0x00010000 /* This Initiator is First */
#define BFE_CW_MASK 0x000c0000 /* Cycle Counter Width */
#define BFE_TP_MASK 0x00f00000 /* Target Ports */
#define BFE_IP_MASK 0x0f000000 /* Initiator Ports */
#define BFE_AR_SHIFT 3
#define BFE_MINLAT_SHIFT 8
#define BFE_MAXLAT_SHIFT 12
#define BFE_CW_SHIFT 18
#define BFE_TP_SHIFT 20
#define BFE_IP_SHIFT 24
#define BFE_SBIDHIGH 0x00000FFC /* BFE_SB Identification High */
#define BFE_RC_MASK 0x0000000f /* Revision Code */
#define BFE_CC_MASK 0x0000fff0 /* Core Code */
#define BFE_VC_MASK 0xffff0000 /* Vendor Code */
#define BFE_CC_SHIFT 4
#define BFE_VC_SHIFT 16
#define BFE_CORE_ILINE20 0x801
#define BFE_CORE_SDRAM 0x803
#define BFE_CORE_PCI 0x804
#define BFE_CORE_MIPS 0x805
#define BFE_CORE_ENET 0x806
#define BFE_CORE_CODEC 0x807
#define BFE_CORE_USB 0x808
#define BFE_CORE_ILINE100 0x80a
#define BFE_CORE_EXTIF 0x811
/* SSB PCI config space registers. */
#define BFE_BAR0_WIN 0x80
#define BFE_BAR1_WIN 0x84
#define BFE_SPROM_CONTROL 0x88
#define BFE_BAR1_CONTROL 0x8c
/* SSB core and hsot control registers. */
#define BFE_SSB_CONTROL 0x00000000
#define BFE_SSB_ARBCONTROL 0x00000010
#define BFE_SSB_ISTAT 0x00000020
#define BFE_SSB_IMASK 0x00000024
#define BFE_SSB_MBOX 0x00000028
#define BFE_SSB_BCAST_ADDR 0x00000050
#define BFE_SSB_BCAST_DATA 0x00000054
#define BFE_SSB_PCI_TRANS_0 0x00000100
#define BFE_SSB_PCI_TRANS_1 0x00000104
#define BFE_SSB_PCI_TRANS_2 0x00000108
#define BFE_SSB_SPROM 0x00000800
#define BFE_SSB_PCI_MEM 0x00000000
#define BFE_SSB_PCI_IO 0x00000001
#define BFE_SSB_PCI_CFG0 0x00000002
#define BFE_SSB_PCI_CFG1 0x00000003
#define BFE_SSB_PCI_PREF 0x00000004
#define BFE_SSB_PCI_BURST 0x00000008
#define BFE_SSB_PCI_MASK0 0xfc000000
#define BFE_SSB_PCI_MASK1 0xfc000000
#define BFE_SSB_PCI_MASK2 0xc0000000
#define BFE_DESC_LEN 0x00001fff
#define BFE_DESC_CMASK 0x0ff00000 /* Core specific bits */
#define BFE_DESC_EOT 0x10000000 /* End of Table */
#define BFE_DESC_IOC 0x20000000 /* Interrupt On Completion */
#define BFE_DESC_EOF 0x40000000 /* End of Frame */
#define BFE_DESC_SOF 0x80000000 /* Start of Frame */
#define BFE_RX_CP_THRESHOLD 256
#define BFE_RX_HEADER_LEN 28
#define BFE_RX_FLAG_OFIFO 0x00000001 /* FIFO Overflow */
#define BFE_RX_FLAG_CRCERR 0x00000002 /* CRC Error */
#define BFE_RX_FLAG_SERR 0x00000004 /* Receive Symbol Error */
#define BFE_RX_FLAG_ODD 0x00000008 /* Frame has odd number of nibbles */
#define BFE_RX_FLAG_LARGE 0x00000010 /* Frame is > RX MAX Length */
#define BFE_RX_FLAG_MCAST 0x00000020 /* Dest is Multicast Address */
#define BFE_RX_FLAG_BCAST 0x00000040 /* Dest is Broadcast Address */
#define BFE_RX_FLAG_MISS 0x00000080 /* Received due to promisc mode */
#define BFE_RX_FLAG_LAST 0x00000800 /* Last buffer in frame */
#define BFE_RX_FLAG_ERRORS (BFE_RX_FLAG_ODD | BFE_RX_FLAG_SERR | \
BFE_RX_FLAG_CRCERR | BFE_RX_FLAG_OFIFO)
#define BFE_MCAST_TBL_SIZE 32
#define BFE_PCI_DMA 0x40000000
#define BFE_REG_PCI 0x18002000
#define BCOM_VENDORID 0x14E4
#define BCOM_DEVICEID_BCM4401 0x4401
#define BCOM_DEVICEID_BCM4401B0 0x170c
#define PCI_SETBIT(dev, reg, x, s) \
pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s)
#define PCI_CLRBIT(dev, reg, x, s) \
pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s)
#define BFE_TX_LIST_CNT 128
#define BFE_RX_LIST_CNT 128
#define BFE_TX_LIST_SIZE BFE_TX_LIST_CNT * sizeof(struct bfe_desc)
#define BFE_RX_LIST_SIZE BFE_RX_LIST_CNT * sizeof(struct bfe_desc)
#define BFE_RX_OFFSET 30
#define BFE_TX_QLEN 256
#define BFE_RX_RING_ALIGN 4096
#define BFE_TX_RING_ALIGN 4096
#define BFE_MAXTXSEGS 16
#define BFE_DMA_MAXADDR 0x3FFFFFFF /* 1GB DMA address limit. */
#define BFE_ADDR_LO(x) ((uint64_t)(x) & 0xFFFFFFFF)
#define CSR_READ_4(sc, reg) bus_read_4(sc->bfe_res, reg)
#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->bfe_res, reg, val)
#define BFE_OR(sc, name, val) \
CSR_WRITE_4(sc, name, CSR_READ_4(sc, name) | val)
#define BFE_AND(sc, name, val) \
CSR_WRITE_4(sc, name, CSR_READ_4(sc, name) & val)
#define BFE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bfe_mtx, MA_OWNED)
#define BFE_LOCK(_sc) mtx_lock(&(_sc)->bfe_mtx)
#define BFE_UNLOCK(_sc) mtx_unlock(&(_sc)->bfe_mtx)
#define BFE_INC(x, y) (x) = ((x) == ((y)-1)) ? 0 : (x)+1
struct bfe_tx_data {
struct mbuf *bfe_mbuf;
bus_dmamap_t bfe_map;
};
struct bfe_rx_data {
struct mbuf *bfe_mbuf;
bus_dmamap_t bfe_map;
u_int32_t bfe_ctrl;
};
struct bfe_desc {
u_int32_t bfe_ctrl;
u_int32_t bfe_addr;
};
struct bfe_rxheader {
u_int16_t len;
u_int16_t flags;
u_int16_t pad[12];
};
#define MIB_TX_GOOD_O 0
#define MIB_TX_GOOD_P 1
#define MIB_TX_O 2
#define MIB_TX_P 3
#define MIB_TX_BCAST 4
#define MIB_TX_MCAST 5
#define MIB_TX_64 6
#define MIB_TX_65_127 7
#define MIB_TX_128_255 8
#define MIB_TX_256_511 9
#define MIB_TX_512_1023 10
#define MIB_TX_1024_MAX 11
#define MIB_TX_JABBER 12
#define MIB_TX_OSIZE 13
#define MIB_TX_FRAG 14
#define MIB_TX_URUNS 15
#define MIB_TX_TCOLS 16
#define MIB_TX_SCOLS 17
#define MIB_TX_MCOLS 18
#define MIB_TX_ECOLS 19
#define MIB_TX_LCOLS 20
#define MIB_TX_DEFERED 21
#define MIB_TX_CLOST 22
#define MIB_TX_PAUSE 23
#define MIB_RX_GOOD_O 24
#define MIB_RX_GOOD_P 25
#define MIB_RX_O 26
#define MIB_RX_P 27
#define MIB_RX_BCAST 28
#define MIB_RX_MCAST 29
#define MIB_RX_64 30
#define MIB_RX_65_127 31
#define MIB_RX_128_255 32
#define MIB_RX_256_511 33
#define MIB_RX_512_1023 34
#define MIB_RX_1024_MAX 35
#define MIB_RX_JABBER 36
#define MIB_RX_OSIZE 37
#define MIB_RX_FRAG 38
#define MIB_RX_MISS 39
#define MIB_RX_CRCA 40
#define MIB_RX_USIZE 41
#define MIB_RX_CRC 42
#define MIB_RX_ALIGN 43
#define MIB_RX_SYM 44
#define MIB_RX_PAUSE 45
#define MIB_RX_NPAUSE 46
#define BFE_MIB_CNT (MIB_RX_NPAUSE - MIB_TX_GOOD_O + 1)
struct bfe_hw_stats {
uint64_t tx_good_octets;
uint64_t tx_good_frames;
uint64_t tx_octets;
uint64_t tx_frames;
uint64_t tx_bcast_frames;
uint64_t tx_mcast_frames;
uint64_t tx_pkts_64;
uint64_t tx_pkts_65_127;
uint64_t tx_pkts_128_255;
uint64_t tx_pkts_256_511;
uint64_t tx_pkts_512_1023;
uint64_t tx_pkts_1024_max;
uint32_t tx_jabbers;
uint64_t tx_oversize_frames;
uint64_t tx_frag_frames;
uint32_t tx_underruns;
uint32_t tx_colls;
uint32_t tx_single_colls;
uint32_t tx_multi_colls;
uint32_t tx_excess_colls;
uint32_t tx_late_colls;
uint32_t tx_deferrals;
uint32_t tx_carrier_losts;
uint32_t tx_pause_frames;
uint64_t rx_good_octets;
uint64_t rx_good_frames;
uint64_t rx_octets;
uint64_t rx_frames;
uint64_t rx_bcast_frames;
uint64_t rx_mcast_frames;
uint64_t rx_pkts_64;
uint64_t rx_pkts_65_127;
uint64_t rx_pkts_128_255;
uint64_t rx_pkts_256_511;
uint64_t rx_pkts_512_1023;
uint64_t rx_pkts_1024_max;
uint32_t rx_jabbers;
uint64_t rx_oversize_frames;
uint64_t rx_frag_frames;
uint32_t rx_missed_frames;
uint32_t rx_crc_align_errs;
uint32_t rx_runts;
uint32_t rx_crc_errs;
uint32_t rx_align_errs;
uint32_t rx_symbol_errs;
uint32_t rx_pause_frames;
uint32_t rx_control_frames;
};
struct bfe_softc
{
struct ifnet *bfe_ifp; /* interface info */
device_t bfe_dev;
device_t bfe_miibus;
bus_dma_tag_t bfe_tag;
bus_dma_tag_t bfe_parent_tag;
bus_dma_tag_t bfe_tx_tag, bfe_rx_tag;
bus_dmamap_t bfe_tx_map, bfe_rx_map;
bus_dma_tag_t bfe_txmbuf_tag, bfe_rxmbuf_tag;
bus_dmamap_t bfe_rx_sparemap;
void *bfe_intrhand;
struct resource *bfe_irq;
struct resource *bfe_res;
struct callout bfe_stat_co;
struct bfe_hw_stats bfe_stats;
struct bfe_desc *bfe_tx_list, *bfe_rx_list;
struct bfe_tx_data bfe_tx_ring[BFE_TX_LIST_CNT]; /* XXX */
struct bfe_rx_data bfe_rx_ring[BFE_RX_LIST_CNT]; /* XXX */
struct mtx bfe_mtx;
u_int32_t bfe_flags;
#define BFE_FLAG_DETACH 0x4000
#define BFE_FLAG_LINK 0x8000
u_int32_t bfe_imask;
u_int32_t bfe_dma_offset;
u_int32_t bfe_tx_cnt, bfe_tx_cons, bfe_tx_prod;
u_int32_t bfe_rx_prod, bfe_rx_cons;
u_int32_t bfe_tx_dma, bfe_rx_dma;
int bfe_watchdog_timer;
u_int8_t bfe_phyaddr; /* Address of the card's PHY */
u_int8_t bfe_mdc_port;
u_int8_t bfe_core_unit;
u_char bfe_enaddr[6];
int bfe_if_flags;
};
struct bfe_type
{
u_int16_t bfe_vid;
u_int16_t bfe_did;
char *bfe_name;
};
#endif /* _BFE_H */

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@ -0,0 +1,423 @@
#include <freebsd/machine/rtems-bsd-config.h>
/*-
* Copyright (c) 1997, 1998, 1999
* Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Bill Paul.
* 4. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <freebsd/sys/cdefs.h>
__FBSDID("$FreeBSD$");
/*
* Pseudo-driver for internal NWAY support on DEC 21143 and workalike
* controllers. Technically we're abusing the miibus code to handle
* media selection and NWAY support here since there is no MII
* interface. However the logical operations are roughly the same,
* and the alternative is to create a fake MII interface in the driver,
* which is harder to do.
*/
#include <freebsd/sys/param.h>
#include <freebsd/sys/systm.h>
#include <freebsd/sys/kernel.h>
#include <freebsd/sys/socket.h>
#include <freebsd/sys/errno.h>
#include <freebsd/sys/lock.h>
#include <freebsd/sys/module.h>
#include <freebsd/sys/mutex.h>
#include <freebsd/sys/bus.h>
#include <freebsd/net/if.h>
#include <freebsd/net/if_arp.h>
#include <freebsd/net/if_media.h>
#include <freebsd/dev/mii/mii.h>
#include <freebsd/dev/mii/miivar.h>
#include <freebsd/local/miidevs.h>
#include <freebsd/machine/bus.h>
#include <freebsd/machine/resource.h>
#include <freebsd/sys/bus.h>
#include <freebsd/dev/pci/pcivar.h>
#include <freebsd/dev/dc/if_dcreg.h>
#include <freebsd/local/miibus_if.h>
#define DC_SETBIT(sc, reg, x) \
CSR_WRITE_4(sc, reg, \
CSR_READ_4(sc, reg) | x)
#define DC_CLRBIT(sc, reg, x) \
CSR_WRITE_4(sc, reg, \
CSR_READ_4(sc, reg) & ~x)
#define MIIF_AUTOTIMEOUT 0x0004
/*
* This is the subsystem ID for the built-in 21143 ethernet
* in several Compaq Presario systems. Apparently these are
* 10Mbps only, so we need to treat them specially.
*/
#define COMPAQ_PRESARIO_ID 0xb0bb0e11
static int dcphy_probe(device_t);
static int dcphy_attach(device_t);
static device_method_t dcphy_methods[] = {
/* device interface */
DEVMETHOD(device_probe, dcphy_probe),
DEVMETHOD(device_attach, dcphy_attach),
DEVMETHOD(device_detach, mii_phy_detach),
DEVMETHOD(device_shutdown, bus_generic_shutdown),
{ 0, 0 }
};
static devclass_t dcphy_devclass;
static driver_t dcphy_driver = {
"dcphy",
dcphy_methods,
sizeof(struct mii_softc)
};
DRIVER_MODULE(dcphy, miibus, dcphy_driver, dcphy_devclass, 0, 0);
static int dcphy_service(struct mii_softc *, struct mii_data *, int);
static void dcphy_status(struct mii_softc *);
static void dcphy_reset(struct mii_softc *);
static int dcphy_auto(struct mii_softc *);
static int
dcphy_probe(device_t dev)
{
struct mii_attach_args *ma;
ma = device_get_ivars(dev);
/*
* The dc driver will report the 21143 vendor and device
* ID to let us know that it wants us to attach.
*/
if (ma->mii_id1 != DC_VENDORID_DEC ||
ma->mii_id2 != DC_DEVICEID_21143)
return (ENXIO);
device_set_desc(dev, "Intel 21143 NWAY media interface");
return (BUS_PROBE_DEFAULT);
}
static int
dcphy_attach(device_t dev)
{
struct mii_softc *sc;
struct mii_attach_args *ma;
struct mii_data *mii;
struct dc_softc *dc_sc;
device_t brdev;
sc = device_get_softc(dev);
ma = device_get_ivars(dev);
sc->mii_dev = device_get_parent(dev);
mii = ma->mii_data;
LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
sc->mii_flags = miibus_get_flags(dev);
sc->mii_inst = mii->mii_instance++;
sc->mii_phy = ma->mii_phyno;
sc->mii_service = dcphy_service;
sc->mii_pdata = mii;
/*
* Apparently, we can neither isolate nor do loopback.
*/
sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP;
/*dcphy_reset(sc);*/
dc_sc = mii->mii_ifp->if_softc;
CSR_WRITE_4(dc_sc, DC_10BTSTAT, 0);
CSR_WRITE_4(dc_sc, DC_10BTCTRL, 0);
brdev = device_get_parent(sc->mii_dev);
switch (pci_get_subdevice(brdev) << 16 | pci_get_subvendor(brdev)) {
case COMPAQ_PRESARIO_ID:
/* Example of how to only allow 10Mbps modes. */
sc->mii_capabilities = BMSR_ANEG | BMSR_10TFDX | BMSR_10THDX;
break;
default:
if (dc_sc->dc_pmode == DC_PMODE_SIA)
sc->mii_capabilities =
BMSR_ANEG | BMSR_10TFDX | BMSR_10THDX;
else
sc->mii_capabilities =
BMSR_ANEG | BMSR_100TXFDX | BMSR_100TXHDX |
BMSR_10TFDX | BMSR_10THDX;
break;
}
sc->mii_capabilities &= ma->mii_capmask;
device_printf(dev, " ");
mii_phy_add_media(sc);
printf("\n");
MIIBUS_MEDIAINIT(sc->mii_dev);
return (0);
}
static int
dcphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
{
struct dc_softc *dc_sc;
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
int reg;
u_int32_t mode;
dc_sc = mii->mii_ifp->if_softc;
switch (cmd) {
case MII_POLLSTAT:
break;
case MII_MEDIACHG:
/*
* If the interface is not up, don't do anything.
*/
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
break;
mii->mii_media_active = IFM_NONE;
mode = CSR_READ_4(dc_sc, DC_NETCFG);
mode &= ~(DC_NETCFG_FULLDUPLEX | DC_NETCFG_PORTSEL |
DC_NETCFG_PCS | DC_NETCFG_SCRAMBLER | DC_NETCFG_SPEEDSEL);
switch (IFM_SUBTYPE(ife->ifm_media)) {
case IFM_AUTO:
/*dcphy_reset(sc);*/
(void) dcphy_auto(sc);
break;
case IFM_100_T4:
/*
* XXX Not supported as a manual setting right now.
*/
return (EINVAL);
case IFM_100_TX:
dcphy_reset(sc);
DC_CLRBIT(dc_sc, DC_10BTCTRL, DC_TCTL_AUTONEGENBL);
mode |= DC_NETCFG_PORTSEL | DC_NETCFG_PCS |
DC_NETCFG_SCRAMBLER;
if ((ife->ifm_media & IFM_GMASK) == IFM_FDX)
mode |= DC_NETCFG_FULLDUPLEX;
else
mode &= ~DC_NETCFG_FULLDUPLEX;
CSR_WRITE_4(dc_sc, DC_NETCFG, mode);
break;
case IFM_10_T:
DC_CLRBIT(dc_sc, DC_SIARESET, DC_SIA_RESET);
DC_CLRBIT(dc_sc, DC_10BTCTRL, 0xFFFF);
if ((ife->ifm_media & IFM_GMASK) == IFM_FDX)
DC_SETBIT(dc_sc, DC_10BTCTRL, 0x7F3D);
else
DC_SETBIT(dc_sc, DC_10BTCTRL, 0x7F3F);
DC_SETBIT(dc_sc, DC_SIARESET, DC_SIA_RESET);
DC_CLRBIT(dc_sc, DC_10BTCTRL, DC_TCTL_AUTONEGENBL);
mode &= ~DC_NETCFG_PORTSEL;
mode |= DC_NETCFG_SPEEDSEL;
if ((ife->ifm_media & IFM_GMASK) == IFM_FDX)
mode |= DC_NETCFG_FULLDUPLEX;
else
mode &= ~DC_NETCFG_FULLDUPLEX;
CSR_WRITE_4(dc_sc, DC_NETCFG, mode);
break;
default:
return (EINVAL);
}
break;
case MII_TICK:
/*
* Is the interface even up?
*/
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
return (0);
/*
* Only used for autonegotiation.
*/
if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
break;
reg = CSR_READ_4(dc_sc, DC_10BTSTAT);
if (!(reg & DC_TSTAT_LS10) || !(reg & DC_TSTAT_LS100))
break;
/*
* Only retry autonegotiation every 5 seconds.
*
* Otherwise, fall through to calling dcphy_status()
* since real Intel 21143 chips don't show valid link
* status until autonegotiation is switched off, and
* that only happens in dcphy_status(). Without this,
* successful autonegotiation is never recognised on
* these chips.
*/
if (++sc->mii_ticks <= 50)
break;
sc->mii_ticks = 0;
dcphy_auto(sc);
break;
}
/* Update the media status. */
dcphy_status(sc);
/* Callback if something changed. */
mii_phy_update(sc, cmd);
return (0);
}
static void
dcphy_status(struct mii_softc *sc)
{
struct mii_data *mii = sc->mii_pdata;
int reg, anlpar, tstat = 0;
struct dc_softc *dc_sc;
dc_sc = mii->mii_ifp->if_softc;
mii->mii_media_status = IFM_AVALID;
mii->mii_media_active = IFM_ETHER;
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
return;
reg = CSR_READ_4(dc_sc, DC_10BTSTAT);
if (!(reg & DC_TSTAT_LS10) || !(reg & DC_TSTAT_LS100))
mii->mii_media_status |= IFM_ACTIVE;
if (CSR_READ_4(dc_sc, DC_10BTCTRL) & DC_TCTL_AUTONEGENBL) {
/* Erg, still trying, I guess... */
tstat = CSR_READ_4(dc_sc, DC_10BTSTAT);
if ((tstat & DC_TSTAT_ANEGSTAT) != DC_ASTAT_AUTONEGCMP) {
if ((DC_IS_MACRONIX(dc_sc) || DC_IS_PNICII(dc_sc)) &&
(tstat & DC_TSTAT_ANEGSTAT) == DC_ASTAT_DISABLE)
goto skip;
mii->mii_media_active |= IFM_NONE;
return;
}
if (tstat & DC_TSTAT_LP_CAN_NWAY) {
anlpar = tstat >> 16;
if (anlpar & ANLPAR_TX_FD &&
sc->mii_capabilities & BMSR_100TXFDX)
mii->mii_media_active |= IFM_100_TX | IFM_FDX;
else if (anlpar & ANLPAR_T4 &&
sc->mii_capabilities & BMSR_100T4)
mii->mii_media_active |= IFM_100_T4 | IFM_HDX;
else if (anlpar & ANLPAR_TX &&
sc->mii_capabilities & BMSR_100TXHDX)
mii->mii_media_active |= IFM_100_TX | IFM_HDX;
else if (anlpar & ANLPAR_10_FD)
mii->mii_media_active |= IFM_10_T | IFM_FDX;
else if (anlpar & ANLPAR_10)
mii->mii_media_active |= IFM_10_T | IFM_HDX;
else
mii->mii_media_active |= IFM_NONE;
if (DC_IS_INTEL(dc_sc))
DC_CLRBIT(dc_sc, DC_10BTCTRL,
DC_TCTL_AUTONEGENBL);
return;
}
/*
* If the other side doesn't support NWAY, then the
* best we can do is determine if we have a 10Mbps or
* 100Mbps link. There's no way to know if the link
* is full or half duplex, so we default to half duplex
* and hope that the user is clever enough to manually
* change the media settings if we're wrong.
*/
if (!(reg & DC_TSTAT_LS100))
mii->mii_media_active |= IFM_100_TX | IFM_HDX;
else if (!(reg & DC_TSTAT_LS10))
mii->mii_media_active |= IFM_10_T | IFM_HDX;
else
mii->mii_media_active |= IFM_NONE;
if (DC_IS_INTEL(dc_sc))
DC_CLRBIT(dc_sc, DC_10BTCTRL, DC_TCTL_AUTONEGENBL);
return;
}
skip:
if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_SPEEDSEL)
mii->mii_media_active |= IFM_10_T;
else
mii->mii_media_active |= IFM_100_TX;
if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_FULLDUPLEX)
mii->mii_media_active |= IFM_FDX;
else
mii->mii_media_active |= IFM_HDX;
}
static int
dcphy_auto(struct mii_softc *mii)
{
struct dc_softc *sc;
sc = mii->mii_pdata->mii_ifp->if_softc;
DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
if (mii->mii_capabilities & BMSR_100TXHDX)
CSR_WRITE_4(sc, DC_10BTCTRL, 0x3FFFF);
else
CSR_WRITE_4(sc, DC_10BTCTRL, 0xFFFF);
DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
DC_SETBIT(sc, DC_10BTCTRL, DC_TCTL_AUTONEGENBL);
DC_SETBIT(sc, DC_10BTSTAT, DC_ASTAT_TXDISABLE);
return (EJUSTRETURN);
}
static void
dcphy_reset(struct mii_softc *mii)
{
struct dc_softc *sc;
sc = mii->mii_pdata->mii_ifp->if_softc;
DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
DELAY(1000);
DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
}

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#include <freebsd/machine/rtems-bsd-config.h>
/*
* Copyright (c) 1997, 1998, 1999
* Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Bill Paul.
* 4. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <freebsd/sys/cdefs.h>
__FBSDID("$FreeBSD$");
/*
* Pseudo-driver for media selection on the Lite-On PNIC 82c168
* chip. The NWAY support on this chip is horribly broken, so we
* only support manual mode selection. This is lame, but getting
* NWAY to work right is amazingly difficult.
*/
#include <freebsd/sys/param.h>
#include <freebsd/sys/systm.h>
#include <freebsd/sys/kernel.h>
#include <freebsd/sys/socket.h>
#include <freebsd/sys/errno.h>
#include <freebsd/sys/lock.h>
#include <freebsd/sys/module.h>
#include <freebsd/sys/mutex.h>
#include <freebsd/sys/bus.h>
#include <freebsd/net/if.h>
#include <freebsd/net/if_arp.h>
#include <freebsd/net/if_media.h>
#include <freebsd/dev/mii/mii.h>
#include <freebsd/dev/mii/miivar.h>
#include <freebsd/local/miidevs.h>
#include <freebsd/machine/bus.h>
#include <freebsd/machine/resource.h>
#include <freebsd/sys/bus.h>
#include <freebsd/dev/dc/if_dcreg.h>
#include <freebsd/local/miibus_if.h>
#define DC_SETBIT(sc, reg, x) \
CSR_WRITE_4(sc, reg, \
CSR_READ_4(sc, reg) | x)
#define DC_CLRBIT(sc, reg, x) \
CSR_WRITE_4(sc, reg, \
CSR_READ_4(sc, reg) & ~x)
static int pnphy_probe(device_t);
static int pnphy_attach(device_t);
static device_method_t pnphy_methods[] = {
/* device interface */
DEVMETHOD(device_probe, pnphy_probe),
DEVMETHOD(device_attach, pnphy_attach),
DEVMETHOD(device_detach, mii_phy_detach),
DEVMETHOD(device_shutdown, bus_generic_shutdown),
{ 0, 0 }
};
static devclass_t pnphy_devclass;
static driver_t pnphy_driver = {
"pnphy",
pnphy_methods,
sizeof(struct mii_softc)
};
DRIVER_MODULE(pnphy, miibus, pnphy_driver, pnphy_devclass, 0, 0);
static int pnphy_service(struct mii_softc *, struct mii_data *, int);
static void pnphy_status(struct mii_softc *);
static int
pnphy_probe(device_t dev)
{
struct mii_attach_args *ma;
ma = device_get_ivars(dev);
/*
* The dc driver will report the 82c168 vendor and device
* ID to let us know that it wants us to attach.
*/
if (ma->mii_id1 != DC_VENDORID_LO ||
ma->mii_id2 != DC_DEVICEID_82C168)
return (ENXIO);
device_set_desc(dev, "PNIC 82c168 media interface");
return (BUS_PROBE_DEFAULT);
}
static int
pnphy_attach(device_t dev)
{
struct mii_softc *sc;
struct mii_attach_args *ma;
struct mii_data *mii;
sc = device_get_softc(dev);
ma = device_get_ivars(dev);
sc->mii_dev = device_get_parent(dev);
mii = ma->mii_data;
LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
sc->mii_flags = miibus_get_flags(dev);
sc->mii_inst = mii->mii_instance++;
sc->mii_phy = ma->mii_phyno;
sc->mii_service = pnphy_service;
sc->mii_pdata = mii;
/*
* Apparently, we can neither isolate nor do loopback.
*/
sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP;
sc->mii_capabilities =
BMSR_100TXFDX | BMSR_100TXHDX | BMSR_10TFDX | BMSR_10THDX;
sc->mii_capabilities &= ma->mii_capmask;
device_printf(dev, " ");
mii_phy_add_media(sc);
printf("\n");
MIIBUS_MEDIAINIT(sc->mii_dev);
return (0);
}
static int
pnphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
{
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
switch (cmd) {
case MII_POLLSTAT:
break;
case MII_MEDIACHG:
/*
* If the interface is not up, don't do anything.
*/
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
break;
switch (IFM_SUBTYPE(ife->ifm_media)) {
case IFM_AUTO:
/* NWAY is busted on this chip */
case IFM_100_T4:
/*
* XXX Not supported as a manual setting right now.
*/
return (EINVAL);
case IFM_100_TX:
mii->mii_media_active = IFM_ETHER | IFM_100_TX;
if ((ife->ifm_media & IFM_GMASK) == IFM_FDX)
mii->mii_media_active |= IFM_FDX;
MIIBUS_STATCHG(sc->mii_dev);
return (0);
case IFM_10_T:
mii->mii_media_active = IFM_ETHER | IFM_10_T;
if ((ife->ifm_media & IFM_GMASK) == IFM_FDX)
mii->mii_media_active |= IFM_FDX;
MIIBUS_STATCHG(sc->mii_dev);
return (0);
default:
return (EINVAL);
}
break;
case MII_TICK:
/*
* Is the interface even up?
*/
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
return (0);
break;
}
/* Update the media status. */
pnphy_status(sc);
/* Callback if something changed. */
mii_phy_update(sc, cmd);
return (0);
}
static void
pnphy_status(struct mii_softc *sc)
{
struct mii_data *mii = sc->mii_pdata;
int reg;
struct dc_softc *dc_sc;
dc_sc = mii->mii_ifp->if_softc;
mii->mii_media_status = IFM_AVALID;
mii->mii_media_active = IFM_ETHER;
reg = CSR_READ_4(dc_sc, DC_ISR);
if (!(reg & DC_ISR_LINKFAIL))
mii->mii_media_status |= IFM_ACTIVE;
if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_SPEEDSEL)
mii->mii_media_active |= IFM_10_T;
else
mii->mii_media_active |= IFM_100_TX;
if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_FULLDUPLEX)
mii->mii_media_active |= IFM_FDX;
else
mii->mii_media_active |= IFM_HDX;
}

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/*-
* Copyright (c) 2000
* Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Bill Paul.
* 4. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _DEV_MII_BRGPHYREG_HH_
#define _DEV_MII_BRGPHYREG_HH_
/*
* Broadcom BCM5400 registers
*/
#define BRGPHY_MII_BMCR 0x00
#define BRGPHY_BMCR_RESET 0x8000
#define BRGPHY_BMCR_LOOP 0x4000
#define BRGPHY_BMCR_SPD0 0x2000 /* Speed select, lower bit */
#define BRGPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
#define BRGPHY_BMCR_PDOWN 0x0800 /* Power down */
#define BRGPHY_BMCR_ISO 0x0400 /* Isolate */
#define BRGPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
#define BRGPHY_BMCR_FDX 0x0100 /* Duplex mode */
#define BRGPHY_BMCR_CTEST 0x0080 /* Collision test enable */
#define BRGPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */
#define BRGPHY_S1000 BRGPHY_BMCR_SPD1 /* 1000mbps */
#define BRGPHY_S100 BRGPHY_BMCR_SPD0 /* 100mpbs */
#define BRGPHY_S10 0 /* 10mbps */
#define BRGPHY_MII_BMSR 0x01
#define BRGPHY_BMSR_EXTSTS 0x0100 /* Extended status present */
#define BRGPHY_BMSR_PRESUB 0x0040 /* Preamble surpression */
#define BRGPHY_BMSR_ACOMP 0x0020 /* Autoneg complete */
#define BRGPHY_BMSR_RFAULT 0x0010 /* Remote fault condition occured */
#define BRGPHY_BMSR_ANEG 0x0008 /* Autoneg capable */
#define BRGPHY_BMSR_LINK 0x0004 /* Link status */
#define BRGPHY_BMSR_JABBER 0x0002 /* Jabber detected */
#define BRGPHY_BMSR_EXT 0x0001 /* Extended capability */
#define BRGPHY_MII_ANAR 0x04
#define BRGPHY_ANAR_NP 0x8000 /* Next page */
#define BRGPHY_ANAR_RF 0x2000 /* Remote fault */
#define BRGPHY_ANAR_ASP 0x0800 /* Asymmetric Pause */
#define BRGPHY_ANAR_PC 0x0400 /* Pause capable */
#define BRGPHY_ANAR_SEL 0x001F /* Selector field, 00001=Ethernet */
#define BRGPHY_MII_ANLPAR 0x05
#define BRGPHY_ANLPAR_NP 0x8000 /* Next page */
#define BRGPHY_ANLPAR_RF 0x2000 /* Remote fault */
#define BRGPHY_ANLPAR_ASP 0x0800 /* Asymmetric Pause */
#define BRGPHY_ANLPAR_PC 0x0400 /* Pause capable */
#define BRGPHY_ANLPAR_SEL 0x001F /* Selector field, 00001=Ethernet */
#define BRGPHY_SEL_TYPE 0x0001 /* Ethernet */
#define BRGPHY_MII_ANER 0x06
#define BRGPHY_ANER_PDF 0x0010 /* Parallel detection fault */
#define BRGPHY_ANER_LPNP 0x0008 /* Link partner can next page */
#define BRGPHY_ANER_NP 0x0004 /* Local PHY can next page */
#define BRGPHY_ANER_RX 0x0002 /* Next page received */
#define BRGPHY_ANER_LPAN 0x0001 /* Link partner autoneg capable */
#define BRGPHY_MII_NEXTP 0x07 /* Next page */
#define BRGPHY_MII_NEXTP_LP 0x08 /* Next page of link partner */
#define BRGPHY_MII_1000CTL 0x09 /* 1000baseT control */
#define BRGPHY_1000CTL_TST 0xE000 /* Test modes */
#define BRGPHY_1000CTL_MSE 0x1000 /* Master/Slave enable */
#define BRGPHY_1000CTL_MSC 0x0800 /* Master/Slave configuration */
#define BRGPHY_1000CTL_RD 0x0400 /* Repeater/DTE */
#define BRGPHY_1000CTL_AFD 0x0200 /* Advertise full duplex */
#define BRGPHY_1000CTL_AHD 0x0100 /* Advertise half duplex */
#define BRGPHY_MII_1000STS 0x0A /* 1000baseT status */
#define BRGPHY_1000STS_MSF 0x8000 /* Master/slave fault */
#define BRGPHY_1000STS_MSR 0x4000 /* Master/slave result */
#define BRGPHY_1000STS_LRS 0x2000 /* Local receiver status */
#define BRGPHY_1000STS_RRS 0x1000 /* Remote receiver status */
#define BRGPHY_1000STS_LPFD 0x0800 /* Link partner can FD */
#define BRGPHY_1000STS_LPHD 0x0400 /* Link partner can HD */
#define BRGPHY_1000STS_IEC 0x00FF /* Idle error count */
#define BRGPHY_MII_EXTSTS 0x0F /* Extended status */
#define BRGPHY_EXTSTS_X_FD_CAP 0x8000 /* 1000base-X FD capable */
#define BRGPHY_EXTSTS_X_HD_CAP 0x4000 /* 1000base-X HD capable */
#define BRGPHY_EXTSTS_T_FD_CAP 0x2000 /* 1000base-T FD capable */
#define BRGPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */
#define BRGPHY_MII_PHY_EXTCTL 0x10 /* PHY extended control */
#define BRGPHY_PHY_EXTCTL_MAC_PHY 0x8000 /* 10BIT/GMI-interface */
#define BRGPHY_PHY_EXTCTL_DIS_CROSS 0x4000 /* Disable MDI crossover */
#define BRGPHY_PHY_EXTCTL_TX_DIS 0x2000 /* TX output disabled */
#define BRGPHY_PHY_EXTCTL_INT_DIS 0x1000 /* Interrupts disabled */
#define BRGPHY_PHY_EXTCTL_F_INT 0x0800 /* Force interrupt */
#define BRGPHY_PHY_EXTCTL_BY_45 0x0400 /* Bypass 4B5B-Decoder */
#define BRGPHY_PHY_EXTCTL_BY_SCR 0x0200 /* Bypass scrambler */
#define BRGPHY_PHY_EXTCTL_BY_MLT3 0x0100 /* Bypass MLT3 encoder */
#define BRGPHY_PHY_EXTCTL_BY_RXA 0x0080 /* Bypass RX alignment */
#define BRGPHY_PHY_EXTCTL_RES_SCR 0x0040 /* Reset scrambler */
#define BRGPHY_PHY_EXTCTL_EN_LTR 0x0020 /* Enable LED traffic mode */
#define BRGPHY_PHY_EXTCTL_LED_ON 0x0010 /* Force LEDs on */
#define BRGPHY_PHY_EXTCTL_LED_OFF 0x0008 /* Force LEDs off */
#define BRGPHY_PHY_EXTCTL_EX_IPG 0x0004 /* Extended TX IPG mode */
#define BRGPHY_PHY_EXTCTL_3_LED 0x0002 /* Three link LED mode */
#define BRGPHY_PHY_EXTCTL_HIGH_LA 0x0001 /* GMII Fifo Elasticy (?) */
#define BRGPHY_MII_PHY_EXTSTS 0x11 /* PHY extended status */
#define BRGPHY_PHY_EXTSTS_CROSS_STAT 0x2000 /* MDI crossover status */
#define BRGPHY_PHY_EXTSTS_INT_STAT 0x1000 /* Interrupt status */
#define BRGPHY_PHY_EXTSTS_RRS 0x0800 /* Remote receiver status */
#define BRGPHY_PHY_EXTSTS_LRS 0x0400 /* Local receiver status */
#define BRGPHY_PHY_EXTSTS_LOCKED 0x0200 /* Locked */
#define BRGPHY_PHY_EXTSTS_LS 0x0100 /* Link status */
#define BRGPHY_PHY_EXTSTS_RF 0x0080 /* Remove fault */
#define BRGPHY_PHY_EXTSTS_CE_ER 0x0040 /* Carrier ext error */
#define BRGPHY_PHY_EXTSTS_BAD_SSD 0x0020 /* Bad SSD */
#define BRGPHY_PHY_EXTSTS_BAD_ESD 0x0010 /* Bad ESS */
#define BRGPHY_PHY_EXTSTS_RX_ER 0x0008 /* RX error */
#define BRGPHY_PHY_EXTSTS_TX_ER 0x0004 /* TX error */
#define BRGPHY_PHY_EXTSTS_LOCK_ER 0x0002 /* Lock error */
#define BRGPHY_PHY_EXTSTS_MLT3_ER 0x0001 /* MLT3 code error */
#define BRGPHY_MII_RXERRCNT 0x12 /* RX error counter */
#define BRGPHY_MII_FCERRCNT 0x13 /* False carrier sense counter */
#define BGRPHY_FCERRCNT 0x00FF /* False carrier counter */
#define BRGPHY_MII_RXNOCNT 0x14 /* RX not OK counter */
#define BRGPHY_RXNOCNT_LOCAL 0xFF00 /* Local RX not OK counter */
#define BRGPHY_RXNOCNT_REMOTE 0x00FF /* Local RX not OK counter */
#define BRGPHY_MII_DSP_RW_PORT 0x15 /* DSP coefficient r/w port */
#define BRGPHY_MII_DSP_ADDR_REG 0x17 /* DSP coefficient addr register */
#define BRGPHY_MII_EPHY_PTEST 0x17 /* 5906 PHY register */
#define BRGPHY_DSP_TAP_NUMBER_MASK 0x00
#define BRGPHY_DSP_AGC_A 0x00
#define BRGPHY_DSP_AGC_B 0x01
#define BRGPHY_DSP_MSE_PAIR_STATUS 0x02
#define BRGPHY_DSP_SOFT_DECISION 0x03
#define BRGPHY_DSP_PHASE_REG 0x04
#define BRGPHY_DSP_SKEW 0x05
#define BRGPHY_DSP_POWER_SAVER_UPPER_BOUND 0x06
#define BRGPHY_DSP_POWER_SAVER_LOWER_BOUND 0x07
#define BRGPHY_DSP_LAST_ECHO 0x08
#define BRGPHY_DSP_FREQUENCY 0x09
#define BRGPHY_DSP_PLL_BANDWIDTH 0x0A
#define BRGPHY_DSP_PLL_PHASE_OFFSET 0x0B
#define BRGPHYDSP_FILTER_DCOFFSET 0x0C00
#define BRGPHY_DSP_FILTER_FEXT3 0x0B00
#define BRGPHY_DSP_FILTER_FEXT2 0x0A00
#define BRGPHY_DSP_FILTER_FEXT1 0x0900
#define BRGPHY_DSP_FILTER_FEXT0 0x0800
#define BRGPHY_DSP_FILTER_NEXT3 0x0700
#define BRGPHY_DSP_FILTER_NEXT2 0x0600
#define BRGPHY_DSP_FILTER_NEXT1 0x0500
#define BRGPHY_DSP_FILTER_NEXT0 0x0400
#define BRGPHY_DSP_FILTER_ECHO 0x0300
#define BRGPHY_DSP_FILTER_DFE 0x0200
#define BRGPHY_DSP_FILTER_FFE 0x0100
#define BRGPHY_DSP_CONTROL_ALL_FILTERS 0x1000
#define BRGPHY_DSP_SEL_CH_0 0x0000
#define BRGPHY_DSP_SEL_CH_1 0x2000
#define BRGPHY_DSP_SEL_CH_2 0x4000
#define BRGPHY_DSP_SEL_CH_3 0x6000
#define BRGPHY_MII_AUXCTL 0x18 /* AUX control */
#define BRGPHY_AUXCTL_LOW_SQ 0x8000 /* Low squelch */
#define BRGPHY_AUXCTL_LONG_PKT 0x4000 /* RX long packets */
#define BRGPHY_AUXCTL_ER_CTL 0x3000 /* Edgerate control */
#define BRGPHY_AUXCTL_TX_TST 0x0400 /* TX test, always 1 */
#define BRGPHY_AUXCTL_DIS_PRF 0x0080 /* dis part resp filter */
#define BRGPHY_AUXCTL_DIAG_MODE 0x0004 /* Diagnostic mode */
#define BRGPHY_MII_AUXSTS 0x19 /* AUX status */
#define BRGPHY_AUXSTS_ACOMP 0x8000 /* Autoneg complete */
#define BRGPHY_AUXSTS_AN_ACK 0x4000 /* Autoneg complete ack */
#define BRGPHY_AUXSTS_AN_ACK_D 0x2000 /* Autoneg complete ack detect */
#define BRGPHY_AUXSTS_AN_NPW 0x1000 /* Autoneg next page wait */
#define BRGPHY_AUXSTS_AN_RES 0x0700 /* Autoneg HCD */
#define BRGPHY_AUXSTS_PDF 0x0080 /* Parallel detect. fault */
#define BRGPHY_AUXSTS_RF 0x0040 /* Remote fault */
#define BRGPHY_AUXSTS_ANP_R 0x0020 /* Autoneg page received */
#define BRGPHY_AUXSTS_LP_ANAB 0x0010 /* Link partner autoneg ability */
#define BRGPHY_AUXSTS_LP_NPAB 0x0008 /* Link partner next page ability */
#define BRGPHY_AUXSTS_LINK 0x0004 /* Link status */
#define BRGPHY_AUXSTS_PRR 0x0002 /* Pause resolution-RX */
#define BRGPHY_AUXSTS_PRT 0x0001 /* Pause resolution-TX */
#define BRGPHY_RES_1000FD 0x0700 /* 1000baseT full duplex */
#define BRGPHY_RES_1000HD 0x0600 /* 1000baseT half duplex */
#define BRGPHY_RES_100FD 0x0500 /* 100baseT full duplex */
#define BRGPHY_RES_100T4 0x0400 /* 100baseT4 */
#define BRGPHY_RES_100HD 0x0300 /* 100baseT half duplex */
#define BRGPHY_RES_10FD 0x0200 /* 10baseT full duplex */
#define BRGPHY_RES_10HD 0x0100 /* 10baseT half duplex */
#define BRGPHY_MII_ISR 0x1A /* Interrupt status */
#define BRGPHY_ISR_PSERR 0x4000 /* Pair swap error */
#define BRGPHY_ISR_MDXI_SC 0x2000 /* MDIX Status Change */
#define BRGPHY_ISR_HCT 0x1000 /* Counter above 32K */
#define BRGPHY_ISR_LCT 0x0800 /* All counter below 128 */
#define BRGPHY_ISR_AN_PR 0x0400 /* Autoneg page received */
#define BRGPHY_ISR_NO_HDCL 0x0200 /* No HCD Link */
#define BRGPHY_ISR_NO_HDC 0x0100 /* No HCD */
#define BRGPHY_ISR_USHDC 0x0080 /* Negotiated Unsupported HCD */
#define BRGPHY_ISR_SCR_S_ERR 0x0040 /* Scrambler sync error */
#define BRGPHY_ISR_RRS_CHG 0x0020 /* Remote RX status change */
#define BRGPHY_ISR_LRS_CHG 0x0010 /* Local RX status change */
#define BRGPHY_ISR_DUP_CHG 0x0008 /* Duplex mode change */
#define BRGPHY_ISR_LSP_CHG 0x0004 /* Link speed changed */
#define BRGPHY_ISR_LNK_CHG 0x0002 /* Link status change */
#define BRGPHY_ISR_CRCERR 0x0001 /* CRC error */
#define BRGPHY_MII_IMR 0x1B /* Interrupt mask */
#define BRGPHY_IMR_PSERR 0x4000 /* Pair swap error */
#define BRGPHY_IMR_MDXI_SC 0x2000 /* MDIX Status Change */
#define BRGPHY_IMR_HCT 0x1000 /* Counter above 32K */
#define BRGPHY_IMR_LCT 0x0800 /* All counter below 128 */
#define BRGPHY_IMR_AN_PR 0x0400 /* Autoneg page received */
#define BRGPHY_IMR_NO_HDCL 0x0200 /* No HCD Link */
#define BRGPHY_IMR_NO_HDC 0x0100 /* No HCD */
#define BRGPHY_IMR_USHDC 0x0080 /* Negotiated Unsupported HCD */
#define BRGPHY_IMR_SCR_S_ERR 0x0040 /* Scrambler sync error */
#define BRGPHY_IMR_RRS_CHG 0x0020 /* Remote RX status change */
#define BRGPHY_IMR_LRS_CHG 0x0010 /* Local RX status change */
#define BRGPHY_IMR_DUP_CHG 0x0008 /* Duplex mode change */
#define BRGPHY_IMR_LSP_CHG 0x0004 /* Link speed changed */
#define BRGPHY_IMR_LNK_CHG 0x0002 /* Link status change */
#define BRGPHY_IMR_CRCERR 0x0001 /* CRC error */
/*******************************************************/
/* Begin: Shared SerDes PHY register definitions */
/*******************************************************/
/* SerDes autoneg is different from copper */
#define BRGPHY_SERDES_ANAR 0x04
#define BRGPHY_SERDES_ANAR_FDX 0x0020
#define BRGPHY_SERDES_ANAR_HDX 0x0040
#define BRGPHY_SERDES_ANAR_NO_PAUSE (0x0 << 7)
#define BRGPHY_SERDES_ANAR_SYM_PAUSE (0x1 << 7)
#define BRGPHY_SERDES_ANAR_ASYM_PAUSE (0x2 << 7)
#define BRGPHY_SERDES_ANAR_BOTH_PAUSE (0x3 << 7)
#define BRGPHY_SERDES_ANLPAR 0x05
#define BRGPHY_SERDES_ANLPAR_FDX 0x0020
#define BRGPHY_SERDES_ANLPAR_HDX 0x0040
#define BRGPHY_SERDES_ANLPAR_NO_PAUSE (0x0 << 7)
#define BRGPHY_SERDES_ANLPAR_SYM_PAUSE (0x1 << 7)
#define BRGPHY_SERDES_ANLPAR_ASYM_PAUSE (0x2 << 7)
#define BRGPHY_SERDES_ANLPAR_BOTH_PAUSE (0x3 << 7)
/*******************************************************/
/* End: Shared SerDes PHY register definitions */
/*******************************************************/
/*******************************************************/
/* Begin: PHY register values for the 5706 PHY */
/*******************************************************/
/*
* Shadow register 0x1C, bit 15 is write enable,
* bits 14-10 select function (0x00 to 0x1F).
*/
#define BRGPHY_MII_SHADOW_1C 0x1C
#define BRGPHY_SHADOW_1C_WRITE_EN 0x8000
#define BRGPHY_SHADOW_1C_SELECT_MASK 0x7C00
/* Shadow 0x1C Mode Control Register (select value 0x1F) */
#define BRGPHY_SHADOW_1C_MODE_CTRL (0x1F << 10)
/* When set, Regs 0-0x0F are 1000X, else 1000T */
#define BRGPHY_SHADOW_1C_ENA_1000X 0x0001
#define BRGPHY_MII_TEST1 0x1E
#define BRGPHY_TEST1_TRIM_EN 0x0010
#define BRGPHY_TEST1_CRC_EN 0x8000
#define BRGPHY_MII_TEST2 0x1F
/*******************************************************/
/* End: PHY register values for the 5706 PHY */
/*******************************************************/
/*******************************************************/
/* Begin: PHY register values for the 5708S SerDes PHY */
/*******************************************************/
/* Autoneg Next Page Transmit 1 Regiser */
#define BRGPHY_5708S_ANEG_NXT_PG_XMIT1 0x0B
#define BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G 0x0001
/* Use the BLOCK_ADDR register to select the page for registers 0x10 to 0x1E */
#define BRGPHY_5708S_BLOCK_ADDR 0x1f
#define BRGPHY_5708S_DIG_PG0 0x0000
#define BRGPHY_5708S_DIG3_PG2 0x0002
#define BRGPHY_5708S_TX_MISC_PG5 0x0005
/* 5708S SerDes "Digital" Registers (page 0) */
#define BRGPHY_5708S_PG0_1000X_CTL1 0x10
#define BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN 0x0010
#define BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE 0x0001
#define BRGPHY_5708S_PG0_1000X_STAT1 0x14
#define BRGPHY_5708S_PG0_1000X_STAT1_LINK 0x0002
#define BRGPHY_5708S_PG0_1000X_STAT1_FDX 0x0004
#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK 0x0018
#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10 (0x0 << 3)
#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100 (0x1 << 3)
#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G (0x2 << 3)
#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G (0x3 << 3)
#define BRGPHY_5708S_PG0_1000X_CTL2 0x11
#define BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN 0x0001
/* 5708S SerDes "Digital 3" Registers (page 2) */
#define BRGPHY_5708S_PG2_DIGCTL_3_0 0x10
#define BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE 0x0001
/* 5708S SerDes "TX Misc" Registers (page 5) */
#define BRGPHY_5708S_PG5_2500STATUS1 0x10
#define BRGPHY_5708S_PG5_TXACTL1 0x15
#define BRGPHY_5708S_PG5_TXACTL3 0x17
/*******************************************************/
/* End: PHY register values for the 5708S SerDes PHY */
/*******************************************************/
/*******************************************************/
/* Begin: PHY register values for the 5709S SerDes PHY */
/*******************************************************/
/* 5709S SerDes "General Purpose Status" Registers */
#define BRGPHY_BLOCK_ADDR_GP_STATUS 0x8120
#define BRGPHY_GP_STATUS_TOP_ANEG_STATUS 0x1B
#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK 0x3F00
#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10 0x0000
#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100 0x0100
#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G 0x0200
#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G 0x0300
#define BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1GKX 0x0D00
#define BRGPHY_GP_STATUS_TOP_ANEG_FDX 0x0008
#define BRGPHY_GP_STATUS_TOP_ANEG_LINK_UP 0x0004
#define BRGPHY_GP_STATUS_TOP_ANEG_CL73_COMP 0x0001
/* 5709S SerDes "SerDes Digital" Registers */
#define BRGPHY_BLOCK_ADDR_SERDES_DIG 0x8300
#define BRGPHY_SERDES_DIG_1000X_CTL1 0x0010
#define BRGPHY_SD_DIG_1000X_CTL1_AUTODET 0x0010
#define BRGPHY_SD_DIG_1000X_CTL1_FIBER 0x0001
/* 5709S SerDes "Over 1G" Registers */
#define BRGPHY_BLOCK_ADDR_OVER_1G 0x8320
#define BRGPHY_OVER_1G_UNFORMAT_PG1 0x19
/* 5709S SerDes "Multi-Rate Backplane Ethernet" Registers */
#define BRGPHY_BLOCK_ADDR_MRBE 0x8350
#define BRGPHY_MRBE_MSG_PG5_NP 0x10
#define BRGPHY_MRBE_MSG_PG5_NP_MBRE 0x0001
#define BRGPHY_MRBE_MSG_PG5_NP_T2 0x0002
/* 5709S SerDes "IEEE Clause 73 User B0" Registers */
#define BRGPHY_BLOCK_ADDR_CL73_USER_B0 0x8370
#define BRGPHY_CL73_USER_B0_MBRE_CTL1 0x12
#define BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP 0x2000
#define BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR 0x4000
#define BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG 0x8000
/* 5709S SerDes "IEEE Clause 73 User B0" Registers */
#define BRGPHY_BLOCK_ADDR_ADDR_EXT 0xFFD0
/* 5709S SerDes "Combo IEEE 0" Registers */
#define BRGPHY_BLOCK_ADDR_COMBO_IEEE0 0xFFE0
#define BRGPHY_ADDR_EXT 0x1E
#define BRGPHY_BLOCK_ADDR 0x1F
#define BRGPHY_ADDR_EXT_AN_MMD 0x3800
/*******************************************************/
/* End: PHY register values for the 5709S SerDes PHY */
/*******************************************************/
#define BRGPHY_INTRS \
~(BRGPHY_IMR_LNK_CHG|BRGPHY_IMR_LSP_CHG|BRGPHY_IMR_DUP_CHG)
#endif /* _DEV_BRGPHY_MIIREG_HH_ */

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/*-
* Copyright (c) 2006 Benno Rice. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*
*/
#ifndef _IF_SMCREG_HH_
#define _IF_SMCREG_HH_
/* All Banks, Offset 0xe: Bank Select Register */
#define BSR 0xe
#define BSR_BANK_MASK 0x0007 /* Which bank is currently selected */
#define BSR_IDENTIFY 0x3300 /* Static value for identification */
#define BSR_IDENTIFY_MASK 0xff00
/* Bank 0, Offset 0x0: Transmit Control Register */
#define TCR 0x0
#define TCR_TXENA 0x0001 /* Enable/disable transmitter */
#define TCR_LOOP 0x0002 /* Put the PHY into loopback mode */
#define TCR_FORCOL 0x0004 /* Force a collision */
#define TCR_PAD_EN 0x0080 /* Pad TX frames to 64 bytes */
#define TCR_NOCRC 0x0100 /* Disable/enable CRC */
#define TCR_MON_CSN 0x0400 /* Monitor carrier signal */
#define TCR_FDUPLX 0x0800 /* Enable/disable full duplex */
#define TCR_STP_SQET 0x1000 /* Stop TX on signal quality error */
#define TCR_EPH_LOOP 0x2000 /* Internal loopback */
#define TCR_SWFDUP 0x8000 /* Switched full duplex */
/* Bank 0, Offset 0x2: EPH Status Register */
#define EPHSR 0x2
#define EPHSR_TX_SUC 0x0001 /* Last TX was successful */
#define EPHSR_SNGLCOL 0x0002 /* Single collision on last TX */
#define EPHSR_MULCOL 0x0004 /* Multiple collisions on last TX */
#define EPHSR_LTX_MULT 0x0008 /* Last TX was multicast */
#define EPHSR_16COL 0x0010 /* 16 collisions on last TX */
#define EPHSR_SQET 0x0020 /* Signal quality error test */
#define EPHSR_LTX_BRD 0x0040 /* Last TX was broadcast */
#define EPHSR_TX_DEFR 0x0080 /* Transmit deferred */
#define EPHSR_LATCOL 0x0200 /* Late collision on last TX */
#define EPHSR_LOST_CARR 0x0400 /* Lost carrier sense */
#define EPHSR_EXC_DEF 0x0800 /* Excessive deferral */
#define EPHSR_CTR_ROL 0x1000 /* Counter rollover */
#define EPHSR_LINK_OK 0x4000 /* Inverse of nLNK pin */
#define EPHSR_TXUNRN 0x8000 /* Transmit underrun */
/* Bank 0, Offset 0x4: Receive Control Register */
#define RCR 0x4
#define RCR_RX_ABORT 0x0001 /* RX aborted */
#define RCR_PRMS 0x0002 /* Enable/disable promiscuous mode */
#define RCR_ALMUL 0x0004 /* Accept all multicast frames */
#define RCR_RXEN 0x0100 /* Enable/disable receiver */
#define RCR_STRIP_CRC 0x0200 /* Strip CRC from RX packets */
#define RCR_ABORT_ENB 0x2000 /* Abort RX on collision */
#define RCR_FILT_CAR 0x4000 /* Filter leading 12 bits of carrier */
#define RCR_SOFT_RST 0x8000 /* Software reset */
/* Bank 0, Offset 0x6: Counter Register */
#define ECR 0x6
#define ECR_SNGLCOL_MASK 0x000f /* Single collisions */
#define ECR_SNGLCOL_SHIFT 0
#define ECR_MULCOL_MASK 0x00f0 /* Multiple collisions */
#define ECR_MULCOL_SHIFT 4
#define ECR_TX_DEFR_MASK 0x0f00 /* Transmit deferrals */
#define ECR_TX_DEFR_SHIFT 8
#define ECR_EXC_DEF_MASK 0xf000 /* Excessive deferrals */
#define ECR_EXC_DEF_SHIFT 12
/* Bank 0, Offset 0x8: Memory Information Register */
#define MIR 0x8
#define MIR_SIZE_MASK 0x00ff /* Memory size (2k pages) */
#define MIR_SIZE_SHIFT 0
#define MIR_FREE_MASK 0xff00 /* Memory free (2k pages) */
#define MIR_FREE_SHIFT 8
#define MIR_PAGE_SIZE 2048
/* Bank 0, Offset 0xa: Receive/PHY Control Reigster */
#define RPCR 0xa
#define RPCR_ANEG 0x0800 /* Put PHY in autonegotiation mode */
#define RPCR_DPLX 0x1000 /* Put PHY in full-duplex mode */
#define RPCR_SPEED 0x2000 /* Manual speed selection */
#define RPCR_LSA_MASK 0x00e0 /* Select LED A function */
#define RPCR_LSA_SHIFT 5
#define RPCR_LSB_MASK 0x001c /* Select LED B function */
#define RPCR_LSB_SHIFT 2
#define RPCR_LED_LINK_ANY 0x0 /* 10baseT or 100baseTX link detected */
#define RPCR_LED_LINK_10 0x2 /* 10baseT link detected */
#define RPCR_LED_LINK_FDX 0x3 /* Full-duplex link detected */
#define RPCR_LED_LINK_100 0x5 /* 100baseTX link detected */
#define RPCR_LED_ACT_ANY 0x4 /* TX or RX activity detected */
#define RPCR_LED_ACT_RX 0x6 /* RX activity detected */
#define RPCR_LED_ACT_TX 0x7 /* TX activity detected */
/* Bank 1, Offset 0x0: Configuration Register */
#define CR 0x0
#define CR_EXT_PHY 0x0200 /* Enable/disable external PHY */
#define CR_GPCNTRL 0x0400 /* Inverse drives nCNTRL pin */
#define CR_NO_WAIT 0x1000 /* Do not request additional waits */
#define CR_EPH_POWER_EN 0x8000 /* Disable/enable low power mode */
/* Bank 1, Offset 0x2: Base Address Register */
#define BAR 0x2
#define BAR_HIGH_MASK 0xe000
#define BAR_LOW_MASK 0x1f00
#define BAR_LOW_SHIFT 4
#define BAR_ADDRESS(val) \
((val & BAR_HIGH_MASK) | ((val & BAR_LOW_MASK) >> BAR_LOW_SHIFT))
/* Bank 1, Offsets 0x4: Individual Address Registers */
#define IAR0 0x4
#define IAR1 0x5
#define IAR2 0x6
#define IAR3 0x7
#define IAR4 0x8
#define IAR5 0x9
/* Bank 1, Offset 0xa: General Purpose Register */
#define GPR 0xa
/* Bank 1, Offset 0xc: Control Register */
#define CTR 0xa
#define CTR_STORE 0x0001 /* Store registers to EEPROM */
#define CTR_RELOAD 0x0002 /* Reload registers from EEPROM */
#define CTR_EEPROM_SELECT 0x0004 /* Select registers to store/reload */
#define CTR_TE_ENABLE 0x0020 /* TX error causes EPH interrupt */
#define CTR_CR_ENABLE 0x0040 /* Ctr rollover causes EPH interrupt */
#define CTR_LE_ENABLE 0x0080 /* Link error causes EPH interrupt */
#define CTR_AUTO_RELEASE 0x0800 /* Automatically release TX packets */
#define CTR_RCV_BAD 0x4000 /* Receive/discard bad CRC packets */
/* Bank 2, Offset 0x0: MMU Command Register */
#define MMUCR 0x0
#define MMUCR_BUSY 0x0001 /* MMU is busy */
#define MMUCR_CMD_NOOP (0<<5) /* No operation */
#define MMUCR_CMD_TX_ALLOC (1<<5) /* Alloc TX memory (256b chunks) */
#define MMUCR_CMD_MMU_RESET (2<<5) /* Reset MMU */
#define MMUCR_CMD_REMOVE (3<<5) /* Remove frame from RX FIFO */
#define MMUCR_CMD_RELEASE (4<<5) /* Remove and release from RX FIFO */
#define MMUCR_CMD_RELEASE_PKT (5<<5) /* Release packet specified in PNR */
#define MMUCR_CMD_ENQUEUE (6<<5) /* Enqueue packet for TX */
#define MMUCR_CMD_TX_RESET (7<<5) /* Reset TX FIFOs */
/* Bank 2, Offset 0x2: Packet Number Register */
#define PNR 0x2
#define PNR_MASK 0x3fff
/* Bank 2, Offset 0x3: Allocation Result Register */
#define ARR 0x3
#define ARR_FAILED 0x8000 /* Last allocation request failed */
#define ARR_MASK 0x3000
/* Bank 2, Offset 0x4: FIFO Ports Register */
#define FIFO_TX 0x4
#define FIFO_RX 0x5
#define FIFO_EMPTY 0x80 /* FIFO empty */
#define FIFO_PACKET_MASK 0x3f /* Packet number mask */
/* Bank 2, Offset 0x6: Pointer Register */
#define PTR 0x6
#define PTR_MASK 0x07ff /* Address accessible within TX/RX */
#define PTR_NOT_EMPTY 0x0800 /* Write Data FIFO not empty */
#define PTR_ETEN 0x1000 /* Enable early TX underrun detection */
#define PTR_READ 0x2000 /* Set read/write */
#define PTR_AUTO_INCR 0x4000 /* Auto increment on read/write */
#define PTR_RCV 0x8000 /* Read/write to/from RX/TX */
/* Bank 2, Offset 0x8: Data Registers */
#define DATA0 0x8
#define DATA1 0xa
/* Bank 2, Offset 0xc: Interrupt Status Registers */
#define IST 0xc /* read only */
#define ACK 0xc /* write only */
#define MSK 0xd
#define RCV_INT 0x0001 /* RX */
#define TX_INT 0x0002 /* TX */
#define TX_EMPTY_INT 0x0004 /* TX empty */
#define ALLOC_INT 0x0008 /* Allocation complete */
#define RX_OVRN_INT 0x0010 /* RX overrun */
#define EPH_INT 0x0020 /* EPH interrupt */
#define ERCV_INT 0x0040 /* Early RX */
#define MD_INT 0x0080 /* MII */
#define IST_PRINTF "\20\01RCV\02TX\03TX_EMPTY\04ALLOC" \
"\05RX_OVRN\06EPH\07ERCV\10MD"
/* Bank 3, Offset 0x0: Multicast Table Registers */
#define MT 0x0
/* Bank 3, Offset 0x8: Management Interface */
#define MGMT 0x8
#define MGMT_MDO 0x0001 /* MII management output */
#define MGMT_MDI 0x0002 /* MII management input */
#define MGMT_MCLK 0x0004 /* MII management clock */
#define MGMT_MDOE 0x0008 /* MII management output enable */
#define MGMT_MSK_CRS100 0x4000 /* Disable CRS100 detection during TX */
/* Bank 3, Offset 0xa: Revision Register */
#define REV 0xa
#define REV_CHIP_MASK 0x00f0 /* Chip ID */
#define REV_CHIP_SHIFT 4
#define REV_REV_MASK 0x000f /* Revision ID */
#define REV_REV_SHIFT 0
#define REV_CHIP_9192 3
#define REV_CHIP_9194 4
#define REV_CHIP_9195 5
#define REV_CHIP_9196 6
#define REV_CHIP_91100 7
#define REV_CHIP_91100FD 8
#define REV_CHIP_91110FD 9
/* Bank 3, Offset 0xc: Early RCV Register */
#define ERCV 0xc
#define ERCV_THRESHOLD_MASK 0x001f /* ERCV int threshold (64b chunks) */
#define ERCV_RCV_DISCARD 0x0080 /* Discard packet being received */
/* Control Byte */
#define CTRL_CRC 0x10 /* Frame has CRC */
#define CTRL_ODD 0x20 /* Frame has odd byte count */
/* Receive Frame Status */
#define RX_MULTCAST 0x0001 /* Frame was multicast */
#define RX_HASH_MASK 0x007e /* Hash value for multicast */
#define RX_HASH_SHIFT 1
#define RX_TOOSHORT 0x0400 /* Frame was too short */
#define RX_TOOLNG 0x0800 /* Frame was too long */
#define RX_ODDFRM 0x1000 /* Frame has odd number of bytes */
#define RX_BADCRC 0x2000 /* Frame failed CRC */
#define RX_BROADCAST 0x4000 /* Frame was broadcast */
#define RX_ALGNERR 0x8000 /* Frame had alignment error */
#define RX_LEN_MASK 0x07ff
/* Length of status word + byte count + control bytes for packets */
#define PKT_CTRL_DATA_LEN 6
/* Number of times to spin on TX allocations */
#define TX_ALLOC_WAIT_TIME 1000
#endif /* IF_SMCREG_HH_ */

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/*-
* Copyright (c) 2008 Benno Rice. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*
*/
#ifndef _IF_SMCVAR_HH_
#define _IF_SMCVAR_HH_
struct smc_softc {
struct ifnet *smc_ifp;
device_t smc_dev;
struct mtx smc_mtx;
u_int smc_chip;
u_int smc_rev;
u_int smc_mask;
/* Resources */
int smc_usemem;
int smc_reg_rid;
int smc_irq_rid;
struct resource *smc_reg;
struct resource *smc_irq;
void *smc_ih;
/* Tasks */
struct taskqueue *smc_tq;
struct task smc_intr;
struct task smc_rx;
struct task smc_tx;
struct mbuf *smc_pending;
struct callout smc_watchdog;
/* MII support */
device_t smc_miibus;
struct callout smc_mii_tick_ch;
void (*smc_mii_tick)(void *);
void (*smc_mii_mediachg)(struct smc_softc *);
int (*smc_mii_mediaioctl)(struct smc_softc *,
struct ifreq *, u_long);
/* DMA support */
void (*smc_read_packet)(struct smc_softc *,
bus_addr_t, uint8_t *, bus_size_t);
void *smc_read_arg;
};
int smc_probe(device_t);
int smc_attach(device_t);
int smc_detach(device_t);
int smc_miibus_readreg(device_t, int, int);
int smc_miibus_writereg(device_t, int, int, int);
void smc_miibus_statchg(device_t);
#endif /* _IF_SMCVAR_HH_ */

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/* EMPTY */