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https://git.rtems.org/rtems-libbsd/
synced 2025-07-25 06:34:06 +08:00
if_atsam: Optimize receive
Do not use the interface mutex in the receive loop. Avoid multiple reads of DMA descriptor words. Use a compile-time constant for the receive DMA descriptor count to simplify calculations. Update #4652.
This commit is contained in:
Sebastian Huber
parent
2cb974fa20
commit
967613fbce
@ -95,26 +95,26 @@
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/** RX Defines */
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#define GMAC_RX_BUFFER_SIZE 1536
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#define GMAC_RX_BUF_DESC_ADDR_MASK 0xFFFFFFFC
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#define GMAC_RX_SET_OFFSET (1u << 15)
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#define GMAC_RX_SET_USED_WRAP ((1u << 1) | (1u << 0))
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#define GMAC_RX_SET_WRAP (1u << 1)
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#define GMAC_RX_SET_USED (1u << 0)
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#define GMAC_DESCRIPTOR_ALIGNMENT 8
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/** Events */
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#define ATSAMV7_ETH_RX_EVENT_INTERRUPT RTEMS_EVENT_1
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#define ATSAMV7_ETH_RX_DATA_OFFSET 2
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#define WATCHDOG_TIMEOUT 5
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/* FIXME: Make these configurable */
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#define MDIO_RETRIES 10
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#define MDIO_PHY MII_PHY_ANY
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#define RXBUF_COUNT 8
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#define IGNORE_RX_ERR false
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#define RX_DESC_LOG2 3
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#define RX_DESC_COUNT (1U << RX_DESC_LOG2)
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#define RX_DESC_WRAP(idx) \
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((((idx) + 1) & RX_DESC_COUNT) >> (RX_DESC_LOG2 - 1))
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RTEMS_STATIC_ASSERT(RX_DESC_WRAP(RX_DESC_COUNT - 1) ==
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GMAC_RX_WRAP_BIT, rx_desc_wrap);
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RTEMS_STATIC_ASSERT(RX_DESC_WRAP(RX_DESC_COUNT - 2) ==
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0, rx_desc_no_wrap);
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#define TX_DESC_LOG2 6
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#define TX_DESC_COUNT (1U << TX_DESC_LOG2)
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#define TX_DESC_WRAP(idx) \
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@ -137,6 +137,10 @@ struct if_atsam_tx_bds {
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volatile sGmacTxDescriptor bds[TX_DESC_COUNT];
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};
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struct if_atsam_rx_bds {
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volatile sGmacRxDescriptor bds[RX_DESC_COUNT];
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};
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/*
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* Per-device data
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*/
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@ -152,12 +156,11 @@ typedef struct if_atsam_softc {
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size_t tx_idx_tail;
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struct if_atsam_tx_bds *tx;
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struct mbuf *tx_mbufs[TX_DESC_COUNT];
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struct if_atsam_rx_bds *rx;
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struct mbuf *rx_mbufs[RX_DESC_COUNT];
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uint8_t GMacAddress[6];
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rtems_id rx_daemon_tid;
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rtems_vector_number interrupt_number;
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struct mbuf **rx_mbuf;
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size_t rx_bd_fill_idx;
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size_t amount_rx_buf;
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struct callout tick_ch;
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/*
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@ -242,27 +245,6 @@ static void if_atsam_poll_hw_stats(struct if_atsam_softc *sc);
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#define IF_ATSAM_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
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static void if_atsam_event_send(rtems_id task, rtems_event_set event)
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{
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rtems_event_send(task, event);
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}
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static void if_atsam_event_receive(if_atsam_softc *sc, rtems_event_set in)
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{
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rtems_event_set out;
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IF_ATSAM_UNLOCK(sc);
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rtems_event_receive(
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in,
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RTEMS_EVENT_ANY | RTEMS_WAIT,
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RTEMS_NO_TIMEOUT,
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&out
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);
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IF_ATSAM_LOCK(sc);
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}
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static struct mbuf *if_atsam_new_mbuf(struct ifnet *ifp)
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{
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struct mbuf *m;
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@ -425,17 +407,17 @@ static void if_atsam_interrupt_handler(void *arg)
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/* Erase the interrupts for RX completion and errors */
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pHw->GMAC_IDR = GMAC_IER_RCOMP | GMAC_IER_ROVR;
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(void)if_atsam_event_send(sc->rx_daemon_tid,
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(void)rtems_event_send(sc->rx_daemon_tid,
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ATSAMV7_ETH_RX_EVENT_INTERRUPT);
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}
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}
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static void rx_update_mbuf(struct mbuf *m,
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volatile sGmacRxDescriptor *buffer_desc)
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static void
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if_atsam_rx_update_mbuf(struct mbuf *m, uint32_t status)
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{
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int frame_len;
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frame_len = (int) (buffer_desc->status.bm.len);
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frame_len = (int)(status & GMAC_LENGTH_FRAME);
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m->m_data = mtod(m, char*)+ETHER_ALIGN;
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m->m_len = frame_len;
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@ -443,7 +425,7 @@ static void rx_update_mbuf(struct mbuf *m,
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/* check checksum offload result */
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m->m_pkthdr.csum_flags = 0;
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switch (buffer_desc->status.bm.typeIDMatchOrCksumResult) {
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switch ((status >> 22) & 0x3) {
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case GMAC_RXDESC_ST_CKSUM_RESULT_IP_CHECKED:
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m->m_pkthdr.csum_flags = CSUM_IP_CHECKED | CSUM_IP_VALID;
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m->m_pkthdr.csum_data = 0xffff;
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@ -464,12 +446,12 @@ static void if_atsam_rx_daemon(void *arg)
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{
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if_atsam_softc *sc = (if_atsam_softc *)arg;
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struct ifnet *ifp = sc->ifp;
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void *rx_bd_base;
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struct mbuf *m;
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struct mbuf *n;
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volatile sGmacRxDescriptor *buffer_desc;
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uint32_t tmp_rx_bd_address;
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volatile sGmacRxDescriptor *base;
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struct if_atsam_rx_bds *rx;
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Gmac *pHw = sc->Gmac_inst.gGmacd.pHw;
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size_t idx;
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struct mbuf **mbufs;
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struct mbuf *m;
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IF_ATSAM_LOCK(sc);
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@ -480,47 +462,37 @@ static void if_atsam_rx_daemon(void *arg)
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}
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/* Allocate memory space for priority queue descriptor list */
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rx_bd_base = rtems_cache_coherent_allocate(sizeof(sGmacRxDescriptor),
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base = rtems_cache_coherent_allocate(sizeof(*base),
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GMAC_DESCRIPTOR_ALIGNMENT, 0);
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assert(rx_bd_base != NULL);
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assert(base != NULL);
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buffer_desc = (sGmacRxDescriptor *)rx_bd_base;
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buffer_desc->addr.val = GMAC_RX_SET_USED_WRAP;
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buffer_desc->status.val = 0;
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base->addr.val = GMAC_RX_OWNERSHIP_BIT | GMAC_RX_WRAP_BIT;
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base->status.val = 0;
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GMAC_SetRxQueue(pHw, (uint32_t)buffer_desc, 1);
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GMAC_SetRxQueue(pHw, (uint32_t)buffer_desc, 2);
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GMAC_SetRxQueue(pHw, (uint32_t)base, 1);
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GMAC_SetRxQueue(pHw, (uint32_t)base, 2);
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/* Allocate memory space for buffer descriptor list */
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rx_bd_base = rtems_cache_coherent_allocate(
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sc->amount_rx_buf * sizeof(sGmacRxDescriptor),
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rx = rtems_cache_coherent_allocate(sizeof(*rx),
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GMAC_DESCRIPTOR_ALIGNMENT, 0);
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assert(rx_bd_base != NULL);
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buffer_desc = (sGmacRxDescriptor *)rx_bd_base;
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assert(rx != NULL);
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sc->rx = rx;
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mbufs = &sc->rx_mbufs[0];
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/* Create descriptor list and mark as empty */
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for (sc->rx_bd_fill_idx = 0; sc->rx_bd_fill_idx < sc->amount_rx_buf;
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++sc->rx_bd_fill_idx) {
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for (idx = 0; idx < RX_DESC_COUNT; ++idx) {
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m = if_atsam_new_mbuf(ifp);
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assert(m != NULL);
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sc->rx_mbuf[sc->rx_bd_fill_idx] = m;
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buffer_desc->addr.val = ((uint32_t)m->m_data) &
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GMAC_RX_BUF_DESC_ADDR_MASK;
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buffer_desc->status.val = 0;
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if (sc->rx_bd_fill_idx == (sc->amount_rx_buf - 1)) {
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buffer_desc->addr.bm.bWrap = 1;
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} else {
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buffer_desc++;
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}
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mbufs[idx] = m;
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rx->bds[idx].addr.val = mtod(m, uint32_t) | RX_DESC_WRAP(idx);
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}
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buffer_desc = (sGmacRxDescriptor *)rx_bd_base;
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/* Set 2 Byte Receive Buffer Offset */
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pHw->GMAC_NCFGR |= GMAC_RX_SET_OFFSET;
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pHw->GMAC_NCFGR |= GMAC_NCFGR_RXBUFO(2);
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/* Write Buffer Queue Base Address Register */
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GMAC_ReceiveEnable(pHw, 0);
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GMAC_SetRxQueue(pHw, (uint32_t)buffer_desc, 0);
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GMAC_SetRxQueue(pHw, (uint32_t)&rx->bds[0], 0);
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/* Set address for address matching */
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GMAC_SetAddress(pHw, 0, sc->GMacAddress);
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@ -528,58 +500,50 @@ static void if_atsam_rx_daemon(void *arg)
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/* Enable Receiving of data */
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GMAC_ReceiveEnable(pHw, 1);
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/* Setup the interrupts for RX completion and errors */
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GMAC_EnableIt(pHw, GMAC_IER_RCOMP | GMAC_IER_ROVR, 0);
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IF_ATSAM_UNLOCK(sc);
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sc->rx_bd_fill_idx = 0;
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idx = 0;
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while (true) {
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/* Wait for events */
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if_atsam_event_receive(sc, ATSAMV7_ETH_RX_EVENT_INTERRUPT);
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rtems_event_set out;
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/*
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* Check for all packets with a set ownership bit
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*/
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while (buffer_desc->addr.bm.bOwnership == 1) {
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if (buffer_desc->status.bm.bEof == 1) {
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m = sc->rx_mbuf[sc->rx_bd_fill_idx];
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/* Enable RX interrupts */
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pHw->GMAC_IER = GMAC_IER_RCOMP | GMAC_IER_ROVR;
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(void) rtems_event_receive(ATSAMV7_ETH_RX_EVENT_INTERRUPT,
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RTEMS_EVENT_ALL | RTEMS_WAIT, RTEMS_NO_TIMEOUT, &out);
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while (true) {
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uint32_t addr;
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uint32_t status;
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addr = rx->bds[idx].addr.val;
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if ((addr & GMAC_RX_OWNERSHIP_BIT) == 0) {
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break;
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}
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status = rx->bds[idx].status.val;
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m = mbufs[idx];
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if (__predict_true((status & GMAC_RX_EOF_BIT) != 0)) {
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struct mbuf *n;
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/* New mbuf for desc */
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n = if_atsam_new_mbuf(ifp);
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if (n != NULL) {
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rx_update_mbuf(m, buffer_desc);
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IF_ATSAM_UNLOCK(sc);
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sc->ifp->if_input(ifp, m);
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IF_ATSAM_LOCK(sc);
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if_atsam_rx_update_mbuf(m, status);
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(*ifp->if_input)(ifp, m);
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m = n;
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}
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sc->rx_mbuf[sc->rx_bd_fill_idx] = m;
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tmp_rx_bd_address = (uint32_t)m->m_data &
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GMAC_RX_BUF_DESC_ADDR_MASK;
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/* Switch pointer to next buffer descriptor */
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if (sc->rx_bd_fill_idx ==
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(sc->amount_rx_buf - 1)) {
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tmp_rx_bd_address |= GMAC_RX_SET_WRAP;
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sc->rx_bd_fill_idx = 0;
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} else {
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++sc->rx_bd_fill_idx;
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}
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/*
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* Give ownership to GMAC for further processing
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*/
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tmp_rx_bd_address &= ~GMAC_RX_SET_USED;
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_ARM_Data_synchronization_barrier();
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buffer_desc->addr.val = tmp_rx_bd_address;
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buffer_desc = (sGmacRxDescriptor *)rx_bd_base
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+ sc->rx_bd_fill_idx;
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} else {
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if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
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}
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mbufs[idx] = m;
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rx->bds[idx].addr.val = mtod(m, uint32_t) |
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RX_DESC_WRAP(idx);
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idx = (idx + 1) % RX_DESC_COUNT;
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}
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/* Setup the interrupts for RX completion and errors */
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GMAC_EnableIt(pHw, GMAC_IER_RCOMP | GMAC_IER_ROVR, 0);
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}
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}
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@ -944,12 +908,6 @@ if_atsam_init(if_atsam_softc *sc)
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GMAC_StatisticsWriteEnable(sc->Gmac_inst.gGmacd.pHw, 1);
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/*
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* Allocate mbuf pointers
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*/
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sc->rx_mbuf = malloc(sc->amount_rx_buf * sizeof *sc->rx_mbuf,
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M_TEMP, M_WAITOK | M_ZERO);
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/* Install interrupt handler */
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status = rtems_interrupt_handler_install(sc->interrupt_number,
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"Ethernet",
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@ -1417,8 +1375,6 @@ static int if_atsam_driver_attach(device_t dev)
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memcpy(sc->GMacAddress, eaddr, ETHER_ADDR_LEN);
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sc->amount_rx_buf = RXBUF_COUNT;
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/* Set Initial Link Speed */
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sc->link_speed = GMAC_SPEED_100M;
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sc->link_duplex = GMAC_DUPLEX_FULL;
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