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https://git.rtems.org/rtems-libbsd/
synced 2025-06-06 17:29:24 +08:00
if_dwc: Checksum offload
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5deeb69c7e
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b99c023a08
@ -102,13 +102,22 @@ __FBSDID("$FreeBSD$");
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#define DDESC_TDES0_TXLAST (1U << 29)
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#define DDESC_TDES0_TXLAST (1U << 29)
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#define DDESC_TDES0_TXFIRST (1U << 28)
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#define DDESC_TDES0_TXFIRST (1U << 28)
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#define DDESC_TDES0_TXCRCDIS (1U << 27)
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#define DDESC_TDES0_TXCRCDIS (1U << 27)
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#define DDESC_TDES0_CIC_IP_HDR (0x1U << 22)
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#define DDESC_TDES0_CIC_IP_HDR_PYL (0x2U << 22)
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#define DDESC_TDES0_CIC_IP_HDR_PYL_PHDR (0x3U << 22)
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#define DDESC_TDES0_TXRINGEND (1U << 21)
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#define DDESC_TDES0_TXRINGEND (1U << 21)
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#define DDESC_TDES0_TXCHAIN (1U << 20)
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#define DDESC_TDES0_TXCHAIN (1U << 20)
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#define DDESC_RDES0_OWN (1U << 31)
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#define DDESC_RDES0_OWN (1U << 31)
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#define DDESC_RDES0_FL_MASK 0x3fff
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#define DDESC_RDES0_FL_MASK 0x3fff
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#define DDESC_RDES0_FL_SHIFT 16 /* Frame Length */
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#define DDESC_RDES0_FL_SHIFT 16 /* Frame Length */
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#define DDESC_RDES0_ESA (1U << 0)
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#define DDESC_RDES1_CHAINED (1U << 14)
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#define DDESC_RDES1_CHAINED (1U << 14)
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#define DDESC_RDES4_IP_PYL_ERR (1U << 4)
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#define DDESC_RDES4_IP_HDR_ERR (1U << 3)
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#define DDESC_RDES4_IP_PYL_TYPE_MSK 0x7U
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#define DDESC_RDES4_IP_PYL_UDP 1U
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#define DDESC_RDES4_IP_PYL_TCP 2U
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/* Alt descriptor bits. */
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/* Alt descriptor bits. */
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#define DDESC_CNTL_TXINT (1U << 31)
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#define DDESC_CNTL_TXINT (1U << 31)
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@ -130,6 +139,10 @@ struct dwc_hwdesc
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uint32_t tdes1; /* cntl for alt layout */
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uint32_t tdes1; /* cntl for alt layout */
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uint32_t addr; /* pointer to buffer data */
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uint32_t addr; /* pointer to buffer data */
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uint32_t addr_next; /* link to next descriptor */
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uint32_t addr_next; /* link to next descriptor */
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uint32_t tdes4;
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uint32_t tdes5;
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uint32_t timestamp_low;
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uint32_t timestamp_high;
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};
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};
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/*
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/*
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@ -138,6 +151,9 @@ struct dwc_hwdesc
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*/
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*/
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#define DWC_DESC_RING_ALIGN 2048
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#define DWC_DESC_RING_ALIGN 2048
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#define DWC_CKSUM_ASSIST (CSUM_IP | CSUM_TCP | CSUM_UDP | \
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CSUM_TCP_IPV6 | CSUM_UDP_IPV6)
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static struct resource_spec dwc_spec[] = {
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static struct resource_spec dwc_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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@ -173,8 +189,8 @@ dwc_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
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}
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}
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static void
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static void
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dwc_setup_txdesc(struct dwc_softc *sc, int idx, bus_dma_segment_t segs[TX_MAX_DMA_SEGS],
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dwc_setup_txdesc(struct dwc_softc *sc, int csum_flags, int idx,
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int nsegs)
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bus_dma_segment_t segs[TX_MAX_DMA_SEGS], int nsegs)
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{
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{
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int i;
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int i;
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@ -211,9 +227,17 @@ dwc_setup_txdesc(struct dwc_softc *sc, int idx, bus_dma_segment_t segs[TX_MAX_DM
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flags = DDESC_TDES0_TXCHAIN | DDESC_TDES0_TXINT |
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flags = DDESC_TDES0_TXCHAIN | DDESC_TDES0_TXINT |
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DDESC_TDES0_OWN;
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DDESC_TDES0_OWN;
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if (i == 0)
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if (i == 0) {
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flags |= DDESC_TDES0_TXFIRST;
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flags |= DDESC_TDES0_TXFIRST;
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if ((csum_flags & (CSUM_TCP | CSUM_UDP |
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CSUM_TCP_IPV6 | CSUM_UDP_IPV6)) != 0)
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flags |=
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DDESC_TDES0_CIC_IP_HDR_PYL_PHDR;
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else if ((csum_flags & CSUM_IP) != 0)
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flags |= DDESC_TDES0_CIC_IP_HDR;
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}
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if (i == nsegs - 1)
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if (i == nsegs - 1)
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flags |= DDESC_TDES0_TXLAST;
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flags |= DDESC_TDES0_TXLAST;
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@ -262,7 +286,7 @@ dwc_setup_txbuf(struct dwc_softc *sc, struct mbuf *m, int *start_tx)
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bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map,
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bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map,
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BUS_DMASYNC_PREWRITE);
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BUS_DMASYNC_PREWRITE);
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dwc_setup_txdesc(sc, idx, segs, nsegs);
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dwc_setup_txdesc(sc, m->m_pkthdr.csum_flags, idx, segs, nsegs);
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ETHER_BPF_MTAP(sc->ifp, m);
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ETHER_BPF_MTAP(sc->ifp, m);
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*start_tx = 1;
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*start_tx = 1;
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@ -462,6 +486,7 @@ dwc_init_locked(struct dwc_softc *sc)
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/* Enable transmitters */
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/* Enable transmitters */
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reg = READ4(sc, MAC_CONFIGURATION);
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reg = READ4(sc, MAC_CONFIGURATION);
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reg |= (CONF_IPC);
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reg |= (CONF_JD | CONF_ACS | CONF_BE);
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reg |= (CONF_JD | CONF_ACS | CONF_BE);
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reg |= (CONF_TE | CONF_RE);
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reg |= (CONF_TE | CONF_RE);
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WRITE4(sc, MAC_CONFIGURATION, reg);
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WRITE4(sc, MAC_CONFIGURATION, reg);
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@ -770,6 +795,7 @@ dwc_rxfinish_locked(struct dwc_softc *sc)
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struct mbuf *m;
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struct mbuf *m;
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int error, idx, len;
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int error, idx, len;
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uint32_t rdes0;
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uint32_t rdes0;
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uint32_t rdes4;
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ifp = sc->ifp;
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ifp = sc->ifp;
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@ -791,6 +817,31 @@ dwc_rxfinish_locked(struct dwc_softc *sc)
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m->m_pkthdr.len = len;
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m->m_pkthdr.len = len;
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m->m_len = len;
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m->m_len = len;
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/* Check checksum offload flags. */
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if ((rdes0 & DDESC_RDES0_ESA) != 0) {
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rdes4 = sc->rxdesc_ring[idx].tdes4;
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/* TCP or UDP checks out, IP checks out too. */
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if ((rdes4 & DDESC_RDES4_IP_PYL_TYPE_MSK) ==
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DDESC_RDES4_IP_PYL_UDP ||
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(rdes4 & DDESC_RDES4_IP_PYL_TYPE_MSK) ==
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DDESC_RDES4_IP_PYL_TCP) {
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m->m_pkthdr.csum_flags |=
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CSUM_IP_CHECKED |
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CSUM_IP_VALID |
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CSUM_DATA_VALID |
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CSUM_PSEUDO_HDR;
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m->m_pkthdr.csum_data = 0xffff;
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} else if ((rdes4 & (DDESC_RDES4_IP_PYL_ERR |
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DDESC_RDES4_IP_HDR_ERR)) == 0) {
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/* Only IP checks out. */
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m->m_pkthdr.csum_flags |=
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CSUM_IP_CHECKED |
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CSUM_IP_VALID;
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m->m_pkthdr.csum_data = 0xffff;
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}
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}
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/* Remove trailing FCS */
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/* Remove trailing FCS */
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m_adj(m, -ETHER_CRC_LEN);
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m_adj(m, -ETHER_CRC_LEN);
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@ -1014,6 +1065,7 @@ setup_dma(struct dwc_softc *sc)
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"could not create new RX buffer.\n");
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"could not create new RX buffer.\n");
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goto out;
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goto out;
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}
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}
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sc->rxdesc_ring[idx].tdes4 = 0;
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}
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}
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out:
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out:
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@ -1229,6 +1281,7 @@ dwc_attach(device_t dev)
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} else
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} else
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reg = (BUS_MODE_EIGHTXPBL);
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reg = (BUS_MODE_EIGHTXPBL);
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reg |= (BUS_MODE_PBL_BEATS_8 << BUS_MODE_PBL_SHIFT);
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reg |= (BUS_MODE_PBL_BEATS_8 << BUS_MODE_PBL_SHIFT);
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reg |= (BUS_MODE_ATDS);
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WRITE4(sc, BUS_MODE, reg);
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WRITE4(sc, BUS_MODE, reg);
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/*
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/*
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@ -1256,8 +1309,10 @@ dwc_attach(device_t dev)
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ifp->if_softc = sc;
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ifp->if_softc = sc;
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if_initname(ifp, device_get_name(dev), device_get_unit(dev));
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if_initname(ifp, device_get_name(dev), device_get_unit(dev));
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ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
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ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
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ifp->if_capabilities = IFCAP_VLAN_MTU;
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ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6 |
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IFCAP_VLAN_MTU | IFCAP_VLAN_HWCSUM;
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ifp->if_capenable = ifp->if_capabilities;
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ifp->if_capenable = ifp->if_capabilities;
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ifp->if_hwassist = DWC_CKSUM_ASSIST;
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ifp->if_start = dwc_txstart;
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ifp->if_start = dwc_txstart;
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ifp->if_ioctl = dwc_ioctl;
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ifp->if_ioctl = dwc_ioctl;
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ifp->if_init = dwc_init;
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ifp->if_init = dwc_init;
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@ -43,6 +43,7 @@
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#define CONF_PS (1 << 15) /* GMII/MII */
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#define CONF_PS (1 << 15) /* GMII/MII */
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#define CONF_FES (1 << 14) /* MII speed select */
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#define CONF_FES (1 << 14) /* MII speed select */
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#define CONF_DM (1 << 11) /* Full Duplex Enable */
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#define CONF_DM (1 << 11) /* Full Duplex Enable */
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#define CONF_IPC (1 << 10) /* Checksum Enable */
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#define CONF_ACS (1 << 7)
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#define CONF_ACS (1 << 7)
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#define CONF_TE (1 << 3)
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#define CONF_TE (1 << 3)
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#define CONF_RE (1 << 2)
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#define CONF_RE (1 << 2)
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@ -220,6 +221,7 @@
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#define BUS_MODE_PRIORXTX_11 0
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#define BUS_MODE_PRIORXTX_11 0
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#define BUS_MODE_PBL_SHIFT 8 /* Single block transfer size */
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#define BUS_MODE_PBL_SHIFT 8 /* Single block transfer size */
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#define BUS_MODE_PBL_BEATS_8 8
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#define BUS_MODE_PBL_BEATS_8 8
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#define BUS_MODE_ATDS (1 << 7) /* Alternate Descriptor Size */
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#define BUS_MODE_SWR (1 << 0) /* Reset */
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#define BUS_MODE_SWR (1 << 0) /* Reset */
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#define TRANSMIT_POLL_DEMAND 0x1004
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#define TRANSMIT_POLL_DEMAND 0x1004
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#define RECEIVE_POLL_DEMAND 0x1008
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#define RECEIVE_POLL_DEMAND 0x1008
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