mirror of
https://git.rtems.org/rtems-libbsd/
synced 2025-06-02 07:43:08 +08:00
at91_mci: Get rid of bounce buffer
This commit is contained in:
Sebastian Huber
parent
3fac9e9cd4
commit
d45899bce8
@ -140,15 +140,14 @@ static sXdmad *pXdmad = &XDMAD_Instance;
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* than 16K gets turned into a dcache_wbinv_all(). That needlessly flushes the
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* entire data cache, impacting overall system performance.
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*/
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#define BBCOUNT 2
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#ifndef __rtems__
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#define BBSIZE (16*1024)
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#define MAX_BLOCKS ((BBSIZE*BBCOUNT)/512)
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#else /* __rtems__ */
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#define BBCOUNT 2
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#define BBSIZE (32*1024)
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#define MAX_BLOCKS ((BBSIZE)/512)
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/* FIXME: It would be better to split the DMA up in that case like in the
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* original driver. But that would need some rework. */
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#else /* __rtems__ */
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#define MAX_BLOCKS 32
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#endif /* __rtems__ */
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#ifndef __rtems__
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@ -177,17 +176,20 @@ struct at91_mci_softc {
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#ifdef __rtems__
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RTEMS_INTERRUPT_LOCK_MEMBER(sc_lock)
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#endif /* __rtems__ */
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#ifndef __rtems__
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bus_dma_tag_t dmatag;
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#endif /* __rtems__ */
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struct mmc_host host;
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int bus_busy;
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struct mmc_request *req;
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struct mmc_command *curcmd;
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#ifndef __rtems__
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bus_dmamap_t bbuf_map[BBCOUNT];
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char * bbuf_vaddr[BBCOUNT]; /* bounce bufs in KVA space */
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uint32_t bbuf_len[BBCOUNT]; /* len currently queued for bounce buf */
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uint32_t bbuf_curidx; /* which bbuf is the active DMA buffer */
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uint32_t xfer_offset; /* offset so far into caller's buf */
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#ifdef __rtems__
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#else /* __rtems__ */
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uint32_t xdma_tx_channel;
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uint32_t xdma_rx_channel;
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uint8_t xdma_tx_perid;
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@ -207,10 +209,10 @@ static void at91_mci_intr(void *);
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static int at91_mci_activate(device_t dev);
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static void at91_mci_deactivate(device_t dev);
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static int at91_mci_is_mci1rev2xx(void);
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#ifdef __rtems__
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#ifndef __rtems__
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static void at91_mci_read_done(struct at91_mci_softc *sc, uint32_t sr);
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static void at91_mci_write_done(struct at91_mci_softc *sc, uint32_t sr);
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#endif /* __rtems__ */
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static void at91_mci_write_done(struct at91_mci_softc *sc, uint32_t sr);
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#ifndef __rtems__
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#define AT91_MCI_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
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@ -251,6 +253,7 @@ WR4(struct at91_mci_softc *sc, bus_size_t off, uint32_t val)
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bus_write_4(sc->mem_res, off, val);
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}
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#ifndef __rtems__
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static void
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at91_bswap_buf(struct at91_mci_softc *sc, void * dptr, void * sptr, uint32_t memsize)
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{
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@ -295,6 +298,7 @@ at91_mci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
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return;
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*(bus_addr_t *)arg = segs[0].ds_addr;
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}
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#endif /* __rtems__ */
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static void
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at91_mci_pdc_disable(struct at91_mci_softc *sc)
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@ -430,7 +434,11 @@ at91_mci_attach(device_t dev)
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struct sysctl_ctx_list *sctx;
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struct sysctl_oid *soid;
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device_t child;
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#ifndef __rtems__
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int err, i;
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#else /* __rtems__ */
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int err;
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#endif /* __rtems__ */
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#ifdef __rtems__
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#ifdef LIBBSP_ARM_ATSAM_BSP_H
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@ -515,6 +523,7 @@ at91_mci_attach(device_t dev)
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at91_mci_fini(dev);
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at91_mci_init(dev);
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#ifndef __rtems__
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/*
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* Allocate DMA tags and maps and bounce buffers.
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*
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@ -543,7 +552,6 @@ at91_mci_attach(device_t dev)
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/*
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* Activate the interrupt
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*/
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#ifndef __rtems__
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err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
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NULL, at91_mci_intr, sc, &sc->intrhand);
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#else /* __rtems__ */
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@ -604,6 +612,9 @@ at91_mci_attach(device_t dev)
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sc->host.caps |= MMC_CAP_4_BIT_DATA;
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child = device_add_child(dev, "mmc", 0);
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#ifdef __rtems__
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(void)child;
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#endif /* __rtems__ */
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device_set_ivars(dev, &sc->host);
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err = bus_generic_attach(dev);
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out:
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@ -615,14 +626,18 @@ out:
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static int
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at91_mci_detach(device_t dev)
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{
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#ifndef __rtems__
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struct at91_mci_softc *sc = device_get_softc(dev);
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#endif /* __rtems__ */
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at91_mci_fini(dev);
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at91_mci_deactivate(dev);
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#ifndef __rtems__
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bus_dmamem_free(sc->dmatag, sc->bbuf_vaddr[0], sc->bbuf_map[0]);
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bus_dmamem_free(sc->dmatag, sc->bbuf_vaddr[1], sc->bbuf_map[1]);
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bus_dma_tag_destroy(sc->dmatag);
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#endif /* __rtems__ */
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return (EBUSY); /* XXX */
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}
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@ -759,7 +774,7 @@ static LinkedListDescriporView1 dma_desc[MAX_BLOCKS];
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static void
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at91_mci_setup_xdma(struct at91_mci_softc *sc, bool read, uint32_t block_size,
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uint32_t number_blocks, bus_addr_t paddr, uint32_t len)
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uint32_t block_count, void *data, uint32_t len)
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{
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sXdmadCfg *xdma_cfg;
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uint32_t xdma_channel;
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@ -782,17 +797,17 @@ at91_mci_setup_xdma(struct at91_mci_softc *sc, bool read, uint32_t block_size,
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xdma_channel = sc->xdma_tx_channel;
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}
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for (i = 0; i < number_blocks; ++i) {
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for (i = 0; i < block_count; ++i) {
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if (read) {
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dma_desc[i].mbr_sa = sa_rdr;
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dma_desc[i].mbr_da = ((uint32_t)paddr) + i * block_size;
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dma_desc[i].mbr_da = ((uint32_t)data) + i * block_size;
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} else {
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dma_desc[i].mbr_sa = ((uint32_t)paddr) + i * block_size;
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dma_desc[i].mbr_sa = ((uint32_t)data) + i * block_size;
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dma_desc[i].mbr_da = da_tdr;
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}
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dma_desc[i].mbr_ubc = XDMA_UBC_NVIEW_NDV1 |
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XDMA_UBC_NDEN_UPDATED | (block_size/4);
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if (i == number_blocks - 1) {
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if (i == block_count - 1) {
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dma_desc[i].mbr_ubc |= XDMA_UBC_NDE_FETCH_DIS;
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dma_desc[i].mbr_nda = 0;
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} else {
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@ -808,9 +823,9 @@ at91_mci_setup_xdma(struct at91_mci_softc *sc, bool read, uint32_t block_size,
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/* FIXME: Is that correct? */
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if (read) {
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rtems_cache_invalidate_multiple_data_lines(paddr, len);
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rtems_cache_invalidate_multiple_data_lines(data, len);
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} else {
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rtems_cache_flush_multiple_data_lines(paddr, len);
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rtems_cache_flush_multiple_data_lines(data, len);
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}
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rtems_cache_flush_multiple_data_lines(dma_desc, sizeof(dma_desc));
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@ -819,17 +834,16 @@ at91_mci_setup_xdma(struct at91_mci_softc *sc, bool read, uint32_t block_size,
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panic("Could not start XDMA: %d.", rc);
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}
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#endif /* __rtems__ */
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static void
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at91_mci_start_cmd(struct at91_mci_softc *sc, struct mmc_command *cmd)
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{
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uint32_t cmdr, mr;
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struct mmc_data *data;
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#ifdef __rtems__
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uint32_t number_blocks;
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uint32_t block_count;
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uint32_t block_size;
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#endif /* __rtems__ */
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struct mmc_data *data;
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sc->curcmd = cmd;
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data = cmd->data;
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@ -927,16 +941,6 @@ at91_mci_start_cmd(struct at91_mci_softc *sc, struct mmc_command *cmd)
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mr = RD4(sc,MCI_MR) & ~MCI_MR_BLKLEN;
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mr |= min(data->len, 512) << 16;
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WR4(sc, MCI_MR, mr | MCI_MR_PDCMODE|MCI_MR_PDCPADV);
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#else /* __rtems__ */
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mr = RD4(sc,MCI_MR);
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WR4(sc, MCI_MR, mr | MCI_MR_PDCPADV);
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WR4(sc, MCI_DMA, MCI_DMA_DMAEN | MCI_DMA_CHKSIZE_1);
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block_size = min(data->len, 512);
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number_blocks = data->len / block_size;
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WR4(sc, MCI_BLKR, block_size << 16 | number_blocks);
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#endif /* __rtems__ */
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/*
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* Set up DMA.
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@ -970,29 +974,33 @@ at91_mci_start_cmd(struct at91_mci_softc *sc, struct mmc_command *cmd)
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*/
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sc->xfer_offset = 0;
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sc->bbuf_curidx = 0;
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#else /* __rtems__ */
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mr = RD4(sc,MCI_MR);
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WR4(sc, MCI_MR, mr | MCI_MR_PDCPADV);
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WR4(sc, MCI_DMA, MCI_DMA_DMAEN | MCI_DMA_CHKSIZE_1);
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block_size = min(data->len, 512);
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block_count = data->len / block_size;
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WR4(sc, MCI_BLKR, (block_size << 16) | block_count);
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#endif /* __rtems__ */
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if (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE)) {
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#ifndef __rtems__
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uint32_t len;
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uint32_t remaining = data->len;
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bus_addr_t paddr;
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int err;
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#ifndef __rtems__
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if (remaining > (BBCOUNT*BBSIZE))
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#else /* __rtems__ */
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if (remaining > (BBSIZE))
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#endif /* __rtems__ */
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panic("IO read size exceeds MAXDATA\n");
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#endif /* __rtems__ */
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if (data->flags & MMC_DATA_READ) {
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#ifndef __rtems__
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if (remaining > 2048) // XXX
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len = remaining / 2;
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else
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#else
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/* FIXME: This reduces performance. Set up DMA in two
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* parts instead like done on AT91. */
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#endif /* __rtems__ */
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len = remaining;
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err = bus_dmamap_load(sc->dmatag, sc->bbuf_map[0],
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sc->bbuf_vaddr[0], len, at91_mci_getaddr,
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@ -1001,7 +1009,6 @@ at91_mci_start_cmd(struct at91_mci_softc *sc, struct mmc_command *cmd)
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panic("IO read dmamap_load failed\n");
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bus_dmamap_sync(sc->dmatag, sc->bbuf_map[0],
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BUS_DMASYNC_PREREAD);
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#ifndef __rtems__
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WR4(sc, PDC_RPR, paddr);
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WR4(sc, PDC_RCR, len / 4);
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sc->bbuf_len[0] = len;
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@ -1024,16 +1031,11 @@ at91_mci_start_cmd(struct at91_mci_softc *sc, struct mmc_command *cmd)
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}
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WR4(sc, PDC_PTCR, PDC_PTCR_RXTEN);
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#else /* __rtems__ */
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at91_mci_setup_xdma(sc, true, block_size,
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number_blocks, paddr, len);
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sc->bbuf_len[0] = len;
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remaining -= len;
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sc->bbuf_len[1] = 0;
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if (remaining != 0)
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panic("Still rx-data left. This should never happen.");
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at91_mci_setup_xdma(sc, true, block_size, block_count,
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data->data, data->len);
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#endif /* __rtems__ */
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} else {
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#ifndef __rtems__
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len = min(BBSIZE, remaining);
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at91_bswap_buf(sc, sc->bbuf_vaddr[0], data->data, len);
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err = bus_dmamap_load(sc->dmatag, sc->bbuf_map[0],
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@ -1043,7 +1045,6 @@ at91_mci_start_cmd(struct at91_mci_softc *sc, struct mmc_command *cmd)
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panic("IO write dmamap_load failed\n");
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bus_dmamap_sync(sc->dmatag, sc->bbuf_map[0],
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BUS_DMASYNC_PREWRITE);
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#ifndef __rtems__
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/*
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* Erratum workaround: PDC transfer length on a write
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* must not be smaller than 12 bytes (3 words); only
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@ -1073,15 +1074,8 @@ at91_mci_start_cmd(struct at91_mci_softc *sc, struct mmc_command *cmd)
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}
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/* do not enable PDC xfer until CMDRDY asserted */
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#else /* __rtems__ */
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at91_mci_setup_xdma(sc, false, block_size,
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number_blocks, paddr, len);
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sc->bbuf_len[0] = len;
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remaining -= len;
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sc->bbuf_len[1] = 0;
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if (remaining != 0)
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panic("Still tx-data left. This should never happen.");
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at91_mci_setup_xdma(sc, false, block_size, block_count,
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data->data, data->len);
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#endif /* __rtems__ */
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}
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data->xfer_len = 0; /* XXX what's this? appears to be unused. */
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@ -1190,6 +1184,7 @@ at91_mci_release_host(device_t brdev, device_t reqdev)
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return (0);
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}
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#ifndef __rtems__
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static void
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at91_mci_read_done(struct at91_mci_softc *sc, uint32_t sr)
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{
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@ -1207,10 +1202,8 @@ at91_mci_read_done(struct at91_mci_softc *sc, uint32_t sr)
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* operation, otherwise we wait for another ENDRX for the next bufer.
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*/
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#ifndef __rtems__
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bus_dmamap_sync(sc->dmatag, sc->bbuf_map[curidx], BUS_DMASYNC_POSTREAD);
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bus_dmamap_unload(sc->dmatag, sc->bbuf_map[curidx]);
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#endif /* __rtems__ */
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at91_bswap_buf(sc, dataptr + sc->xfer_offset, sc->bbuf_vaddr[curidx], len);
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@ -1235,13 +1228,10 @@ at91_mci_read_done(struct at91_mci_softc *sc, uint32_t sr)
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at91_mci_next_operation(sc);
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} else {
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WR4(sc, PDC_RNCR, 0);
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#ifndef __rtems__
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WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_ENDRX);
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#else /* __rtems__ */
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WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_XFRDONE);
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#endif /* __rtems__ */
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}
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}
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#endif /* __rtems__ */
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static void
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at91_mci_write_done(struct at91_mci_softc *sc, uint32_t sr)
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@ -1259,9 +1249,11 @@ at91_mci_write_done(struct at91_mci_softc *sc, uint32_t sr)
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WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS);
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#ifndef __rtems__
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bus_dmamap_sync(sc->dmatag, sc->bbuf_map[sc->bbuf_curidx],
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BUS_DMASYNC_POSTWRITE);
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bus_dmamap_unload(sc->dmatag, sc->bbuf_map[sc->bbuf_curidx]);
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#endif /* __rtems__ */
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if ((cmd->data->flags & MMC_DATA_MULTI) || (sr & MCI_SR_NOTBUSY)) {
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cmd->error = MMC_ERR_NONE;
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@ -1532,9 +1524,11 @@ at91_mci_intr(void *arg)
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}
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#else /* __rtems__ */
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if (isr & MCI_SR_XFRDONE) {
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struct mmc_command *cmd = sc->curcmd;
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if (cmd->data->flags & MMC_DATA_READ) {
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at91_mci_read_done(sc, sr);
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WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS |
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PDC_PTCR_TXTDIS);
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cmd->error = MMC_ERR_NONE;
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at91_mci_next_operation(sc);
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} else {
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if (sr & MCI_SR_BLKE)
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isr |= MCI_SR_BLKE;
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