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zy7_slcr: Import from FreeBSD
This commit is contained in:
Sebastian Huber
parent
946611a1af
commit
dae9f66600
1
Makefile
1
Makefile
@ -403,6 +403,7 @@ LIB_C_FILES += freebsd/sys/dev/mii/e1000phy.c
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LIB_C_FILES += freebsd/sys/dev/mii/brgphy.c
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LIB_C_FILES += freebsd/sys/dev/tsec/if_tsec.c
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LIB_C_FILES += freebsd/sys/dev/cadence/if_cgem.c
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LIB_C_FILES += freebsd/sys/arm/xilinx/zy7_slcr.c
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LIB_C_FILES += freebsd/sys/dev/usb/usb_busdma.c
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LIB_C_FILES += freebsd/sys/dev/usb/usb_core.c
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LIB_C_FILES += freebsd/sys/dev/usb/usb_debug.c
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@ -1260,6 +1260,7 @@ devNet.addKernelSpaceHeaderFiles(
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'sys/dev/tsec/if_tsec.h',
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'sys/dev/tsec/if_tsecreg.h',
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'sys/dev/cadence/if_cgem_hw.h',
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'sys/arm/xilinx/zy7_slcr.h',
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]
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)
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devNet.addKernelSpaceSourceFiles(
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@ -1272,6 +1273,7 @@ devNet.addKernelSpaceSourceFiles(
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'sys/dev/mii/brgphy.c',
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'sys/dev/tsec/if_tsec.c',
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'sys/dev/cadence/if_cgem.c',
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'sys/arm/xilinx/zy7_slcr.c',
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]
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)
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449
freebsd/sys/arm/xilinx/zy7_slcr.c
Normal file
449
freebsd/sys/arm/xilinx/zy7_slcr.c
Normal file
@ -0,0 +1,449 @@
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#include <machine/rtems-bsd-kernel-space.h>
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/*-
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* Copyright (c) 2013 Thomas Skibo
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Zynq-700 SLCR driver. Provides hooks for cpu_reset and PL control stuff.
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* In the future, maybe MIO control, clock control, etc. could go here.
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*
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* Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
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* (v1.4) November 16, 2012. Xilinx doc UG585.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <rtems/bsd/sys/param.h>
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#include <sys/systm.h>
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#ifdef __rtems__
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#include <sys/bus.h>
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#endif /* __rtems__ */
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <rtems/bsd/sys/lock.h>
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#include <sys/mutex.h>
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#include <rtems/bsd/sys/resource.h>
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#include <sys/sysctl.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <machine/stdarg.h>
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#ifndef __rtems__
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#endif /* __rtems__ */
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#include <arm/xilinx/zy7_slcr.h>
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struct zy7_slcr_softc {
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device_t dev;
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struct mtx sc_mtx;
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struct resource *mem_res;
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};
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static struct zy7_slcr_softc *zy7_slcr_softc_p;
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#ifndef __rtems__
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extern void (*zynq7_cpu_reset);
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#endif /* __rtems__ */
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#define ZSLCR_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
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#define ZSLCR_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
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#define ZSLCR_LOCK_INIT(sc) \
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mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \
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"zy7_slcr", MTX_DEF)
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#define ZSLCR_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
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#define RD4(sc, off) (bus_read_4((sc)->mem_res, (off)))
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#define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val)))
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#define ZYNQ_DEFAULT_PS_CLK_FREQUENCY 33333333 /* 33.3 Mhz */
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SYSCTL_NODE(_hw, OID_AUTO, zynq, CTLFLAG_RD, 0, "Xilinx Zynq-7000");
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static char zynq_bootmode[64];
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SYSCTL_STRING(_hw_zynq, OID_AUTO, bootmode, CTLFLAG_RD, zynq_bootmode, 0,
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"Zynq boot mode");
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static char zynq_pssid[100];
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SYSCTL_STRING(_hw_zynq, OID_AUTO, pssid, CTLFLAG_RD, zynq_pssid, 0,
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"Zynq PSS IDCODE");
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static uint32_t zynq_reboot_status;
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SYSCTL_INT(_hw_zynq, OID_AUTO, reboot_status, CTLFLAG_RD, &zynq_reboot_status,
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0, "Zynq REBOOT_STATUS register");
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static int ps_clk_frequency;
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SYSCTL_INT(_hw_zynq, OID_AUTO, ps_clk_frequency, CTLFLAG_RD, &ps_clk_frequency,
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0, "Zynq PS_CLK Frequency");
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static int io_pll_frequency;
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SYSCTL_INT(_hw_zynq, OID_AUTO, io_pll_frequency, CTLFLAG_RD, &io_pll_frequency,
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0, "Zynq IO PLL Frequency");
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static int arm_pll_frequency;
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SYSCTL_INT(_hw_zynq, OID_AUTO, arm_pll_frequency, CTLFLAG_RD,
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&arm_pll_frequency, 0, "Zynq ARM PLL Frequency");
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static int ddr_pll_frequency;
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SYSCTL_INT(_hw_zynq, OID_AUTO, ddr_pll_frequency, CTLFLAG_RD,
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&ddr_pll_frequency, 0, "Zynq DDR PLL Frequency");
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static void
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zy7_slcr_unlock(struct zy7_slcr_softc *sc)
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{
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/* Unlock SLCR with magic number. */
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WR4(sc, ZY7_SLCR_UNLOCK, ZY7_SLCR_UNLOCK_MAGIC);
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}
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static void
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zy7_slcr_lock(struct zy7_slcr_softc *sc)
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{
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/* Lock SLCR with magic number. */
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WR4(sc, ZY7_SLCR_LOCK, ZY7_SLCR_LOCK_MAGIC);
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}
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#ifndef __rtems__
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static void
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zy7_slcr_cpu_reset(void)
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{
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struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
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/* Unlock SLCR registers. */
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zy7_slcr_unlock(sc);
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/* This has something to do with a work-around so the fsbl will load
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* the bitstream after soft-reboot. It's very important.
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*/
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WR4(sc, ZY7_SLCR_REBOOT_STAT,
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RD4(sc, ZY7_SLCR_REBOOT_STAT) & 0xf0ffffff);
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/* Soft reset */
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WR4(sc, ZY7_SLCR_PSS_RST_CTRL, ZY7_SLCR_PSS_RST_CTRL_SOFT_RESET);
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for (;;)
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;
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}
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/* Assert PL resets and disable level shifters in preparation of programming
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* the PL (FPGA) section. Called from zy7_devcfg.c.
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*/
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void
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zy7_slcr_preload_pl(void)
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{
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struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
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if (!sc)
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return;
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ZSLCR_LOCK(sc);
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/* Unlock SLCR registers. */
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zy7_slcr_unlock(sc);
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/* Assert top level output resets. */
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WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, ZY7_SLCR_FPGA_RST_CTRL_RST_ALL);
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/* Disable all level shifters. */
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WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, 0);
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/* Lock SLCR registers. */
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zy7_slcr_lock(sc);
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ZSLCR_UNLOCK(sc);
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}
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/* After PL configuration, enable level shifters and deassert top-level
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* PL resets. Called from zy7_devcfg.c. Optionally, the level shifters
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* can be left disabled but that's rare of an FPGA application. That option
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* is controled by a sysctl in the devcfg driver.
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*/
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void
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zy7_slcr_postload_pl(int en_level_shifters)
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{
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struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
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if (!sc)
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return;
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ZSLCR_LOCK(sc);
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/* Unlock SLCR registers. */
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zy7_slcr_unlock(sc);
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if (en_level_shifters)
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/* Enable level shifters. */
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WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, ZY7_SLCR_LVL_SHFTR_EN_ALL);
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/* Deassert top level output resets. */
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WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, 0);
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/* Lock SLCR registers. */
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zy7_slcr_lock(sc);
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ZSLCR_UNLOCK(sc);
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}
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#endif /* __rtems__ */
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/* Override cgem_set_refclk() in gigabit ethernet driver
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* (sys/dev/cadence/if_cgem.c). This function is called to
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* request a change in the gem's reference clock speed.
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*/
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int
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cgem_set_ref_clk(int unit, int frequency)
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{
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struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
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int div0, div1;
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if (!sc)
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return (-1);
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/* Find suitable divisor pairs. Round result to nearest khz
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* to test for match.
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*/
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for (div1 = 1; div1 <= ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_MAX; div1++) {
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div0 = (io_pll_frequency + div1 * frequency / 2) /
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div1 / frequency;
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if (div0 > 0 && div0 <= ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_MAX &&
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((io_pll_frequency / div0 / div1) + 500) / 1000 ==
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(frequency + 500) / 1000)
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break;
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}
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if (div1 > ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_MAX)
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return (-1);
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ZSLCR_LOCK(sc);
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/* Unlock SLCR registers. */
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zy7_slcr_unlock(sc);
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/* Modify GEM reference clock. */
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WR4(sc, unit ? ZY7_SLCR_GEM1_CLK_CTRL : ZY7_SLCR_GEM0_CLK_CTRL,
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(div1 << ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_SHIFT) |
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(div0 << ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_SHIFT) |
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ZY7_SLCR_GEM_CLK_CTRL_SRCSEL_IO_PLL |
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ZY7_SLCR_GEM_CLK_CTRL_CLKACT);
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/* Lock SLCR registers. */
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zy7_slcr_lock(sc);
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ZSLCR_UNLOCK(sc);
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return (0);
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}
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static int
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zy7_slcr_probe(device_t dev)
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{
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#ifndef __rtems__
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "xlnx,zy7_slcr"))
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return (ENXIO);
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#endif /* __rtems__ */
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device_set_desc(dev, "Zynq-7000 slcr block");
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return (0);
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}
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static int
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zy7_slcr_attach(device_t dev)
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{
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struct zy7_slcr_softc *sc = device_get_softc(dev);
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int rid;
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#ifndef __rtems__
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phandle_t node;
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pcell_t cell;
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#endif /* __rtems__ */
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uint32_t bootmode;
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uint32_t pss_idcode;
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uint32_t arm_pll_ctrl;
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uint32_t ddr_pll_ctrl;
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uint32_t io_pll_ctrl;
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static char *bootdev_names[] = {
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"JTAG", "Quad-SPI", "NOR", "(3?)",
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"NAND", "SD Card", "(6?)", "(7?)"
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};
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/* Allow only one attach. */
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if (zy7_slcr_softc_p != NULL)
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return (ENXIO);
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sc->dev = dev;
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ZSLCR_LOCK_INIT(sc);
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/* Get memory resource. */
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rid = 0;
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sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (sc->mem_res == NULL) {
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device_printf(dev, "could not allocate memory resources.\n");
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return (ENOMEM);
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}
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/* Hook up cpu_reset. */
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zy7_slcr_softc_p = sc;
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#ifndef __rtems__
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zynq7_cpu_reset = zy7_slcr_cpu_reset;
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#endif /* __rtems__ */
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/* Read info and set sysctls. */
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bootmode = RD4(sc, ZY7_SLCR_BOOT_MODE);
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snprintf(zynq_bootmode, sizeof(zynq_bootmode),
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"0x%x: boot device: %s", bootmode,
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bootdev_names[bootmode & ZY7_SLCR_BOOT_MODE_BOOTDEV_MASK]);
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pss_idcode = RD4(sc, ZY7_SLCR_PSS_IDCODE);
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snprintf(zynq_pssid, sizeof(zynq_pssid),
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"0x%x: manufacturer: 0x%x device: 0x%x "
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"family: 0x%x sub-family: 0x%x rev: 0x%x",
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pss_idcode,
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(pss_idcode & ZY7_SLCR_PSS_IDCODE_MNFR_ID_MASK) >>
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ZY7_SLCR_PSS_IDCODE_MNFR_ID_SHIFT,
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(pss_idcode & ZY7_SLCR_PSS_IDCODE_DEVICE_MASK) >>
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ZY7_SLCR_PSS_IDCODE_DEVICE_SHIFT,
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(pss_idcode & ZY7_SLCR_PSS_IDCODE_FAMILY_MASK) >>
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ZY7_SLCR_PSS_IDCODE_FAMILY_SHIFT,
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(pss_idcode & ZY7_SLCR_PSS_IDCODE_SUB_FAMILY_MASK) >>
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ZY7_SLCR_PSS_IDCODE_SUB_FAMILY_SHIFT,
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(pss_idcode & ZY7_SLCR_PSS_IDCODE_REVISION_MASK) >>
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ZY7_SLCR_PSS_IDCODE_REVISION_SHIFT);
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zynq_reboot_status = RD4(sc, ZY7_SLCR_REBOOT_STAT);
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/* Derive PLL frequencies from PS_CLK. */
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#ifndef __rtems__
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node = ofw_bus_get_node(dev);
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if (OF_getprop(node, "clock-frequency", &cell, sizeof(cell)) > 0)
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ps_clk_frequency = fdt32_to_cpu(cell);
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else
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#endif /* __rtems__ */
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ps_clk_frequency = ZYNQ_DEFAULT_PS_CLK_FREQUENCY;
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arm_pll_ctrl = RD4(sc, ZY7_SLCR_ARM_PLL_CTRL);
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ddr_pll_ctrl = RD4(sc, ZY7_SLCR_DDR_PLL_CTRL);
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io_pll_ctrl = RD4(sc, ZY7_SLCR_IO_PLL_CTRL);
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/* Determine ARM PLL frequency. */
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if (((arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) == 0 &&
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(arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_FORCE) != 0) ||
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((arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) != 0 &&
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(bootmode & ZY7_SLCR_BOOT_MODE_PLL_BYPASS) != 0))
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/* PLL is bypassed. */
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arm_pll_frequency = ps_clk_frequency;
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else
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arm_pll_frequency = ps_clk_frequency *
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((arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_FDIV_MASK) >>
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ZY7_SLCR_PLL_CTRL_FDIV_SHIFT);
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/* Determine DDR PLL frequency. */
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if (((ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) == 0 &&
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(ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_FORCE) != 0) ||
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((ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) != 0 &&
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(bootmode & ZY7_SLCR_BOOT_MODE_PLL_BYPASS) != 0))
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/* PLL is bypassed. */
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ddr_pll_frequency = ps_clk_frequency;
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else
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ddr_pll_frequency = ps_clk_frequency *
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((ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_FDIV_MASK) >>
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ZY7_SLCR_PLL_CTRL_FDIV_SHIFT);
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/* Determine IO PLL frequency. */
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if (((io_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) == 0 &&
|
||||
(io_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_FORCE) != 0) ||
|
||||
((io_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) != 0 &&
|
||||
(bootmode & ZY7_SLCR_BOOT_MODE_PLL_BYPASS) != 0))
|
||||
/* PLL is bypassed. */
|
||||
io_pll_frequency = ps_clk_frequency;
|
||||
else
|
||||
io_pll_frequency = ps_clk_frequency *
|
||||
((io_pll_ctrl & ZY7_SLCR_PLL_CTRL_FDIV_MASK) >>
|
||||
ZY7_SLCR_PLL_CTRL_FDIV_SHIFT);
|
||||
|
||||
/* Lock SLCR registers. */
|
||||
zy7_slcr_lock(sc);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
zy7_slcr_detach(device_t dev)
|
||||
{
|
||||
struct zy7_slcr_softc *sc = device_get_softc(dev);
|
||||
|
||||
bus_generic_detach(dev);
|
||||
|
||||
/* Release memory resource. */
|
||||
if (sc->mem_res != NULL)
|
||||
bus_release_resource(dev, SYS_RES_MEMORY,
|
||||
rman_get_rid(sc->mem_res), sc->mem_res);
|
||||
|
||||
zy7_slcr_softc_p = NULL;
|
||||
#ifndef __rtems__
|
||||
zynq7_cpu_reset = NULL;
|
||||
#endif /* __rtems__ */
|
||||
|
||||
ZSLCR_LOCK_DESTROY(sc);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static device_method_t zy7_slcr_methods[] = {
|
||||
/* device_if */
|
||||
DEVMETHOD(device_probe, zy7_slcr_probe),
|
||||
DEVMETHOD(device_attach, zy7_slcr_attach),
|
||||
DEVMETHOD(device_detach, zy7_slcr_detach),
|
||||
|
||||
DEVMETHOD_END
|
||||
};
|
||||
|
||||
static driver_t zy7_slcr_driver = {
|
||||
"zy7_slcr",
|
||||
zy7_slcr_methods,
|
||||
sizeof(struct zy7_slcr_softc),
|
||||
};
|
||||
static devclass_t zy7_slcr_devclass;
|
||||
|
||||
#ifndef __rtems__
|
||||
DRIVER_MODULE(zy7_slcr, simplebus, zy7_slcr_driver, zy7_slcr_devclass, 0, 0);
|
||||
#else /* __rtems__ */
|
||||
DRIVER_MODULE(zy7_slcr, nexus, zy7_slcr_driver, zy7_slcr_devclass, 0, 0);
|
||||
#endif /* __rtems__ */
|
||||
MODULE_VERSION(zy7_slcr, 1);
|
||||
292
freebsd/sys/arm/xilinx/zy7_slcr.h
Normal file
292
freebsd/sys/arm/xilinx/zy7_slcr.h
Normal file
@ -0,0 +1,292 @@
|
||||
/*-
|
||||
* Copyright (c) 2013 Thomas Skibo
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
/*
|
||||
* Defines for Zynq-7000 SLCR registers.
|
||||
*
|
||||
* Most of these registers are initialized by the First Stage Boot
|
||||
* Loader and are not modified by the kernel.
|
||||
*
|
||||
* Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
|
||||
* (v1.4) November 16, 2012. Xilinx doc UG585. SLCR register definitions
|
||||
* are in appendix B.28.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _ZY7_SLCR_H_
|
||||
#define _ZY7_SLCR_H_
|
||||
|
||||
#define ZY7_SCLR_SCL 0x0000
|
||||
#define ZY7_SLCR_LOCK 0x0004
|
||||
#define ZY7_SLCR_LOCK_MAGIC 0x767b
|
||||
#define ZY7_SLCR_UNLOCK 0x0008
|
||||
#define ZY7_SLCR_UNLOCK_MAGIC 0xdf0d
|
||||
#define ZY7_SLCR_LOCKSTA 0x000c
|
||||
|
||||
/* PLL controls. */
|
||||
#define ZY7_SLCR_ARM_PLL_CTRL 0x0100
|
||||
#define ZY7_SLCR_DDR_PLL_CTRL 0x0104
|
||||
#define ZY7_SLCR_IO_PLL_CTRL 0x0108
|
||||
#define ZY7_SLCR_PLL_CTRL_RESET (1<<0)
|
||||
#define ZY7_SLCR_PLL_CTRL_PWRDWN (1<<1)
|
||||
#define ZY7_SLCR_PLL_CTRL_BYPASS_QUAL (1<<3)
|
||||
#define ZY7_SLCR_PLL_CTRL_BYPASS_FORCE (1<<4)
|
||||
#define ZY7_SLCR_PLL_CTRL_FDIV_SHIFT 12
|
||||
#define ZY7_SLCR_PLL_CTRL_FDIV_MASK (0x7f<<12)
|
||||
#define ZY7_SLCR_PLL_STATUS 0x010c
|
||||
#define ZY7_SLCR_PLL_STAT_ARM_PLL_LOCK (1<<0)
|
||||
#define ZY7_SLCR_PLL_STAT_DDR_PLL_LOCK (1<<1)
|
||||
#define ZY7_SLCR_PLL_STAT_IO_PLL_LOCK (1<<2)
|
||||
#define ZY7_SLCR_PLL_STAT_ARM_PLL_STABLE (1<<3)
|
||||
#define ZY7_SLCR_PLL_STAT_DDR_PLL_STABLE (1<<4)
|
||||
#define ZY7_SLCR_PLL_STAT_IO_PLL_STABLE (1<<5)
|
||||
#define ZY7_SLCR_ARM_PLL_CFG 0x0110
|
||||
#define ZY7_SLCR_DDR_PLL_CFG 0x0114
|
||||
#define ZY7_SLCR_IO_PLL_CFG 0x0118
|
||||
#define ZY7_SLCR_PLL_CFG_RES_SHIFT 4
|
||||
#define ZY7_SLCR_PLL_CFG_RES_MASK (0xf<<4)
|
||||
#define ZY7_SLCR_PLL_CFG_PLL_CP_SHIFT 8
|
||||
#define ZY7_SLCR_PLL_CFG_PLL_CP_MASK (0xf<<8)
|
||||
#define ZY7_SLCR_PLL_CFG_LOCK_CNT_SHIFT 12
|
||||
#define ZY7_SLCR_PLL_CFG_LOCK_CNT_MASK (0x3ff<<12)
|
||||
|
||||
/* Clock controls. */
|
||||
#define ZY7_SLCR_ARM_CLK_CTRL 0x0120
|
||||
#define ZY7_SLCR_ARM_CLK_CTRL_CPU_PERI_CLKACT (1<<28)
|
||||
#define ZY7_SLCR_ARM_CLK_CTRL_CPU_1XCLKACT (1<<27)
|
||||
#define ZY7_SLCR_ARM_CLK_CTRL_CPU_2XCLKACT (1<<26)
|
||||
#define ZY7_SLCR_ARM_CLK_CTRL_CPU_3OR2XCLKACT (1<<25)
|
||||
#define ZY7_SLCR_ARM_CLK_CTRL_CPU_6OR4XCLKACT (1<<24)
|
||||
#define ZY7_SLCR_ARM_CLK_CTRL_SRCSEL_MASK (3<<4)
|
||||
#define ZY7_SLCR_ARM_CLK_CTRL_SRCSEL_ARM_PLL (0<<4)
|
||||
#define ZY7_SLCR_ARM_CLK_CTRL_SRCSEL_DDR_PLL (2<<4)
|
||||
#define ZY7_SLCR_ARM_CLK_CTRL_SRCSEL_IO_PLL (3<<4)
|
||||
#define ZY7_SLCR_ARM_CLK_CTRL_DIVISOR_SHIFT 8
|
||||
#define ZY7_SLCR_ARM_CLK_CTRL_DIVISOR_MASK (0x3f<<8)
|
||||
#define ZY7_SLCR_DDR_CLK_CTRL 0x0124
|
||||
#define ZY7_SLCR_DDR_CLK_CTRL_2XCLK_DIV_SHIFT 26
|
||||
#define ZY7_SLCR_DDR_CLK_CTRL_2XCLK_DIV_MASK (0x3f<<26)
|
||||
#define ZY7_SLCR_DDR_CLK_CTRL_3XCLK_DIV_SHIFT 20
|
||||
#define ZY7_SLCR_DDR_CLK_CTRL_3XCLK_DIV_MASK (0x3f<<20)
|
||||
#define ZY7_SLCR_DDR_CLK_CTRL_2XCLKACT (1<<1)
|
||||
#define ZY7_SLCR_DDR_CLK_CTRL_3XCLKACT (1<<0)
|
||||
#define ZY7_SLCR_DCI_CLK_CTRL 0x0128
|
||||
#define ZY7_SLCR_DCI_CLK_CTRL_DIVISOR1_SHIFT 20
|
||||
#define ZY7_SLCR_DCI_CLK_CTRL_DIVISOR1_MASK (0x3f<<20)
|
||||
#define ZY7_SLCR_DCI_CLK_CTRL_DIVISOR0_SHIFT 8
|
||||
#define ZY7_SLCR_DCI_CLK_CTRL_DIVISOR0_MASK (0x3f<<8)
|
||||
#define ZY7_SLCR_DCI_CLK_CTRL_CLKACT (1<<0)
|
||||
#define ZY7_SLCR_APER_CLK_CTRL 0x012c /* amba periph clk ctrl */
|
||||
#define ZY7_SLCR_APER_CLK_CTRL_SMC_CPU_1XCLKACT (1<<24)
|
||||
#define ZY7_SLCR_APER_CLK_CTRL_LQSPI_CPU_1XCLKACT (1<<23)
|
||||
#define ZY7_SLCR_APER_CLK_CTRL_GPIO_CPU_1XCLKACT (1<<22)
|
||||
#define ZY7_SLCR_APER_CLK_CTRL_UART1_CPU_1XCLKACT (1<<21)
|
||||
#define ZY7_SLCR_APER_CLK_CTRL_UART0_CPU_1XCLKACT (1<<20)
|
||||
#define ZY7_SLCR_APER_CLK_CTRL_I2C1_CPU_1XCLKACT (1<<19)
|
||||
#define ZY7_SLCR_APER_CLK_CTRL_I2C0_CPU_1XCLKACT (1<<18)
|
||||
#define ZY7_SLCR_APER_CLK_CTRL_CAN1_CPU_1XCLKACT (1<<17)
|
||||
#define ZY7_SLCR_APER_CLK_CTRL_CAN0_CPU_1XCLKACT (1<<16)
|
||||
#define ZY7_SLCR_APER_CLK_CTRL_SPI1_CPU_1XCLKACT (1<<15)
|
||||
#define ZY7_SLCR_APER_CLK_CTRL_SPI0_CPU_1XCLKACT (1<<14)
|
||||
#define ZY7_SLCR_APER_CLK_CTRL_SDI1_CPU_1XCLKACT (1<<11)
|
||||
#define ZY7_SLCR_APER_CLK_CTRL_SDI0_CPU_1XCLKACT (1<<10)
|
||||
#define ZY7_SLCR_APER_CLK_CTRL_GEM1_CPU_1XCLKACT (1<<7)
|
||||
#define ZY7_SLCR_APER_CLK_CTRL_GEM0_CPU_1XCLKACT (1<<6)
|
||||
#define ZY7_SLCR_APER_CLK_CTRL_USB1_CPU_1XCLKACT (1<<3)
|
||||
#define ZY7_SLCR_APER_CLK_CTRL_USB0_CPU_1XCLKACT (1<<2)
|
||||
#define ZY7_SLCR_APER_CLK_CTRL_DMA_CPU_1XCLKACT (1<<0)
|
||||
#define ZY7_SLCR_USB0_CLK_CTRL 0x0130
|
||||
#define ZY7_SLCR_USB1_CLK_CTRL 0x0134
|
||||
#define ZY7_SLCR_GEM0_RCLK_CTRL 0x0138
|
||||
#define ZY7_SLCR_GEM1_RCLK_CTRL 0x013c
|
||||
#define ZY7_SLCR_GEM0_CLK_CTRL 0x0140
|
||||
#define ZY7_SLCR_GEM1_CLK_CTRL 0x0144
|
||||
#define ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_MASK (0x3f<<20)
|
||||
#define ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_SHIFT 20
|
||||
#define ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_MAX 0x3f
|
||||
#define ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_MASK (0x3f<<8)
|
||||
#define ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_SHIFT 8
|
||||
#define ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_MAX 0x3f
|
||||
#define ZY7_SLCR_GEM_CLK_CTRL_SRCSEL_MASK (7<<4)
|
||||
#define ZY7_SLCR_GEM_CLK_CTRL_SRCSEL_IO_PLL (0<<4)
|
||||
#define ZY7_SLCR_GEM_CLK_CTRL_SRCSEL_ARM_PLL (2<<4)
|
||||
#define ZY7_SLCR_GEM_CLK_CTRL_SRCSEL_DDR_PLL (3<<4)
|
||||
#define ZY7_SLCR_GEM_CLK_CTRL_SRCSEL_EMIO_CLK (4<<4)
|
||||
#define ZY7_SLCR_GEM_CLK_CTRL_CLKACT 1
|
||||
#define ZY7_SLCR_SMC_CLK_CTRL 0x0148
|
||||
#define ZY7_SLCR_LQSPI_CLK_CTRL 0x014c
|
||||
#define ZY7_SLCR_SDIO_CLK_CTRL 0x0150
|
||||
#define ZY7_SLCR_UART_CLK_CTRL 0x0154
|
||||
#define ZY7_SLCR_SPI_CLK_CTRL 0x0158
|
||||
#define ZY7_SLCR_CAN_CLK_CTRL 0x015c
|
||||
#define ZY7_SLCR_CAN_MIOCLK_CTRL 0x0160
|
||||
#define ZY7_SLCR_DBG_CLK_CTRL 0x0164
|
||||
#define ZY7_SLCR_PCAP_CLK_CTRL 0x0168
|
||||
#define ZY7_SLCR_TOPSW_CLK_CTRL 0x016c /* central intercnn clk ctrl */
|
||||
#define ZY7_SLCR_FPGA0_CLK_CTRL 0x0170
|
||||
#define ZY7_SLCR_FPGA1_CLK_CTRL 0x0180
|
||||
#define ZY7_SLCR_FPGA2_CLK_CTRL 0x0190
|
||||
#define ZY7_SLCR_FPGA3_CLK_CTRL 0x01a0
|
||||
#define ZY7_SLCR_CLK_621_TRUE 0x01c4 /* cpu clock ratio mode */
|
||||
|
||||
/* Reset controls. */
|
||||
#define ZY7_SLCR_PSS_RST_CTRL 0x0200
|
||||
#define ZY7_SLCR_PSS_RST_CTRL_SOFT_RESET (1<<0)
|
||||
#define ZY7_SLCR_DDR_RST_CTRL 0x0204
|
||||
#define ZY7_SLCR_TOPSW_RST_CTRL 0x0208
|
||||
#define ZY7_SLCR_DMAC_RST_CTRL 0x020c
|
||||
#define ZY7_SLCR_USB_RST_CTRL 0x0210
|
||||
#define ZY7_SLCR_GEM_RST_CTRL 0x0214
|
||||
#define ZY7_SLCR_SDIO_RST_CTRL 0x0218
|
||||
#define ZY7_SLCR_SPI_RST_CTRL 0x021c
|
||||
#define ZY7_SLCR_CAN_RST_CTRL 0x0220
|
||||
#define ZY7_SLCR_I2C_RST_CTRL 0x0224
|
||||
#define ZY7_SLCR_UART_RST_CTRL 0x0228
|
||||
#define ZY7_SLCR_GPIO_RST_CTRL 0x022c
|
||||
#define ZY7_SLCR_LQSPI_RST_CTRL 0x0230
|
||||
#define ZY7_SLCR_SMC_RST_CTRL 0x0234
|
||||
#define ZY7_SLCR_OCM_RST_CTRL 0x0238
|
||||
#define ZY7_SLCR_DEVCI_RST_CTRL 0x023c
|
||||
#define ZY7_SLCR_FPGA_RST_CTRL 0x0240
|
||||
#define ZY7_SLCR_FPGA_RST_CTRL_FPGA3_OUT_RST (1<<3)
|
||||
#define ZY7_SLCR_FPGA_RST_CTRL_FPGA2_OUT_RST (1<<2)
|
||||
#define ZY7_SLCR_FPGA_RST_CTRL_FPGA1_OUT_RST (1<<1)
|
||||
#define ZY7_SLCR_FPGA_RST_CTRL_FPGA0_OUT_RST (1<<0)
|
||||
#define ZY7_SLCR_FPGA_RST_CTRL_RST_ALL 0xf
|
||||
#define ZY7_SLCR_A9_CPU_RST_CTRL 0x0244
|
||||
#define ZY7_SLCR_RS_AWDT_CTRL 0x024c
|
||||
|
||||
#define ZY7_SLCR_REBOOT_STAT 0x0258
|
||||
#define ZY7_SLCR_REBOOT_STAT_STATE_MASK (0xff<<24)
|
||||
#define ZY7_SLCR_REBOOT_STAT_POR (1<<22)
|
||||
#define ZY7_SLCR_REBOOT_STAT_SRST_B (1<<21)
|
||||
#define ZY7_SLCR_REBOOT_STAT_DBG_RST (1<<20)
|
||||
#define ZY7_SLCR_REBOOT_STAT_SLC_RST (1<<19)
|
||||
#define ZY7_SLCR_REBOOT_STAT_AWDT1_RST (1<<18)
|
||||
#define ZY7_SLCR_REBOOT_STAT_AWDT0_RST (1<<17)
|
||||
#define ZY7_SLCR_REBOOT_STAT_SWDT_RST (1<<16)
|
||||
#define ZY7_SLCR_REBOOT_STAT_BOOTROM_ERR_CODE_MASK (0xffff)
|
||||
#define ZY7_SLCR_BOOT_MODE 0x025c
|
||||
#define ZY7_SLCR_BOOT_MODE_PLL_BYPASS (1<<4)
|
||||
#define ZY7_SLCR_BOOT_MODE_JTAG_INDEP (1<<3)
|
||||
#define ZY7_SLCR_BOOT_MODE_BOOTDEV_MASK 7
|
||||
#define ZY7_SLCR_BOOT_MODE_BOOTDEV_JTAG 0
|
||||
#define ZY7_SLCR_BOOT_MODE_BOOTDEV_QUAD_SPI 1
|
||||
#define ZY7_SLCR_BOOT_MODE_BOOTDEV_NOR 2
|
||||
#define ZY7_SLCR_BOOT_MODE_BOOTDEV_NAND 4
|
||||
#define ZY7_SLCR_BOOT_MODE_BOOTDEV_SD_CARD 5
|
||||
#define ZY7_SLCR_APU_CTRL 0x0300
|
||||
#define ZY7_SLCR_WDT_CLK_SEL 0x0304
|
||||
|
||||
#define ZY7_SLCR_PSS_IDCODE 0x0530
|
||||
#define ZY7_SLCR_PSS_IDCODE_REVISION_MASK (0xf<<28)
|
||||
#define ZY7_SLCR_PSS_IDCODE_REVISION_SHIFT 28
|
||||
#define ZY7_SLCR_PSS_IDCODE_FAMILY_MASK (0x7f<<21)
|
||||
#define ZY7_SLCR_PSS_IDCODE_FAMILY_SHIFT 21
|
||||
#define ZY7_SLCR_PSS_IDCODE_SUB_FAMILY_MASK (0xf<<17)
|
||||
#define ZY7_SLCR_PSS_IDCODE_SUB_FAMILY_SHIFT 17
|
||||
#define ZY7_SLCR_PSS_IDCODE_DEVICE_MASK (0x1f<<12)
|
||||
#define ZY7_SLCR_PSS_IDCODE_DEVICE_SHIFT 12
|
||||
#define ZY7_SLCR_PSS_IDCODE_MNFR_ID_MASK (0x7ff<<1)
|
||||
#define ZY7_SLCR_PSS_IDCODE_MNFR_ID_SHIFT 1
|
||||
|
||||
#define ZY7_SLCR_DDR_URGENT 0x0600
|
||||
#define ZY7_SLCR_DDR_CAL_START 0x060c
|
||||
#define ZY7_SLCR_DDR_REF_START 0x0614
|
||||
#define ZY7_SLCR_DDR_CMD_STA 0x0618
|
||||
#define ZY7_SLCR_DDR_URGENT_SEL 0x061c
|
||||
#define ZY7_SLCR_DDR_DFI_STATUS 0x0620
|
||||
|
||||
/* MIO Pin controls */
|
||||
#define ZY7_SLCR_MIO_PIN(n) (0x0700+(n)*4) /* 0-53 */
|
||||
#define ZY7_SLCR_MIO_PIN_RCVR_DIS (1<<13)
|
||||
#define ZY7_SLCR_MIO_PIN_PULLUP_EN (1<<12)
|
||||
#define ZY7_SLCR_MIO_PIN_IO_TYPE_MASK (7<<9)
|
||||
#define ZY7_SLCR_MIO_PIN_IO_TYPE_LVTTL (0<<9)
|
||||
#define ZY7_SLCR_MIO_PIN_IO_TYPE_LVCMOS18 (1<<9)
|
||||
#define ZY7_SLCR_MIO_PIN_IO_TYPE_LVCMOS25 (2<<9)
|
||||
#define ZY7_SLCR_MIO_PIN_IO_TYPE_LVCMOS33 (3<<9)
|
||||
#define ZY7_SLCR_MIO_PIN_IO_TYPE_HSTL (4<<9)
|
||||
#define ZY7_SLCR_MIO_PIN_L2_SEL_MASK (3<<3)
|
||||
#define ZY7_SLCR_MIO_PIN_L2_SEL_L3_MUX (0<<3)
|
||||
#define ZY7_SLCR_MIO_PIN_L2_SEL_SRAM_NOR_CS0 (1<<3)
|
||||
#define ZY7_SLCR_MIO_PIN_L2_SEL_NAND_CS (2<<3)
|
||||
#define ZY7_SLCR_MIO_PIN_L2_SEL_SDIO0_PC (3<<3)
|
||||
#define ZY7_SLCR_MIO_PIN_L1_SEL (1<<2)
|
||||
#define ZY7_SLCR_MIO_PIN_L0_SEL (1<<1)
|
||||
#define ZY7_SLCR_MIO_PIN_TRI_EN (1<<0)
|
||||
|
||||
#define ZY7_SLCR_MIO_LOOPBACK 0x0804
|
||||
#define ZY7_SLCR_MIO_LOOPBACK_I2C0_I2C1 (1<<3)
|
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#define ZY7_SLCR_MIO_LOOPBACK_CAN0_CAN1 (1<<2)
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#define ZY7_SLCR_MIO_LOOPBACK_UA0_UA1 (1<<1)
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#define ZY7_SLCR_MIO_LOOPBACK_SPI0_SPI1 (1<<0)
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#define ZY7_SLCR_MIO_MST_TRI0 0x080c
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#define ZY7_SLCR_MIO_MST_TRI1 0x0810
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#define ZY7_SLCR_SD0_WP_CD_SEL 0x0830
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#define ZY7_SLCR_SD1_WP_CD_SEL 0x0834
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/* PS-PL level shifter control. */
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#define ZY7_SLCR_LVL_SHFTR_EN 0x900
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#define ZY7_SLCR_LVL_SHFTR_EN_USER_LVL_IN_EN_0 (1<<3) /* PL to PS */
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#define ZY7_SLCR_LVL_SHFTR_EN_USER_LVL_OUT_EN_0 (1<<2) /* PS to PL */
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#define ZY7_SLCR_LVL_SHFTR_EN_USER_LVL_IN_EN_1 (1<<1) /* PL to PS */
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#define ZY7_SLCR_LVL_SHFTR_EN_USER_LVL_OUT_EN_1 (1<<0) /* PS to PL */
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#define ZY7_SLCR_LVL_SHFTR_EN_ALL 0xf
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#define ZY7_SLCR_OCM_CFG 0x0910
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#define ZY7_SLCR_GPIOB_CTRL 0x0b00
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#define ZY7_SLCR_GPIOB_CFG_CMOS18 0x0b04
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#define ZY7_SLCR_GPIOB_CFG_CMOS25 0x0b08
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#define ZY7_SLCR_GPIOB_CFG_CMOS33 0x0b0c
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#define ZY7_SLCR_GPIOB_CFG_LVTTL 0x0b10
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#define ZY7_SLCR_GPIOB_CFG_HSTL 0x0b14
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#define ZY7_SLCR_GPIOB_DRVR_BIAS_CTRL 0x0b18
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#define ZY7_SLCR_DDRIOB_ADDR0 0x0b40
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#define ZY7_SLCR_DDRIOB_ADDR1 0x0b44
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#define ZY7_SLCR_DDRIOB_DATA0 0x0b48
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#define ZY7_SLCR_DDRIOB_DATA1 0x0b4c
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#define ZY7_SLCR_DDRIOB_DIFF0 0x0b50
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#define ZY7_SLCR_DDRIOB_DIFF1 0x0b54
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#define ZY7_SLCR_DDRIOB_CLK 0x0b58
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#define ZY7_SLCR_DDRIOB_DRIVE_SLEW_ADDR 0x0b5c
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#define ZY7_SLCR_DDRIOB_DRIVE_SLEW_DATA 0x0b60
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#define ZY7_SLCR_DDRIOB_DRIVE_SLEW_DIFF 0x0b64
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#define ZY7_SLCR_DDRIOB_DRIVE_SLEW_CLK 0x0b68
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#define ZY7_SLCR_DDRIOB_DDR_CTRL 0x0b6c
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#define ZY7_SLCR_DDRIOB_DCI_CTRL 0x0b70
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#define ZY7_SLCR_DDRIOB_DCI_STATUS 0x0b74
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|
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#ifdef _KERNEL
|
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extern void zy7_slcr_preload_pl(void);
|
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extern void zy7_slcr_postload_pl(int en_level_shifters);
|
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extern int cgem_set_ref_clk(int unit, int frequency);
|
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#endif
|
||||
#endif /* _ZY7_SLCR_H_ */
|
||||
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Reference in New Issue
Block a user