mirror of
https://git.rtems.org/rtems-libbsd/
synced 2025-10-14 20:19:28 +08:00
nexus: Add ZynqMP SLCR driver
Add a System Level Control Register driver for the Xilinx Zynq Ultrascale+ MPSoC with basic clock control functionality for use with the Cadence GEM. This also removes the Zynq-7000 clock control weakref from compilation depending on the BSP in use.
This commit is contained in:
Kinsey Moore
committed by
Joel Sherrill
Joel Sherrill
parent
1d9f93cbaa
commit
e256668d6e
@@ -45,6 +45,7 @@ __FBSDID("$FreeBSD$");
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#include <sys/systm.h>
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#ifdef __rtems__
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#include <sys/bus.h>
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#include <bsp.h>
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#endif /* __rtems__ */
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#include <sys/conf.h>
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#include <sys/kernel.h>
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@@ -217,6 +218,7 @@ zy7_slcr_postload_pl(int en_level_shifters)
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ZSLCR_UNLOCK(sc);
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}
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#if defined(LIBBSP_ARM_XILINX_ZYNQ_BSP_H)
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/* Override cgem_set_refclk() in gigabit ethernet driver
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* (sys/dev/cadence/if_cgem.c). This function is called to
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* request a change in the gem's reference clock speed.
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@@ -264,6 +266,7 @@ cgem_set_ref_clk(int unit, int frequency)
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return (0);
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}
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#endif /* LIBBSP_ARM_XILINX_ZYNQ_BSP_H */
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/*
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* PL clocks management function
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@@ -1423,6 +1423,7 @@ class dev_net(builder.Module):
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self.addRTEMSKernelSourceFiles(
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[
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'sys/dev/mii/ksz8091rnb_50MHz.c',
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'sys/arm64/xilinx/zynqmp_slcr.c',
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],
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mm.generator['source']()
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)
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@@ -107,6 +107,7 @@ RTEMS_BSD_DRIVER_MMC;
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#include <bsp/irq.h>
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RTEMS_BSD_DRIVER_XILINX_ZYNQMP_SLCR;
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/* Qemu only applies user-mode networking to the first interface by default, so
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* all 4 CGEM instances must be configured in the Qemu arguments using
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* "-nic user,model=cadence_gem" for each nic.
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@@ -38,6 +38,7 @@
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*
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* Devices:
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* RTEMS_BSD_DRIVER_XILINX_ZYNQ_SLCR
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* RTEMS_BSD_DRIVER_XILINX_ZYNQMP_SLCR
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* RTEMS_BSD_DRIVER_LPC32XX_PWR
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* RTEMS_BSD_DRIVER_LPC32XX_TSC
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*
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@@ -117,6 +118,26 @@ extern "C" {
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&zy7_slcr_res[0])
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#endif /* RTEMS_BSD_DRIVER_XILINX_ZYNQ_SLCR */
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/*
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* Xilinx ZynqMP System Level Control Registers (SLCR).
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*/
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#if !defined(RTEMS_BSD_DRIVER_XILINX_ZYNQMP_SLCR)
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/*
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* Hard IP part of the ZynqMP so a fixed address.
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*/
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#define RTEMS_BSD_DRIVER_XILINX_ZYNQMP_SLCR \
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static const rtems_bsd_device_resource zynqmp_slcr_res[] = { \
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{ \
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.type = RTEMS_BSD_RES_MEMORY, \
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.start_request = 0, \
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.start_actual = 0xf0000000 \
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} \
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}; \
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RTEMS_BSD_DEFINE_NEXUS_DEVICE(zynqmp_slcr, 0, \
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RTEMS_ARRAY_SIZE(zynqmp_slcr_res), \
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&zynqmp_slcr_res[0])
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#endif /* RTEMS_BSD_DRIVER_XILINX_ZYNQMP_SLCR */
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/*
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* Xilinx Zynq Arasan SDIO Driver.
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*/
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233
rtemsbsd/sys/arm64/xilinx/zynqmp_slcr.c
Normal file
233
rtemsbsd/sys/arm64/xilinx/zynqmp_slcr.c
Normal file
@@ -0,0 +1,233 @@
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#include <machine/rtems-bsd-kernel-space.h>
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2021 Kinsey Moore
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Zynq Ultrascale+ MPSoC SLCR driver. Provides hook for CGEM clocks.
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*
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* Reference: Zynq Ultrascale+ MPSoC Technical Reference Manual.
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* (v2.2) December 4, 2020. Xilinx doc UG1085.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <bsp.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <rtems/bsd/sys/resource.h>
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#include <sys/sysctl.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <machine/stdarg.h>
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#include <arm64/xilinx/zynqmp_slcr.h>
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struct zynqmp_slcr_softc {
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device_t dev;
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struct mtx sc_mtx;
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struct resource *mem_res;
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};
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static struct zynqmp_slcr_softc *zynqmp_slcr_softc_p;
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#define RD4(sc, off) (bus_read_4((sc)->mem_res, (off)))
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#define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val)))
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SYSCTL_NODE(_hw, OID_AUTO, zynqmp, CTLFLAG_RD, 0, "Xilinx Zynq Ultrascale+ MPSoC");
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#if defined(LIBBSP_AARCH64_XILINX_ZYNQMP_BSP_H)
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/* Override cgem_set_refclk() in gigabit ethernet driver
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* (sys/dev/cadence/if_cgem.c). This function is called to
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* request a change in the gem's reference clock speed.
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*/
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int
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cgem_set_ref_clk(int unit, int frequency)
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{
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struct zynqmp_slcr_softc *sc = zynqmp_slcr_softc_p;
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int div0, div1;
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uint64_t clk_ctrl, pll_ctrl;
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uint32_t clk_ctrl_val, pll_ctrl_val, pll_freq, pll_bypass;
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if (!sc)
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return (-1);
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switch (unit) {
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case 0:
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clk_ctrl = ZYNQMP_SLCR_GEM0_CLK_CTRL;
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break;
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case 1:
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clk_ctrl = ZYNQMP_SLCR_GEM1_CLK_CTRL;
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break;
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case 2:
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clk_ctrl = ZYNQMP_SLCR_GEM2_CLK_CTRL;
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break;
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case 3:
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clk_ctrl = ZYNQMP_SLCR_GEM3_CLK_CTRL;
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break;
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default:
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return (-1);
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}
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clk_ctrl_val = RD4(sc, clk_ctrl);
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switch (clk_ctrl_val & ZYNQMP_SLCR_GEM_CLK_CTRL_SRCSEL_MASK) {
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case 0:
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pll_ctrl = ZYNQMP_SLCR_IO_PLL_CTRL;
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break;
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case 2:
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pll_ctrl = ZYNQMP_SLCR_R_PLL_CTRL;
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break;
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case 3:
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pll_ctrl = ZYNQMP_SLCR_D_PLL_CTRL;
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break;
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default:
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return (-1);
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}
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/* Get PLL frequency */
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pll_ctrl_val = RD4(sc, pll_ctrl);
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pll_bypass = pll_ctrl_val & ZYNQMP_SLCR_PLL_CTRL_BYPASS;
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if ((pll_ctrl_val & ZYNQMP_SLCR_PLL_CTRL_RESET) && !pll_bypass) {
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return 0;
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}
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pll_freq = ZYNQMP_DEFAULT_PS_CLK_FREQUENCY;
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if (!pll_bypass) {
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pll_freq *= (pll_ctrl_val & ZYNQMP_SLCR_PLL_CTRL_FBDIV_MASK) >> ZYNQMP_SLCR_PLL_CTRL_FBDIV_SHIFT;
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}
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/* Divide by 2 if necessary */
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pll_freq >>= !!(pll_ctrl_val & ZYNQMP_SLCR_PLL_CTRL_DIV2);
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/* Find suitable divisor pairs. Round result to nearest khz
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* to test for match.
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*/
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for (div1 = 1; div1 <= ZYNQMP_SLCR_GEM_CLK_CTRL_DIVISOR1_MAX; div1++) {
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div0 = (pll_freq + div1 * frequency / 2) /
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div1 / frequency;
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if (div0 > 0 && div0 <= ZYNQMP_SLCR_GEM_CLK_CTRL_DIVISOR0_MAX &&
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((pll_freq / div0 / div1) + 500) / 1000 ==
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(frequency + 500) / 1000)
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break;
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}
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if (div1 > ZYNQMP_SLCR_GEM_CLK_CTRL_DIVISOR1_MAX)
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return (-1);
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/* Modify GEM reference clock. */
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clk_ctrl_val &= ~ZYNQMP_SLCR_GEM_CLK_CTRL_DIVISOR1_MASK;
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clk_ctrl_val &= ~ZYNQMP_SLCR_GEM_CLK_CTRL_DIVISOR0_MASK;
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clk_ctrl_val |= div1 << ZYNQMP_SLCR_GEM_CLK_CTRL_DIVISOR1_SHIFT;
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clk_ctrl_val |= div0 << ZYNQMP_SLCR_GEM_CLK_CTRL_DIVISOR0_SHIFT;
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WR4(sc, clk_ctrl, clk_ctrl_val);
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return (0);
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}
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#endif
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static int
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zynqmp_slcr_probe(device_t dev)
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{
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device_set_desc(dev, "Zynq Ultrascale+ MPSoC SLCR block");
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return (0);
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}
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static int
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zynqmp_slcr_attach(device_t dev)
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{
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struct zynqmp_slcr_softc *sc = device_get_softc(dev);
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int rid;
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/* Allow only one attach. */
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if (zynqmp_slcr_softc_p != NULL)
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return (ENXIO);
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sc->dev = dev;
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/* Get memory resource. */
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rid = 0;
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sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (sc->mem_res == NULL) {
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device_printf(dev, "could not allocate memory resources.\n");
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return (ENOMEM);
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}
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/* For use with CGEM clock setting */
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zynqmp_slcr_softc_p = sc;
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return (0);
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}
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static int
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zynqmp_slcr_detach(device_t dev)
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{
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struct zynqmp_slcr_softc *sc = device_get_softc(dev);
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bus_generic_detach(dev);
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/* Release memory resource. */
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if (sc->mem_res != NULL)
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bus_release_resource(dev, SYS_RES_MEMORY,
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rman_get_rid(sc->mem_res), sc->mem_res);
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zynqmp_slcr_softc_p = NULL;
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return (0);
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}
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static device_method_t zynqmp_slcr_methods[] = {
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/* device_if */
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DEVMETHOD(device_probe, zynqmp_slcr_probe),
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DEVMETHOD(device_attach, zynqmp_slcr_attach),
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DEVMETHOD(device_detach, zynqmp_slcr_detach),
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DEVMETHOD_END
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};
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static driver_t zynqmp_slcr_driver = {
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"zynqmp_slcr",
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zynqmp_slcr_methods,
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sizeof(struct zynqmp_slcr_softc),
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};
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static devclass_t zynqmp_slcr_devclass;
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DRIVER_MODULE(zynqmp_slcr, nexus, zynqmp_slcr_driver, zynqmp_slcr_devclass, 0, 0);
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MODULE_VERSION(zynqmp_slcr, 1);
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90
rtemsbsd/sys/arm64/xilinx/zynqmp_slcr.h
Normal file
90
rtemsbsd/sys/arm64/xilinx/zynqmp_slcr.h
Normal file
@@ -0,0 +1,90 @@
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2021 Kinsey Moore
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
|
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* are met:
|
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* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
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*
|
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Defines for Zynq Ultrascale+ MPSoC SLCR registers.
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*
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* Reference: Zynq Ultrascale+ MPSoC Technical Reference Manual.
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* (v2.2) December 4, 2020. Xilinx doc UG1085.
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*
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* Additional Reference: Zynq Ultrascale+ MPSoC Register Reference.
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* (v1.7) February 8, 2019. Xilinx doc UG1087.
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*/
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#ifndef _ZYNQMP_SLCR_H_
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#define _ZYNQMP_SLCR_H_
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#define ZYNQMP_SLCR_CRF_OFFSET 0x0d1a0000
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#define ZYNQMP_SLCR_CRL_OFFSET 0x0f5e0000
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/* PLL controls. */
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#define ZYNQMP_SLCR_IO_PLL_CTRL (ZYNQMP_SLCR_CRL_OFFSET + 0x20)
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#define ZYNQMP_SLCR_R_PLL_CTRL (ZYNQMP_SLCR_CRL_OFFSET + 0x30)
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#define ZYNQMP_SLCR_D_PLL_CTRL (ZYNQMP_SLCR_CRF_OFFSET + 0x2c)
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#define ZYNQMP_SLCR_PLL_CTRL_RESET (1<<0)
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#define ZYNQMP_SLCR_PLL_CTRL_BYPASS (1<<3)
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#define ZYNQMP_SLCR_PLL_CTRL_FBDIV_SHIFT 8
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#define ZYNQMP_SLCR_PLL_CTRL_FBDIV_MASK (0x7f<<8)
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#define ZYNQMP_SLCR_PLL_CTRL_FBDIV_MAX 0x7f
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#define ZYNQMP_SLCR_PLL_CTRL_DIV2 (1<<16)
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#define ZYNQMP_SLCR_PLL_CTRL_PRE_SRC_SHIFT 20
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#define ZYNQMP_SLCR_PLL_CTRL_PRE_SRC_MASK (0x7<<20)
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#define ZYNQMP_SLCR_PLL_CTRL_POST_SRC_SHIFT 24
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#define ZYNQMP_SLCR_PLL_CTRL_POST_SRC_MASK (0x7<<24)
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#define ZYNQMP_SLCR_PLL_CTRL_SRC_PS 0x0
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#define ZYNQMP_SLCR_PLL_CTRL_SRC_VIDEO 0x4
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#define ZYNQMP_SLCR_PLL_CTRL_SRC_ALT 0x5
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#define ZYNQMP_SLCR_PLL_CTRL_SRC_AUX 0x6
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#define ZYNQMP_SLCR_PLL_CTRL_SRC_GT 0x7
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/* Clock controls. */
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#define ZYNQMP_SLCR_GEM0_CLK_CTRL (ZYNQMP_SLCR_CRL_OFFSET + 0x50)
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#define ZYNQMP_SLCR_GEM1_CLK_CTRL (ZYNQMP_SLCR_CRL_OFFSET + 0x54)
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#define ZYNQMP_SLCR_GEM2_CLK_CTRL (ZYNQMP_SLCR_CRL_OFFSET + 0x58)
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#define ZYNQMP_SLCR_GEM3_CLK_CTRL (ZYNQMP_SLCR_CRL_OFFSET + 0x5c)
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#define ZYNQMP_SLCR_GEM_CLK_CTRL_RX_CLKACT (1<<26)
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#define ZYNQMP_SLCR_GEM_CLK_CTRL_CLKACT (1<<25)
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#define ZYNQMP_SLCR_GEM_CLK_CTRL_DIVISOR1_MASK (0x3f<<16)
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#define ZYNQMP_SLCR_GEM_CLK_CTRL_DIVISOR1_SHIFT 16
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#define ZYNQMP_SLCR_GEM_CLK_CTRL_DIVISOR1_MAX 0x3f
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#define ZYNQMP_SLCR_GEM_CLK_CTRL_DIVISOR0_MASK (0x3f<<8)
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#define ZYNQMP_SLCR_GEM_CLK_CTRL_DIVISOR0_SHIFT 8
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#define ZYNQMP_SLCR_GEM_CLK_CTRL_DIVISOR0_MAX 0x3f
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#define ZYNQMP_SLCR_GEM_CLK_CTRL_SRCSEL_MASK (7<<0)
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#define ZYNQMP_SLCR_GEM_CLK_CTRL_SRCSEL_IO_PLL (0<<0)
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#define ZYNQMP_SLCR_GEM_CLK_CTRL_SRCSEL_R_PLL (2<<0)
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#define ZYNQMP_SLCR_GEM_CLK_CTRL_SRCSEL_D_PLL (3<<0)
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#define ZYNQMP_DEFAULT_PS_CLK_FREQUENCY 33333333
|
||||
|
||||
#ifdef _KERNEL
|
||||
extern int cgem_set_ref_clk(int unit, int frequency);
|
||||
#endif
|
||||
#endif /* _ZYNQMP_SLCR_H_ */
|
||||
Reference in New Issue
Block a user