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nexus: Add ZynqMP SLCR driver
Add a System Level Control Register driver for the Xilinx Zynq Ultrascale+ MPSoC with basic clock control functionality for use with the Cadence GEM. This also removes the Zynq-7000 clock control weakref from compilation depending on the BSP in use.
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committed by
Joel Sherrill

parent
1d9f93cbaa
commit
e256668d6e