nexus: Add ZynqMP SLCR driver

Add a System Level Control Register driver for the Xilinx Zynq
Ultrascale+ MPSoC with basic clock control functionality for use with
the Cadence GEM. This also removes the Zynq-7000 clock control weakref
from compilation depending on the BSP in use.
This commit is contained in:
Kinsey Moore
2021-02-09 07:14:11 -06:00
committed by Joel Sherrill
parent 1d9f93cbaa
commit e256668d6e
6 changed files with 349 additions and 0 deletions

View File

@@ -1423,6 +1423,7 @@ class dev_net(builder.Module):
self.addRTEMSKernelSourceFiles(
[
'sys/dev/mii/ksz8091rnb_50MHz.c',
'sys/arm64/xilinx/zynqmp_slcr.c',
],
mm.generator['source']()
)