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nexus: Add ZynqMP SLCR driver

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Add a System Level Control Register driver for the Xilinx Zynq
Ultrascale+ MPSoC with basic clock control functionality for use with
the Cadence GEM. This also removes the Zynq-7000 clock control weakref
from compilation depending on the BSP in use.
This commit is contained in:
Kinsey Moore
2021-02-09 07:14:11 -06:00
committed by Joel Sherrill
parent 1d9f93cbaa
commit e256668d6e
6 changed files with 349 additions and 0 deletions
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21
rtemsbsd/include/machine/rtems-bsd-nexus-bus.h
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@@ -38,6 +38,7 @@
*
* Devices:
* RTEMS_BSD_DRIVER_XILINX_ZYNQ_SLCR
* RTEMS_BSD_DRIVER_XILINX_ZYNQMP_SLCR
* RTEMS_BSD_DRIVER_LPC32XX_PWR
* RTEMS_BSD_DRIVER_LPC32XX_TSC
*
@@ -117,6 +118,26 @@ extern "C" {
&zy7_slcr_res[0])
#endif /* RTEMS_BSD_DRIVER_XILINX_ZYNQ_SLCR */
/*
* Xilinx ZynqMP System Level Control Registers (SLCR).
*/
#if !defined(RTEMS_BSD_DRIVER_XILINX_ZYNQMP_SLCR)
/*
* Hard IP part of the ZynqMP so a fixed address.
*/
#define RTEMS_BSD_DRIVER_XILINX_ZYNQMP_SLCR \
static const rtems_bsd_device_resource zynqmp_slcr_res[] = { \
{ \
.type = RTEMS_BSD_RES_MEMORY, \
.start_request = 0, \
.start_actual = 0xf0000000 \
} \
}; \
RTEMS_BSD_DEFINE_NEXUS_DEVICE(zynqmp_slcr, 0, \
RTEMS_ARRAY_SIZE(zynqmp_slcr_res), \
&zynqmp_slcr_res[0])
#endif /* RTEMS_BSD_DRIVER_XILINX_ZYNQMP_SLCR */
/*
* Xilinx Zynq Arasan SDIO Driver.
*/